High-power-density distributed feedback type laser chip and preparation process thereof

Abstract

The invention relates to the technical field of semiconductor laser devices, in particular to a high-power-density distributed feedback type laser chip and a preparation process thereof. According to the technical scheme, the chip comprises a chip body, the chip body comprises a back electrode, a substrate, a lower waveguide layer, a lower limiting layer, an active layer, an upper limiting layer, an upper waveguide layer, a highly-doped layer and a front electrode which are sequentially stacked from bottom to top, and graphene layers are arranged on the sides, close to the active layer, of the lower limiting layer and the upper limiting layer. According to the invention, the graphene heat conduction layer and the conical bulge and micropore array are introduced between the active layer and the limiting layer, so that heat is directly and quickly dredged, thermal resistance and interface strain are reduced, heat accumulation is relieved from the source, and the reliability of the chip is improved; the artificial micro-nano grating formed by the conical structure and the DFB built-in grating cooperatively enhance longitudinal mode feedback, and improve the side mode rejection ratio and the light field limiting factor. Meanwhile, mode locking and 1 microsecond-level wavelength tuning are achieved through array type current injection, and the light spot and coupling efficiency is improved in cooperation with a unit-level micro lens.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser device technology, and in particular to a high power density distributed feedback laser chip and its fabrication process. Background Technology

[0002] In fields such as optical communication, lidar, and industrial processing, increasingly stringent requirements are being placed on the power density, beam quality, and stability of laser light sources. Distributed feedback laser chips, with their single-mode output characteristics, narrow linewidth, and good temperature stability, have become the core light source devices for these high-end applications. As application demands move towards higher power densities, chip output power continues to increase. However, the heat dissipation performance of the active layer, the core region for laser generation, is gradually becoming a key bottleneck restricting device performance improvement and reliability. Generally, high thermal conductivity materials are used as the chip substrate to accelerate heat dissipation from the active layer.

[0003] An upper confinement layer and a lower confinement layer are respectively set above and below the active layer. The heat generated by the active layer still needs to overcome the thermal resistance of the upper and lower confinement layers before it can be transferred to the substrate. This cannot fundamentally solve the problem of internal heat accumulation caused by the lack of heat dissipation components above and below the active layer. Therefore, this application proposes a high power density distributed feedback laser chip. Summary of the Invention

[0004] The purpose of this invention is to address the problem of heat accumulation inside the active layer in the prior art, which restricts the improvement of chip performance and reliability, and to propose a high power density distributed feedback laser chip and its fabrication process.

[0005] The technical solution of the present invention: A high power density distributed feedback laser chip, comprising a chip body, wherein the chip body comprises, from bottom to top, a back electrode, a substrate, a lower waveguide layer, a lower confinement layer, an active layer, an upper confinement layer, an upper waveguide layer, a highly doped layer, and a front electrode, wherein the lower confinement layer and the upper confinement layer are provided with a graphene layer on the side near the active layer, and the graphene layer is provided with a tapered protrusion on the side near the active layer; The distance between the conical protrusion below the upper limiting layer and the conical protrusion above the lower limiting layer is 200-250nm. The conical protrusion above the lower limiting layer is a regular cone that is narrower at the top and wider at the bottom, while the conical protrusion below the upper limiting layer is an inverted cone that is wider at the top and narrower at the bottom.

[0006] Optionally, multiple conical grooves are provided on both sides of the active layer, and the conical grooves and the conical protrusions are adapted to each other.

[0007] Optionally, the sides of the conical protrusion are provided with multiple sets of micropore arrays to prevent hot spot formation and enhance lateral heat diffusion.

[0008] Optionally, the inner wall of the conical groove is provided with a filling layer, which is adapted to the contour of the conical protrusion to form a tightly fitting interface structure.

[0009] Optionally, the substrate has a pit array on the side near the lower waveguide layer. The pit array is used to scatter stray light transmitted within the substrate to reduce its interference with the active layer.

[0010] Optionally, the pits in the pit array are circular, with a diameter of 1.5-2 μm and a depth of 0.9-1.2 μm.

[0011] Optionally, the highly doped layer has a silicon oxide insulating layer on the side near the front electrode, and the surface of the silicon oxide insulating layer has multiple perforated windows, which are used for array-type current injection and mode locking.

[0012] Optionally, the hollowed-out window is provided with a microlens, which is any one of glass material, polymer material or composite functional material.

[0013] Optionally, the surface of the graphene layer is provided with a plurality of micro-circular holes, which can be used to release stress and prevent the graphene layer from cracking.

[0014] This invention also proposes a fabrication process for a high power density distributed feedback laser chip, characterized in that the fabrication process includes the following steps: ① Substrate pretreatment: An n-type GaAs substrate is provided, and a pit array is formed on one side of the substrate through photolithography and etching processes. The pits are then cleaned and ready for use. A metal layer is sequentially evaporated and annealed on the other side of the substrate to form a back electrode; ② Fabrication of the lower waveguide layer and confinement layer: An n-type lower waveguide layer is epitaxially grown on the pit side of the substrate; An n-type lower confinement layer is epitaxially grown on the lower waveguide layer, and a graphene layer is grown on its surface. Conical protrusions are formed by nanoimprinting. ③ Integration of the active layer and the upper confinement layer: An epitaxial multi-quantum-well active layer is formed above the lower confinement layer protrusion, and a conical groove adapted to the lower confinement layer protrusion is formed by photolithography and etching processes, and a filling layer is deposited on the inner wall of the groove. A p-type upper confinement layer is epitaxially grown on the active layer, followed by the growth of a graphene layer and the fabrication of an inverted conical protrusion, and then a p-type upper waveguide layer is epitaxially grown. ④ Highly doped layers and microlens fabrication: A silicon oxide insulating layer is deposited on a p-type highly doped layer epitaxially outside the upper waveguide layer, and a hollow window is formed by photolithography and etching. Microlenses were fabricated within a hollowed-out window; ⑤ Electrode packaging and testing: A metal layer is evaporated on the surface of the highly doped layer and the insulating layer, and then annealed to form the front electrode. After laser cutting the chips, electrical and optical performance tests are conducted to screen qualified products.

[0015] Compared with the prior art, the present invention has the following beneficial technical effects: 1. This invention introduces a graphene thermally conductive layer at the interface between the active layer and the upper and lower confinement layers. Through the design of conical protrusions and micropore arrays, the heat generated in the active region can be directly and quickly conducted laterally and longitudinally, significantly reducing thermal resistance and interface strain. This alleviates the problem of internal heat accumulation caused by the need for heat to cross the confinement layer to be conducted to the substrate in traditional structures. At the same time, the conical grooves and protrusions form periodic artificial micro-nano gratings, which work synergistically with the built-in grating of the DFB laser to significantly enhance specific longitudinal mode feedback, improve the side-mode suppression ratio and optical field confinement factor, reduce the leakage of the optical field to the substrate and the upper confinement layer, effectively reduce the threshold current and improve mode stability. 2. This invention employs an array-type current injection structure, dividing the active layer into multiple independent light-emitting units through perforated windows in the silicon oxide insulating layer. This allows for precise control of the injection current in each unit to achieve mode locking, resulting in ultra-short pulse outputs of less than 10 ps. Combined with the stress effect of the silicon oxide insulating layer, it enables fine wavelength tuning at the 1 μs level, eliminating the need for an additional temperature control unit. Each current injection unit is equipped with a silicon dioxide microlens for precise collimation or focusing of the output beam, significantly improving the far-field spot shape and symmetry, enhancing beam quality and system coupling efficiency, and providing a high-performance light source for applications such as high-speed optical communication and precision sensing. In summary, this invention achieves direct and rapid heat dissipation by introducing a graphene thermally conductive layer, conical protrusions, and a micropore array between the active layer and the confinement layer, thereby reducing thermal resistance and interfacial strain, alleviating heat accumulation at the source, and improving chip reliability. The conical structure forms an artificial micro / nano grating, which, together with the DFB built-in grating, enhances longitudinal mode feedback, improves the side-mode suppression ratio and optical field confinement factor. At the same time, array-type current injection achieves mode locking and 1μs-level wavelength tuning, and unit-level microlenses improve the spot size and coupling efficiency. Attached Figure Description

[0016] Figure 1 A first-view three-dimensional structural diagram of a high power density distributed feedback laser chip; Figure 2 This is a second-view three-dimensional structural diagram of a high power density distributed feedback laser chip. Figure 3 This is a first-view exploded view of a high power density distributed feedback laser chip. Figure 4This is a second-view exploded schematic diagram of a high power density distributed feedback laser chip. Figure 5 for Figure 3 A schematic diagram of the front section structure; Figure 6 A three-dimensional schematic diagram of the lower limit layer; Figure 7 for Figure 6 Enlarged structural diagram at point A; Figure 8 A three-dimensional schematic diagram of a silicon oxide insulating layer; Figure 9 This is a schematic diagram of a cross-section of a silicon oxide insulating layer; Figure 10 This is a three-dimensional schematic diagram of the active layer; Figure 11 for Figure 10 A magnified structural diagram of part B.

[0017] Figure label: 1. Chip body; 11. Back electrode; 12. Substrate; 121. Pits array; 13. Lower waveguide layer; 14. Lower confinement layer; 141. Graphene layer; 142. Micro-circular holes; 143. Conical protrusions; 1431. Micropore array; 15. Active layer; 151. Conical groove; 152. Filler layer; 16. Upper restriction layer; 17. Upper waveguide layer; 18. Highly doped layer; 181. Silicon oxide insulating layer; 182. Hollowed-out window; 183. Microlens; 19. Front electrode. Detailed Implementation

[0018] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] like Figure 1 - Figure 5 As shown, the present invention proposes a high power density distributed feedback laser chip, which includes a chip body 1. The chip body 1 includes a back electrode 11, a substrate 12, a lower waveguide layer 13, a lower confinement layer 14, an active layer 15, an upper confinement layer 16, an upper waveguide layer 17, a highly doped layer 18, and a front electrode 19, which are stacked sequentially from bottom to top.

[0020] Specifically, the back electrode 11 adopts an Au-Ge-Ni / Au composite structure, which is formed by co-evaporation and rapid thermal annealing to achieve low contact resistivity and low impedance electrical contact with the substrate 12 without rectification effect, ensuring efficient tunneling transport of charge carriers. The top layer of the back electrode 11 is covered with a 2μm Au layer as a conductivity and heat dissipation enhancement layer, which can efficiently dissipate the heat generated during chip operation.

[0021] Furthermore, the substrate 12 is made of n-type doped GaAs single crystal material, and a circular pit array 121 is provided on one side of the substrate. The pits are 2μm in diameter, 1μm in depth, squarely arranged and spaced 4μm apart. Through the directional scattering and energy dissipation of stray light transmitted in the substrate by the micro-nano structure, the stray light transmitted in the substrate can be attenuated by more than 60%, which significantly improves the laser side-mode suppression ratio.

[0022] Furthermore, the lower waveguide layer 13 is an n-type AlGaAs ternary compound semiconductor material, which is precisely prepared by vapor deposition to form a reasonable refractive index gradient with the adjacent layers, effectively reducing waveguide loss.

[0023] Furthermore, the active layer 15 adopts a GaInAs / GaAsP structure combination, which contains 5 cycles of quantum well units. The quantum well unit is the basic structural unit, which is usually composed of a well layer (GaInAs) and a barrier layer (GaAsP) as a pair. One cycle is a complete set of well and barrier layer structures. The five cycles are repeated 5 times. Each unit consists of a 6nm thick GaInAs well layer and a 10nm thick GaAsP barrier layer.

[0024] Furthermore, the upper waveguide layer 17 is made of p-type AlGaAs material. By adopting a gradient refractive index profile design for the core optical structure and working synergistically with the lower waveguide layer 13, a highly confined optical field transmission channel is constructed. This design can significantly enhance the localization effect of the optical field in the core region of the waveguide, effectively improve the optical field confinement factor, and precisely control the distribution pattern of the optical field perpendicular to the waveguide propagation direction, reducing the leakage of the optical field to the substrate and cladding region, thereby optimizing the coupling efficiency between the optical field and the active region and laying the foundation for improving the optical performance of the device.

[0025] Furthermore, the front electrode 19 adopts a Ti / Pt / Au multilayer structure, with a bottom layer of 20nm Ti as an adhesion layer, a middle layer of 50nm Pt as a diffusion barrier layer, and a top layer of 200nm Au as a conductive layer. It is prepared by electron beam evaporation and annealed for 30 seconds to form an electrode contact structure with low contact resistance. It forms an array-type current injection structure corresponding to the hollow window 182. Through the independent control mechanism of the injected current of each unit, the precise triggering and maintenance of mode lock can be achieved. By adjusting the current parameters of each unit individually, the reliable realization of the mode lock state is ensured.

[0026] Reference Figure 10 and Figure 11 As shown, both the lower confinement layer 14 and the upper confinement layer 16 have graphene layers 141 on the side near the active layer 15. Graphene layer 141 is a two-dimensional nano-carbon material, possessing not only ultra-high thermal conductivity but also the ability to rapidly dissipate heat generated by the active layer 15. Furthermore, utilizing the electron delocalization and structural flexibility of the π-electron conjugated system, it can buffer and disperse lattice mismatch stress between epitaxial layers, reducing the adverse effects of interlayer stress accumulation on material properties. Specifically, the structural flexibility buffering effect allows the conjugated system's molecular framework to adapt to differences in lattice parameters between epitaxial layers through bond angle adjustments and slight bending, absorbing local stress like an "elastic structure" and avoiding stress concentration. The electron delocalization stress dispersion occurs because delocalized π electrons can redistribute throughout the conjugated system, balancing energy differences caused by lattice mismatch between layers through charge transfer, indirectly dispersing the influence of stress on atomic bonding states. Reducing the chain reaction of stress accumulation: Buffering and dispersion effects jointly reduce the continuous accumulation of interlayer stress, avoiding crystal defects caused by excessive stress, thereby ensuring the integrity of the epitaxial structure, reducing damage to the optoelectronic and mechanical properties of the material, improving the integrity of the epitaxial structure, and reducing interfacial strain. On the side of the graphene layer 141 near the active layer 15, a conical protrusion array 143 is formed by the combined application of nanoimprinting and inductively coupled plasma etching. The conical protrusions 143 can expand the contact area between the graphene layer 141 and the active layer 15. Combined with the isotropic thermal conductivity of graphene, the lateral thermal diffusion coefficient can be improved. A micropore array 1431 is provided on the side of the conical protrusions 143 to improve lateral thermal diffusion efficiency and prevent hot spot formation.

[0027] Specifically, the spacing between the conical protrusions 143 below the upper confinement layer 16 and above the lower confinement layer 14 is 200 nm. The conical protrusions 143 above the lower confinement layer 14 are upright cones, narrower at the top and wider at the bottom, while the conical protrusions 143 below the upper confinement layer 16 are inverted cones, wider at the top and narrower at the bottom. The arrangement of the conical protrusions 143 and the conical grooves 151 increases the contact area with the active layer 15, thereby improving heat dissipation. When the conical grooves 151 and the conical protrusions 143 are arranged according to a preset specific periodic pattern, they work together to form an artificial micro / nano grating structure. Through the periodic combination of concave and convex structures, the optical control function requirements of the grating are met. The micro / nano grating structure works synergistically with the built-in grating of the DFB laser to enhance the feedback intensity of specific longitudinal modes, and the side-mode suppression ratio can be improved by 5 dB. The DFB laser is a type of nuclear... The core semiconductor laser has advantages such as single longitudinal mode output, narrow linewidth, and high stability. The periodic refractive index contrast of the artificial micro-nano grating is precisely matched with the period of the built-in grating of the DFB laser, so that the target longitudinal mode light forms two reflections with the same phase and superimposes, which enhances the feedback. At the same time, the refractive index difference in the region of the conical protrusion 143 will change the refraction and reflection behavior due to the sudden change in refractive index. The propagation path of the light is restricted by the spatial barrier formed by the refractive index difference, which cannot leak to the outside at will, reducing the leakage of the light field to the substrate or the upper confinement layer. The light field confinement factor is increased by 10%, and the threshold current is reduced. The gap between the conical protrusion 143 and the conical groove 151 is 5-10nm, which can act as a stress buffer zone to alleviate the interface stress caused by the difference in thermal expansion coefficient between the active layer 15 and the lower confinement layer 14, and reduce the risk of interface cracking after long-term operation.

[0028] Specifically, multiple conical grooves 151 are provided on both sides of the active layer 15. The conical grooves 151 are only distributed in the central region of the active area, which can protect the edge of the active area, reduce non-radiative recombination centers to avoid current concentration at the edge, reduce the risk of overheating, improve the process fault tolerance, and reduce edge etching damage. The conical structure in the central region is gradually formed through multiple, staged etching operations. The inner wall of the conical grooves 151 is provided with a filling layer 152. The raw material of the filling layer 152 is hexagonal boron nitride, which is formed by using trimethylboron and ammonia as precursors and at 250°C through 100 deposition cycles. Its thermal conductivity reaches 400 W / (m²). K), and has a high degree of matching with the graphene lattice, avoiding carrier recombination loss caused by direct contact between graphene and the active region. The filling layer 152 is used to avoid direct contact between graphene and the active region, while providing an efficient thermal channel. The conical groove 151 and the conical protrusion 143 are adapted to each other.

[0029] Furthermore, the backlight surface of substrate 12 is fabricated with a square array of pits 121 by combining a composite adhesive layer structure of a thick bottom layer and a thin top layer, along with two photolithography and selective etching processes, to transfer the designed micro-nano patterns from the photomask to the substrate surface. The pits in the array 121 utilize the synergistic effect of plasma generation, chemical reaction, and physical bombardment to achieve the pattern transfer of the material, forming a standard hemispherical bottom. The pits have a diameter of 2 μm, a depth of 1 μm, and a center-to-center spacing of 4 μm between adjacent pits. The array covers the entire substrate surface. By optimizing the size parameters and array arrangement of the pits, the pit array 121 can effectively scatter stray light transmitted within the substrate, significantly reducing its interference with the energy states and motion modes of charge carriers or photons in the quantum well structure of the active layer 15 under confined dimensions, thereby improving the laser side-mode suppression ratio. At the same time, the microstructure formed by the pits can also increase the contact area between substrate 12 and back electrode 11, reduce thermal resistance, and provide an additional heat dissipation path for high-power operation.

[0030] Reference Figure 8 - Figure 9 As shown, a silicon oxide insulating layer 181 is provided on the side of the highly doped layer 18 near the front electrode 19. The thickness of the silicon oxide insulating layer 181 is 200 nm, and 5% GeO2 is doped into the silicon oxide insulating layer 181. The insulating layer uses SiH4 and N2O as the reaction gas source. The film stress is controlled by adjusting the deposition temperature. The quantum well energy level of the active layer can be finely tuned using this stress, so as to achieve fine tuning of the laser wavelength. The tuning speed reaches the 1 μs level without the need for an additional temperature control unit. The surface of the silicon oxide insulating layer 181 is provided with multiple hollow windows 182. Current is only allowed to be injected into the active layer 15 through the hollow windows 182 to form an array current injection mode. This structure can divide the active layer 15 into multiple independent light-emitting units. By controlling the injection current of each unit, mode locking can be achieved, so that the laser pulse width is compressed to less than 10 ps, ​​which meets the requirements of high-speed optical communication.

[0031] Specifically, the cutout window 182 is used for array-type current injection and mode locking. The cutout window 182 is formed by i-line lithography and CF4 / O2 plasma etching. i-line lithography is a lithography technology that uses 365nm wavelength ultraviolet light (i-line) as the exposure source. It is a mature and commonly used mid-ultraviolet lithography process in semiconductor manufacturing. The center-to-center spacing of adjacent windows is 4-5μm, and the window duty cycle is precisely controlled between 30-40%. Microlenses 183 are provided inside the cutout window 182. The microlenses 183 are formed of silicon dioxide. The formation of the microlenses 183 adopts atomic layer deposition technology. By alternately introducing titanium source and oxygen source gas, atomic layer-scale deposition is performed on the surface of the cutout window 182. The growth thickness and shape of silicon dioxide are precisely controlled to finally form the microlenses 183. Each microlens 183 corresponds to a current injection light-emitting unit, which can collimate or focus the diverging laser beam, significantly improve the far-field spot shape, and improve the beam quality.

[0032] Reference Figures 6 to 7 As shown, the surface of the graphene layer 141 has multiple micro-circular holes 142, which are formed by electron beam lithography and reactive ion etching (RIE) processes. Electron beam lithography uses a focused electron beam to selectively expose the photoresist, achieving nanoscale precision patterning based on the interaction between electrons and photoresist molecules. Reactive ion etching introduces plasma containing reactive ions, combining the physical action of ion bombardment with the chemical corrosion effect of plasma to precisely transfer the photoresist pattern formed by electron beam lithography to the underlying substrate material. Ultimately, the micro-circular holes 142 can be used to release stress and prevent cracking of the graphene layer 141. As stress release channels, the micro-circular holes 142 can disperse and release the thermal stress generated in the graphene layer 141 during high and low temperature cycling from -40℃ to 125℃. By discretizing the graphene-related structures into a finite number of interconnected units, mechanical equations are established and boundary conditions are considered. The system solves for the stress and strain of the graphene structure, effectively dispersing the load and reducing the maximum strain from 0.8% to below 0.3%, significantly improving structural stability and lifespan. This effectively prevents cracks caused by thermal expansion and contraction. Secondly, the array of circular holes forms a periodic dielectric structure that strongly couples with the surface plasmons of the graphene. By adjusting the diameter and spacing of the holes, a plasmon bandgap can be formed in the 1.3-1.55μm communication band, reducing surface light absorption by 15% and improving light transmission efficiency. Finally, multiple micro-circular holes 142 can serve as a photonic crystal structure to regulate the propagation of surface plasmons on the graphene. Simultaneously, the micro-circular holes 142 increase the contact area between the graphene and the surrounding medium, facilitating the rapid dissipation of heat from local hotspots and significantly improving the stability and reliability of the graphene layer in high-power laser operating environments.

[0033] This embodiment also proposes a high power density distributed feedback laser chip fabrication process, including the following steps: The laser chip of this invention is based on an n-type GaAs substrate 12 with a thickness of 300 μm, a crystal orientation of 100, and a doping concentration of 1*10. 18 A circular pit array 121 with a diameter of 2μm, a depth of 1μm, and a spacing of 4μm is formed on one side of the substrate 12 by photolithography and ICP-RIE etching. During fabrication, a combination of oxidative cleaning, deionized water rinsing, reducing cleaning, and deionized water rinsing is first used to remove organic contaminants, inorganic particles, metallic impurities, and the natural oxide layer on the substrate surface. Then, BCl3 / Cl2 mixed gas is used for etching. Finally, the target material is removed through chemical reaction or physical action using a liquid as the working medium. This pit array 121 can scatter stray light transmitted within the substrate, reduce interference to the active layer, and significantly improve the laser side-mode suppression ratio.

[0034] On the pitless side of substrate 12, Au 100nm / Ge 20nm / Ni 20nm metal layers are sequentially deposited by electron beam evaporation and then rapidly thermally annealed in N atmosphere at 400–450℃ for 30 seconds to form ohmic contacts. This structure achieves low contact resistance and good current spread, ensuring efficient device conductivity and laying the foundation for high power injection. An n-type lower waveguide layer 13 is epitaxially grown on the side of the pit array 121. The material is a ternary compound semiconductor material composed of aluminum (Al), gallium (Ga), and arsenic (As), with a thickness of 0.7 μm and a Si doping concentration of 5*10⁻⁶. 17 cm -3 Subsequently, an epitaxial n-type lower confinement layer 14, with a thickness of 1.5–2.0 μm and a Si doping concentration of 1*10⁻⁶, was constructed. 17 cm -3 These two layers work together to confine the light field and carrier diffusion, improving the light confinement factor and injection efficiency; A graphene layer 141 is grown on the surface of the lower confinement layer by CVD, and micro-circular holes 142 with a diameter of 200 nm and a spacing of 500 nm are fabricated on its surface to release stress. Subsequently, a micro-nano structure pattern transfer technique is used to realize the transfer of micro-nano structure patterns by template imprinting. Taking advantage of the thermoplastic or photocurable properties of polymer materials, the micro-nano pattern on the template is accurately copied to the surface of the substrate material. Then, through ion bombardment and chemical active particle reaction in plasma, high-precision etching of the material is achieved to form a positive conical protrusion 143 with a height of 100 nm and a bottom diameter of 200 nm. A micro-hole array 1431 with a diameter of 60 nm and a spacing of 100 nm is etched on the side. This structure increases the contact area with the active layer and improves the lateral thermal diffusion efficiency. At the same time, the micro-holes and circular holes have the functions of stress buffering and photonic crystal modulation. An epitaxial multi-quantum-well active layer 15 is formed above the protrusion of the lower confinement layer 14. The structure is a GaInAs / GaAsP combination, where GaInAs is a ternary alloy composed of indium arsenide and gallium arsenide, and GaAsP is a solid solution composed of gallium arsenide and gallium phosphide. The well width is 6 nm, and there are 5 pairs of wells. High-density plasma is generated through photolithography and inductive coupling to perform high-precision, highly selective patterning etching of the semiconductor material. A conical groove 151 matching the protrusion is formed in the central region of the active layer. The inner wall of the groove undergoes a cyclic process of surface chemical adsorption-reaction-purification to form a 5–10 nm thick hexagonal boron nitride (h-BN) filling layer 152. The conical groove is only distributed in the central region, which can protect the edge of the active region and reduce non-radiative recombination. The h-BN has a thermal conductivity as high as 400 W / (m²). K), which also acts as a stress buffer zone to mitigate the risk of interface cracking; An epitaxial p-type confinement layer 16 is formed on the active layer 15. The AlGaAs material has an Al composition of 0.3–0.4, a thickness of 1.5 μm, and a Zn doping concentration of 1*10⁻⁶. 17 cm -3 Graphene is grown on its lower surface, and inverted conical protrusions 143 are fabricated with parameters consistent with those of the regular conical protrusion. Subsequently, a p-type waveguide layer 17 with a thickness of 0.5 μm and a Zn doping concentration of 5*10⁻⁶ is formed. 17 cm -3 The upper and lower confinement layers jointly constrain the charge carriers, and the waveguide layer optimizes the optical field distribution to improve device efficiency; A highly doped p-type layer of GaAs material, with a thickness of 0.2–0.3 μm and a Zn doping concentration of 1*10⁻⁶, is epitaxially grown on the upper waveguide layer. 20 cm -3 To reduce contact resistance, plasma was then used to lower the reaction activation energy, enabling efficient thin film growth at low temperatures. This resulted in the deposition of a 200–300 nm thick SiO2 insulating layer 181, doped with 5% GeO2, at a deposition temperature of 250–300 °C. This insulating layer allows for stress-tuning of the active layer quantum well energy levels, achieving 1 μs-level wavelength fine-tuning without the need for additional temperature control. A perforated window 182 with a diameter of 2–3 μm and a spacing of 4–5 μm is formed on the insulating layer by photolithography and dry etching. Current is injected into the active layer only through the window, forming an array-type current injection mode. This structure divides the active layer into multiple independent light-emitting units, and mode locking is achieved by controlling the injection current of each unit, compressing the laser pulse width to less than 10 ps to meet the requirements of high-speed optical communication. Silica microlenses 183 were fabricated within each hollowed-out window using atomic layer deposition at a deposition temperature of 200℃. The radius of curvature was precisely controlled by alternating the introduction of TiCl4 and H2O. Each microlens corresponds to a current injection unit, which can collimate or focus the diverging beam, significantly improving the far-field spot shape and beam quality. Electron beam evaporation of 20nm Ti / 50nm Pt / 200nm Au metal layers on the surfaces of highly doped and insulating layers, followed by annealing at 350–400℃ for 30 seconds to form ohmic contacts, and finally laser dicing to divide the chip for electrical and optical testing and screening. This complete structure integrates multiple functions such as efficient heat dissipation, low interface stress, wavelength tuning, and mode locking, realizing a high power density and high reliability distributed feedback laser.

[0035] The above specific embodiments are merely several optional embodiments of the present invention. Based on the technical solutions of the present invention and the relevant teachings of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

Claims

1. A high power density distributed feedback laser chip, comprising a chip body (1), wherein the chip body (1) comprises, from bottom to top, a back electrode (11), a substrate (12), a lower waveguide layer (13), a lower confinement layer (14), an active layer (15), an upper confinement layer (16), an upper waveguide layer (17), a highly doped layer (18), and a front electrode (19), wherein: The lower confinement layer (14) and the upper confinement layer (16) are each provided with a graphene layer (141) on the side near the active layer (15), and the graphene layer (141) is provided with a conical protrusion (143) on the side near the active layer (15). The distance between the conical protrusion (143) below the upper limiting layer (16) and the conical protrusion (143) above the lower limiting layer (14) is 200-250nm. The conical protrusion (143) above the lower limiting layer (14) is a positive cone that is narrow at the top and wide at the bottom, and the conical protrusion (143) below the upper limiting layer (16) is an inverted cone that is wide at the top and narrow at the bottom.

2. The high power density distributed feedback laser chip according to claim 1, characterized in that, The active layer (15) has multiple conical grooves (151) on both sides, and the conical grooves (151) and the conical protrusions (143) are adapted to each other.

3. The high power density distributed feedback laser chip according to claim 1, characterized in that, The side of the conical protrusion (143) is provided with multiple sets of micropore arrays (1431) to avoid hot spot formation and enhance lateral heat diffusion.

4. A high power density distributed feedback laser chip according to claim 2, characterized in that, The inner wall of the conical groove (151) is provided with a filling layer (152), which is adapted to the contour of the conical protrusion (143) to form a tightly fitted interface structure.

5. A high power density distributed feedback laser chip according to claim 1, characterized in that, The substrate (12) has a pit array (121) on the side near the lower waveguide layer (13). The pit array (121) is used to scatter stray light transmitted in the substrate (12) to reduce its interference to the active layer (15).

6. A high power density distributed feedback laser chip according to claim 5, characterized in that, The pits in the pit array (121) are circular, with a diameter of 1.5-2 μm and a depth of 0.9-1.2 μm.

7. A high power density distributed feedback laser chip according to claim 1, characterized in that, The highly doped layer (18) has a silicon oxide insulating layer (181) on the side near the front electrode (19). The surface of the silicon oxide insulating layer (181) has a plurality of hollow windows (182), which are used for array current injection and mode locking.

8. A high power density distributed feedback laser chip according to claim 7, characterized in that, The hollow window (182) is provided with a microlens (183), which is any one of glass material, polymer material or composite functional material.

9. A high power density distributed feedback laser chip according to claim 1, characterized in that, The surface of the graphene layer (141) is provided with a plurality of micro-circular holes (142), which can be used to release stress and prevent the graphene layer (141) from cracking.

10. A fabrication process for a high power density distributed feedback laser chip according to any one of claims 1-9, characterized in that, The preparation process includes the following steps: Step 1: Provide an n-GaAs substrate (12), form a pit array (121) on one side of the substrate through photolithography and etching processes, clean it and set it aside, evaporate metal layers on the other side of the substrate (12) and anneal it to form a back electrode (11). Step 2: An n-type lower waveguide layer (13) is epitaxially grown on the pit side of the substrate (12), an n-type lower confinement layer (14) is epitaxially grown on the lower waveguide layer (13), a graphene layer (141) is grown on its surface, and a positive conical protrusion (143) is formed by nanoimprinting process. Step 3: Epitaxially grow a multi-quantum well active layer (5) above the lower confinement layer protrusion (143), and form a conical groove (151) adapted to the lower confinement layer protrusion (143) by photolithography and etching process, and deposit a filling layer (152) on the inner wall of the groove. A p-type upper confinement layer (16) is epitaxially grown on the active layer (5), a graphene layer (141) is grown, and an inverted conical protrusion (143) is fabricated. Then, a p-type upper waveguide layer (17) is epitaxially grown. Step 4: Epitaxially grow a p-type highly doped layer (18) on the upper waveguide layer (17), deposit a silicon oxide insulating layer (181), form a cutout window (182) by photolithography and etching, and fabricate a microlens (183) inside the cutout window. Step 5: Evaporate the metal layer on the surface of the highly doped layer (18) and the insulating layer (181), anneal to form the front electrode (19), laser cut the chip, and then perform electrical and optical performance tests to screen qualified products.

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