PCB layout method for inhibiting driving crosstalk of silicon carbide device

Abstract

The invention provides a PCB (Printed Circuit Board) layout method for inhibiting driving crosstalk of silicon carbide devices, which comprises the following steps of: dividing a PCB into a first region and a second region, and arranging each device on the surface of the PCB; layering the PCB, and respectively arranging a driving circuit and a switching circuit in each sub-layer of the PCB in the first area and the second area; the wires are arranged in the top layer of the PCB and the sub-layer close to the top layer of the PCB according to the principle of minimizing the backflow area; the wires are arranged in the PCB bottom layer and the sublayers close to the PCB bottom layer at intervals to form a mutual inductance structure; and after wiring is completed, copper laying processing is carried out on the PCB. According to the invention, by optimizing the layout of the PCB, the system performance and reliability are improved under the condition that no extra negative-voltage power supply chip or passive element needs to be added, and the whole PCB obtains stronger robustness.

Description

Technical Field

[0001] This invention belongs to the field of PCB layout technology, and particularly relates to a PCB layout method for suppressing crosstalk in silicon carbide device drivers. Background Technology

[0002] Silicon carbide (SiC) MOSFETs are gradually replacing traditional silicon-based IGBTs due to their superior characteristics such as high switching frequency, high operating junction temperature, and low on-resistance, and are widely used in new energy vehicles, industrial motor drives, photovoltaic inverters, and rail transportation. However, the higher switching speed of SiC devices also brings serious challenges, among which crosstalk is particularly prominent. When the upper half-bridge device switches at high speed, the changing voltage couples with the parasitic inductance of the drive circuit through the gate-source capacitance (Cgd, or Miller capacitance Cress), generating a voltage spike between the gate and source of the lower half-bridge device. If this voltage spike exceeds the device's threshold voltage, it will trigger false turn-on.

[0003] Currently, the most commonly used crosstalk suppression solutions in the industry mainly include: 1. Increase the gate drive resistor: Reduce dv / dt by decreasing the switching speed, but this will sacrifice the core advantage of SiC devices of high frequency and low loss and increase switching losses.

[0004] 2. Increase the turn-off negative voltage (VEE): Provide a more negative turn-off voltage to improve the noise immunity margin. This is currently the most widely used method, but the disadvantage is that it requires an additional negative power supply or a more complex drive circuit, increasing system cost, complexity, and power consumption.

[0005] Therefore, there is an urgent need for a layout solution that can suppress crosstalk without requiring additional hardware. Summary of the Invention

[0006] To address the problem described in the background section that existing technical solutions cannot suppress crosstalk without providing additional hardware, this invention proposes the following technical solution: A PCB layout method for suppressing crosstalk in silicon carbide device drivers, comprising: The PCB board is divided into a first region and a second region, and each component is placed on the surface of the PCB board. The PCB board is layered, and driving circuits and switching circuits are respectively provided in each sub-layer of the PCB board in the first region and the second region; The conductors are arranged in the top layer of the PCB board and in the sub-layers near the top layer of the PCB board according to the principle of minimizing the reflow area; The conductors are spaced apart in the bottom layer of the PCB board and the sub-layer near the bottom layer of the PCB board to form a mutual inductance structure; After the wiring is completed, copper plating is performed on the PCB board.

[0007] The conductors include: a positive wire, a negative wire, a ground wire, and a signal wire, and each sub-layer contains at least one of the positive wire, the negative wire, the ground wire, and the signal wire; In the first region, each sub-layer is isolated by taking the sub-layer where the ground wire is located as the reference layer, and the positive wire and the negative wire are arranged alternately in each sub-layer; in the second region, the signal line in each sub-layer is located between the positive wire and the negative wire.

[0008] Furthermore, in the mutual inductance structure, adjacent conductors are parallel to each other and the spacing between adjacent conductors is fixed.

[0009] Furthermore, during the copper plating process, a copper layer is deposited on the surface of each of the sub-layers, and the copper layer on the top layer of the PCB board and the copper layer on the bottom layer of the PCB board have the same thickness, the copper layer between the top layer and the bottom layer has the same thickness, and the copper layer on the top layer has a greater thickness than the copper layer between the top layer and the bottom layer.

[0010] Furthermore, in each of the sub-layers within the PCB board, there is only one junction between the power ground and the drive power ground.

[0011] Furthermore, within each of the sub-layers, the spacing between the conductors is 0.5mm to 1mm.

[0012] Furthermore, within the first region, through-holes are provided in the sub-layer where the driving circuit is located.

[0013] Beneficial effects: By optimizing the PCB layout, this invention improves system performance and reliability without the need to add additional negative voltage power chips or passive components, and makes the entire PCB board more robust. Attached Figure Description

[0014] Figure 1 This is a flowchart of a PCB layout method for suppressing crosstalk in silicon carbide device drivers according to an embodiment of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the present invention will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0016] It should be understood that the terms “center,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this patent and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this patent.

[0017] Figure 1 This is a flowchart of a PCB layout method for suppressing crosstalk in silicon carbide device drivers according to an embodiment of the present invention.

[0018] Reference Figure 1 A PCB layout method for suppressing drive crosstalk of silicon carbide devices according to an embodiment of the present invention includes: S000. Divide the PCB board into a first region and a second region, and place each component on the surface of the PCB board.

[0019] Specifically, in this step, the PCB board surface needs to be divided into a first region and a second region. The first region is located between the voltage source and the driver chip, and the second region is located between the driver chip and the power transistor. By dividing the region, the subsequent layout of the wires and the setting of the corresponding circuits are guided.

[0020] S010. The PCB board is layered, and driving circuits and switching circuits are respectively provided in each sub-layer of the PCB board in the first region and the second region.

[0021] Furthermore, this step requires delving deeper into the various sub-layers of the PCB board. The first sub-layer (i.e., the top layer) is used to house the various components, while the second and other sub-layers require the placement of corresponding wires. Preferably, during the wire placement process, the wires are categorized into: positive lines, negative lines, ground lines, and signal lines. Positive and negative lines are power lines, primarily used to provide voltage input to the components; signal lines are used to transmit signals between components; and ground lines are used for grounding. Drive circuits are located in the sub-layers within the first region, thereby providing power to other components. Switching circuits are located in the sub-layers within the second region, thereby controlling the switching of the components.

[0022] S020. The conductors are arranged in the top layer of the PCB board and the sub-layer near the top layer of the PCB board according to the principle of minimizing the reflow area.

[0023] Specifically, during signal transmission, current forms a closed loop through the "wire-load-return path." The loop area is quadratically related to the electromagnetic interference (EMI) intensity. Furthermore, a larger loop area results in a longer crosstalk coupling path and poorer signal integrity. Therefore, in this step, to reduce the current loop area, decrease EMI interference, suppress crosstalk, and improve signal transmission stability, a small number of vias are used between conductors on the top layer of the PCB and in sub-layers adjacent to the top layer (such as the first and second sub-layers) to connect the voltage source and the corresponding pins of the driver chip. These vias are only located on the top layer and adjacent sub-layers within the first region.

[0024] S030. The conductors are spaced apart in the bottom layer of the PCB board and the sub-layer near the bottom layer of the PCB board to form a mutual inductance structure.

[0025] Specifically, in this step, parallel conductors need to be laid out in the bottom layer and sublayers near the bottom layer of the PCB board according to the mutual inductance effect to reduce parasitic inductance. In the first region, each sublayer does not include signal lines, and the sublayers in the first region are designed with the sublayer containing the ground line as the reference layer. The top layer of the PCB board in the first region is the power layer (i.e., positive and negative lines) and the ground layer. The middle sublayer of the PCB board is set with a ground line as a reference, and the sublayers between the top and bottom layers are set with the sublayer containing the ground line as the reference. Within each sublayer between the top and bottom layers, positive and negative lines are arranged alternately to form a mutual inductance structure.

[0026] Taking a four-layer PCB as an example, in this embodiment, within the first region of the PCB, the first sub-layer (i.e., the top layer) has a positive and / or negative line, the second sub-layer is a ground, the third sub-layer has a positive line, and the fourth sub-layer (i.e., the bottom layer) has a negative line. Within the second region of the PCB, the first sub-layer has a ground signal line and / or a positive and / or negative line, the second sub-layer is a signal line, the third sub-layer has a negative line, and the fourth sub-layer has a positive line. The sub-layers containing the positive and negative lines can be interchanged. With this arrangement, regardless of whether it's the first or second region, the corresponding areas within the top layer of the PCB and its adjacent sub-layers have complete lines (i.e., positive and negative lines) or signal line planes as their return paths, thus forming a natural parallel plate capacitor directly beneath it, thereby minimizing the loop area for high-frequency current.

[0027] Furthermore, in this embodiment, the spacing between the conductors is fixed at 0.75 mm. In other embodiments, the spacing between the conductors is 0.5 mm, 1 mm, or any value between 0.5 mm and 1 mm. The conductors are arranged closely parallel to each other at the above spacing in the bottom layer of the PCB and the sublayers near the bottom layer, thus forming a "pseudo-differential pair" structure. When the drive current changes rapidly, the induced noise voltage generated on this pair of traces can cancel each other out, ensuring a purer actual drive voltage applied between the gate and source terminals of the SiC device, reducing ringing and voltage spikes. Within each sublayer of the PCB, there is only one junction point between the power ground and the drive power ground, and this junction point is located near the source return pin of the driver chip to avoid forming a large ground loop and prevent noise from the power ground from directly coupling into the sensitive drive circuit.

[0028] S040. After the wiring is completed, copper pouring is performed on the PCB board.

[0029] Specifically, in this step, after completing the routing, copper plating is required for each sub-layer within the PCB board to form a heat dissipation structure. The top and bottom copper layers have the same thickness, and the copper layer thickness on each sub-layer between the top and bottom layers is also equal. The copper layer thickness on the top layer is greater than the copper layer thickness between the top and bottom layers. Furthermore, throughout the copper plating process, the thickness of the prepreg is greater than the thickness of the core board, and the core board thickness decreases from the layer closest to the top layer to the layer closest to the bottom layer.

[0030] In summary, this invention improves system performance and reliability by optimizing the PCB layout without adding additional negative voltage power chips or passive components, and makes the entire PCB board more robust.

[0031] The foregoing has described specific embodiments of the invention. Other embodiments are within the scope of the appended claims.

[0032] The terms “exemplary,” “example,” etc., used throughout this specification mean “serving as an example, instance, or illustration” and do not imply “preferred” or “advantageous” than other embodiments. Detailed descriptions are included for the purpose of providing an understanding of the described techniques. However, these techniques can be practiced without these detailed descriptions. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0033] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.

[0034] The foregoing description of this specification is provided to enable any person skilled in the art to implement or use the content of this specification. Various modifications to the content of this specification will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of protection of this specification. Therefore, this specification is not limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A PCB layout method for suppressing crosstalk in silicon carbide device drivers, characterized in that, include: The PCB board is divided into a first region and a second region, and each component is placed on the surface of the PCB board. The PCB board is layered, and driving circuits and switching circuits are respectively provided in each sub-layer of the PCB board in the first region and the second region; The conductors are arranged in the top layer of the PCB board and in the sub-layers near the top layer of the PCB board according to the principle of minimizing the reflow area; The conductors are spaced apart in the bottom layer of the PCB board and the sub-layer near the bottom layer of the PCB board to form a mutual inductance structure; After the wiring is completed, copper plating is performed on the PCB board.

2. The PCB layout method for suppressing crosstalk in silicon carbide device drivers according to claim 1, characterized in that, The conductors include: a positive wire, a negative wire, a ground wire, and a signal wire, and each sub-layer contains at least one of the positive wire, the negative wire, the ground wire, and the signal wire; In the first region, each sub-layer is isolated by taking the sub-layer where the ground wire is located as the reference layer, and the positive wire and the negative wire are arranged alternately in each sub-layer; in the second region, the signal line in each sub-layer is located between the positive wire and the negative wire.

3. The PCB layout method for suppressing crosstalk in silicon carbide device drivers according to claim 2, characterized in that, In the mutual inductance structure, adjacent conductors are parallel to each other and the spacing between adjacent conductors is fixed.

4. A PCB layout method for suppressing drive crosstalk of silicon carbide devices according to claim 3, characterized in that, During the copper plating process, a copper layer is laid on the surface of each sub-layer, and the copper layer on the top layer of the PCB board and the copper layer on the bottom layer of the PCB board have the same thickness, the copper layer between the top layer and the bottom layer has the same thickness, and the copper layer on the top layer has a greater thickness than the copper layer between the top layer and the bottom layer.

5. A PCB layout method for suppressing drive crosstalk of silicon carbide devices according to claim 4, characterized in that, In each of the sub-layers within the PCB board, there is only one junction between the power ground and the drive power ground.

6. A PCB layout method for suppressing crosstalk in silicon carbide device drivers according to claim 3, characterized in that, Within each of the sub-layers, the spacing between the conductors is 0.5 mm to 1 mm.

7. A PCB layout method for suppressing crosstalk in silicon carbide device drivers according to claim 3, characterized in that, Within the first region, through-holes are provided in the sub-layer where the driving circuit is located.

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