Semiconductor structure and preparation method thereof
By introducing cut-off trenches and anti-diffusion regions into the semiconductor structure, and using carbon ion and fluorine ion implantation to prevent the diffusion of dopant ions, the problem of lateral diffusion of dopant atoms in semiconductor devices is solved, improving device performance and yield, and reducing process costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-14
AI Technical Summary
In semiconductor devices, as integration density increases, the distance between P-type doped regions and N-type doped regions decreases. Doped atoms or doped ions are prone to lateral diffusion during high-temperature annealing, leading to performance deviations in adjacent devices, such as causing data retention failure in SRAM.
Introducing cut-off trenches and anti-diffusion regions into semiconductor structures, and forming anti-diffusion regions by ion implantation within the trench isolation structure to prevent the lateral diffusion of doped ions, using carbon ions and/or fluorine ions as anti-diffusion ions, avoids the need for additional mask templates and simplifies the process.
It effectively prevents the lateral diffusion of doped ions, improves the design window and product yield of semiconductor devices such as SRAM, and reduces process costs.
Smart Images
Figure CN121865608A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of semiconductor manufacturing technology, the integration requirements for semiconductor devices (such as Static Random Access Memory (SRAM)) are becoming increasingly stringent, and the dimensions of semiconductor processes are shrinking. Consequently, the distance between the P-type and N-type doped regions of semiconductor devices is also decreasing. This makes it easier for dopant atoms or ions in the P-type and / or N-type doped regions to laterally diffuse beyond the trench isolation structure during high-temperature annealing. This lateral diffusion of dopant atoms or ions can easily lead to performance shifts in adjacent devices within adjacent P-type and N-type doped regions. For example, in SRAM, the threshold voltage (Vt) of adjacent MOS transistors within adjacent P-type and N-type doped regions shifts, reducing the static noise margin (SNM) and thus increasing the likelihood of data retention failure. Summary of the Invention
[0003] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of lateral diffusion of doped atoms or doped ions in the prior art.
[0004] A semiconductor structure, comprising:
[0005] The substrate includes a first device region and a second device region, wherein the first device region is a doped region of a second conductivity type and the second device region is a doped region of a first conductivity type, and the first conductivity type and the second conductivity type are opposite.
[0006] A trench isolation structure is located within the substrate and isolates the substrate into multiple active regions, the multiple active regions including a first active region and a second active region, the first active region being located in the first device region and the second active region being located in the second device region;
[0007] A gate line is located on one side of the substrate, and the orthogonal projection of the gate line on the substrate passes through the first active region and the second active region;
[0008] Multiple cut-off trenches cut the gate line into multiple gates, and the multiple cut-off trenches include a first cut-off trench, which is located between adjacent first active regions and second active regions of adjacent first device regions and second device regions;
[0009] The first anti-diffusion zone is located within the trench isolation structure and is positioned opposite to the first cutting groove.
[0010] In one embodiment, the plurality of cutting trenches further includes a second cutting trench; the second cutting trench is located within a first device region and between adjacent first active regions; and / or, the second cutting trench is located within a second device region and between adjacent second active regions;
[0011] The second anti-diffusion zone is located within the trench isolation structure and is positioned opposite to the second cutting groove.
[0012] In one embodiment, the semiconductor structure further includes a gate dielectric layer located on the side of the gate line near the substrate and covering the substrate and the trench isolation structure, wherein the cut-off trench extends through the gate dielectric layer.
[0013] In one embodiment, the doping ions in the first diffusion-blocking region include carbon ions and / or fluorine ions.
[0014] The aforementioned semiconductor structure includes a first cut-off trench and a first anti-diffusion region. The first cut-off trench is located between adjacent first and second active regions of adjacent first and second device regions, thereby cutting off different transistors within adjacent first and second device regions. The first anti-diffusion region is disposed opposite to the first cut-off trench. Therefore, during the formation of the first cut-off trench, ion implantation can be performed on the trench isolation structure opposite to the first cut-off trench to form the first anti-diffusion region, which is located between adjacent first and second active regions of adjacent first and second device regions. Therefore, the first anti-diffusion region can effectively prevent the lateral diffusion of dopant ions (such as boron (B) ions) or dopant atoms in the first and / or second device regions, thereby increasing the design window of semiconductor devices such as SRAM and improving product yield and reliability.
[0015] A method for fabricating a semiconductor structure, comprising:
[0016] A substrate is provided, the substrate including a first device region and a second device region; the first device region is a doped region of a second conductivity type, the second device region is a doped region of a first conductivity type, and the first conductivity type and the second conductivity type are opposite;
[0017] A trench isolation structure is formed in the substrate, the trench isolation structure isolating the substrate into multiple active regions, the multiple active regions including a first active region and a second active region, the first active region being located in the first device region, and the second active region being located in the second device region;
[0018] An initial gate line is formed on one side of the substrate, and the orthographic projection of the initial gate line on the substrate passes through the first active region and the second active region;
[0019] The initial gate line is etched to form a first initial trench, the depth of which is less than the thickness of the initial gate line, and the first initial trench is located between adjacent first active regions and second active regions of adjacent first device regions and second device regions.
[0020] From the first initial groove, anti-diffusion ion implantation is performed on the trench isolation structure to form a first anti-diffusion region;
[0021] From the first initial groove, the initial gate line is etched further to form the first cut-off groove.
[0022] In one embodiment, while etching the initial gate line to form a first initial trench, the initial gate line is also etched to form a second initial trench, the depth of the second initial trench being less than the thickness of the initial gate line, and the second initial trench being located within a first device region and between adjacent first active regions; and / or, the second initial trench being located within a second device region and between adjacent second active regions;
[0023] From the first initial groove, anti-diffusion ion implantation is performed on the trench isolation structure to form a first anti-diffusion region. At the same time, anti-diffusion ion implantation is also performed on the trench isolation structure from the second initial groove to form a second anti-diffusion region.
[0024] While etching the initial gate line from the first initial groove to form the first cut-off groove, etching the initial gate line from the second initial groove to form the second cut-off groove is also continued.
[0025] In one embodiment, before forming the initial gate line on one side of the substrate, the method further includes:
[0026] A gate dielectric material layer is formed covering the substrate and the trench isolation structure;
[0027] The step of continuing to etch the initial gate line from the first initial groove to form the first cut-off groove includes:
[0028] The initial gate line and the gate dielectric material layer are etched sequentially to form a first cut-off groove. The remaining gate dielectric material layer forms a gate dielectric layer. The first cut-off groove penetrates the gate dielectric layer to expose the first anti-diffusion region.
[0029] In one embodiment, before etching the initial gate line to form the first initial trench, the method further includes:
[0030] A patterned mask layer is formed on the side of the initial gate line away from the substrate;
[0031] The etching of the initial gate line to form the first initial groove includes:
[0032] Based on the patterned mask layer, the initial gate lines are etched to form a first initial groove.
[0033] In one embodiment, before forming a patterned mask layer on the side of the initial gate line away from the substrate, the process includes:
[0034] Form a stress-buffering material layer covering the initial gate lines;
[0035] Before etching the initial gate lines based on the patterned mask layer to form the first initial trench, the method further includes:
[0036] Based on the patterned mask layer, the stress buffer material layer is etched to form a stress buffer layer.
[0037] In one embodiment, the anti-diffusion ions include carbon ions and / or fluorine ions.
[0038] In the above-described semiconductor structure fabrication method, during the formation of a first cut-off trench that severs different transistors within adjacent first and second device regions, ion implantation is performed on the trench isolation structure opposite the first cut-off trench to form a first anti-diffusion region. Therefore, the first anti-diffusion region is located between adjacent first and second active regions of adjacent first and second device regions. Thus, the first anti-diffusion region can effectively prevent the lateral diffusion of dopant ions (such as boron (B) ions) or dopant atoms in the first and / or second device regions, thereby increasing the design window for semiconductor devices such as SRAM and improving product yield and reliability.
[0039] Furthermore, during the formation of the first cutting groove, a first anti-diffusion zone is formed, thus eliminating the need for additional mask templates and reducing process costs.
[0040] Simultaneously, a portion of the initial gate line thickness is first etched to form a first initial trench. Then, ion implantation is performed on the trench isolation structure based on the first initial trench to form a first anti-diffusion region. After forming the first anti-diffusion region, the initial gate line below the first initial trench is etched to form a first cut-off trench. At this point, during the anti-diffusion ion implantation process, the initial gate line retained below the first initial trench can protect the trench isolation structure within the substrate, preventing damage to the trench isolation structure during ion implantation. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0043] Figure 2 This is a partial top view of the structure obtained during the fabrication process of the semiconductor structure provided in one embodiment;
[0044] Figures 3 to 8 This is a partial cross-sectional schematic diagram of the structure obtained in different steps of the semiconductor structure fabrication process provided in one embodiment;
[0045] Figure 9 This is a partial top view of a semiconductor structure provided in one embodiment.
[0046] Explanation of reference numerals in the attached figures:
[0047] 110 - First device region, 111 - First active region, 120 - Second device region, 121 - Second active region, 200 - Trench isolation structure, 210 - First anti-diffusion region, 300a - Initial gate line, 300 - Gate line, 400a - Gate dielectric material layer, 400 - Gate dielectric layer, 500a - Mask material layer, 500 - Patterned mask layer, 600 - Patterned photoresist, 700a - Stress buffer material layer, 700 - Stress buffer layer, 10a - First initial trench, 10 - First cut trench, 20 - Second cut trench. Detailed Implementation
[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0050] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0051] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0052] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0053] In one embodiment, see Figure 1 A method for fabricating a semiconductor structure is provided, comprising the following steps:
[0054] Step S10, please refer to Figure 2A substrate is provided, the substrate including a first device region 110 and a second device region 120; the first device region 110 is a doped region of a second conductivity type, and the second device region 120 is a doped region of a first conductivity type, wherein the first conductivity type and the second conductivity type are opposite.
[0055] For step S20, please refer to... Figure 2 A trench isolation structure 200 is formed in the substrate, and the trench isolation structure 200 isolates the substrate into multiple active regions, including a first active region 111 and a second active region 121. The first active region 111 is located in the first device region 110, and the second active region 121 is located in the second device region 120.
[0056] For step S40, please refer to... Figure 2 An initial gate line 300a is formed on one side of the substrate, and the orthogonal projection of the initial gate line 300a on the substrate passes through the first active region 111 and the second active region 121.
[0057] For step S60, please refer to... Figure 5 The initial gate line 300a is etched to form the first initial trench 10a. The depth of the first initial trench 10a is less than the thickness of the initial gate line 300a, and the first initial trench 10a is located between the adjacent first active region 111 and the second active region 121 of the adjacent first device region 110 and the second device region 120.
[0058] For step S70, please refer to... Figure 6 as well as Figure 7 Starting from the first initial trench 10a, anti-diffusion ion implantation is performed on the trench isolation structure 200 to form the first anti-diffusion region 210;
[0059] For step S80, please refer to... Figure 8 From the first initial groove 10a, the initial gate line 300a is etched to form the first cut-off groove 10.
[0060] In step S10, please refer to Figure 2 First, a raw semiconductor substrate can be provided. Then, dopant ions or dopant atoms of different conductivity types are implanted into different regions of the raw semiconductor substrate to form a substrate including a first device region 110 and a second device region 120.
[0061] The original semiconductor substrate can be a single-layer structure or a multi-layer structure. For example, the semiconductor substrate may include silicon (Si) substrates, silicon-germanium (SiGe) substrates, silicon-germanium-carbon (SiGeC) substrates, silicon carbide (SiC) substrates, gallium arsenide (GaAs) substrates, indium arsenide (InAs) substrates, indium phosphide (InP) substrates, or other III / V or II / VI semiconductor substrates. Alternatively, the semiconductor substrate may also include substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.
[0062] The first device region 110 is a doped region of the second conductivity type, and the second device region 120 is a doped region of the first conductivity type, with the first conductivity type and the second conductivity type being opposite.
[0063] For example, if the first conductivity type is N-type and the second conductivity type is P-type, then the first device region 110 is a P-type doped region and the second device region 120 is an N-type doped region. In this case, the first device region 110 can be an N-type transistor region (such as an NMOS region), and the second device region 120 can be a P-type transistor region (such as a PMOS region).
[0064] For example, if the first conductivity type is P-type and the second conductivity type is N-type, then the first device region 110 is an N-type doped region and the second device region 120 is a P-type doped region. In this case, the first device region 110 can be a P-type transistor region (such as an NMOS region), and the second device region 120 can be an N-type transistor region (such as a PMOS region).
[0065] In step S20, please refer to Figure 2 First, trenches can be formed within the substrate. Then, insulating material is filled into the trenches to form a trench isolation structure 200. Exemplarily, the trench isolation structure 200 can be a shallow trench isolation structure 200.
[0066] The trench isolation structure 200 can isolate the first device region 110 into a plurality of first active regions 111 having a second conductivity type, and at the same time isolate the second device region 120 into a plurality of second active regions 121 having a first conductivity type.
[0067] In step S40, please refer to Figure 2 First, a gate line material layer can be formed. Then, the gate line material layer is etched using a photolithography process to form multiple initial gate lines 300a.
[0068] For example, the material of the initial gate line 300a includes polycrystalline silicon.
[0069] For example, the first device region 110 and the second device region 120 are arranged along a first direction. A plurality of initial gate lines 300a may be arranged along a second direction, and each initial gate line 300a may extend along the first direction. The first direction and the second direction intersect, and both are perpendicular to the thickness direction of the substrate. For example, the first direction is perpendicular to the second direction.
[0070] In step S60, please refer to Figure 5 When etching the initial gate line 300a to form the first initial groove 10a, the initial gate line 300a is not etched through, so that the depth of the first initial groove 10a is less than the thickness of the initial gate line 300a. At this time, a portion of the initial gate line 300a is still retained below the first initial groove 10a.
[0071] For example, the initial gate line 300a can be dry etched to effectively control the size of the first initial trench 10a.
[0072] Of course, when forming the first initial groove 10a, the etching method for the initial gate line 300a is not limited to dry etching. For example, the initial gate line 300a can also be etched by wet etching.
[0073] In step S70, please refer to Figure 6 as well as Figure 7 When anti-diffusion ion implantation is performed on the trench isolation structure 200 from the first initial trench 10a, the initial gate line 300a retained below the first initial trench 10a can protect the trench isolation structure 200 in the substrate and prevent the trench isolation structure 200 from being damaged during ion implantation.
[0074] Meanwhile, by way of example, the anti-diffusion ions injected into the trench isolation structure 200 include carbon ions and / or fluorine ions.
[0075] For example, the trench isolation structure 200 can be co-implanted with carbon ions and fluorine ions to form a first diffusion-blocking region 210. The first diffusion-blocking region 210 can enhance the diffusion blocking effect through the synergistic effect of multiple defects, thereby suppressing the diffusion of dopant ions or dopant atoms in the first device region 110 and / or the second device region 120.
[0076] For example, the implantation energy of carbon ions can be from 10 keV to 12 keV, and the implantation dose can be from 3E+14 ions / cm² to 3E+14 ions / cm². The implantation energy of fluoride ions can be from 8 keV to 11 keV, and the implantation dose can be from 1E+15 ions / cm² to 1.5E+15 ions / cm².
[0077] In step S80, please refer to Figure 8 as well as Figure 9 After further etching of the initial gate line 300a, the initial gate line 300a located below the first initial trench 10a can be removed, thereby forming the first cut-off trench 10. At this time, the etching method for further etching of the initial gate line 300a can be, but is not limited to, dry etching; for example, the etching method can also be wet etching.
[0078] After etching to form the first cut-off groove 10, the first cut-off groove 10 can isolate the initial gate line 300a, thereby cutting off the gates of different transistors formed in adjacent first device regions 110 and second device regions 120, thereby cutting off different transistors of different conductivity types formed in adjacent first device regions 110 and second device regions 120.
[0079] In this embodiment, during the formation of the first cut-off trench 10 that cuts off different transistors in adjacent first device regions 110 and second device regions 120, ion implantation is performed on the trench isolation structure 200 opposite to the first cut-off trench 10 to form a first anti-diffusion region 210. Therefore, the first anti-diffusion region 210 is located between adjacent first active regions 111 and second active regions 121 of adjacent first device regions 110 and second device regions 120. Thus, the first anti-diffusion region 210 can effectively prevent the lateral diffusion of dopant ions (such as boron (B) ions) or dopant atoms in the first device region 110 and / or the second device region 120, thereby increasing the design window for semiconductor devices such as SRAM and improving product yield and reliability.
[0080] Furthermore, in this embodiment, a first anti-diffusion zone 210 is formed during the formation of the first cutting groove 10, thereby eliminating the need for additional mask templates and thus reducing process costs.
[0081] In this embodiment, a portion of the initial gate line 300a is first etched to form a first initial trench 10a. Then, ion implantation is performed on the trench isolation structure 200 based on the first initial trench 10a to form a first anti-diffusion region 210. After forming the first anti-diffusion region 210, the initial gate line 300a below the first initial trench 10a is etched to form a first cut-off trench 10. During the anti-diffusion ion implantation process, the initial gate line 300a retained below the first initial trench 10a can protect the trench isolation structure 200 within the substrate, preventing damage to the trench isolation structure 200 during ion implantation.
[0082] In one embodiment, in step S60, while etching the initial gate line 300a to form the first initial trench 10a, the initial gate line 300a is also etched to form a second initial trench. The depth of the second initial trench is less than the thickness of the initial gate line 300a. The second initial trench is located within the first device region 110 and between adjacent first active regions 111. And / or, the second initial trench is located within the second device region 120 and between adjacent second active regions 121.
[0083] That is, the first initial trench 10a and the second initial trench are etched and formed simultaneously in the same etching process. For example, the second initial trench and the first initial trench 10a have the same or nearly the same etching depth. In this case, the first initial trench 10a and the second initial trench are etched and formed using a conventional photolithography process with a photomask, thus simplifying the etching process. Of course, in some cases, the second initial trench and the first initial trench 10a can also be etched and formed to different depths using a photolithography process with a halftone photomask, etc., and this is not limited here.
[0084] Furthermore, in step S70, while performing anti-diffusion ion implantation on the trench isolation structure 200 from the first initial trench 10a to form the first anti-diffusion region 210, anti-diffusion ion implantation is also performed on the trench isolation structure 200 from the second initial trench to form the second anti-diffusion region.
[0085] At this time, the second anti-diffusion region and the first anti-diffusion region 210 are formed in the same anti-diffusion ion implantation process, so that they can be doped with the same anti-diffusion ions.
[0086] In step S80, while etching continues on the initial gate line 300a from the first initial trench 10a to form the first cut-off trench 10, etching also continues on the initial gate line 300a from the second initial trench to form the second cut-off trench 20 (see [link]). Figure 9 ).
[0087] After further etching of the initial gate line 300a to form the first cut trench 10 and the second cut trench 20, the remaining initial gate line 300a can form multiple gate lines 300. The same gate line 300 can be cut into multiple gates by at least one first cut trench 10 and / or the second cut trench 20. That is, both the second cut trench 20 and the first cut trench 10 are cut trenches, both used to cut the gate line 300 to form the gates of different transistors. It is understood that in this document, "multiple" means two or more.
[0088] The second cut-off groove 20 is formed based on the etching of the second initial groove. Therefore, the second cut-off groove 20 is located within the first device region 110 and between adjacent first active regions 111, thereby enabling the cutting off of different transistors of the same conductivity type within the first device region 110. And / or, the second cut-off groove 20 is located within the second device region 120 and between adjacent second active regions 121, thereby enabling the cutting off of different transistors of the same conductivity type within the second device region 120.
[0089] In this embodiment, the second cutting groove 20 that cuts different transistors in the same device region and the first cutting groove 10 that cuts different transistors in different device regions can be processed and formed simultaneously, thereby effectively simplifying the process.
[0090] At the same time, a diffusion prevention region (second diffusion prevention region) is also formed between different transistors in the same device region, so that different transistors in the same device region do not affect each other.
[0091] Of course, in other embodiments, the second cutting groove 20 and the first cutting groove 10 may be formed asynchronously. The second anti-diffusion region may not be formed within the trench isolation structure 200 under the second cutting groove 20, thereby preventing doped anti-diffusion ions from affecting device performance. Alternatively, in other embodiments, the second cutting groove 20 may not be formed. This application does not impose any limitations on this.
[0092] In one embodiment, see Figure 3 Before step S40, the following are included:
[0093] Step S30: Form a gate dielectric material layer 400a covering the substrate and the trench isolation structure 200.
[0094] A gate dielectric material layer 400a covering the substrate and the trench isolation structure 200 can be formed by a deposition process. For example, the material of the gate dielectric material layer 400a may include silicon oxide, etc.
[0095] Step S80 includes:
[0096] Step S81, please refer to Figure 8 The initial gate line 300a and the gate dielectric material layer 400a are etched sequentially to form the first cut-off groove 10. The remaining gate dielectric material layer 400a forms the gate dielectric layer 400. The first cut-off groove 10 penetrates the gate dielectric layer 400 and exposes the first anti-diffusion region 210.
[0097] For example, in step S81, the initial gate line 300a and the gate dielectric material layer 400a may also be etched sequentially to simultaneously form the first cut-off groove 10 and the second cut-off groove 20. Both the first cut-off groove 10 and the second cut-off groove 20 are cut-off trenches.
[0098] In this embodiment, both the initial gate line 300a and the gate dielectric material layer 400a are etched. This ensures that the initial gate line 300a can be sufficiently etched in the actual process, thereby ensuring that the cut trench (including the first cut trench 10) can completely cut off the initial gate line 300a. In other words, it ensures that each gate of the final gate line 300 can be effectively isolated.
[0099] Meanwhile, the thickness of the gate dielectric material layer 400a is usually small. At this time, setting both the initial gate line 300a and the gate dielectric material layer 400a to be etched can effectively reduce the etching accuracy requirements of the etching process, thereby reducing the process difficulty.
[0100] Of course, in some embodiments, in step S80, when forming the first cut-off groove 10 (or simultaneously forming the first cut-off groove 10 and the second cut-off groove 20), only the initial gate line 300a may be etched, without etching the gate dielectric material layer 400a. This application does not impose any limitations on this.
[0101] In one embodiment, prior to step S60, the method further includes:
[0102] Step S52: A patterned mask layer 500 is formed on the side of the initial gate line 300a away from the substrate.
[0103] Please see Figure 3 , Figure 4 as well as Figure 5 First, a mask material layer 500a can be formed. Then, a patterned photoresist 600 is formed on the mask material layer 500a. Afterward, the mask material layer 500a is etched based on the patterned photoresist 600, thereby forming the patterned mask layer 500.
[0104] For example, the material of the mask layer includes, but is not limited to, silicon nitride.
[0105] Step S60 includes:
[0106] Step S62, please refer to Figure 5 Based on the patterned mask layer 500, initial gate lines 300a are etched to form the first initial groove 10a.
[0107] After etching to form the first initial trench 10a, the remaining patterned mask layer 500 can serve as an implantation barrier layer when performing anti-diffusion ion implantation on the trench isolation structure 200 from the first initial trench 10a in step S70.
[0108] For example, prior to step S62, the following may also be included:
[0109] Step S611: Remove the patterned photoresist 600.
[0110] In one embodiment, before step S52, the following is also included:
[0111] For step S51, please refer to... Figure 3 A stress-reducing material layer 700a is formed covering the initial gate line 300a.
[0112] Simultaneously, before subsequent step S62, which involves etching the initial gate line 300a based on the patterned mask layer 500 to form the first initial trench 10a, may further include:
[0113] For step S612, please refer to... Figure 5 Based on the patterned mask layer 500, the stress buffer material layer 700a is etched to form the stress buffer layer 700.
[0114] In this embodiment, before forming the patterned mask layer 500, a stress buffer material layer 700a is first formed, so that the subsequent mask material layer 500a can be formed on the stress buffer material layer 700a, thereby effectively relieving the stress between the mask material layer 500a and the initial gate line 300a.
[0115] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.
[0116] In one embodiment, a semiconductor structure is also provided, which can be formed by, but is not limited to, the semiconductor structure preparation method described above.
[0117] Please see Figure 9 as well as Figure 8 The semiconductor structure includes a substrate, a trench isolation structure 200, a gate line 300, multiple cut-off trenches, and a first anti-diffusion region 210.
[0118] The substrate includes a first device region 110 and a second device region 120. The first device region 110 is a doped region of the second conductivity type, and the second device region 120 is a doped region of the first conductivity type, with the first conductivity type and the second conductivity type being opposite.
[0119] For example, if the first conductivity type is N-type and the second conductivity type is P-type, then the first device region 110 is a P-type doped region and the second device region 120 is an N-type doped region. In this case, the first device region 110 can be an N-type transistor region (such as an NMOS region), and the second device region 120 can be a P-type transistor region (such as a PMOS region).
[0120] For example, if the first conductivity type is P-type and the second conductivity type is N-type, then the first device region 110 is an N-type doped region and the second device region 120 is a P-type doped region. In this case, the first device region 110 can be a P-type transistor region (such as an NMOS region), and the second device region 120 can be an N-type transistor region (such as a PMOS region).
[0121] The trench isolation structure 200 is located within the substrate. Exemplarily, the trench isolation structure 200 may be a shallow trench isolation structure 200.
[0122] The trench isolation structure 200 isolates the substrate into multiple active regions. The multiple active regions include a first active region 111 and a second active region 121, with the first active region 111 located in the first device region 110 and the second active region 121 located in the second device region 120.
[0123] For example, the trench isolation structure 200 can isolate the first device region 110 into a plurality of first active regions 111 having a second conductivity type, while isolating the second device region 120 into a plurality of second active regions 121 having a first conductivity type.
[0124] The gate line 300 is located on one side of the substrate, and the orthogonal projection of the gate line 300 on the substrate passes through the first active region 111 and the second active region 121.
[0125] For example, the material of the gate line 300 includes polycrystalline silicon.
[0126] Multiple cut trenches cut the gate line 300 into multiple gates.
[0127] For example, the first device region 110 and the second device region 120 are arranged along a first direction. A plurality of gate lines 300 may be arranged along a second direction, and the same gate line 300 may be cut into a plurality of gates arranged along the first direction by a corresponding cut trench. The first direction and the second direction intersect, and both are perpendicular to the thickness direction of the substrate. For example, the first direction and the second direction are perpendicular. It is understood that, herein, "a plurality of" means two or more.
[0128] The plurality of cutting grooves includes a first cutting groove 10. The first cutting groove 10 is located between adjacent first active regions 111 and second active regions 121 of adjacent first device regions 110 and second device regions 120.
[0129] The first anti-diffusion zone 210 is located within the trench isolation structure 200 and is positioned opposite to the first cutting groove 10, thus also located between the adjacent first active region 111 and the second active region 121 of the adjacent first device region 110 and the second device region 120.
[0130] The first anti-diffusion region 210 can enhance the diffusion blocking effect through the synergistic effect of multiple defects, thereby suppressing the diffusion of dopant ions or dopant atoms in the first device region 110 and / or the second device region 120.
[0131] For example, the doped ions of the first diffusion-blocking region 210 include carbon ions and / or fluorine ions.
[0132] In this embodiment, the semiconductor structure includes a first cut-off trench 10 and a first anti-diffusion region 210. The first cut-off trench 10 is located between adjacent first active regions 111 and second active regions 121 of adjacent first device regions 110 and second device regions 120, thereby cutting off different transistors within adjacent first device regions 110 and second device regions 120. The first anti-diffusion region 210 is disposed opposite to the first cut-off trench 10. Therefore, during the formation of the first cut-off trench 10, ion implantation can be performed on the trench isolation structure 200 opposite to the first cut-off trench 10 to form the first anti-diffusion region 210, and the first anti-diffusion region 210 is located between adjacent first active regions 111 and second active regions 121 of adjacent first device regions 110 and second device regions 120. Therefore, the first anti-diffusion region 210 can effectively prevent the lateral diffusion of dopant ions (such as boron (B) ions) or dopant atoms in the first device region 110 and / or the second device region 120, thereby increasing the design window of semiconductor devices such as SRAM and improving product yield and reliability.
[0133] In one embodiment, the plurality of cutting grooves further includes a second cutting groove 20.
[0134] The second cut-off groove 20 is located within the first device region 110 and between adjacent first active regions 111, thereby cutting off different transistors of the same conductivity type within the first device region 110. And / or, the second cut-off groove 20 is located within the second device region 120 and between adjacent second active regions 121, thereby cutting off different transistors of the same conductivity type within the second device region 120.
[0135] In this embodiment, an anti-diffusion region (second anti-diffusion region) is also formed between different transistors in the same device region, so that different transistors in the same device region do not affect each other.
[0136] Of course, in other embodiments, the trench isolation structure 200 under the second cutting groove 20 may not have a second anti-diffusion region, thereby preventing doped anti-diffusion ions from affecting device performance. This application does not impose any limitations on this.
[0137] In one embodiment, the semiconductor structure further includes a gate dielectric layer 400.
[0138] The gate dielectric layer 400 is located on the side of the gate line 300 closest to the substrate. The gate dielectric layer 400 covers the substrate and the trench isolation structure 200. The cut trench (including the first cut trench 10 and / or the second cut trench 20) also extends through the gate dielectric layer 400.
[0139] For example, the first cut-off groove 10 penetrates the gate line 300 and the gate dielectric layer 400 to expose the first anti-diffusion region 210.
[0140] For example, the second cut-off groove 20 penetrates the gate line 300 and the gate dielectric layer 400 to expose the second anti-diffusion region.
[0141] For example, the first cut-off groove 10 penetrates the gate line 300 and the gate dielectric layer 400 to expose the first anti-diffusion region 210. And the second cut-off groove 20 penetrates the gate line 300 and the gate dielectric layer 400 to expose the second anti-diffusion region.
[0142] In this embodiment, it can be ensured that the cutting trench can effectively isolate each gate of the gate line 300.
[0143] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0145] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a first device region and a second device region, wherein the first device region is a doped region of a second conductivity type and the second device region is a doped region of a first conductivity type, and the first conductivity type and the second conductivity type are opposite. A trench isolation structure is located within the substrate and isolates the substrate into multiple active regions, the multiple active regions including a first active region and a second active region, the first active region being located in the first device region and the second active region being located in the second device region; A gate line is located on one side of the substrate, and the orthogonal projection of the gate line on the substrate passes through the first active region and the second active region; Multiple cut-off trenches cut the gate line into multiple gates, and the multiple cut-off trenches include a first cut-off trench, which is located between adjacent first active regions and second active regions of adjacent first device regions and second device regions; The first anti-diffusion zone is located within the trench isolation structure and is positioned opposite to the first cutting groove.
2. The semiconductor structure according to claim 1, characterized in that, The plurality of cutting trenches further includes a second cutting trench; the second cutting trench is located within the first device region and between adjacent first active regions; and / or, the second cutting trench is located within the second device region and between adjacent second active regions; The second anti-diffusion zone is located within the trench isolation structure and is positioned opposite to the second cutting groove.
3. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor structure further includes a gate dielectric layer located on the side of the gate line near the substrate and covering the substrate and the trench isolation structure, wherein the cut-off trench extends through the gate dielectric layer.
4. The semiconductor structure according to claim 1, characterized in that, The doped ions in the first diffusion-blocking region include carbon ions and / or fluorine ions.
5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region; The first device region is a doped region of the second conductivity type, and the second device region is a doped region of the first conductivity type, wherein the first conductivity type and the second conductivity type are opposite; A trench isolation structure is formed in the substrate, the trench isolation structure isolating the substrate into multiple active regions, the multiple active regions including a first active region and a second active region, the first active region being located in the first device region, and the second active region being located in the second device region; An initial gate line is formed on one side of the substrate, and the orthographic projection of the initial gate line on the substrate passes through the first active region and the second active region; The initial gate line is etched to form a first initial trench, the depth of which is less than the thickness of the initial gate line, and the first initial trench is located between adjacent first active regions and second active regions of adjacent first device regions and second device regions. From the first initial groove, anti-diffusion ion implantation is performed on the trench isolation structure to form a first anti-diffusion region; From the first initial groove, the initial gate line is etched further to form the first cut-off groove.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, While etching the initial gate line to form a first initial trench, the initial gate line is also etched to form a second initial trench. The depth of the second initial trench is less than the thickness of the initial gate line, and the second initial trench is located within a first device region and between adjacent first active regions; and / or, the second initial trench is located within a second device region and between adjacent second active regions. From the first initial groove, anti-diffusion ion implantation is performed on the trench isolation structure to form a first anti-diffusion region. At the same time, anti-diffusion ion implantation is also performed on the trench isolation structure from the second initial groove to form a second anti-diffusion region. While etching the initial gate line from the first initial groove to form the first cut-off groove, etching the initial gate line from the second initial groove to form the second cut-off groove is also continued.
7. The method for preparing a semiconductor structure according to claim 5, characterized in that, Before forming the initial gate line on one side of the substrate, the method further includes: A gate dielectric material layer is formed covering the substrate and the trench isolation structure; The step of continuing to etch the initial gate line from the first initial groove to form the first cut-off groove includes: The initial gate line and the gate dielectric material layer are etched sequentially to form a first cut-off groove. The remaining gate dielectric material layer forms a gate dielectric layer. The first cut-off groove penetrates the gate dielectric layer to expose the first anti-diffusion region.
8. The method for preparing a semiconductor structure according to claim 5, characterized in that, Before etching the initial gate line to form the first initial groove, the method further includes: A patterned mask layer is formed on the side of the initial gate line away from the substrate; The etching of the initial gate line to form the first initial groove includes: Based on the patterned mask layer, the initial gate lines are etched to form a first initial groove.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, Before forming a patterned mask layer on the side of the initial gate line away from the substrate, the process includes: Form a stress-buffering material layer covering the initial gate lines; Before etching the initial gate lines based on the patterned mask layer to form the first initial trench, the method further includes: Based on the patterned mask layer, the stress buffer material layer is etched to form a stress buffer layer.
10. The method for preparing a semiconductor structure according to claim 5, characterized in that, The anti-diffusion ions include carbon ions and / or fluorine ions.