Preparation method of semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a substrate; sequentially forming a sacrificial layer and a protective layer on the substrate; forming a stack layer with alternate first sub-layers and second sub-layers on the protective layer; and at least etching the stack layer to form a first groove, wherein the first groove exposes the protection layer. Thus, the depth of the obtained first groove can be consistent to a great extent, at least part of materials between the substrate and the stacking layer can be smoothly and effectively removed based on the first groove in the subsequent process, and a replacement material with a good filling effect can be formed at the position where the materials are removed. The accuracy of the material replacement process is improved, so that the effective protection of the substrate can be realized in the subsequent process, the performance of the finally obtained semiconductor structure is optimized, and the integration level is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), typically consist of a single transistor and a capacitor in a memory cell, known as a 1T1C structure. In practice, the transistor and capacitor structures within a memory cell can be arranged in a tiled configuration. However, with the increasing demands for integration density and the continuous miniaturization of process nodes, many problems still exist in existing DRAMs that urgently need improvement. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, including: Provide substrate; A protective layer is formed on the substrate, the material of the protective layer including silicon boride; An alternating stack of first and second sublayers is formed on the protective layer; At least the stacked layers are etched to form a first trench, which exposes the protective layer.

[0004] In some embodiments, at least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers are etched to form the first trench, at least the bottom of the first trench exposes the protective layer.

[0005] In some embodiments, at least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers and the protective layer are etched to form the first trench, the sidewalls of the first trench exposing the stacked layers and the protective layer, and the first trench does not penetrate the protective layer.

[0006] In some embodiments, the atomic percentage of boron atoms in the silicon boride is 1:2500 to 1:2.

[0007] In some embodiments, the thickness of the protective layer ranges from 5 to 60 nm.

[0008] In some embodiments, after forming the first trench, the fabrication method further includes: A cover layer is formed, which covers the sidewalls and bottom of the first trench and the surface of the stacked layers; At least the portion of the cover layer located at the bottom of the first trench shall be removed.

[0009] In some embodiments, at least the portion of the cover layer located at the bottom of the first trench is removed, including: Remove the portion of the cover layer located at the bottom of the first trench; After removing the portion of the cover layer located at the bottom of the first trench, the preparation method further includes: The protective layer surrounding the bottom of the first trench is removed from the bottom of the first trench to form the structure to be filled.

[0010] In some embodiments, after forming the structure to be filled, the preparation method further includes: A filling layer is formed, which fills the structure to be filled.

[0011] In some embodiments, after forming the filler layer, the preparation method includes: Remove the covering layer; The first sublayer is replaced with an isolation layer, at least based on the first trench; A lateral etching process is performed on the second sublayer, and the remaining second sublayer constitutes the active region.

[0012] This disclosure also provides a method for fabricating a semiconductor structure, including: Provide substrate; A sacrificial layer and a protective layer are sequentially formed on the substrate, wherein the material of the protective layer includes silicon boride; An alternating stack of first and second sublayers is formed on the protective layer; At least the stacked layers are etched to form a first trench, which exposes the protective layer.

[0013] In some embodiments, at least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers are etched to form the first trench, at least the bottom of the first trench exposes the protective layer.

[0014] In some embodiments, at least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers and the protective layer are etched to form the first trench, the sidewalls of the first trench exposing the stacked layers and the protective layer, and the bottom of the first trench exposing the upper region of the sacrificial layer. The first trench does not penetrate the sacrificial layer. In some embodiments, the material of the sacrificial layer includes a silicon-germanium layer.

[0015] In some embodiments, the atomic percentage of boron atoms in the silicon boride is 1:2500 to 1:2.

[0016] In some embodiments, the thickness of the protective layer ranges from 5 to 60 nm.

[0017] In some embodiments, after forming the first trench, the fabrication method further includes: A cover layer is formed, which covers the sidewalls and bottom of the first trench and the surface of the stacked layers; At least the portion of the cover layer located at the bottom of the first trench shall be removed.

[0018] In some embodiments, at least the portion of the cover layer located at the bottom of the first trench is removed, including: The portion of the cover layer located at the bottom of the first trench is removed, and at least a portion of the sacrificial layer is removed to form a second trench, the second trench not penetrating the sacrificial layer; After forming the second trench, the preparation method further includes: The sacrificial layer surrounding the second trench is removed based on the second trench to form the structure to be filled.

[0019] In some embodiments, after forming the structure to be filled, the preparation method further includes: A filling layer is formed, which fills the structure to be filled.

[0020] In some embodiments, after forming the filler layer, the preparation method includes: Remove the covering layer; The first sublayer is replaced with an isolation layer, at least based on the first trench; A lateral etching process is performed on the second sublayer, and the remaining second sublayer constitutes the active region.

[0021] This disclosure also provides a semiconductor structure, which is fabricated using the preparation method described in any of the above embodiments.

[0022] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure include: providing a substrate; sequentially forming a sacrificial layer and a protective layer on the substrate; forming a stacked layer of alternating first and second sub-layers on the protective layer; and etching at least the stacked layer to form a first trench, the first trench exposing the protective layer. To improve the integration density of the semiconductor structure, a 3D stacked structure can be formed. For example, an epitaxial layer containing a predetermined material can be formed on the substrate using an epitaxial process, and then another epitaxial process can be performed on the epitaxial layer to obtain a stacked layer containing multiple sub-layers. A series of material replacement, material deposition, and etching processes can then be performed to obtain structures such as transistors or capacitors. However, in the above process, since the epitaxial process usually requires material based on the substrate, this increases the difficulty of material replacement in the epitaxial layer formed between the stacked layer and the substrate, which can easily lead to a risk of performance degradation in the final semiconductor structure. In other words, how to achieve material replacement at specific locations in the sacrificial layer and protective layer and prevent damage to the substrate during subsequent lateral etching of the stacked layer is a difficult problem to solve. In this embodiment of the disclosure, by forming a protective layer, it is beneficial that the first trench can be smoothly stopped at the desired position during its formation. This allows for the effective removal of at least a portion of the material located between the substrate and the stacked layers based on the first trench in subsequent processes, and the formation of a replacement material with good filling effect at the material removal location. This enables effective protection of the substrate in subsequent processes and improves the performance of the final semiconductor structure.

[0023] Details of one or more embodiments of this disclosure will be set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 2 This is one of the schematic diagrams of a semiconductor structure during the fabrication process provided in an embodiment of this disclosure; Figure 3 A second schematic diagram of the semiconductor structure during the fabrication process provided in an embodiment of this disclosure; Figure 4This is the third schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of the present disclosure; Figure 5 Fourth schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of this disclosure; Figure 6 Fifth schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of this disclosure; Figure 7 This is one of the schematic diagrams of the semiconductor structure during the fabrication process provided in another embodiment of this disclosure; Figure 8 This is a second schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of the present disclosure. Figure 9 This is the third schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of this disclosure. Figure 10 This is one of the schematic diagrams of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figure 11 This is a second schematic diagram of the semiconductor structure during the fabrication process provided in this embodiment of the disclosure; wherein, Figure 11 for Figure 10 Detailed sectional view along the A1-A2 direction in the center; Figure 12 This is the third schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figure 13 This is the fourth schematic diagram of the semiconductor structure during the fabrication process provided in the embodiments of this disclosure; Figure 14 One of the schematic diagrams of the semiconductor structure during the fabrication process provided in yet another embodiment of this disclosure; Figure 15 A second schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 16 The third schematic diagram of the semiconductor structure during the fabrication process, which is yet another embodiment of this disclosure; Figure 17 Fourth schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 18 Fifth schematic diagram of the semiconductor structure during the fabrication process, which is another embodiment of this disclosure; Figure 19 Sixth schematic diagram of the semiconductor structure during the fabrication process, which is another embodiment of this disclosure; Figure 20 This is one of the schematic diagrams of the semiconductor structure during the fabrication process provided in another embodiment of the present disclosure; Figure 21 A second schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 22 The third schematic diagram of the semiconductor structure during the fabrication process provided in yet another embodiment of this disclosure; Figure 23 Fourth schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 24 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process. Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] In dynamic random access memory (DRAM) architectures, in order to further increase the density of memory cells, a three-dimensional stacked 3D DRAM architecture is usually adopted. This technology expands along the vertical substrate direction rather than shrinking the planar structure, which is beneficial for stacking memory cells in multiple layers in the vertical direction. This effectively alleviates the problem of low integration caused by the transistors and capacitors contained in the memory cells being arranged on a planar surface.

[0029] However, there are still many problems in the fabrication of three-dimensional dynamic random access memory structures that need to be improved.

[0030] Based on this, the technical solution of the present disclosure embodiment is proposed as follows: This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps: Step S101: Provide a substrate; Step S102: Sequentially form a sacrificial layer and a protective layer on the substrate; Step S103: Form an alternating stack of first and second sublayers on the protective layer; Step S104: At least the stacked layers are etched to form a first trench, the first trench exposing the protective layer.

[0031] To improve the integration density of semiconductor structures, 3D stacked structures can be formed. For example, an epitaxial layer containing a predetermined material can be formed on a substrate using an epitaxial process. Then, another epitaxial process can be performed on this epitaxial layer to obtain a stacked layer containing multiple sublayers. A series of material replacement, deposition, and etching processes can then be performed to obtain structures such as transistors or capacitors. However, in the above process, since the epitaxial process usually requires substrate material, it increases the difficulty of material replacement in the epitaxial layer formed between the stacked layer and the substrate. This can easily lead to a risk of performance degradation in the final semiconductor structure. In other words, how to achieve material replacement at specific locations in the sacrificial layer and protective layer while preventing damage to the substrate during subsequent lateral etching of the stacked layer is a difficult problem. In the embodiments of this disclosure, forming a protective layer facilitates the successful placement of the first trench at the desired location during formation. This allows for the effective removal of at least a portion of the material between the substrate and the stacked layer based on the first trench in subsequent processes, forming a well-filled replacement material at the material removal location. This effectively protects the substrate in subsequent processes and improves the performance of the final semiconductor structure.

[0032] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0033] Figures 2 to 6 This is a schematic diagram of the semiconductor structure during the fabrication process provided in one embodiment of the present disclosure; Figures 7 to 9 This is a schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of this disclosure; Figures 10 to 13 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process; wherein, Figure 11 for Figure 10 Detailed sectional view along the A1-A2 direction in the center; Figures 14 to 19 A schematic diagram of the semiconductor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figures 20 to 23 This is a schematic diagram of the semiconductor structure during the fabrication process provided in another embodiment of the present disclosure; Figure 24 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the fabrication process.

[0034] The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] First, execute step S101, as follows: Figure 2 As shown, a substrate 10 is provided.

[0036] This disclosure does not specifically limit the constituent materials of the substrate 10. As an example, the substrate 10 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a stacked substrate including, for example, Si and SiGe, or a stacked substrate 10 of Si and SiC.

[0037] In some specific embodiments, the substrate 10 may be made of silicon.

[0038] Then, proceed with step S102, as follows: Figure 3 As shown, a sacrificial layer 11 and a protective layer 12 are sequentially formed on the substrate 10.

[0039] In some embodiments, the material of the sacrificial layer 11 may comprise a silicon-germanium layer.

[0040] In some embodiments, the material of the protective layer 12 may comprise any suitable material having a greater etching selectivity than the material of the sacrificial layer 11.

[0041] In some embodiments, the material of the protective layer 12 may be a material that has a larger etching selectivity ratio than the material of the sacrificial layer 11 during the dry etching process.

[0042] In some specific embodiments, the material of the protective layer 12 is doped silicon, specifically, the material of the protective layer 12 can be silicon boride (SiB).

[0043] In some embodiments, when the material of the protective layer 12 is silicon boride (SiB), the concentration of boron atoms ranges from 2 × 10⁻⁶. 19 atoms / cm 3 Up to 3.5×10 20 atoms / cm 3 (Including endpoint values), for example, 5×10 19 atoms / cm 3 7×1019 atoms / cm 3 8×10 19 atoms / cm 3 1×10 20 atoms / cm 3 2×10 20 atoms / cm 3 3×10 20 atoms / cm 3 wait.

[0044] In some embodiments, when the material of the protective layer 12 is silicon boride (SiB), the atomic percentage of boron atoms in the silicon boride ranges from (1:2500) to (1:2) (inclusive), for example, from 1:2500 to 1:140 (inclusive), or from (1:5) to (1:2) (inclusive).

[0045] In some specific embodiments, the atomic percentage of boron atoms in silicon boride ranges from (1:2500) to (1:140) (inclusive). Specifically, this ratio range can be, for example, 0.04%, 0.05%, 0.1%, 0.2%, 0.3%, 0.4%, 0.5%, 0.6%, 0.7%, etc. This allows for the formation of a high etch selectivity between the sacrificial layer 11 and the protective layer 12, while also promoting higher growth quality of the subsequent stacked layer ST formed above the protective layer 12.

[0046] In some embodiments, when performing a dry etching process, the etching selectivity ratio of the sacrificial layer 11 to the protective layer 12 can be greater than 10, for example, an etching selectivity ratio of 15, 16, 20, 25, etc.

[0047] To successfully remove and replace the sacrificial layer 11 while minimizing damage to surrounding material layers, the applicant discovered that using a protective layer of a specific material, and depending on the different etching selectivity ratios of the two materials during dry etching removal of the sacrificial layer, efficient etching removal of the silicon-germanium sacrificial layer can be achieved, while effectively protecting the surrounding material layers and avoiding damage to the surrounding material structure during sacrificial layer removal. This is particularly true when the protective layer 12 is made of silicon boride, in the subsequent dry etching selective removal step of the sacrificial layer 11 (silicon-germanium layer) (see details...). Figure 10 When using etching gases, such as dry etching based on chlorine or fluorine, or hot hydrochloric acid vapor etchants, the etching rate of silicon germanium can be extremely high while the etching rate of silicon boride is extremely low. This allows the sacrificial layer 11 to be removed smoothly while the surrounding material layers, including but not limited to the substrate 10, remain essentially undamaged, effectively reducing damage during the process.

[0048] Furthermore, when the material of the protective layer 12 is silicon boride, excellent process windows and good etching uniformity can be obtained during the removal of the sacrificial layer 11. This is because when there is a large etch selectivity ratio between the sacrificial layer 11 and the protective layer 12, the process's tolerance to over-etching is greatly increased. This means that even if there are only slight differences in the etching rate in different regions of the substrate 10, it can be ensured that silicon germanium is completely removed while the silicon boride layer has low loss, thereby obtaining a highly uniform semiconductor structure after the etching operation.

[0049] Furthermore, the silicon boride layer exhibits excellent thermal stability and interface quality, enabling it to withstand high-temperature steps in stacked layer deposition (such as epitaxial growth) and subsequent processes without decomposition or adverse reactions with the substrate. In other words, it provides a high-quality, chemically stable starting surface, which is beneficial for epitaxially growing silicon / silicon-germanium superlattice structures with fewer defects.

[0050] In addition to the effects described above, the silicon-germanium layer is removed and replaced with a filling layer 14 containing oxides (see Appendix for details). Figure 13 During the process of replacing the silicon-germanium layer, this silicon boride layer prevents the oxidant from diffusing downwards into the silicon substrate, ensuring that the oxide fills only the predetermined area. This helps to prevent substrate oxidation during the replacement of the silicon-germanium layer.

[0051] Based on the above, the applicant has discovered that when the material of the protective layer 12 is silicon boride, compared to cases where the material of the protective layer 12 is, for example, silicon carbide (SiC), silicon nitride (SiN), or doped silicon boride (e.g., C or N doped silicon boride), using silicon boride as the material of the protective layer 12 can better achieve a balance between high etch selectivity and high growth quality of the stacked layers. This is because: If the protective layer 12 is made of silicon carbide (SiC), although a large etch selectivity ratio can be formed between the protective layer 12 and the sacrificial layer 11, the presence of silicon carbide can easily lead to lattice mismatch and stress between the bottom material layer and the silicon carbide layer in the stacked layer ST formed above it. This can easily generate defects such as dislocations and stacking faults, reducing the growth quality of the formed stacked layer ST. In other words, although the introduction of silicon carbide can form a good etch stop layer on the sacrificial layer 11, it will affect the growth quality of the material layer formed by subsequent epitaxy, which is not conducive to improving the performance of the final semiconductor structure. Furthermore, if the protective layer 12 is made of silicon nitride (SiN), it will cause growth difficulties. Since silicon nitride is an amorphous material, while the silicon-germanium layer material contained in the sacrificial layer 11 is a crystalline structure, it is difficult to obtain the material of the protective layer 12 by epitaxial growth on the sacrificial layer 11. At the same time, it is also difficult to obtain a high-quality stacked layer material by epitaxial growth on the silicon nitride material. It can also be understood that when the protective layer is made of silicon nitride, there will be a situation where the growth of the protective layer 12 is incompatible with the epitaxial growth process.

[0052] Furthermore, when the material of the protective layer 12 includes doped silicon boride (e.g., C or N doped silicon boride), or when the material of the protective layer 12 is SiCB, the incorporation of C may further increase the etching resistance of the material because the bond energy of the Si-C bond is higher than that of the Si-Si or Si-Ge bond. However, this effect is gradual and highly dependent on the specific etching formulation (gas type, bias voltage, power, etc.). Therefore, the final selectivity must be confirmed through actual process calibration. It can also be understood that although this material, when used as the protective layer 12, has the potential to increase the etching selectivity, it has high requirements for etching conditions, and its stability during the etching process may be poor. At the same time, the use of this material in this scenario is not a conventional choice. If it is insisted upon, multiple verifications are required to determine whether it is suitable for use, which will significantly increase the production cycle, the uncertainty of the production process, and the production cost. Furthermore, when the material of the protective layer 12 is SiBN, since SiBN is an amorphous material layer, it cannot be obtained through epitaxial processes. In other words, although the material of the protective layer 12, SiBN, has a large etching selectivity ratio with the silicon-germanium contained in the sacrificial layer, it is incompatible with the epitaxial process. It is impossible to obtain a high-quality stacked layer structure by epitaxial growth on the basis of the protective layer 12, which is not conducive to the normal production process.

[0053] In some embodiments, the thickness of the protective layer 12 ranges from 5 to 60 nm (including the endpoint values), for example, 6 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 55 nm, etc.

[0054] The configuration of the sacrificial layer 11 and the protective layer 12 provided in this embodiment can include various situations, which will be further explained below with reference to the accompanying drawings: In some embodiments, such as Figure 3 and Figure 7 As shown, the sacrificial layer 11 and the protective layer 12 coexist and both have a certain thickness.

[0055] However, this is not the only one; in other embodiments, such as Figure 14 As shown, the thickness of the sacrificial layer 11 located between the substrate 10 and the stacked layer ST can also be 0, but the thickness of the protective layer 12 is not 0.

[0056] In some embodiments, when the thickness of the sacrificial layer 11 is not zero, the thickness of the sacrificial layer 11 can be the same as the thickness of the first trench T1 to be formed in the subsequent step S104 (see subsequent steps for details). Figure 4 or Figure 7 The width dimension is related to the size of the first trench T1. For example, the thickness dimension of the sacrificial layer 11 can be related to the width dimension of the first trench T1 (see subsequent details). Figure 4 or Figure 7 The width of the device is between 1 and 2 times (including endpoint values), such as 1.2 times, 1.5 times, or 1.8 times.

[0057] However, this is not the only embodiment disclosed, such as... Figures 20 to 23 As shown, when the thickness of the sacrificial layer 11 is not 0, its thickness can also be set to a larger thickness, and the desired process can be successfully achieved through a series of process steps.

[0058] It is understood that, based on the above-described embodiments of setting the sacrificial layer 11 and the protective layer 12, it is beneficial to ensure that the bottom of the first trench T1 is smoothly stopped at the desired position during the etching process of the stacked layer ST to form the first trench T1 in the subsequent step S104 after the stacked layer ST is formed in step S103. This prevents a series of undesirable situations such as large differences in etching depth of the first trench T1 at different positions (which can also be understood as poor height consistency of the first trench T1). The specific situation will be explained in the following steps.

[0059] Then, proceed to step S103, as follows: Figure 3 , Figure 7 as well as Figure 14 As shown, a stacked layer ST consisting of alternating first sublayer L1 and second sublayer L2 is formed on the protective layer 12.

[0060] In some embodiments, the material of the first sublayer L1 includes a silicon-germanium layer, and the material of the second sublayer L2 may include a silicon layer. It can be seen that the stacked layer ST in the embodiments of this disclosure is a Si / SiGe superlattice epitaxial structure.

[0061] In some embodiments, the material layer located on top of the stacked layer ST can be a second sublayer L2.

[0062] In practice, the first sublayer L1 and the second sublayer L2 can be formed using epitaxial technology, which helps to improve the quality of the final semiconductor structure.

[0063] It should be noted that although the attached figure only shows the case where the stacked layer ST contains a total of 8 layers, including the first sublayer L1 and the second sublayer L2, in actual operation, the total number of the first sublayer L1 and the second sublayer L2 can be more or less, for example, 2 layers, 4 layers, 6 layers, 10 layers, a dozen layers, several dozen layers, several hundred layers or even more layers. Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0064] Finally, proceed with step S104, as follows: Figure 4 , Figure 7 as well as Figure 15 As shown, at least the stacked layer ST is etched to form a first trench T1, and the first trench T1 exposes the protective layer 12.

[0065] In some embodiments, before forming the first trench T1, the preparation method further includes: A mask layer M is formed over the stacked layer ST. The mask layer M can form a patterned structure (not shown) before the subsequent etching process to form the first trench T1. The first trench T1 can then be obtained based on the patterned structure (not shown).

[0066] Understandably, since the stacked layer ST needs to be formed through epitaxial processes, and since the substrate 10 and the second sublayer L2 in the stacked layer ST are made of the same material, the material of the substrate 10 can easily be etched or damaged during subsequent operations such as etching of the material in the stacked layer ST. Therefore, before forming the memory cell of the semiconductor structure based on the material in the stacked layer ST, it is necessary to replace at least part of the material between the substrate 10 and the stacked layer ST with a material layer of suitable composition.

[0067] In some embodiments, the operation of replacing at least a portion of the material located between the substrate 10 and the stacked layer ST with a material layer having a suitable composition (specifically, this can be understood as the subsequent...) Figure 13 , Figure 19 , Figure 23(The process of forming the intermediate filling layer 14). Specifically, it may include the operation of introducing an oxide material, such as silicon oxide, into the region located between the substrate 10 and the stacked layer ST.

[0068] Understandably, replacing at least a portion of the material between the substrate 10 and the stacked layer ST with a filler layer, such as an oxide or silicon oxide, facilitates electrical isolation between the substrate 10 and the stacked layer ST. Furthermore, if subsequent etching processes penetrating the stacked layer ST are required, this material layer can also act as an etching stop layer. In addition, since silicon and silicon oxide have relatively similar coefficients of thermal expansion, this silicon oxide layer can partially alleviate stress caused by thermal mismatch during high-temperature processes (such as epitaxial growth and annealing), preventing warping or defects in the entire thin film structure.

[0069] Therefore, replacing at least a portion of the material formed by epitaxial process in the substrate 10 and the stacked layer ST with an oxide layer (filling layer 14) is a very important process. If the material replacement effect is not good, for example, if there is an uneven surface morphology, such as unevenness or many internal defects, it is easy to fail to meet the performance requirements and cause the performance of the final semiconductor structure to deteriorate.

[0070] In practice, before officially replacing the material located in the substrate 10 and the stacked layer ST, it is necessary to perform the step of etching the stacked layer ST to form the first trench T1. Then, the area between the substrate 10 and the stacked layer ST will be opened based on the first trench T1. Therefore, forming the first trench T1 is a very critical step. However, due to various possible reasons, such as the uneven distribution density of the first trench T1 on the substrate or the different dimensions of the first trench T1 at different locations in the same direction parallel to the plane of the substrate 10, it is easy for the distance between the bottom of the first trench T1 and the surface of the substrate 10 to be inconsistent at different locations. That is, the first trench T1 is prone to have inconsistent height, or inconsistency in depth, at different locations.

[0071] Understandably, when the depth of the first trench T1 is too shallow, it can easily cause subsequent etching operations to remove the material that should have been removed (for example, it can be understood as...). Figure 10 The process of removing the sacrificial layer 11, or as understood as Figure 18 During the process of removing the protective layer 12, errors in material removal can occur, leading to material replacement failure. Furthermore, if the depth of the first trench T1 is too deep, it can easily cause the subsequent formation of the capping layer La (see reference [link to documentation]). Figure 5 , Figure 8 or Figure 16When the capping layer La is located on the bottom sidewall of the first trench T1 (which can be understood as the portion of capping layer La on the sidewall of the first trench T1 that is closer to the substrate 10), it will completely cover the area that needs to be opened for material replacement, making it impossible to perform the correct material removal and replacement operation. This can even lead to damage to the substrate 10 during this step. Furthermore, when the depth of the first trench T1 varies significantly at different locations, it is easy to encounter situations where the etching time cannot be accurately set when removing the capping layer La at the bottom of the first trench T1, thus exacerbating damage to the substrate 10.

[0072] In this embodiment, due to the presence of the protective layer 12, when the material between the substrate 10 and the stacked layer ST simultaneously includes both the sacrificial layer 11 and the protective layer 12, the protective layer 12 can function as an etching stop layer. This allows the bottom of the first trench T1 to remain within the protective layer 12 during subsequent etching to form the first trench T1. Alternatively, even if the bottom of the first trench T1 falls within the sacrificial layer 11, the large etching selectivity between the protective layer 12 and the sacrificial layer 11 ensures a significant distance between the bottom of the first trench T1 and the substrate 10. This facilitates the smooth replacement of the material between the substrate 10 and the stacked layer ST with an oxide layer, significantly reducing the possibility of damage to the substrate 10. Furthermore, when the thickness of the sacrificial layer 11 in the material layer between the substrate 10 and the stacked layer ST is zero, the presence of the protective layer 12 prevents etching of the substrate 10 during the formation of the first trench T1, further reducing damage to the substrate 10 during the smooth replacement of the material between the substrate 10 and the stacked layer ST with an oxide layer.

[0073] The process of forming the first trench T1, the capping layer La, and replacing the material layer located between the substrate 10 and the stacked layer ST will be described in further detail below with reference to the accompanying drawings.

[0074] In some embodiments, such as Figure 4 , Figure 7 as well as Figure 15 As shown, at least the stacked layer ST is etched to form a first trench T1, the first trench T1 exposing a protective layer 12, including: The first trench T1 is formed using a dry etching process, and when the dry etching process is performed, an etchant with a relatively slow etching rate for the protective layer 12 is required.

[0075] In some embodiments, during the formation of the first trench T1, which exposes the protective layer 12, the etchant used includes, but is not limited to, chlorine-based mixed gas, fluorine-based mixed gas, and bromine-based mixed gas. Specifically, Cl2 / O2 mixed gas (volume ratio 3:1), HBr / O2 mixed gas (volume ratio 4:1), and CF4 / O2 mixed gas (volume ratio 5:1) can be selected. The etching pressure is 1~5 mTorr, the etching temperature is 25~50℃, and the etching rate is 50~100 nm / min. Among them, chlorine-based and bromine-based gases can preferentially ensure the etching rate and anisotropy of the stacked layer, while fluorine-based gases can help adjust the etching selectivity and avoid excessive loss of the protective layer.

[0076] In some embodiments, such as Figure 4 and Figure 15 As shown, at least the stacked layer ST is etched to form a first trench T1, the first trench T1 exposing a protective layer 12, including: The stacked layers ST are etched to form a first trench T1, at least the bottom of the first trench T1 exposes the protective layer 12.

[0077] In this embodiment, the protective layer 12 effectively functions as an etching stop layer, ensuring that the first trenches T1 at various locations on the substrate 10 have a consistent depth. This facilitates the formation of the capping layer La in the next step, ensuring that the portion located on the sidewall of the first trench T1 does not obscure the area where the sacrificial layer 11 is located. This allows for the smooth removal and material replacement of the sacrificial layer 11 (specifically, it can be understood as...). Figure 13 The process of forming the filling layer 14 shown is to ensure that the filling layer 14 functions smoothly.

[0078] In other embodiments, such as Figure 7 As shown, at least the stacked layer ST is etched to form a first trench T1, the first trench T1 exposing a protective layer 12, including: The stacked layer ST and the protective layer 12 are etched to form a first trench T1. The sidewalls of the first trench T1 expose the stacked layer ST and the protective layer 12, and the bottom of the first trench T1 exposes the upper region of the sacrificial layer 11. The first trench T1 does not penetrate the sacrificial layer 11.

[0079] In this embodiment, one possible understanding is that although the first trench T1 penetrates the protective layer 12, due to the presence of the protective layer 12 and the slow etching rate during the etching process of the protective layer 12, the bottom of the formed first trench T1, although penetrating the protective layer 12, stops at a position very close to the stacked layer ST of the sacrificial layer 11. This is beneficial because the capping layer La formed on the sidewall of the first trench T1 in the next step will not cover a large area of ​​the area where the sacrificial layer 11 is located near the bottom of the first trench T1, thereby achieving smooth removal and material replacement of the sacrificial layer 11 (specifically, this can be understood as...). Figure 13 The process of forming the filling layer 14 (as shown) is to ensure the smooth functioning of the filling layer 14. Another possible understanding is that at some locations, the first trench T1 is formed as shown in the diagram. Figure 4 The structure shown has a first groove T1 at other locations forming a shape as shown in the diagram. Figure 7 As shown in the structure, in this embodiment, due to the introduction of the protective layer 12, the protective layer 12 not only functions as an etching stop layer but also as a buffer layer, slowing down the extension speed of the first trench T1 in the sacrificial layer and keeping it in the upper region of the sacrificial layer 11. This prevents the extension length of the first trench T1 in the sacrificial layer 11 in the direction perpendicular to the plane of the substrate 10 from becoming uncontrolled (e.g., extending to the lower region of the sacrificial layer or penetrating the sacrificial layer). This is beneficial because, regardless of its location on the substrate 10, the portion of the capping layer La formed in the next step located on the sidewall of the first trench T1 will not extensively cover the area where the sacrificial layer 11 is located, thereby achieving smooth removal and material replacement of the sacrificial layer 11 (specifically, it can be understood as...). Figure 13 The process of forming the filling layer 14 shown is to ensure that the filling layer 14 functions smoothly.

[0080] In some other embodiments, such as Figure 15 As shown, the thickness of the sacrificial layer 11 is 0; at least the stacked layer ST is etched to form a first trench T1, the first trench T1 exposing the protective layer 12, including: The stacked layers ST are etched to form a first trench T1, at least the bottom of the first trench T1 exposes the protective layer 12.

[0081] In some other embodiments, such as Figure 15 As shown, the thickness of the sacrificial layer 11 is 0; at least the stacked layer ST is etched to form a first trench T1, the first trench T1 exposing the protective layer 12, including: The stacked layer ST is etched to form a first trench T1, the bottom and part of the sidewalls of the first trench T1 exposing the protective layer 12.

[0082] In some embodiments, where the thickness of the sacrificial layer 11 is 0, the thickness of the protective layer 12 can be made slightly thicker than in embodiments where the thickness of the sacrificial layer 11 is not 0, so that the protective layer 12 can effectively function as an etching stop layer during the etching process to form the first trench T1.

[0083] In some embodiments, when the thickness of the sacrificial layer 11 is 0, the thickness of the protective layer 12 can range from 30 nm to 60 nm (inclusive), such as 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, etc. In this embodiment, even if the thickness of the protective layer 12 is increased, the volume of the final semiconductor structure will not increase due to the omission of the sacrificial layer 11; on the contrary, it may even reduce the volume of the final semiconductor structure, which is beneficial for improving integration density.

[0084] In some embodiments, when etching to form the first trench T1, when etching to the protective layer 12, the etching conditions can be adjusted, such as by changing the etchant or adjusting the etching parameters, so that the etching rate of the protective layer 12 is relatively low. At the same time, the adjustment of the etching conditions can also make the etching rate of the protective layer greater than the etching rate of the material contained in the substrate 10, so as to reduce or even avoid the possibility of damage to the substrate 10 in the process.

[0085] exist Figure 15 In the embodiment shown, since the etching rate of the protective layer 12 is relatively slow when it is etched to the protective layer 12 during the formation of the first trench T1, the first trench T1 can be accurately stopped in the protective layer 12 even without the formation of the sacrificial layer 11. This helps to prevent the first trench T1 from having large depth differences in different areas of the substrate 10, and at the same time, it can accurately expose the material layer between the substrate 10 and the stacked layer ST, so as to provide good preconditions for material replacement (formation of the filling layer 14) in subsequent steps.

[0086] It can be seen that even in embodiments where the sacrificial layer 11 is not formed, by adjusting the thickness of the protective layer 12 and the parameters of the etching process, a first trench T1 that stops within the protective layer 12 but does not penetrate it can be obtained. This is beneficial because the portion of the capping layer La formed in the next step located on the sidewall of the first trench T1 will not extensively cover the area where the protective layer 12 is located, thereby achieving smooth removal and material replacement of the protective layer 12 (specifically, this can be understood as...). Figure 19 The process of forming the filling layer 14 shown is to ensure that the filling layer 14 functions smoothly.

[0087] In some embodiments, such as Figures 5 to 6 , Figures 8 to 9 , Figures 16 to 17 As shown, after forming the first trench T1, the fabrication method further includes: A capping layer La is formed, which covers the sidewalls and bottom of the first trench T1 and the surface of the stacked layer ST; At least the portion of the cover layer La located at the bottom of the first trench T1 should be removed.

[0088] In some embodiments, such as Figures 5 to 6 as well as Figures 8 to 11 As shown, when the thickness of the sacrificial layer 11 is not 0, at least the portion of the cover layer La located at the bottom of the first trench T1 is removed, including: The portion of the capping layer La located at the bottom of the first trench T1 is removed, and at least a portion of the sacrificial layer 11 is removed to form the second trench T2, which does not penetrate the sacrificial layer 11 (see details). Figures 5 to 6 as well as Figures 8 to 9 ); After forming the second trench T2, the preparation method also includes: Based on the second trench T2, the sacrificial layer 11 surrounding the second trench T2 is removed to form the structure to be filled 13 (see details). Figures 10 to 11 ).

[0089] Here, the sacrificial layer 11 located around the second trench T2 that is removed based on the second trench T2 may specifically include at least a portion of the material of the sacrificial layer 11 exposed by the sidewalls and bottom of the second trench T2.

[0090] In some embodiments, the understanding of removing the sacrificial layer 11 surrounding the second trench T2 based on the second trench T2 can further include various cases, such as: In some cases, the sacrificial layer located between the substrate 10 and the protective layer 12 can be completely removed based on the second trench T2. However, this is not the only possibility. In other cases, the sacrificial layer 11 can be retained at certain locations, taking into account where its presence would not cause adverse effects during subsequent etching processes. The specific choice can be made flexibly according to the actual situation, and no particular limitation is made here.

[0091] In some embodiments, such as Figure 5 and Figure 6 As shown, when the thickness of the sacrificial layer 11 is not zero, and the bottom of the first trench T1 is located in the protective layer 12, a second trench T2 is formed, including: The portion of the capping layer La located at the bottom of the first trench T1 is removed, and a portion of the protective layer 12 is also removed to form a second trench T2 that penetrates the protective layer 12. The second trench T2 does not penetrate the sacrificial layer 11 (see details). Figures 5 to 6 as well as Figures 8 to 9 ).

[0092] In some embodiments, when forming the second trench T2, the etching conditions, such as the etchant or etching parameters, can be adjusted to make the etching rate of the sacrificial layer 11 lower. At the same time, the adjustment of the etching conditions can also make the etching rate of the sacrificial layer 11 greater than the etching rate of the material contained in the substrate 10, so as to reduce or even avoid the possibility of damage to the substrate 10 in the process.

[0093] Here, in Figures 5 to 6 as well as Figures 8 to 9 In the illustrated embodiment, due to the protective layer 12 disposed between the sacrificial layer 11 and the stacked layer ST, the bottom of the formed first trench T1 can have a high degree of consistency in the depth position of the material layer in different regions of the substrate 10 where it resides. Specifically, it can stop in the protective layer 12, or even if it stops in the sacrificial layer 11, it can stop in the upper region. That is, the first trench T1 will not extend indefinitely to form a structure that penetrates the sacrificial layer 11. This ensures that the portion of the capping layer La located on the sidewall of the first trench T1 will not significantly cover or even not cover the area where the sacrificial layer 11 is located. This facilitates the smooth exposure of the material of the sacrificial layer 11 on the sidewall and bottom of the subsequently formed second trench T2, thereby achieving the smooth removal of the sacrificial layer 11 and the subsequent filling layer 14 (see Appendix for details). Figure 14 The smooth filling of (etc.)

[0094] In any of the above embodiments, removing the sacrificial layer 11 surrounding the second trench T2 based on the second trench T2 to form the structure to be filled 13 includes: The sacrificial layer 11 exposed in the second trench T2 is removed by a side-penetration process. The side-penetration process uses an etching gas of HBr / O2 mixture and the etching depth is 20~50nm.

[0095] In some embodiments, such as Figures 16 to 18 As shown, when the thickness of the sacrificial layer 11 is 0, at least the portion of the cover layer La located at the bottom of the first trench T1 is removed, including: Remove the portion of the cover layer La located at the bottom of the first trench T1; After removing the portion of the capping layer La located at the bottom of the first trench T1, the fabrication method further includes: The protective layer 12 located around the bottom of the first trench T1 is removed to form the structure to be filled 13.

[0096] Here, the removal of the protective layer 12 around the bottom of the first trench T1 based on the bottom of the first trench T1 may specifically include at least a portion of the material of the protective layer 12 exposed by the sidewalls and bottom of the first trench T1.

[0097] In some embodiments, the understanding of removing the protective layer 12 surrounding the bottom of the first trench T1 based on the bottom of the first trench T1 can further include various cases, such as: In some cases, the protective layer 12 located between the substrate 10 and the stacked layer ST can be completely removed based on the first trench T1. However, this is not the only possibility. In other cases, the protective layer 12 can be retained at certain locations, taking into account where its presence would not cause adverse effects during subsequent etching processes. The specific choice can be made flexibly according to the actual situation, and no particular limitation is made here.

[0098] In some embodiments, the material of the capping layer La may include, but is not limited to, nitrides, such as silicon nitride. Silicon nitride as the capping layer La helps to protect the stacked layers ST located on both sides of the first trench from simultaneous etching or damage during the removal of the sacrificial layer 11 or the protective layer 12.

[0099] In an embodiment where the thickness of the sacrificial layer 11 is 0, such as Figure 18 As shown, the protective layer 12 surrounding the bottom of the first trench T1 is removed from the bottom of the first trench T1 to form the structure to be filled 13, including: The protective layer 12 is removed by performing a side-cutting process on the protective layer exposed at the bottom of the first trench T1.

[0100] Here, in Figures 16 to 17 In the illustrated embodiment, because a protective layer 12 is provided between the substrate 10 and the stacked layer ST, and because the protective layer 12 can be made relatively thick, the bottom of the formed first trench T1 can be located in different regions of the substrate 10. The depth of the first trench T1 in the protective layer has a high degree of consistency. This ensures that the portion of the capping layer La located on the sidewall of the first trench T1 does not significantly cover the area where the protective layer 12 is located. This facilitates the subsequent removal of the capping layer La located at the bottom of the first trench T1. After this step, the area of ​​the first trench T1 not covered by the capping layer La can be easily exposed to the material of the surrounding protective layer 12, thereby achieving the smooth removal of the protective layer 12 and the subsequent filling layer 14 (see Appendix for details). Figure 19 The smooth filling of (etc.)

[0101] In some embodiments, such as Figure 12 and Figure 13 , Figure 19 as well as Figures 20 to 23 As shown, after forming the structure to be filled 13, the preparation method further includes: A filling layer 14 is formed, and the filling layer 14 fills the structure 13 to be filled.

[0102] In some embodiments, the material of the filling layer 14 includes, but is not limited to, an oxide layer, such as silicon oxide.

[0103] In some embodiments, such as Figure 12 and Figure 13 as well as Figure 19 As shown, a filling layer 14 is formed, comprising: A filling material layer 14a is formed, which at least fills the first trench T1 and the structure to be filled 13 (see appendix for details). Figure 12 ); An etching process is performed to remove part of the filler material layer 14a, leaving the filler material layer 14a remaining in the structure to be filled 13 to form the filler layer 14 (see appendix for details). Figure 13 and appendix Figure 19 ).

[0104] In other embodiments, such as Figures 20 to 23 As shown, a filling layer 14 is formed, comprising: A first filling material layer 14b is formed, which at least fills the first trench T1 and partially fills the structure to be filled 13 (see appendix for details). Figure 20 The portion of the structure 13 not filled by the first filling material layer 14b constitutes gap H (see appendix for details). Figure 20 ); An etching process is performed to remove at least a portion of the first filler material layer 14b located at least within the first trench T1, to form a third trench T3 located at the bottom of the second trench T2, exposing a gap H in the third trench T3 (see attached diagram for details). Figure 21 ); A second filler material layer 14c is formed, which at least fills the first trench T1 and the gap H (see appendix for details). Figure 22 ); An etching process is performed to remove part of the second filler material layer 14c, leaving the first filler material layer 14b and the second filler material layer 14c in the structure to be filled 13 to form the filler layer 14 (see appendix for details). Figure 23 ).

[0105] In such Figures 20 to 23 In the method shown, the operation of forming the fill layer 14 can correspond to Figures 4 to 6 or Figures 7 to 9 After the steps of any embodiment are completed, and the structure to be filled 13 is obtained, the filling layer 14 is formed. Thus, the thickness of the sacrificial layer 11 formed in the semiconductor is not limited by the width of the first trench T1 in the direction parallel to the substrate plane, and a larger thickness can be achieved based on actual product requirements; for example, it can be [missing information]. Figure 6 or Figure 7The embodiment shows that the thickness of the sacrificial layer 11 is 2 to 3 times (including the endpoint value), specifically 2.2 times, 2.5 times, 2.8 times, etc. The filling layer 14 obtained by this embodiment can have an enhanced function. Specifically, the thickness of the sacrificial layer 11 formed in the semiconductor structure can be 20nm to 800nm.

[0106] However, this is not the only option. When the thickness of the sacrificial layer 11 is 0 and the thickness of the protective layer 12 is not 0 and a relatively large thickness is required, it can also be directly adopted or referenced. Figures 20 to 23 The method shown is used to obtain a fill layer 14 with good filling effect. It will not be described in detail here. Please refer to the corresponding steps to perform the operation.

[0107] In any of the above embodiments, forming the filler layer 14 includes directly filling it with an oxide-containing material, such as silicon oxide, to form the filler layer 14. However, it is not limited to this. In other cases, it can also be obtained by first filling with silicon material and then performing a thermal oxidation process. The specific method can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0108] In some embodiments, such as Figure 24 As shown, after forming the filling layer 14, the preparation method includes: Remove the covering layer La; At least based on the first trench T1, the first sublayer L1 is replaced with the isolation layer L3; A lateral etching process is performed on the second sublayer L2, and the remaining second sublayer L2 constitutes the active region SL.

[0109] Here, the transistor structure can be obtained based on the active region SL, and the isolation layer L3 is used to achieve the isolation effect between the multilayer transistors stacked perpendicular to the substrate 10.

[0110] This disclosure also provides a semiconductor structure, such as... Figure 24 As shown, the semiconductor structure is fabricated using the preparation method of any of the above embodiments.

[0111] In some embodiments, such as Figure 24 As shown, the semiconductor structure includes at least an active region SL.

[0112] In some embodiments, such as Figure 24 As shown, the semiconductor structure also includes a filling layer 14 and a protective layer 12 located on the substrate 10, wherein the filling layer 14 is located between the substrate 10 and the protective layer 12, and the filling layer 14 is located between a plurality of active regions SL and the substrate 10.

[0113] In some embodiments, the semiconductor structure may include, but is not limited to, a 3D-DRAM structure.

[0114] It should be noted that the technical features described in the embodiments provided in this disclosure can be combined arbitrarily without conflict.

[0115] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: Provide substrate; A protective layer is formed on the substrate, the material of the protective layer including silicon boride; An alternating stack of first and second sublayers is formed on the protective layer; At least the stacked layers are etched to form a first trench, which exposes the protective layer.

2. The preparation method according to claim 1, characterized in that, At least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers are etched to form the first trench, at least the bottom of the first trench exposes the protective layer.

3. The preparation method according to claim 1, characterized in that, At least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers and the protective layer are etched to form the first trench, the sidewalls of the first trench exposing the stacked layers and the protective layer, and the first trench does not penetrate the protective layer.

4. The preparation method according to any one of claims 1-3, characterized in that, The atomic percentage of boron atoms in the silicon boride is 1:2500 to 1:

2.

5. The preparation method according to claim 1, characterized in that, The thickness of the protective layer ranges from 5 to 60 nm.

6. The preparation method according to claim 1, characterized in that, After forming the first trench, the preparation method further includes: A cover layer is formed, which covers the sidewalls and bottom of the first trench and the surface of the stacked layers; At least the portion of the cover layer located at the bottom of the first trench shall be removed.

7. The preparation method according to claim 6, characterized in that, At least the portion of the cover layer located at the bottom of the first trench is removed, including: Remove the portion of the cover layer located at the bottom of the first trench; After removing the portion of the cover layer located at the bottom of the first trench, the preparation method further includes: The protective layer surrounding the bottom of the first trench is removed from the bottom of the first trench to form the structure to be filled.

8. The preparation method according to claim 7, characterized in that, After forming the structure to be filled, the preparation method further includes: A filling layer is formed, which fills the structure to be filled.

9. The preparation method according to claim 8, characterized in that, After forming the filling layer, the preparation method includes: Remove the covering layer; The first sublayer is replaced with an isolation layer, at least based on the first trench; A lateral etching process is performed on the second sublayer, and the remaining second sublayer constitutes the active region.

10. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: Provide substrate; A sacrificial layer and a protective layer are sequentially formed on the substrate, wherein the material of the protective layer includes silicon boride; An alternating stack of first and second sublayers is formed on the protective layer; At least the stacked layers are etched to form a first trench, which exposes the protective layer.

11. The preparation method according to claim 10, characterized in that, At least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers are etched to form the first trench, at least the bottom of the first trench exposes the protective layer.

12. The preparation method according to claim 10, characterized in that, At least the stacked layers are etched to form a first trench, the first trench exposing the protective layer, including: The stacked layers and the protective layer are etched to form the first trench, the sidewalls of the first trench exposing the stacked layers and the protective layer, and the bottom of the first trench exposing the upper region of the sacrificial layer, the first trench not penetrating the sacrificial layer.

13. The preparation method according to any one of claims 10-12, characterized in that, The material of the sacrificial layer includes a silicon-germanium layer.

14. The preparation method according to any one of claims 10-12, characterized in that, The atomic percentage of boron atoms in the silicon boride is 1:2500 to 1:

2.

15. The preparation method according to claim 10, characterized in that, The thickness of the protective layer ranges from 5 to 60 nm.

16. The preparation method according to any one of claims 10-12, characterized in that, After forming the first trench, the preparation method further includes: A cover layer is formed, which covers the sidewalls and bottom of the first trench and the surface of the stacked layers; At least the portion of the cover layer located at the bottom of the first trench shall be removed.

17. The preparation method according to claim 16, characterized in that, At least the portion of the cover layer located at the bottom of the first trench is removed, including: The portion of the cover layer located at the bottom of the first trench is removed, and at least a portion of the sacrificial layer is removed to form a second trench, the second trench not penetrating the sacrificial layer; After forming the second trench, the preparation method further includes: The sacrificial layer surrounding the second trench is removed based on the second trench to form the structure to be filled.

18. The preparation method according to claim 17, characterized in that, After forming the structure to be filled, the preparation method further includes: A filling layer is formed, which fills the structure to be filled.

19. The preparation method according to claim 18, characterized in that, After forming the filling layer, the preparation method includes: Remove the covering layer; The first sublayer is replaced with an isolation layer, at least based on the first trench; A lateral etching process is performed on the second sublayer, and the remaining second sublayer constitutes the active region.

20. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the preparation method described in any one of claims 1 to 19.

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