Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes a gate structure including insulating layers and conductive layers alternately stacked. The semiconductor device further includes a channel layer extending through the gate structure, the channel layer including a first portion including a first concentration of metal atoms and a second portion including a second concentration of metal atoms different from the first concentration. The semiconductor device further includes an insulating core in the channel layer and a capping layer on the insulating core. The first portion is on the second portion, and a boundary between the first portion and the second portion is between an upper surface and a lower surface of an uppermost one of the insulating layers.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices and methods of manufacturing electronic devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integration density of a semiconductor device is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed on a single layer on a substrate has reached its limit, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In one embodiment, a semiconductor device may include: a gate structure comprising alternating layers of insulating and conductive layers; a channel layer extending through the gate structure, the channel layer comprising a first portion and a second portion, the first portion comprising a first concentration of metal atoms and the second portion comprising a second concentration of metal atoms different from the first concentration; an insulating core within the channel layer; and a capping layer on the insulating core. The first portion may be on the second portion, and the boundary between the first and second portions may be between the upper and lower surfaces of the uppermost insulating layer in the insulating layer.

[0004] In an embodiment, a semiconductor device may include: a gate structure including alternating layers of insulating and conductive layers; a channel layer extending through the gate structure, the channel layer including a first portion having a first grain size and a second portion having a second grain size different from the first grain size; an insulating core located within the channel layer at a height corresponding to the second portion; and a capping layer located on the insulating core at a height corresponding to the first portion.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include: forming a stack by alternately stacking a first material layer and a second material layer; forming a channel hole extending through the stack; forming a preliminary channel layer in the channel hole; forming a first channel layer by crystallizing a first portion of the preliminary channel layer; doping the first channel layer and the preliminary channel layer with metal atoms; forming a second channel layer by crystallizing a second portion of the preliminary channel layer; forming an insulating core inside the first channel layer and the second channel layer; and forming a capping layer on the insulating core. Attached Figure Description

[0006] Figure 1A and Figure 1B This is a diagram used to describe a semiconductor device according to an embodiment.

[0007] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A and Figure 9B This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment.

[0008] Figure 10 This is a diagram used to describe a semiconductor device according to an embodiment.

[0009] Figure 11 This is a diagram used to describe a semiconductor device according to an embodiment.

[0010] Figure 12 This is a diagram used to describe a semiconductor device according to an embodiment. Detailed Implementation

[0011] Various implementations relate to semiconductor devices with stable structures and improved properties, as well as methods for manufacturing semiconductor devices.

[0012] According to this technology, semiconductor devices with stable structures and improved reliability can be provided.

[0013] In the following description, embodiments based on the technical spirit of this disclosure are described with reference to the accompanying drawings.

[0014] Figure 1A and Figure 1B This is a diagram used to describe a semiconductor device according to an embodiment. Figure 1A It is a cross-sectional view, and Figure 1B yes Figure 1A A magnified view of region A.

[0015] Reference Figure 1A and Figure 1B The semiconductor device may include a gate structure 110 and a channel structure CH.

[0016] The gate structure 110 may include alternating layers of insulating layers 110A and conductive layers 110B. Insulating layer 110A may include an uppermost insulating layer 110A2 and the remaining insulating layers 110A1. Here, the uppermost insulating layer 110A2 may be thicker than the remaining insulating layers 110A1. Each insulating layer 110A may comprise an insulating material such as an oxide. Each conductive layer 110B may comprise a conductive material such as tungsten, molybdenum, or polysilicon.

[0017] The conductive layer 110B can be a gate line such as a source select line, word line, and drain select line. Source select transistors, memory cells, or drain select transistors can be located in the region where the channel structure CH and the conductive layer 110B intersect each other. For example, at least one source select transistor, multiple memory cells, and at least one drain select transistor stacked along the channel structure CH can constitute a memory string.

[0018] The channel structure CH can extend through the gate structure 110. Each channel structure CH may include at least one of a channel layer 120, a memory layer 130, an insulating core 140, and a capping layer 150.

[0019] The channel layer 120 may include a first portion 120A and a second portion 120B located below the first portion 120A. Here, the boundary between the first portion 120A and the second portion 120B may be located at the height between the upper surface and the lower surface of the uppermost insulating layer 110A2.

[0020] The first portion 120A and the second portion 120B may comprise substantially the same material or different materials. For example, the first portion 120A and the second portion 120B may each comprise polycrystalline silicon. Here, the first portion 120A may comprise polycrystalline silicon without metal silicides, and the second portion 120B may comprise polycrystalline silicon containing metal silicides. Here, the metal silicide may comprise nickel silicide (NiSi2). This is because the first portion 120A and the second portion 120B may be formed in different ways in the process of forming the channel layer 120.

[0021] The first portion 120A and the second portion 120B may include metal atoms 160 of different concentrations. For example, the first portion 120A may include metal atoms 160 of a first concentration. The second portion 120B may include metal atoms 160 of a second concentration different from the first concentration. Here, the first concentration may be lower than the second concentration. Metal atoms 160 may include nickel (Ni) atoms. This is because, during the process of forming the channel layer 120, metal atoms 160 of the first portion 120A can migrate to the region of the second portion 120B.

[0022] However, this disclosure is not limited thereto, and the first portion 120A and / or the second portion 120B may not include metal atoms 160. For example, the first portion 120A may not include metal atoms, and the second portion 120B may include metal atoms 160 at a second concentration.

[0023] The first portion 120A may have a first grain size. The second portion 120B may have a second grain size different from the first grain size. Here, the second grain size may be larger than the first grain size. This is because, in the process of forming the channel layer 120, metal atoms 160 of the first portion 120A can move to the region of the second portion 120B and react with amorphous silicon to form a metal silicide, and the second portion 120B is formed while the amorphous silicon crystallizes with the metal silicide as a nucleus. Therefore, the second portion 120B can have a relatively larger grain size than the first portion 120A, and thus, current can flow smoothly in the second portion 120B.

[0024] Memory layer 130 may surround channel layer 120. Memory layer 130 may include multiple layers. For example, memory layer 130 may include a tunneling layer, a data storage layer, and a barrier layer. Here, the tunneling layer and the barrier layer may each include oxides, and the data storage layer may include a floating gate, a nitride layer, a variable resistance layer, etc.

[0025] The insulating core 140 may be located inside the channel layer 120. For example, the insulating core 140 may be located at a height corresponding to the second portion 120B of the channel layer 120. The insulating core 140 may comprise an insulating material such as an oxide.

[0026] A cleaning process can be used to form the insulating core 140, and a dry cleaning method can be implemented as the cleaning process. When the channel layer 120 comprises polycrystalline silicon containing metal silicides, metal atoms 160 can accumulate near the upper surface of the channel layer 120. In this case, when a dry cleaning method is used to form the insulating core 140, the upper surface of the channel layer 120 may be damaged.

[0027] According to embodiments of this disclosure, the first portion 120A may correspond to the vicinity of the upper surface of the channel layer 120 and may comprise polysilicon that does not contain metal silicides. In this case, even if a dry cleaning method is used to form the insulating core 140, damage to the upper surface of the channel layer 120 can be prevented or mitigated.

[0028] The capping layer 150 may be inside the channel layer 120. The capping layer 150 may be on the insulating core 140. For example, the boundary between the capping layer 150 and the insulating core 140 may be located at the height between the upper and lower surfaces of the uppermost insulating layer 110A2. The capping layer 150 may be located at a height corresponding to the first portion 120A of the channel layer 120. The capping layer 150 may include polysilicon, etc.

[0029] exist Figure 1A and Figure 1BThe illustration depicts a case where the boundary between the first portion 120A and the second portion 120B of the channel layer 120 lies at a height between the upper and lower surfaces of the uppermost insulating layer 110A2, but this disclosure is not limited thereto. For example, the boundary between the first portion 120A and the second portion 120B of the channel layer 120 may converge on the upper surface of the uppermost insulating layer 110A2. In this case, the channel layer 120 may include a very small first portion 120A, and the channel layer 120 may exist primarily as the second portion 120B. However, even in this case, the positions of the insulating core 140 and the cover layer 150 may remain unchanged.

[0030] According to the above structure, the channel layer 120 may include a first portion 120A and a second portion 120B, wherein the first portion 120A comprises polysilicon without metal silicide, and the second portion 120B comprises polysilicon containing metal silicide. Therefore, in the process of manufacturing a semiconductor device, damage to the first portion 120A of the channel layer 120 can be prevented or damage can be mitigated.

[0031] Furthermore, the first portion 120A may have a first grain size, and the second portion 120B may have a second grain size larger than the first grain size. Therefore, current can flow more smoothly in the second portion 120B.

[0032] Figures 2 to 8 , Figure 9A and Figure 9B This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment. Figure 2 and Figure 9A It is a cross-sectional view. Figures 3 to 8 yes Figure 2 An enlarged view of region B in the subsequent process, and Figure 9B yes Figure 9A A magnified view. The content already described will not be repeated in the following text.

[0033] Reference Figure 2 The laminate 210S can be formed by alternately stacking a first material layer 210A and a second material layer 210B. The first material layer 210A may include an uppermost first material layer 210A2 and the remaining first material layer 210A1. The second material layer 210B may include an uppermost second material layer 210B2 and the remaining second material layer 210B1. Here, the uppermost second material layer 210B2 may be a sacrificial layer. Each of the first material layers 210A may comprise an insulating material such as an oxide, and each of the second material layers 210B may comprise a sacrificial material such as a nitride.

[0034] A channel hole CHH extending through the laminate 210S can be formed. For example, a channel hole CHH penetrating the laminate 210S can be formed.

[0035] Reference Figure 3 A memory layer 220 can be conventionally formed in the channel via CHH. Here, the memory layer 220 can be multi-layered. For example, the memory layer 220 can be formed by sequentially forming a barrier layer, a data storage layer, and a tunneling layer.

[0036] Subsequently, a preliminary channel layer 230S can be formed in the channel via CHH. For example, the preliminary channel layer 230S can be conformally formed on the memory layer 220. The preliminary channel layer 230S may include amorphous silicon.

[0037] Reference Figure 4 The first trench layer 230A can be formed by crystallizing a portion of the preliminary trench layer 230S into S1. For example, it can be formed by laser annealing. Figure 3 The first portion of the preliminary channel layer 230S shown is crystallized to form the first channel layer 230A. Here, the first portion of the preliminary channel layer 230S may refer to the upper part of the preliminary channel layer 230S. In this case, the first channel layer 230A may comprise polycrystalline silicon formed by crystallizing amorphous silicon. Here, the boundary between the first channel layer 230A and the preliminary channel layer 230S may be between the upper surface and the lower surface of the uppermost first material layer 210A2. However, this disclosure is not limited thereto, and the boundary between the first channel layer 230A and the preliminary channel layer 230S may be between the upper surface and the lower surface of the uppermost second material layer 210B2.

[0038] Reference Figure 5 The first channel layer 230A and the preliminary channel layer 230S can be doped with metal atoms 240 (S2). For example, metal atoms 240 can be adsorbed onto the surfaces of the first channel layer 230A and the preliminary channel layer 230S by depositing a metal layer via chemical vapor deposition (CVD). In other words, the first channel layer 230A and the preliminary channel layer 230S can be doped with precursors of metal atoms 240 via chemical vapor deposition, and volatile byproducts can be volatilized, so that only metal atoms 240 are adsorbed onto the surfaces of the first channel layer 230A and the preliminary channel layer 230S. When a second channel layer is formed in a subsequent process, the metal atoms 240 can increase the grain size of the second channel layer and improve current flow. Here, the metal atoms 240 may include nickel atoms.

[0039] Reference Figure 6 The second channel layer 230B can be formed by crystallizing the second portion of the initial channel layer 230S. For example, the second channel layer 230B can be formed by annealing the initial channel layer 230S for S3. Here, the annealing can be hot annealing, and the second portion of the initial channel layer 230S can refer to the lower part of the initial channel layer 230S.

[0040] When the preliminary channel layer 230S is crystallized, metal atoms 240 can move into the first channel layer 230A and the preliminary channel layer 230S. When the preliminary channel layer 230S crystallizes, metal atoms 240 can move from the first channel layer 230A to the preliminary channel layer 230S, allowing the preliminary channel layer 230S to crystallize to form the second channel layer 230B.

[0041] When the initial channel layer 230S crystallizes, metal atoms 240 can move in the direction where the crystallization energy is low. For example, because nickel atoms may not react with polycrystalline silicon to form nickel silicide, they may not react with polycrystalline silicon. In other words, because nickel atoms can react with amorphous silicon to form nickel silicide (NiSi2), nickel atoms can have the lowest free energy at the boundary between amorphous silicon and nickel silicide, and can have a low crystallization energy. On the other hand, the crystallization energy in the first channel layer 230A may be higher. Therefore, nickel atoms can move from the first channel layer 230A to the initial channel layer 230S.

[0042] When the initial channel layer 230S crystallizes, silicon atoms can move in the direction where the crystallization energy is low. For example, silicon atoms can have the lowest free energy and low crystallization energy at the boundary between polycrystalline silicon and nickel silicide (NiSi2). Therefore, silicon atoms can move from the initial channel layer 230S to the first channel layer 230A.

[0043] In other words, nickel atoms can move from the first channel layer 230A to the preliminary channel layer 230S, and silicon atoms can move from the preliminary channel layer 230S to the first channel layer 230A. In this case, nickel and silicon atoms can react with each other to form nickel silicide, and the preliminary channel layer 230S can form the second channel layer 230B while crystallizing with nickel silicide as a nucleus. Therefore, the first channel layer 230A may include metal atoms 240 at a lower concentration than the second channel layer 230B. Alternatively, the first channel layer 230A may not include metal atoms 240.

[0044] When the second channel layer 230B is formed by metal atoms 240, the grain size of the second channel layer 230B can be larger than the grain size of the first channel layer 230A. For example, the grain size of the second channel layer 230B formed by forming nickel silicide with nickel atoms and crystallizing the initial channel layer 230S using nickel silicide as a nucleus can be larger than the grain size of the first channel layer 230A formed by partially crystallizing the initial channel layer 230S by laser annealing. In this case, the grain size of the second channel layer 230B is relatively large, and therefore, the current can flow smoothly.

[0045] Reference Figure 7 The getter layer 260 can be formed on the first channel layer 230A and the second channel layer 230B. For example, the getter layer 260 can be conformally formed over the first channel layer 230A and the second channel layer 230B. Here, the getter layer 260 can include amorphous silicon or silicon nitride. For example, the getter layer 260 can include Si3N4.

[0046] Subsequently, metal atoms 240 in the first channel layer 230A and the second channel layer 230B can be removed through the getter layer 260. For example, the metal atoms 240 in the first channel layer 230A and the second channel layer 230B can be moved to the getter layer 260 by annealing the first channel layer 230A and the second channel layer 230B. In the process of removing metal atoms 240 in the first channel layer 230A and the second channel layer 230B using the getter layer 260, high-temperature thermal annealing can be used. For example, metal atoms 240 in the first channel layer 230A and the second channel layer 230B can be moved to the getter layer 260 and removed by annealing the first channel layer 230A and the second channel layer 230B at a high temperature of 700°C or higher. When there are no metal atoms 240 in the first channel layer 230A, only the metal atoms 240 present in the second channel layer 230B can be removed.

[0047] For reference, the process of removing S4 metal atoms 240 can be repeated until all metal atoms 240 in the first channel layer 230A and the second channel layer 230B are removed. However, this disclosure is not limited thereto, and even if the process of removing S4 metal atoms 240 is repeated, some metal atoms 240 may remain in the first channel layer 230A and the second channel layer 230B.

[0048] According to embodiments of this disclosure, metal atoms 240 can be used to smooth current flow by increasing the grain size of the second channel layer 230B. Additionally, getter layer 260 can be used to remove metal atoms 240 from the first channel layer 230A and the second channel layer 230B.

[0049] Before forming the getter layer 260, a buffer layer 250 may be formed on the first channel layer 230A and the second channel layer 230B. The buffer layer 250 may include a material different from the getter layer 260. The buffer layer 250 may include a material selective relative to phosphoric acid. The buffer layer 250 may include silicon carbonitride or silicon carbonate. For example, the buffer layer 250 may include SiCN or SiCO.

[0050] Subsequently, the getter layer 260 can be removed. For example, phosphoric acid can be used to remove the getter layer 260. A buffer layer 250 can be formed between the channel layers 230A and 230B and the getter layer 260 to protect the channel layers 230A and 230B during the process of removing the getter layer 260. For example, when the buffer layer 250 is not present, the first channel layer 230A, comprising polysilicon, may be damaged during the removal of the getter layer 260. According to embodiments of this disclosure, the buffer layer 250 may comprise a material selective relative to phosphoric acid, and thus can prevent the channel layers 230A and 230B from being damaged during the process of removing the getter layer 260.

[0051] Subsequently, the buffer layer 250 can be removed. First, an oxide layer can be formed by oxidizing the buffer layer 250. Then, the oxidized buffer layer 250 can be removed with hydrogen fluoride.

[0052] Reference Figure 8 An insulating core 270 can be formed. First, a preliminary insulating core 270S can be formed on the first channel layer 230A and the second channel layer 230B. The preliminary insulating core 270S can be formed to fill the interior portion of the channel hole CHH. Subsequently, the insulating core 270 can be formed by removing a portion of the preliminary insulating core 270S up to a height corresponding to the boundary between the first channel layer 230A and the second channel layer 230B. Here, a dry cleaning method can be used.

[0053] Annealing can be performed on the initial channel layer during the formation of the channel layer. In this process, metal silicides and metal silicide clusters can be formed in the channel layer. Subsequently, in a process of removing metal atoms from the channel layer using a getter layer, the metal silicides and metal silicide clusters can be retained. Then, a dry cleaning method can be used in the process of forming the insulating core. When metal silicides and metal silicide clusters remain near the upper surface of the channel layer, silicon atoms may aggregate, and the area near the upper surface of the channel layer may be damaged during the dry cleaning process.

[0054] According to embodiments of this disclosure, a first channel layer 230A corresponding to the vicinity of the upper surface of the channel layer can be formed before the formation of the second channel layer 230B. For example, the first channel layer 230A can be formed by targeting a portion of the preliminary channel layer 230S and partially crystallizing the preliminary channel layer 230S by laser annealing. Here, the first channel layer 230A may comprise polycrystalline silicon formed by crystallizing amorphous silicon. Subsequently, the first channel layer 230A and the preliminary channel layer 230S may be doped with metal atoms 240. Subsequently, in the process of annealing the preliminary channel layer 230S to form the second channel layer 230B, the metal atoms 240 in the first channel layer 230A may migrate to the preliminary channel layer 230S corresponding to the portion that will become the second channel layer 230B. In other words, the first channel layer 230A may not contain metal atoms 240, or may contain metal atoms 240 at a relatively lower concentration than those in the second channel layer 230B.

[0055] In this case, metal silicide clusters may not form in the first channel layer 230A corresponding to the upper surface of the channel layer, the amount of metal silicide clusters may be reduced, or silicon atoms may not aggregate. Therefore, even if a dry cleaning method is used in the process of forming the insulating core 270, the first channel layer 230A may not be damaged.

[0056] Reference Figure 9A and Figure 9B A capping layer 280 can be formed on the insulating core 270. First, a preliminary capping layer 280S can be formed on the insulating core 270. The preliminary capping layer 280S can be formed to fill the internal portion of the channel via CHH. Subsequently, the preliminary capping layer 280S can be planarized S6 until the uppermost first material layer 210A2 is exposed. For example, the preliminary capping layer 280S and the uppermost second material layer 210B2 can be planarized until the uppermost first material layer 210A2 is exposed. Therefore, the capping layer 280 can be formed. Here, the capping layer 280 may include polysilicon, etc.

[0057] Subsequently, the remaining second material layer 210B1 of the stack 210 can be replaced with a third material layer 210C. The remaining second material layer 210B1 can be removed by extending through a slit (not shown) through the stack 210, and the third material layer 210C can be formed. Here, each of the third material layers 210C may comprise a conductive material such as tungsten. Therefore, a gate structure 210G comprising alternating layers of first material layers 210A and third material layers 210C can be formed. When the remaining second material layers 210B1 each comprise a conductive material, the replacement process can be omitted. In this case, the stack 210 can be used as the gate structure 210G.

[0058] For reference, the case where the first channel layer 230A is retained has been described in this embodiment, but the first channel layer 230A can be removed during the process of forming the cover layer 280. For example, the first channel layer 230A and the second channel layer 230B can be formed as is, the insulating core 270 can be formed such that its upper surface is lower than the lower surface of the uppermost first material layer 210A2, and the preliminary cover layer 280S can be planarized until the first channel layer 230A is removed. In this case, the channel layer can consist of only the second channel layer 230B.

[0059] According to the manufacturing method described above, a first channel layer 230A adjacent to the upper surface of the channel layer can be formed first. In other words, the first channel layer 230A can be formed by partially crystallizing the preliminary channel layer 230S. In this case, in subsequent processes, the first channel layer 230A may not include metal atoms 240, and metal silicide clusters may be absent in the first channel layer 230A, or the amount of metal silicide clusters may be reduced and silicon atoms may not aggregate. Therefore, even if a dry cleaning method is used in the process of forming the insulating core 270, the first channel layer 230A can remain undamaged.

[0060] Figure 10 This is a diagram used to illustrate a semiconductor device according to an embodiment. The content already described will not be repeated below.

[0061] Reference Figure 10 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on the same substrate.

[0062] The substrate SUB may include a semiconductor material. As an example, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0063] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. As an example, the substrate SUB may include graphene.

[0064] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be in a single-crystal, polycrystalline, or amorphous state. The substrate SUB can include Group II, III, IV, V, or VI impurities. As an example, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0065] The peripheral circuitry PC can be located between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. As an example, the peripheral circuitry PC may include one or more of N-channel metal-oxide-semiconductor (NMOS) transistors, P-channel metal-oxide-semiconductor (PMOS) transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wiring, etc.

[0066] A memory cell array (CA) may include memory cells. As an example, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. As an example, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0067] Figure 11 This is a diagram used to illustrate a semiconductor device according to an embodiment. The content already described will not be repeated below.

[0068] Reference Figure 11 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded to each other. The semiconductor device may also include a support substrate SP_B.

[0069] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support substrate SP_B can be used as a support in the process of forming the memory cell array CA. As an example, a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC can be fabricated and then electrically connected to each other via a bonding structure BS. After the first wafer and the second wafer are bonded together, the support substrate SP_B of the first wafer can be at least partially removed. The support substrate SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0070] The supporting substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The supporting substrate SP_B can be a bulk wafer, an epitaxial layer grown by selective epitaxial growth (SEG), or a layer formed by metal-induced lateral crystallization (MILC). The supporting substrate SP_B can be in a single-crystal, polycrystalline, or amorphous state. The supporting substrate SP_B can include Group II, III, IV, V, or VI impurities.

[0071] A bonding structure (BS) can be used to connect a memory cell array (CA) and peripheral circuitry (PC) to each other. As an example, the bonding structure BS can bond the memory cell array (CA) and peripheral circuitry (PC) to each other using wafer-to-wafer bonding, wafer-to-chip bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding interfaces, etc. Bonding pads may include metals such as copper, aluminum, and / or their alloys. Bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array (CA) and peripheral circuitry (PC) can be electrically connected to each other through the bonding structure BS.

[0072] For reference, interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can also be used as bonding structures (BS). As an example, interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly bonded to each other. In this case, bit lines, source lines, etc., can be used as bonding structures without separate bonding pads.

[0073] Other configurations can be found in the above text. Figure 10 The configurations described are the same or similar.

[0074] Semiconductor devices may also have the above-mentioned references. Figure 10 and Figure 11 The described embodiments are structures that are combined with each other or structures with partial modifications. (Refer to...) Figure 10 and Figure 11 In the described implementation, the positions of the memory cell array CA and the peripheral circuitry PC can be changed. (Refer to...) Figure 10 In the described implementation, at least one memory cell array CA and / or at least one peripheral circuit PC may be additionally coupled to each other. As an example, a portion of the peripheral circuit PC may be in the memory cell array CA.

[0075] Figure 12 This is a diagram used to illustrate a semiconductor device according to an embodiment. The content already described will not be repeated below.

[0076] Reference Figure 12The semiconductor device may include a substrate 1200, peripheral circuit PC, source structure SS, bonding structure 1220, stacked component 1230S, gate structure 1230G, channel structure CH, through plug 1250, support component 1260, first contact via 1270, second contact via 1280, component isolation layer ISO, first interconnect structure IC1, second interconnect structure IC2, third interconnect structure IC3, first interlayer insulating layer IL1, second interlayer insulating layer IL2 and third interlayer insulating layer IL3.

[0077] The peripheral circuit PC can be on the substrate 1200. The peripheral circuit PC can include a transistor 1. The transistor 1 can include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. The component isolation layer ISO can be in the substrate 1200, and the active region of the transistor 1 can be defined by the component isolation layer ISO.

[0078] The first interconnect structure IC1 can be on the peripheral circuit PC. The first interconnect structure IC1 can be in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be on the substrate 1200. The first interconnect structure IC1 may include a first via 1210A and a first wiring 1210B. The first interconnect structure IC1 may include a conductive material such as tungsten. The first interlayer insulating layer IL1 may include an insulating material such as an oxide or nitride.

[0079] The bonding structure 1220 may be located above the peripheral circuit PC. For example, the bonding structure 1220 may be located on the first interconnect structure IC1. The bonding structure 1220 may include a first bonding pad 1220A and a second bonding pad 1220B. The first bonding pad 1220A may be located in a first interlayer insulating layer IL1. The second bonding pad 1220B may be located on the first bonding pad 1220A and may also be located in a second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be located on the first interlayer insulating layer IL1. The bonding structure 1220 may include a conductive material such as copper. The second interlayer insulating layer IL2 may include an insulating material such as oxide.

[0080] The second interconnect structure IC2 may be on the bonding structure 1220. The second interconnect structure IC2 may be in the second interlayer insulating layer IL2. The second interconnect structure IC2 may include a second via 1210C and a second wiring 1210D. The second interconnect structure IC2 may be connected to the bonding structure 1220. For example, at least one of the second vias 1210C may be connected to a second bonding pad 1220B. The second interconnect structure IC2 may include a conductive material such as tungsten.

[0081] The stack 1230S may be above the bonding structure 1220. For example, the stack 1230S may be on the second interconnect structure IC2. The stack 1230S may include alternating layers of insulating layer 1230A and sacrificial layer 1230B. The gate structure 1230G may be located at a height corresponding to the stack 1230S. The gate structure 1230G may include alternating layers of insulating layer 1230A and conductive layer 1230C. The gate structure 1230G may include an inverted stepped structure in which the lower surface of the conductive layer 1230C is exposed.

[0082] For ease of explanation, the terms "upper" and "lower" can be relative concepts. For example, gate structure 1230G may include a stepped structure in which the upper surface of conductive layer 1230C is exposed. Figure 12 The diagram already illustrates the state in which the gate structure 1230G is rotated. In other words, the gate structure 1230G, including the inverted stepped structure, has already been... Figure 12 Example in.

[0083] The through-plug 1250 may extend through the laminate 1230S and into the second interlayer insulating layer IL2. The through-plug 1250 may be electrically connected to the peripheral circuit PC via the bonding structure 1220. For example, the through-plug 1250 may be connected to the bonding structure 1220 via the second interconnect structure IC2, and may also be electrically connected to the peripheral circuit PC via the bonding structure 1220. The through-plug 1250 may include a conductive material such as tungsten. However, this disclosure is not limited thereto, and the through-plug 1250 may be a support and may include an insulating material such as oxide.

[0084] The channel structure CH can extend through the gate structure 1230G and into the source structure SS. Here, the source structure SS can be on the gate structure 1230G. Each channel structure CH may include at least one of a channel layer 1240A, a memory layer 1240B surrounding the channel layer 1240A, an insulating core 1240C inside the channel layer 1240A, and a capping layer 1240D on the insulating core 1240C. Here, the channel layer 1240A can be connected to the source structure SS.

[0085] For reference, the channel structure CH can be related to Figure 1A and Figure 1B The channel structure CH corresponds to the channel layer 1240A, memory layer 1240B, insulating core 1240C, and cover layer 1240D, respectively. Figure 1A and Figure 1B The channel layer 120, memory layer 130, insulating core 140 and cover layer 150 correspond to each other.

[0086] The support member 1260 may extend through the gate structure 1230G and into the third interlayer insulating layer IL3. Here, the third interlayer insulating layer IL3 may be on the gate structure 1230G and / or the stack-up 1230S. Each support member 1260 may comprise an insulating material such as an oxide. The third interlayer insulating layer IL3 may comprise an insulating material such as an oxide.

[0087] The first contact vias 1270 can be connected to the conductive layer 1230C of the gate structure 1230G. For example, the first contact vias 1270 can extend into the second interlayer insulating layer IL2 and be connected to the conductive layer 1230C exposed on its lower surface via the inverted step structure of the gate structure 1230G. Each of the first contact vias 1270 can comprise a conductive material such as tungsten.

[0088] The second contact via 1280 can be connected to the channel structure CH. For example, the second contact via 1280 can extend into the second interlayer insulating layer IL2 and can be connected to the channel layer 1240A of the channel structure CH. The second contact via 1280 can each include a conductive material such as tungsten.

[0089] The third interconnect structure IC3 may be located within the third interlayer insulating layer IL3. The third interconnect structure IC3 may include a third via 1210E and a third wiring 1210F. At least one of the third vias 1210E may be connected to the first contact via 1270. At least one of the third vias 1210E may be connected to the source structure SS. At least one of the third wirings 1210F may be connected to the third via 1210E. The third interconnect structure IC3 may include a conductive material such as tungsten.

[0090] According to the above structure, the semiconductor device may include a bonding structure 1220. The bonding structure 1220 may be located above the peripheral circuit PC and may be electrically connected to the peripheral circuit PC.

[0091] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is only for explaining embodiments based on the concept of this disclosure, and this disclosure is not limited to the above embodiments. Various substitutions, modifications, and alterations of various types can be made to the embodiments by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the appended claims, and such substitutions, modifications, and alterations should be construed as falling within the scope of this disclosure.

[0092] Cross-reference to related applications

[0093] This application claims priority to Korean Patent Application No. 10-2024-0138767, filed on October 11, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of insulating and conductive layers; A channel layer extending through the gate structure, the channel layer comprising a first portion and a second portion, the first portion comprising a first concentration of metal atoms, and the second portion comprising a second concentration of metal atoms different from the first concentration; An insulating core, the insulating core being located inside the channel layer; as well as A covering layer, the covering layer being on the insulating core, The first portion is on the second portion, and the boundary between the first portion and the second portion is between the upper and lower surfaces of the uppermost insulating layer in the insulating layer.

2. The semiconductor device according to claim 1, wherein, The covering layer is at a height corresponding to the first portion, and The insulating core is at a height corresponding to the second part.

3. The semiconductor device according to claim 1, wherein, The first concentration is lower than the second concentration.

4. The semiconductor device according to claim 1, wherein, The first portion has a first grain size, and The second portion has a second grain size that is different from the first grain size.

5. The semiconductor device according to claim 4, wherein, The second grain size is larger than the first grain size.

6. The semiconductor device according to claim 1, wherein, The first portion comprises polycrystalline silicon that does not contain metal silicides, and The second part includes polycrystalline silicon containing metal silicides.

7. The semiconductor device according to claim 6, wherein, The metal silicide includes nickel silicide.

8. The semiconductor device according to claim 1, wherein, The metal atoms include nickel atoms.

9. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of insulating and conductive layers; A channel layer extending through the gate structure, the channel layer including a first portion having a first grain size and a second portion having a second grain size different from the first grain size; An insulating core, wherein the insulating core is located within the channel layer at a height corresponding to the second portion; as well as A cover layer, which is located on the insulating core at a height corresponding to the first portion.

10. The semiconductor device according to claim 9, wherein, The boundary between the first part and the second part is between the upper and lower surfaces of the uppermost insulating layer in the insulating layer.

11. The semiconductor device according to claim 9, wherein, The second grain size is larger than the first grain size.

12. The semiconductor device according to claim 9, wherein, The first portion comprises a first concentration of metal atoms, and The second part includes metal atoms of a second concentration that is different from the first concentration.

13. The semiconductor device according to claim 12, wherein, The first concentration is lower than the second concentration.

14. The semiconductor device according to claim 12, wherein, The metal atoms include nickel atoms.

15. The semiconductor device according to claim 9, wherein, The first portion comprises polycrystalline silicon that does not contain metal silicides, and The second part includes polycrystalline silicon containing metal silicides.

16. The semiconductor device according to claim 15, wherein, The metal silicide includes nickel silicide.

17. A method for manufacturing a semiconductor device, the method comprising the following steps: A laminate is formed by alternately stacking a first material layer and a second material layer; Forming channel holes that extend through the laminate; A preliminary channel layer is formed in the channel holes; The first channel layer is formed by crystallizing a first portion of the preliminary channel layer; The first channel layer and the preliminary channel layer are doped with metal atoms; The second trench layer is formed by crystallizing a second portion of the initial trench layer; An insulating core is formed inside the first trench layer and the second trench layer; as well as A covering layer is formed on the insulating core.

18. The manufacturing method according to claim 17, wherein, The step of forming the first channel layer includes selectively crystallizing the first portion of the preliminary channel layer such that the boundary between the first channel layer and the preliminary channel layer lies between the upper and lower surfaces of the uppermost first material layer in the first material layer.

19. The manufacturing method according to claim 18, wherein, The initial channel layer comprises amorphous silicon, and The first channel layer comprises polycrystalline silicon that does not contain metal silicides.

20. The manufacturing method according to claim 19, wherein, The metal silicide includes nickel silicide.

21. The manufacturing method according to claim 17, wherein, The step of doping the first channel layer and the preliminary channel layer with the metal atoms includes: adsorbing the metal atoms onto the surface of the first channel layer and the preliminary channel layer by depositing a metal layer via a chemical vapor deposition (CVD) method.

22. The manufacturing method according to claim 21, wherein, The step of crystallizing the first portion of the preliminary channel layer includes moving the metal atoms into the first channel layer and the preliminary channel layer.

23. The manufacturing method according to claim 17, wherein, The step of crystallizing the second portion of the preliminary channel layer includes: moving the metal atoms from the first channel layer to the second portion of the preliminary channel layer, such that the second portion of the preliminary channel layer is crystallized.

24. The manufacturing method according to claim 17, wherein, The initial channel layer comprises amorphous silicon, and The second channel layer comprises polycrystalline silicon containing metal silicides.

25. The manufacturing method according to claim 24, wherein, The metal silicide includes nickel silicide.

26. The manufacturing method according to claim 17, further comprising the following step: A getter layer is formed on the first channel layer and the second channel layer; The getter layer removes the metal atoms from the first channel layer and the second channel layer; as well as Remove the getter layer.

27. The manufacturing method according to claim 26, wherein, The step of removing the metal atoms includes annealing the first channel layer and the second channel layer so that the metal atoms in the first channel layer and the second channel layer move to the getter layer.

28. The manufacturing method according to claim 26, wherein, The step of removing the getter layer includes removing the getter layer with phosphoric acid.

29. The manufacturing method according to claim 26, wherein, The getter layer comprises amorphous silicon or silicon nitride.

30. The manufacturing method according to claim 26, further comprising the following step: Before forming the getter layer, a buffer layer is formed on the first channel layer and the second channel layer; as well as The buffer layer is removed after the getter layer is removed.

31. The manufacturing method according to claim 30, wherein, The buffer layer comprises a material that is selective relative to phosphoric acid.

32. The manufacturing method according to claim 31, wherein, The buffer layer comprises silicon carbonitride or silicon carbonate.

33. The manufacturing method according to claim 30, wherein, The step of removing the buffer layer includes the following steps: Oxidize the buffer layer; and The oxidized buffer layer is removed with hydrogen fluoride.

34. The manufacturing method according to claim 17, wherein, The step of forming the insulating core includes forming a preliminary insulating core on the first trench layer and the second trench layer.

35. The manufacturing method according to claim 34, wherein, The step of forming the insulating core includes removing the preliminary insulating core via a dry cleaning method up to a height corresponding to the boundary between the first trench layer and the second trench layer.

36. The manufacturing method according to claim 17, wherein, The metal atoms include nickel atoms.

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