Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate and a gate structure, the gate structure comprises an insulating layer, a floating gate, a dielectric layer and a control gate which are stacked on the substrate, the floating gate is provided with a first surface and a second surface which are opposite to each other, and the dielectric layer is arranged on the first surface. The first surface is attached to the insulating layer, the second surface is attached to the bottom surface of the dielectric layer, the top surface, opposite to the bottom surface, of the dielectric layer is attached to the third surface of the control grid electrode, and the second surface is parallel to the third surface; the second surface and the third surface are not parallel to the projection plane of the floating gate and the projection plane of the control gate on the substrate. According to the technical scheme, the overlapping area between the floating gate and the control gate can be increased, so that the gate coupling ratio can be improved, the operation voltage is reduced, the device speed is increased, and the electrical performance is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In flash memory devices, two gates are typically stacked: one gate is a floating gate (FG) formed of polysilicon to store charge, and the other gate is a control gate (CG) used to control information access. The floating gate is generally located below the control gate and close to the substrate, and a dielectric layer is disposed between the control gate and the floating gate.

[0003] One of the key characteristics of flash memory devices is the gate coupling ratio between the floating gate and the control gate, which affects the operating voltage and device speed. Increasing the gate coupling ratio can reduce the operating voltage while simultaneously increasing the device speed. The gate coupling ratio is defined as the ratio of the induced voltage of the floating gate to the applied voltage of the control gate. Therefore, in related technologies, the gate coupling ratio can be improved by increasing the overlap area between the floating gate and the control gate, reducing the dielectric layer thickness between the floating gate and the control gate, and increasing the dielectric constant of the dielectric layer between the floating gate and the control gate. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor device and a method for fabricating the same. Compared with related technologies, the semiconductor device has a larger overlap area between the floating gate and the control gate, which can improve the gate coupling ratio, effectively reduce the operating voltage, and simultaneously increase the device speed and improve electrical performance.

[0005] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor device is provided, comprising: A substrate; and a gate structure comprising an insulating layer, a floating gate, a dielectric layer, and a control gate stacked on the substrate, the floating gate having opposing first and second surfaces, the first surface being bonded to the insulating layer, the second surface being bonded to the bottom surface of the dielectric layer, the top surface of the dielectric layer opposite to the bottom surface being bonded to a third surface of the control gate, the second surface and the third surface being parallel, and neither the second surface nor the third surface being parallel to the projection plane of the floating gate and the control gate on the substrate.

[0006] Optionally, both the second surface and the third surface include a plurality of surfaces connected in sequence, with at least two adjacent surfaces arranged at an included angle.

[0007] Optionally, the plurality of surfaces includes a first surface, a second surface, and a third surface connected in sequence, wherein the first surface and the second surface are arranged at an angle, and the second surface and the third surface are arranged at an angle; or, The plurality of surfaces includes a fourth surface and a fifth surface, which are arranged at an angle to each other.

[0008] Optionally, the floating gate has a first sidewall and a second sidewall located between and opposite the first surface and the second surface, neither of which is in contact with the dielectric layer.

[0009] According to a second aspect of this disclosure, a method for fabricating a semiconductor device is provided, the semiconductor device comprising: Substrate; and A gate structure includes an insulating layer, a floating gate, a dielectric layer, and a control gate stacked on a substrate. The floating gate has a first surface and a second surface opposite to each other. The first surface is attached to the insulating layer, the second surface is attached to the bottom surface of the dielectric layer, and the top surface of the dielectric layer opposite to the bottom surface is attached to a third surface of the control gate. The second surface and the third surface are parallel, and neither the second surface nor the third surface is parallel to the projection plane of the floating gate and the control gate on the substrate. The method includes: Provide the substrate; The gate structure is formed on the substrate.

[0010] Optionally, forming the gate structure on the substrate includes: The insulating layer is disposed on the surface of the substrate; The floating gate layer is disposed on the surface of the insulating layer; The floating gate layer is processed to form the floating gate having the second surface; The dielectric layer is disposed on the second surface; The control gate is disposed on the top surface of the dielectric layer opposite to the floating gate; The control gate, the dielectric layer, the floating gate, and the insulating layer are etched to form the gate structure.

[0011] Optionally, processing the floating gate layer to form the floating gate having the second surface includes: A hard mask layer is disposed on the top surface of the floating gate layer; Etch the floating gate layer to form the floating gate; Remove the hard mask layer.

[0012] Optionally, etching the floating gate layer to form the floating gate includes: Dry etching and / or wet etching are selected based on the shape of the second surface.

[0013] Optionally, selecting dry etching and / or wet etching based on the shape of the second surface includes: The second surface includes a plurality of surfaces connected in sequence, and the extension line of at least one of the surfaces is arranged at an acute or obtuse angle to the first surface; The top surface of the floating gate layer is formed into the second surface by TMAH wet etching, and the floating gate layer is constructed as a single-crystal silicon layer.

[0014] Optionally, selecting dry etching and / or wet etching based on the shape of the second surface includes: The second surface includes a plurality of surfaces connected in sequence, wherein the extension line of any one of the surfaces is arranged at a right angle to the first surface or parallel to the first surface; The top surface of the floating gate layer is formed into the second surface by dry etching, and the floating gate layer is constructed as a crystalline silicon layer.

[0015] The above technical solution, which constructs both the second surface of the floating gate and the third surface of the control gate as non-parallel to their projection surfaces on the substrate, increases the overlap area between the floating gate and the control gate, thereby improving the gate coupling ratio, reducing the operating voltage, increasing device speed, and improving electrical performance. Furthermore, the parallelism of the second and third surfaces enhances the stability of the semiconductor device when it performs its electrical functions.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of an overall structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figures 6 to 15 , Figure 1 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor device provided by an exemplary embodiment of this disclosure; Figures 16 to 23 , Figure 5 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor device provided by an exemplary embodiment of this disclosure; Figures 24 to 27 This is a flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this disclosure.

[0018] Explanation of reference numerals in the attached figures 1. Substrate; 2. Gate structure; 21. Insulating layer; 22. Floating gate; 221. First surface; 222. Second surface; 223. First sidewall; 224. Second sidewall; 23. Dielectric layer; 24. Control gate; 241. Third surface; 3. First surface; 31. Second surface; 32. Third surface; 33. Fourth surface; 34. Fifth surface; 4. Floating gate layer; 41. Seed layer; 5. Control gate layer; 6. Hard mask layer; 7. Photoresist. Detailed Implementation

[0019] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0020] In this disclosure, unless otherwise stated, "inner" and "outer" refer to the interior and exterior of the outline of the corresponding component; "far" and "near" refer to the distance of the corresponding component relative to another component in terms of spatial position. Furthermore, the terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance. When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0021] According to the first aspect of this disclosure, reference to Figures 1 to 23 As shown, this disclosure provides a semiconductor device, which includes a substrate 1 and a gate structure 2. The gate structure 2 includes an insulating layer 21, a floating gate 22, a dielectric layer 23 and a control gate 24 stacked on the substrate 1. The floating gate 22 has a first surface 221 and a second surface 222 opposite to each other. The first surface 221 is attached to the insulating layer 21, and the second surface 222 is attached to the bottom surface of the dielectric layer 23. The top surface of the dielectric layer 23 opposite to the bottom surface is attached to the third surface 241 of the control gate 24. The second surface 222 and the third surface 241 are parallel, and neither the second surface 222 nor the third surface 241 is parallel to the projection surface of the floating gate 22 and the control gate 24 on the substrate 1.

[0022] By employing the above technical solution, where both the second surface 222 of the floating gate 22 and the third surface 241 of the control gate 24 are configured not parallel to their projection surfaces on the substrate 1, the overlap area between the floating gate 22 and the control gate 24 can be increased. This improves the gate coupling ratio, thereby reducing the operating voltage, increasing device speed, and improving electrical performance. Furthermore, the parallelism of the second surface 222 and the third surface 241 enhances the stability of the semiconductor device when it exhibits its electrical performance.

[0023] Specifically, the second surface 222 and the third surface 241 are configured to be non-parallel to the projection surfaces of the floating gate 22 and the control gate 24 on the substrate 1, thereby increasing the overlap area between the floating gate 22 and the control gate 24. (Refer to...) Figures 1 to 5 As shown, this enables in Figures 1 to 5 In the left-right direction, without increasing the size of the floating gate 22 and the control gate 24 in the left-right direction, the area of ​​the second surface 222 and the third surface 241 can be significantly increased. In other words, without increasing the overall size of the gate structure, the area of ​​the second surface 222 and the third surface 241 can be significantly increased.

[0024] Among them, reference Figures 1 to 5 As shown, the projection surface of the floating gate 22 or the control gate 24 onto the substrate 1 can be a horizontal plane along the left-right direction. For example, refer to... Figure 1 , Figures 2 to 5 As shown, both the second surface 222 and the third surface 241 may each include a plurality of surfaces connected in sequence, with at least two adjacent surfaces arranged at an angle. In this way, at least one of the two adjacent surfaces arranged at an angle may not be parallel to the aforementioned projection surface, thereby increasing the overlap area between the floating gate 22 and the control gate 24.

[0025] In some exemplary embodiments, for example, the second surface 222 may include two surfaces connected in sequence, the two surfaces may include a fourth surface 33 and a fifth surface 34, the fourth surface 33 and the fifth surface 34 may be arranged at an angle, the included angle may be selected according to actual needs to be adaptively constructed as an acute angle, a right angle or an obtuse angle.

[0026] In some of these embodiments, reference is made to Figure 3As shown, the fourth surface 33 and the fifth surface 34 may not be parallel to the aforementioned projection plane. In this case, the fourth surface 33 and the fifth surface 34 may form an acute angle. Of course, the fourth surface 33 and the fifth surface 34 can also be adapted to be a right angle or an obtuse angle. For example, when the dimension of the floating gate 22 in the direction in which the multiple surfaces are arranged sequentially is large, the included angle between the fourth surface 33 and the fifth surface 34 can be constructed as a right angle or an obtuse angle. When the dimension of the floating gate 22 in the direction in which the multiple surfaces are arranged sequentially is small, the included angle between the fourth surface 33 and the fifth surface 34 can be constructed as an acute angle. This disclosure does not specifically limit this.

[0027] In some other embodiments, reference is made to Figure 4 As shown, one of the fourth face 33 and the fifth face 34 can be parallel to the aforementioned projection plane, while the other face can be non-parallel to the aforementioned projection plane. It can be understood that in this case, the fourth face 33 and the fifth face 34 form an obtuse angle.

[0028] In some embodiments, the second surface 222 may include three surfaces connected in sequence, namely a first surface 3, a second surface 31, and a third surface 32 connected in sequence, wherein the first surface 3 and the second surface 31 are arranged at an angle to each other, and the second surface 31 and the third surface 32 are arranged at an angle to each other. In this way, at least one of the first surface 3, the second surface 31, and the third surface 32 can be configured as a projection surface that is not parallel to the above-described projection surface, so as to increase the overlap area between the floating gate 22 and the control gate 24.

[0029] For example, refer to Figure 1 As shown, the first surface 3 and the second surface 31 are arranged at an obtuse angle, and the second surface 31 and the third surface 32 are arranged at an obtuse angle. The second surface 31 can be constructed to be parallel to the above-mentioned projection surface. That is, one of the first surface 3, the second surface 31 and the third surface 32 is constructed to be parallel to the above-mentioned projection surface, while the other two surfaces are not parallel to the above-mentioned projection surface.

[0030] Understandably, reference Figure 2 As shown, the first surface 3 can be constructed to be parallel to the above-mentioned projection surface. The first surface 3 and the second surface 31 can be arranged at an obtuse angle. The second surface 31 and the third surface 32 can be arranged at an obtuse angle. The third surface 32 can also be constructed to be parallel to the above-mentioned projection surface. That is, two of the first surface 3, the second surface 31 and the third surface 32 are constructed to be horizontal surfaces, and the other surface is not parallel to the horizontal surface.

[0031] In addition, refer to Figure 5 As shown, the second surface 222 may include more surfaces connected in sequence, such as four surfaces, five surfaces, six surfaces, etc., at least two adjacent surfaces are arranged at an angle, or at least one of the multiple surfaces is not parallel to the horizontal plane, and this disclosure does not make specific limitations in this regard.

[0032] In some embodiments, reference Figures 1 to 5 As shown, the floating gate 22 has a first sidewall 223 and a second sidewall 224 located between and opposite the first surface 221 and the second surface 222. Neither the first sidewall 223 nor the second sidewall 224 is in contact with the dielectric layer 23. This reduces the possibility of charge leakage through the sidewalls, improving charge storage stability. Reduced charge leakage also means that data can be retained in the storage cell for a longer period. Since the sidewalls of the floating gate 22 are not in contact with the dielectric layer 23, the parasitic capacitance between the gate structure 2 and the substrate 1 is reduced, i.e., the capacitance for charging and discharging during read operations is reduced, which helps to improve the speed of read operations. Simultaneously, during erase operations, charge escapes more easily from the floating gate 22, shortening the erase time. Furthermore, the fact that the sidewalls of the floating gate 22 are not in contact with the dielectric layer 23 simplifies the manufacturing process, improving manufacturing yield and reducing production costs.

[0033] According to the second aspect of this disclosure, reference to Figures 24 to 27 As shown, a method for fabricating a semiconductor device is provided. The semiconductor device includes a substrate 1 and a gate structure 2. The gate structure 2 includes an insulating layer 21, a floating gate 22, a dielectric layer 23, and a control gate 24 stacked on the substrate 1. The floating gate 22 has a first surface 221 and a second surface 222 opposite to each other. The first surface 221 is attached to the insulating layer 21, and the second surface 222 is attached to the bottom surface of the dielectric layer 23. The top surface of the dielectric layer 23 opposite to the bottom surface is attached to the third surface 241 of the control gate 24. The second surface 222 and the third surface 241 are parallel, and neither the second surface 222 nor the third surface 241 is parallel to the projection plane of the floating gate 22 and the control gate 24 on the substrate 1. The method for fabricating this semiconductor device includes steps S10000 and S20000.

[0034] In step S10000, substrate 1 is provided; In step S20000, a gate structure 2 is formed on the substrate 1.

[0035] refer to Figure 24 As shown, the above method first provides a substrate 1, and then stacks an insulating layer 21, a floating gate 22, a dielectric layer 23, and a control gate 24 on the substrate 1 to form a gate structure 2 on the substrate 1, thereby fabricating the aforementioned semiconductor device. The substrate 1 can be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-coated insulating substrate; this disclosure is not limited to these.

[0036] refer to Figure 25 As shown, in some embodiments, step S20000 of forming the gate structure 2 on the substrate 1 includes steps S21000 to S26000.

[0037] In step S21000, an insulating layer 21 is formed on the surface of the substrate 1; In step S22000, a floating gate layer 4 is formed on the surface of the insulating layer 21; In step S23000, the floating gate layer 4 is processed to form a floating gate 22 having a second surface 222; In step S24000, a dielectric layer 23 is formed on the second surface 222; In step S25000, a control gate 24 is provided on the top surface of the dielectric layer 23 away from the floating gate 22; In step S26000, the control gate 24, dielectric layer 23, floating gate 22 and insulating layer 21 are etched to form gate structure 2.

[0038] Thus, in step S21000, an insulating layer 21 can be deposited on the surface of the substrate 1 using, for example, chemical vapor deposition (CVD). Specifically, a precursor gas containing silicon and oxygen is introduced into the reaction chamber, and under certain temperature and pressure conditions, the gas decomposes and deposits a silicon dioxide thin film on the surface of the substrate 1. The material of the insulating layer 21 includes, but is not limited to, silicon dioxide or hafnium oxide. It is understood that the insulating layer 21 can also be formed on the surface of the substrate 1 by thermal oxidation, but this disclosure is not limited thereto.

[0039] Then, in step S22000, crystalline silicon can be deposited on the insulating layer 21 by, for example, chemical vapor deposition (CVD) to form the floating gate layer 4. During this process, the conductivity of the crystalline silicon can also be improved by doping (usually using phosphorus or boron). The floating gate layer 4 can be adapted to use polycrystalline silicon or monocrystalline silicon (described below).

[0040] In step S23000, the shape of the second surface 222 of the floating gate 22 can be defined by photolithography and etching to increase the overlap area between the subsequent control gate 24 and the floating gate 22.

[0041] In step S24000, a first oxide layer, an intermediate nitride layer, and a top oxide layer can be sequentially deposited on the second surface 222 of the floating gate 22 by, for example, chemical vapor deposition (CVD) to form a dielectric layer 23. The first oxide layer is typically a silicon dioxide layer, which can act as a tunneling oxide layer to allow electrons to enter and exit the floating gate 22 through the tunneling effect. The intermediate nitride layer is typically a silicon nitride layer, which can effectively capture and store electrons. The top oxide layer is typically a silicon dioxide layer, which can act as an insulating layer 21 between the control gate 24 and the floating gate 22 to prevent charge from leaking from the nitride layer to the control gate 24.

[0042] In step S25000, crystalline silicon can be deposited on the top surface of the dielectric layer 23 away from the floating gate 22 using, for example, chemical vapor deposition (CVD) to form the control gate 24. During this process, the conductivity of the crystalline silicon can also be improved by doping (typically using phosphorus or boron). Surface planarization is then achieved by chemical mechanical polishing (CMP) technology.

[0043] In step S26000, the control gate 24, dielectric layer 23, floating gate 22 and insulating layer 21 are etched to form a trench isolation structure. The etched control gate 24, dielectric layer 23, floating gate 22 and insulating layer 21 together form gate structure 2.

[0044] Understandably, the above steps also include the formation of source and drain regions. Specifically, dopants (such as arsenic or boron) can be implanted into substrate 1 using ion implantation technology to form source and drain regions. Annealing is then used to activate the dopants and improve the doping effect. Contact holes are then formed in insulating layer 21 to expose the source and drain regions. Photolithography is used to define the positions of the contact holes on insulating layer 21. Dry etching (plasma etching) or wet etching is used to remove insulating layer 21, forming contact holes. Physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques are used to deposit metal (such as aluminum or copper) in the contact holes to form metal contacts that connect the source and drain regions.

[0045] refer to Figure 26 As shown, in some embodiments, step S23000 of processing the floating gate layer 4 to form a floating gate 22 having a second surface 222 includes steps S23100 to S23300.

[0046] In step S23100, a hard mask layer 6 is provided on the top surface of the floating gate layer 4; In step S23200, the floating gate layer 4 is etched to form the floating gate 22; In step S23300, the hard mask layer 6 is removed.

[0047] Thus, in step S23100, the hard mask is used to protect the underlying material during etching and to provide higher etching selectivity and precise pattern transfer. Specifically, a silicon dioxide thin film can be deposited on the top surface of the floating gate layer 4 using chemical vapor deposition (CVD) technology, and then a photoresist 7 is coated on the silicon dioxide thin film. The pattern is projected onto the photoresist 7 using photolithography technology, and the photoresist 7 in the exposed area is removed by a developer to form a patterned photoresist mask. The silicon dioxide thin film is etched using dry etching, such as reactive ion etching (RIE) technology, to transfer the pattern of the photoresist mask onto the silicon dioxide thin film. The photoresist 7 is removed using plasma ashing technology or chemical stripping agent. After the hard mask is formed, it can be used in subsequent etching processes to transfer the pattern onto the underlying material, i.e., for subsequent etching of the floating gate layer 4. It is understood that the choice of hard mask material depends on specific process requirements. In addition to silicon dioxide, hard mask materials can also include silicon oxynitride and metal hard masks. For example, a metal hard mask can be deposited on the top surface of the floating gate layer 4 using physical vapor deposition (PVD) technology. This disclosure does not make any specific limitations in this regard.

[0048] In step S23200, the floating gate layer 4 can be adaptively etched by wet etching or dry etching as needed to form a floating gate 22 with a second surface 222 of different shapes.

[0049] In step S23200, the hard mask can be removed by, for example, chemical mechanical polishing (CMP), laser stripping, or chemical solution immersion stripping. It should be noted that when removing the hard mask, it is necessary to ensure that the removal process is harmless to the underlying material, that is, it will not affect the second surface 222 of the floating gate 22 in this disclosure.

[0050] refer to Figure 27 As shown, in some embodiments, step S23200, which involves etching the floating gate layer 4 to form the floating gate 22, includes step S23210.

[0051] In step S23210, dry etching and / or wet etching are selected according to the shape of the second surface 222. For example, when the second surface 222 includes at least one surface that is not parallel to the projection plane, TMAH wet etching can be selected to etch the floating gate layer 4. When the second surface 222 includes one or more surfaces that are not parallel to the projection plane, and the angle between the one or more surfaces and the projection plane is a right angle, dry etching can be selected to etch the floating gate layer 4.

[0052] refer to Figures 1 to 4As shown, in some embodiments, the second surface 222 may include multiple surfaces connected in sequence, with at least one surface arranged at an acute or obtuse angle to the first surface 221. In this embodiment, the top surface of the floating gate layer 4 can be formed by wet etching with TMAH to create the second surface 222. Since at least one surface is arranged at an acute or obtuse angle to the first surface 221, the floating gate layer 4 can be constructed as a single-crystal silicon layer to achieve this arrangement. Tetramethylammonium hydroxide (TMAH) is a commonly used wet etchant. TMAH solution has good selectivity for certain materials (such as silicon, oxides, nitrides, etc.), and can retain materials that do not need to be etched during the etching process, reducing accidental etching of the underlying material and improving the accuracy of pattern transfer, especially suitable for etching single-crystal silicon. In addition, the concentration and temperature of the TMAH solution can be adjusted to control the etching rate, achieve precise etching, and the residual products after etching are easily removed by washing with water, resulting in less waste and less environmental impact.

[0053] refer to Figure 5 As shown, in some embodiments, the second surface 222 includes a plurality of surfaces that are not parallel to the projection plane described above, and the angles formed by the plurality of surfaces and the projection plane are right angles. In this embodiment, the top surface of the floating gate layer 4 can be formed by dry etching to form the second surface 222. In this case, the floating gate layer 4 is constructed as a crystalline silicon layer, which can be a single-crystal silicon layer or a polycrystalline silicon layer, and this disclosure does not specifically limit it.

[0054] The following describes the fabrication method of semiconductor devices in detail with two specific embodiments.

[0055] One embodiment, referenced Figure 6 As shown, a substrate 1 is provided, and a silicon dioxide insulating layer 21 is deposited on the surface of the substrate 1.

[0056] refer to Figure 7 As shown, a single-crystal silicon seed layer 41 is deposited on the surface of the insulating layer 21.

[0057] refer to Figure 8 As shown, a single-crystal silicon is deposited on the surface of the single-crystal silicon seed layer 41 to form a floating gate layer 4.

[0058] refer to Figure 9 As shown, a silicon dioxide hard mask layer 6 is deposited on the top surface of the floating gate layer 4.

[0059] refer to Figure 10 As shown, photoresist 7 is applied to the surface of the hard mask layer 6, and the photoresist 7 is patterned.

[0060] refer to Figure 11 As shown, the pattern of the photoresist mask is transferred onto the hard mask layer 6.

[0061] refer to Figure 12 As shown, the floating gate layer 4 is formed by wet etching using a patterned hard mask layer 6TMAH to form the floating gate 22.

[0062] refer to Figure 13 As shown, remove hard mask layer 6.

[0063] refer to Figure 14 As shown, an ONO-structured dielectric layer 23 is deposited on the second surface 222 of the floating gate 22.

[0064] refer to Figure 15 As shown, a control gate layer 5 is deposited on the top surface of the dielectric layer 23 away from the floating gate 22.

[0065] refer to Figure 1 As shown, the control gate 24, dielectric layer 23, floating gate 22 and insulating layer 21 are etched to form gate structure 2.

[0066] Another embodiment, refer to Figure 16 As shown, a substrate 1 is provided, and a silicon dioxide insulating layer 21 is deposited on the surface of the substrate 1.

[0067] refer to Figure 17 As shown, a floating gate layer 4 is deposited on the surface of the insulating layer 21. The floating gate layer 4 can be a single crystal silicon layer or a polycrystalline silicon layer.

[0068] refer to Figure 18 As shown, a silicon dioxide hard mask layer 6 is deposited on the top surface of the floating gate layer 4.

[0069] refer to Figure 19 As shown, photoresist 7 is applied to the surface of the hard mask layer 6, and the photoresist 7 is patterned.

[0070] refer to Figure 20 As shown, the pattern of the photoresist mask is transferred onto the hard mask layer 6, and the floating gate layer 4 is dry etched to form the floating gate 22.

[0071] refer to Figure 21 As shown, remove hard mask layer 6.

[0072] refer to Figure 22 As shown, an ONO-structured dielectric layer 23 is deposited on the second surface 222 of the floating gate 22.

[0073] refer to Figure 23 As shown, a control gate layer 5 is deposited on the top surface of the dielectric layer 23 away from the floating gate 22.

[0074] refer to Figure 5As shown, the control gate 24, dielectric layer 23, floating gate 22 and insulating layer 21 are etched to form gate structure 2.

[0075] The semiconductor device of this disclosure embodiment can be obtained through the above steps, such as... Figure 1 and Figure 5 As shown, compared with related technologies, in the structure of the semiconductor device disclosed herein, the overlap area between the floating gate 22 and the control gate 24 is increased, which can improve the gate coupling ratio, thereby reducing the operating voltage, increasing the device speed, and improving the electrical performance.

[0076] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0077] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0078] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; as well as A gate structure comprising an insulating layer, a floating gate, a dielectric layer, and a control gate stacked on a substrate, wherein the floating gate has opposing first and second surfaces, the first surface being bonded to the insulating layer, the second surface being bonded to the bottom surface of the dielectric layer, and the top surface of the dielectric layer opposite to the bottom surface being bonded to a third surface of the control gate, the second surface and the third surface being parallel, and neither the second surface nor the third surface being parallel to the projection plane of the floating gate and the control gate on the substrate.

2. The semiconductor device according to claim 1, characterized in that, Both the second surface and the third surface include a plurality of surfaces connected in sequence, with at least two adjacent surfaces arranged at an included angle.

3. The semiconductor device according to claim 2, characterized in that, The plurality of surfaces includes a first surface, a second surface, and a third surface connected in sequence, wherein the first surface and the second surface are arranged at an angle, and the second surface and the third surface are arranged at an angle; or... The plurality of surfaces includes a fourth surface and a fifth surface, which are arranged at an angle to each other.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The floating gate has a first sidewall and a second sidewall located between the first surface and the second surface and opposite to each other, neither of which is in contact with the dielectric layer.

5. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes: Substrate; and A gate structure includes an insulating layer, a floating gate, a dielectric layer, and a control gate stacked on a substrate. The floating gate has a first surface and a second surface opposite to each other. The first surface is attached to the insulating layer, the second surface is attached to the bottom surface of the dielectric layer, and the top surface of the dielectric layer opposite to the bottom surface is attached to a third surface of the control gate. The second surface and the third surface are parallel, and neither the second surface nor the third surface is parallel to the projection plane of the floating gate and the control gate on the substrate. The method includes: Provide the substrate; The gate structure is formed on the substrate.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The formation of the gate structure on the substrate includes: The insulating layer is disposed on the surface of the substrate; The floating gate layer is disposed on the surface of the insulating layer; The floating gate layer is processed to form the floating gate having the second surface; The dielectric layer is disposed on the second surface; The control gate is disposed on the top surface of the dielectric layer opposite to the floating gate; The control gate, the dielectric layer, the floating gate, and the insulating layer are etched to form the gate structure.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The process of processing the floating gate layer to form the floating gate having the second surface includes: A hard mask layer is disposed on the top surface of the floating gate layer; Etch the floating gate layer to form the floating gate; Remove the hard mask layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The etching of the floating gate layer to form the floating gate includes: Dry etching and / or wet etching are selected based on the shape of the second surface.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of selecting dry etching and / or wet etching based on the shape of the second surface includes: The second surface includes a plurality of surfaces connected in sequence, and the extension line of at least one of the surfaces is arranged at an acute or obtuse angle to the first surface; The top surface of the floating gate layer is formed into the second surface by TMAH wet etching, and the floating gate layer is constructed as a single-crystal silicon layer.

10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of selecting dry etching and / or wet etching based on the shape of the second surface includes: The second surface includes a plurality of surfaces connected in sequence, wherein the extension line of any one of the surfaces is arranged at a right angle to the first surface or parallel to the first surface; The top surface of the floating gate layer is formed into the second surface by dry etching, and the floating gate layer is constructed as a crystalline silicon layer.

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