Manufacturing method of semiconductor device
By forming a protective layer gate structure in the NOR Flash memory, the process window problem caused by the difference in the top surface of polysilicon between the memory region and the logic region is solved, achieving height adjustment and process window optimization without additional processes, and avoiding deposition defects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-14
AI Technical Summary
In existing technologies, the polysilicon top surfaces of the storage area and logic area of NOR Flash memory are different, resulting in a large aspect ratio. This leads to a smaller process window and increased process difficulty for subsequent dielectric layer and conductive plug fabrication processes.
A first protective layer is formed in the logic region and a second protective layer is formed in the storage region to protect the first gate structure and the second gate structure respectively. By removing part of the height of the second gate structure in the vertical direction, the first gate structure in the logic region is ensured to be undamaged.
Without the need for additional photomask processes, the height of the second gate structure in the memory region is reduced, the process window is minimized, deposition defects are avoided, and the integrity of the first gate structure in the logic region is ensured.
Smart Images
Figure CN121865621A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology
[0002] NOR Flash memory is a type of non-volatile memory that retains data even after power loss. It is widely used in various electronic systems to store data and code, such as configuration data for FPGAs or runtime code for MCUs. NOR Flash memory uses floating-gate transistors as storage cells; compared to ordinary transistors, the additional floating gate can be used to store electrical charge. Typically, NOR Flash memory includes a storage area for configuring multiple storage cells and a logic area for configuring peripheral circuitry.
[0003] Currently, the control gate polysilicon in the memory region and the gate polysilicon in the logic region are deposited using the same film deposition process. However, because a floating gate layer and an interlayer dielectric layer are formed below the control gate polysilicon in the memory region, the top surfaces of the polysilicon formed using the same film deposition process are different in the memory region and the logic region. This results in a large aspect ratio in the memory region, which leads to defects such as a smaller process window and increased process difficulty for subsequent dielectric layer and conductive plug processes. Summary of the Invention
[0004] One objective of this invention is to provide a method for manufacturing a semiconductor device. By forming a first protective layer on a logic region and a second protective layer on both the logic region and the memory region, the first gate structure in the logic region is protected by both the first and second protective layers, while the second gate structure in the memory region is protected by the second protective layer. This ensures that the first gate structure in the logic region remains undamaged while a removal process is used to remove part of the height of the second gate structure to achieve the designed height.
[0005] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising:
[0006] Provide a substrate, including logic regions and memory regions;
[0007] Multiple gate structures are formed and disposed on the substrate with spacing between them, and include:
[0008] Multiple first gate structures are located on the substrate of the logic region;
[0009] Multiple second gate structures are located on the substrate of the memory region, and the top surface of the second gate structure is higher than the top surface of the first gate structure;
[0010] A first protective layer is formed on the logic region, and the first protective layer buries the plurality of first gate structures;
[0011] A second protective layer is formed on the first protective layer and extends laterally to the memory area, burying the plurality of second gate structures;
[0012] Remove a portion of the height of the first protective layer, the second protective layer, and the second gate structure along the vertical direction.
[0013] Optionally, the step of forming the plurality of gate structures includes:
[0014] A first semiconductor layer and an interlayer dielectric layer are formed on the substrate of the memory region, and the interlayer dielectric layer is located on the first semiconductor layer;
[0015] A second semiconductor layer is formed, conformally covering the logic region and the memory region, and the bottom of the second semiconductor layer located on the memory region is in direct contact with the top surface of the interlayer dielectric layer;
[0016] The second semiconductor layer, the interlayer dielectric layer, and the first semiconductor layer on the memory region are etched to form a plurality of second gate structures;
[0017] The second semiconductor layer on the logic region is etched to form a plurality of the first gate structures.
[0018] Optionally, the top surface of the portion of the second semiconductor layer located on the logic region is lower than the top surface of the portion located on the memory region.
[0019] Optionally, the step of removing a portion of the height of the second gate structure includes removing a portion of the height of the second semiconductor layer on the memory region in a vertical direction.
[0020] Optionally, after removing a portion of the height of the second gate structure, the top surface of the second semiconductor layer located on the memory region is higher than its top surface located on the logic region.
[0021] Optionally, before forming the second gate structure, the height difference between the top surfaces of the second semiconductor layer located in the logic region and the memory region is a first height difference; after removing a portion of the height of the second gate structure, the height difference between the top surfaces of the second semiconductor layer located in the logic region and the memory region is a second height difference, wherein the first height difference is greater than the second height difference.
[0022] Optionally, the first protective layer and the second protective layer may be made of different materials.
[0023] Optionally, the first protective layer and the second protective layer are selected from at least one of spin-coated hard mask material, spin-coated carbon material, anti-reflective coating or photoresist.
[0024] Optionally, the top surface of the first protective layer is higher than the top surface of the second gate structure.
[0025] Optionally, the material of the second semiconductor layer includes a conductive material.
[0026] As described above, the fabrication method of the present invention includes forming multiple gate structures (including a second gate structure located in the memory region), a first protective layer, and a second protective layer. The first protective layer is located only in the logic region, while the second protective layer is located in both the logic region and the memory region. Therefore, during the process of removing a portion of the height of the first protective layer, the second protective layer, and the second gate structure in the vertical direction, the first gate structure with a lower top surface in the logic region is not damaged due to the dual protection of the first and second protective layers; while the second gate structure with a higher top surface in the memory region is only protected by the second protective layer and is therefore partially removed. In this way, the height of the second gate structure in the memory region can be reduced without the need for additional photomask or other processes, thereby reducing the process window for subsequent processes and avoiding deposition defects. Attached Figure Description
[0027] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.
[0028] Figure 1 The illustration is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0029] Figures 2 to 7 The diagram illustrates the structural details of each step in a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein:
[0030] Figure 2 This is a schematic cross-sectional view of a semiconductor device after the formation of the second semiconductor layer.
[0031] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the formation of the second gate structure.
[0032] Figure 4 This is a schematic cross-sectional view of a semiconductor device after the formation of the first gate structure.
[0033] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device after the formation of the first protective layer;
[0034] Figure 6 This is a schematic cross-sectional view of a semiconductor device after the formation of the second protective layer; and
[0035] Figure 7 This is a schematic cross-sectional view of a semiconductor device after removing a portion of the height of the second semiconductor layer on the memory region.
[0036] The reference numerals in the attached figures are explained as follows:
[0037] 100 - Substrate, 101 - Logic region, 102 - Memory region, 112 - Gate dielectric layer, 114 - First semiconductor layer, 116 - Interlayer dielectric layer, 118 / 118' - Second semiconductor layer, 120 / 120' - First protective layer, 130 / 130' - Second protective layer, 251 - First gate structure, 252 / 252' - Second gate structure. Detailed Implementation
[0038] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.
[0039] Please refer to Figure 1 As shown, the illustration is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for fabricating the semiconductor device includes at least the following steps:
[0040] Step S101: Provide a substrate, including a logic region and a memory region.
[0041] Step S102: Forming a plurality of gate structures, the gate structures being disposed on the substrate in a mutually spaced manner, and including: a plurality of first gate structures and a plurality of second gate structures; wherein, the plurality of first gate structures are located on the substrate of the logic region; the plurality of second gate structures are located on the substrate of the memory region, and the top surface of the second gate structure is higher than the top surface of the first gate structure.
[0042] Step S103: A first protective layer is formed on the logic region, and the first protective layer buries the plurality of first gate structures.
[0043] Step S104: A second protective layer is formed, located on the first protective layer and extending laterally to the storage area, and the plurality of second gate structures are buried.
[0044] Step S105: Remove a portion of the height of the first protective layer, the second protective layer, and the second gate structure in the vertical direction.
[0045] To enable those skilled in the art to easily understand the fabrication method of the semiconductor device in the embodiments of this invention, the fabrication method of the semiconductor device proposed in this invention will be further described below with reference to various structural schematic diagrams during the fabrication process. Among them, Figures 2-7 This is a schematic diagram of the fabrication process of a semiconductor device provided in one embodiment of the present invention.
[0046] The following will combine Figures 2-7 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.
[0047] For ease of understanding, the following text defines directions parallel to the substrate 100 and directions perpendicular to the surface of the substrate 100. For simplicity, the direction parallel to the surface of the substrate 100 is simply referred to as the horizontal direction, and the direction perpendicular to the surface of the substrate 100 is simply referred to as the vertical direction.
[0048] Please see Figure 2 Step S101 involves providing a substrate 100, which serves as a platform for subsequently forming a memory, such as a NOR Flash memory, comprising the plurality of gate structures, a first protective layer, and a second protective layer, and other components and / or parts. In one embodiment, the material of the substrate 100 can be any suitable substrate material well known to those skilled in the art, such as at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This application does not limit the material of the substrate 100. Furthermore, the substrate 100 may include, for example, a plurality of adjacent regions 101, 102, which may be respectively provided with components of different functions according to actual device requirements, but are not limited thereto. For example, in this application, the substrate 100 includes an adjacent logic region 101 and a memory region 102. The logic region 101 is, for example, a region for forming the peripheral circuitry of a NOR Flash memory, wherein the peripheral circuitry includes a gate structure (i.e., the first gate structure), and the memory region 102 is, for example, a region for forming a plurality of memory cells of a NOR Flash memory, wherein the memory cells include a gate structure (i.e., the second gate structure) consisting of a floating gate, an interlayer dielectric layer, and a control gate.
[0049] Next, continue reading Figure 2Using at least one deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, a gate dielectric layer 112, a first semiconductor layer 114, and an interlayer dielectric layer 116 are formed on the substrate 100 of the storage region 102, stacked sequentially from bottom to top. In one embodiment, the gate dielectric layer 112 is made of an insulating material, such as silicon dioxide, and serves as a tunnel oxide layer for the memory cells in the storage region 102. The first semiconductor layer 114 is made of a conductive material, such as polysilicon, and serves as the storage layer for the memory cells in the storage region 102. The interlayer dielectric layer 116 is a single or multilayer stacked insulating material, such as an ONO structure of oxide, nitride, or oxide stacks, but is not limited thereto. The interlayer dielectric layer 116 serves as an isolation layer between the storage layer of the memory cells in the storage region 102 and the subsequently formed second semiconductor layer, which serves as a control gate.
[0050] Then, using a deposition process such as physical vapor deposition, a second semiconductor layer 118 of uniform thickness is simultaneously formed on the substrate 100 of the logic region 101 and on the top surface of the interlayer dielectric layer 116 on the memory region 102. In one embodiment, the material of the second semiconductor layer 118 is the same as that of the first semiconductor layer 114, for example, both are polysilicon. At this time, although the thickness of the second semiconductor layer 118 in the logic region 101 and the thickness in the memory region 102 are the same, the presence of the gate dielectric layer 112, the first semiconductor layer 114 and the interlayer dielectric layer 116 in the memory region 102 causes the top surface of the second semiconductor layer 118 on the memory region 102 to be higher than the top surface of the second semiconductor layer 118 on the logic region 101, that is, the height difference between the top surfaces of the two is H1, and H1>0.
[0051] Please see Figure 3 Step S102 is executed as follows: First, a first photoresist layer (not shown) is formed to shield the logic region 101 and expose the memory region 102. Then, using the first photoresist layer as a mask, the second semiconductor layer 118, the interlayer dielectric layer 116, the first semiconductor layer 114, and the gate dielectric layer 112 of the memory region 102 are etched in the vertical direction to form a plurality of mutually spaced second gate structures 252, i.e., a plurality of memory cells of the NOR Flash memory, on the substrate 100 of the memory region 102. Then, the first photoresist layer is removed.
[0052] Please see Figure 4The process continues with step S102: First, a second photoresist layer (not shown) is formed to shield the memory region 102 and expose the logic region 101. Then, using this second photoresist layer as a mask, a portion of the second semiconductor layer 118 in the logic region 101 is etched away in the vertical direction to form multiple first gate structures 251, thereby forming a gate structure composed of multiple first gate structures 251 and multiple second gate structures 252. Since the portions of the second semiconductor layer 118 in the logic region 101 and the memory region 102 are formed in the same process, their thicknesses are consistent. However, the top surface of the portion of the second semiconductor layer 118 located in the logic region 101 is lower than the top surface of the portion located in the memory region 102; thus, the top surface of the second gate structure 252 is higher than the top surface of the first gate structure 251. Then, the second photoresist layer (not shown) is removed.
[0053] Please see Figure 5 Step S103: A first protective layer 120 is formed on the logic region 101 using a deposition process such as chemical vapor deposition. At this time, the top surface of the first protective layer 120 is higher than the top surface of the first gate structure 251, so that the first protective layer 120 can bury all the first gate structures 251 on the logic region 101. In one embodiment, the material of the first protective layer 120 may be at least one of spin-coated hard mask material, spin-coated carbon material, anti-reflective coating, or photoresist, and is preferably photoresist, but is not limited thereto. It should be understood that in other embodiments, the top surface of the first protective layer 120 may also be higher than the top surface of the second gate structure 252 on the memory region 102, so as to protect the first gate structures 251 on the logic region 101 in the subsequent step S105.
[0054] Then, based on other processes of the memory cells in the NOR Flash memory, the memory region 102 not covered by the first protective layer 120 can be subjected to corresponding process technology, such as ion implantation process, to form LDD region or pocket region plasma implantation region located in the substrate 100 on both sides of the second gate structure 252, or for example, sidewall deposition process, but not limited thereto.
[0055] Please see Figure 6Step S104: A second protective layer 130 is formed over the entire area of the logic region 101 and the memory region 102 using a deposition process such as chemical vapor deposition. At this time, the top surface of the second protective layer 130 must be higher than the top surface of the first protective layer 120, and further higher than the top surfaces of the second gate structure 252 and the first gate structure 251, so that the second protective layer 130 can bury all film structures on the logic region 101 and the memory region 102. In one embodiment, the material of the second protective layer 130 may be at least one of spin-coated hard mask material, spin-coated carbon material, anti-reflective coating, or photoresist, and is preferably photoresist, but is not limited thereto. Furthermore, the material of the second protective layer 130 can be different from that of the first protective layer 120. Therefore, during the subsequent step S105, the difference in the etching selectivity of the first and second protective layers 120 can be utilized to allow the etching rate in the memory region 102 to be greater than its etching rate in the logic region 101. This achieves the removal of a portion of the height of the second gate structure 252 in the memory region 102 during the same etching process, while ensuring that the first gate structure 251 on the logic region 101 remains intact, i.e., its structural morphology is complete. Preferably, the material of the second protective layer 130 can be an anti-reflective coating.
[0056] In other embodiments, the first protective layer 120 and the second protective layer 130 may be made of the same material, but their heights must be proportional to ensure that when performing the subsequent step S105, the same etching process only removes a portion of the height of the second gate structure 252 in the memory region 102 without damaging the top surface of the first gate structure 251 in the logic region 101. The height ratio of the first protective layer 120 and the second protective layer 130 may be related to the process parameters of the removal process used in step S105, such as an etching process. For example, the height ratio of the first protective layer 120 and the second protective layer 130 may be proportional to the etching time of the removal process used in step S105, i.e., the height of the second protective layer 130 above the first protective layer 120 in the vertical direction is proportional to the etching time of the removal process used in step S105, but this is not a limitation.
[0057] Please see Figure 7Step S105: Using at least one etching process, such as dry etching or wet etching, the second protective layer 130, the first protective layer 120, a portion of the height of the second semiconductor layer 118 on the memory region 102, and a portion of the height of the first protective layer 120 on the logic region 101 are etched in a vertical direction to remove a portion of the height of the second gate structure 252 on the memory region 102 while protecting the top surface of the first gate structure 251 on the logic region 101. In this step, removing a portion of the height of the second gate structure 252 on the memory region 102 is equivalent to removing a portion of the height of the second semiconductor layer 118 on the memory region 102 in a vertical direction (the remaining second semiconductor layer after removal is identified by reference numeral 118', and the second gate structure after removing a portion of the height of the second semiconductor layer is identified by reference numeral 252'). Furthermore, even after removing a portion of the height of the second gate structure 252, the top surface of the second semiconductor layer 118 located on the storage region 102 is still higher than its top surface located on the logic region 102, in order to meet the height requirements of each component of the memory cell in the NOR Flash memory. In one embodiment, if the height difference between the top surfaces of the second semiconductor layer 118 located in the logic region 101 and the storage region 102 before the formation of the second gate structure 252 is defined as a first height difference H1; and the height difference between the top surfaces of the second semiconductor layer 118 located in the logic region 101 and the storage region 102 after the removal of a portion of the height of the second gate structure 252 is defined as a second height difference H2, then H1 > H2 > 0. Thus, by utilizing the dual protection of the film structure on the logic region 101 by the first protective layer 120 and the second protective layer 130, no additional photomask or photoresist layer is required. This reduces the height difference between the second gate structure 252 and the first gate structure 251, decreases the process window on the memory region 102, and avoids deposition defects such as voids that are prone to occur in subsequent conductive plugs and dielectric layer deposition processes due to the large process window on the memory region 102. Ultimately, this also avoids leakage and short circuit problems in the memory cell.
[0058] It should be understood that, for ease of distinction, in this embodiment of the invention, the first protective layer remaining after step S105 is marked with 120' and the second protective layer remaining after step S105 is marked with 130'.
[0059] In summary, the method for fabricating the semiconductor device of the present invention includes: forming a plurality of gate structures (including a second gate structure located in the memory region), a first protective layer, and a second protective layer. The first protective layer is located only in the logic region, while the second protective layer is located in both the logic region and the memory region. Therefore, during the process of removing a portion of the height of the first protective layer, the second protective layer, and the second gate structure in the vertical direction, the first gate structure with a lower top surface in the logic region is not damaged due to the dual protection of the first and second protective layers; while the second gate structure with a higher top surface in the memory region is only protected by the second protective layer and is therefore partially removed. Thus, the height of the second gate structure in the memory region can be reduced without the need for additional photomasks or other processes, thereby reducing the process window for subsequent processes and avoiding deposition defects.
[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Provide a substrate, including logic regions and memory regions; Multiple gate structures are formed and disposed on the substrate with spacing between them, and include: Multiple first gate structures are located on the substrate of the logic region; Multiple second gate structures are located on the substrate of the memory region, and the top surface of the second gate structure is higher than the top surface of the first gate structure; A first protective layer is formed on the logic region, and the first protective layer buries the plurality of first gate structures; A second protective layer is formed on the first protective layer and extends laterally to the memory area, burying the plurality of second gate structures; Remove a portion of the height of the first protective layer, the second protective layer, and the second gate structure along the vertical direction.
2. The manufacturing method as described in claim 1, characterized in that, The steps of forming the plurality of gate structures include: A first semiconductor layer and an interlayer dielectric layer are formed on the substrate of the memory region, and the interlayer dielectric layer is located on the first semiconductor layer; A second semiconductor layer is formed, conformally covering the logic region and the memory region, and the bottom of the second semiconductor layer located on the memory region is in direct contact with the top surface of the interlayer dielectric layer; The second semiconductor layer, the interlayer dielectric layer, and the first semiconductor layer on the memory region are etched to form a plurality of second gate structures; The second semiconductor layer on the logic region is etched to form a plurality of the first gate structures.
3. The manufacturing method as described in claim 1, characterized in that, The top surface of the portion of the second semiconductor layer located on the logic region is lower than the top surface of the portion located on the memory region.
4. The manufacturing method as described in claim 3, characterized in that, The step of removing a portion of the height of the second gate structure includes removing a portion of the height of the second semiconductor layer on the memory region in a vertical direction.
5. The manufacturing method as described in claim 4, characterized in that, After removing a portion of the height of the second gate structure, the top surface of the second semiconductor layer located on the memory region is higher than its top surface located on the logic region.
6. The manufacturing method as described in claim 5, characterized in that, Before the second gate structure is formed, the height difference between the top surfaces of the second semiconductor layer located in the logic region and the memory region is a first height difference; after a portion of the height of the second gate structure is removed, the height difference between the top surfaces of the second semiconductor layer located in the logic region and the memory region is a second height difference, and the first height difference is greater than the second height difference.
7. The manufacturing method as described in claim 1, characterized in that, The first protective layer and the second protective layer are made of different materials.
8. The manufacturing method as described in claim 7, characterized in that, The first protective layer and the second protective layer are selected from at least one of spin-coated hard mask material, spin-coated carbon material, anti-reflective coating or photoresist.
9. The manufacturing method as described in claim 1, characterized in that, The top surface of the first protective layer is higher than the top surface of the second gate structure.
10. The manufacturing method as described in claim 2, characterized in that, The material of the second semiconductor layer includes a conductive material.