Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device includes a first conductive line extending in a first direction, a second conductive line on the first conductive line and extending in a second direction crossing the first direction, and a memory cell between the first conductive line and the second conductive line, the memory cell includes a lower electrode pattern, an upper electrode pattern on the lower electrode pattern, and a variable resistance pattern between the lower electrode pattern and the upper electrode pattern, and the upper electrode pattern may include a first portion between the variable resistance pattern and the second conductive line, and a pair of second portions, the second portions extend on sidewalls of the variable resistance pattern facing each other and arranged in the second direction such that an interface between the first portion and the variable resistance pattern is located between the second portions.

Description

[0001] Cross-reference to related applications This application claims priority to Korean Patent Application No. 10-2024-0138651, filed on October 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to electronic devices and methods of manufacturing such electronic devices, and more particularly, to semiconductor devices and methods of manufacturing such semiconductor devices. Background Technology

[0003] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices in which memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device may include: a first conductor extending in a first direction; a second conductor located on the first conductor and extending in a second direction intersecting the first direction; and a memory cell located between the first conductor and the second conductor, and including a lower electrode pattern, an upper electrode pattern located on the lower electrode pattern, and a variable resistor pattern located between the lower electrode pattern and the upper electrode pattern. The upper electrode pattern may include: a first portion located between the variable resistor pattern and the second conductor; and a pair of second portions extending on first sidewalls of the variable resistor patterns facing each other and arranged along the second direction, such that the interface between the first portion and the variable resistor pattern is located between the second portions.

[0005] According to one embodiment of this disclosure, a semiconductor device may include: a first conductor extending along a first direction; a second conductor located on the first conductor and extending in a second direction intersecting the first direction; and a memory cell located between the first conductor and the second conductor, and including a lower electrode pattern, an upper electrode pattern located on the lower electrode pattern, and a variable resistor pattern located between the lower electrode pattern and the upper electrode pattern. The upper electrode pattern may include: a first portion located between the variable resistor pattern and the second conductor; a pair of second portions extending on first sidewalls of the variable resistor pattern facing each other and arranged along the second direction; and a pair of third portions extending on second sidewalls of the variable resistor pattern facing each other and arranged along the first direction. The second and third portions of the upper electrode pattern surround the interface between the first portion and the variable resistor pattern.

[0006] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: sequentially forming a lower electrode layer, a variable resistance layer, and an upper electrode layer on a first conductive layer; forming an upper electrode line extending in a first direction by etching the upper electrode layer; etching the variable resistance layer to a partial thickness; forming a first additional electrode layer along the contour of the upper electrode line and the variable resistance layer; and forming a variable resistance line by etching the variable resistance layer. Attached Figure Description

[0007] Figure 1A , Figure 1B and Figure 1C This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Detailed Implementation

[0009] One embodiment of this disclosure provides a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0010] According to one embodiment of this disclosure, a semiconductor device with a stable structure and improved reliability can be provided. Throughout the specification and claims, enumerations introduced by phrases such as "at least one," "one or more," or "one or two" indicate an inclusive enumeration. For example, "at least one of A or B" and "one or two of A and B" each represent A, or B, or AB (i.e., A and B). Furthermore, "on the second element" means that the first element may be "directly" on the second element, or that at least one intermediate element may be between the first and second elements.

[0011] In the following description, some embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0012] Figures 1A to 1C This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure. Figure 1A It's a floor plan. Figure 1B It is along Figure 1A A cross-sectional view taken from line AA′. Figure 1C It is along Figure 1A The cross-sectional view taken from line BB′.

[0013] refer to Figures 1A to 1C The semiconductor device may include a first conductive line 110, a second conductive line 120, and a memory cell 130. The semiconductor device may also include a first liner pattern 140, a second liner pattern 150, a first gap fill pattern 160, a third liner pattern 170, and a second gap fill pattern 180.

[0014] First conductors 110 may each extend in a first direction I. Second conductors 120 may intersect first conductors 110 and may be located on first conductors 110. Second conductors 120 may each extend in a second direction II intersecting the first direction I. For example, first conductors 110 may each be word lines, and second conductors 120 may each be bit lines. As another example, first conductors 110 may each be bit lines, and second conductors 120 may each be word lines.

[0015] The storage cell 130 can be arranged along a first direction I and a second direction II. The storage cell 130 can be located between the first conductor 110 and the second conductor 120. The storage cell 130 may include a lower electrode pattern 131, a variable resistor pattern 133, and an upper electrode pattern 135.

[0016] The lower electrode pattern 131 may be located on the first conductor 110. The lower electrode pattern 131 may be a portion of the first conductor 110, or may be electrically connected to the first conductor 110. The upper electrode pattern 135 may be located on the lower electrode pattern 131. The upper electrode pattern 135 may be a portion of the second conductor 120, or may be electrically connected to the second conductor 120. The variable resistor pattern 133 may be located between the lower electrode pattern 131 and the upper electrode pattern 135.

[0017] The upper electrode pattern 135 may include a first portion 135A, a second portion 135B, and a third portion 135C. The first portion 135A may be located between the variable resistor pattern 133 and the second conductor 120. The second portion 135B may extend along the sidewall of the upper electrode pattern 135 facing in the second direction II and may surround the interface between the first portion 135A and the variable resistor pattern 133. For example, the second portions 135B include pairs of second portions 135B spaced apart from each other in the second direction II. These second portions 135B may extend along the sidewalls of the variable resistor pattern 133 facing each other and arranged in the second direction II, such that the interface between the first portion 135A and the variable resistor pattern 133 may be located between the second portions 135B.

[0018] The third portion 135C may extend along the sidewall of the upper electrode pattern 135 facing each other in the first direction I and the sidewall of the second conductor 120 facing each other in the first direction I, and may surround the interface between the first portion 135A and the variable resistor pattern 133. For example, the third portion 135C includes pairs of third portions 135C spaced apart from each other in the first direction I. These third portions 135C may extend on the second sidewalls of the variable resistor pattern 133 facing each other and arranged in the first direction I, such that the second portion 135B and the third portion 135C of the upper electrode pattern 135 surround the interface between the first portion 135A and the variable resistor pattern 133. The third portion 135C may also extend on the sidewalls of the second conductor 120 facing each other and arranged in the first direction I.

[0019] The second portion 135B and the third portion 135C may contact the sidewalls of the variable resistor pattern 133. For example, each of the second portion 135B and the third portion 135C may contact a corresponding sidewall of the first and second sidewalls of the variable resistor pattern 133. The third portion 135C may contact the sidewalls of the second conductor 120. For example, each third portion 135C may contact a corresponding sidewall of the second conductor 120.

[0020] The second portion 135B may have a first height H1 in a cross-section located in a first plane defined by the second direction II and the third direction III. For example, the second portion 135B includes a pair of portions, each of which has a first height H1 in a cross-section located in the first plane defined by the second direction II and the third direction III. The third portion 135C may have a second height H2 in a cross-section located in a second plane defined by the first direction I and the third direction III, different from the first height H1. For example, the third portion 135C includes a pair of portions, each of which has a second height H2 in a cross-section located in the second plane defined by the first direction I and the third direction III. For example, the third portion 135C may have a second height H2 greater than the first height H1. This is because the process timing for forming the second portion 135B and the third portion 135C is different in the process of manufacturing a semiconductor device. Here, the third direction III may intersect with the first direction I and the second direction II.

[0021] At least one of the lower electrode pattern 131 or the upper electrode pattern 135 may include a material selective relative to the variable resistance pattern 133. Specifically, the lower electrode pattern 131 or the upper electrode pattern 135, or both the lower electrode pattern 131 and the upper electrode pattern 135, may include a material having an etching rate lower than that of the variable resistance pattern 133. For example, at least one of the lower electrode pattern 131 or the upper electrode pattern 135 may include carbon. Here, the variable resistance pattern 133 may include a chalcogenide material.

[0022] The lower electrode pattern 131 or the upper electrode pattern 135 may include polycrystalline silicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., and may include combinations thereof.

[0023] The variable resistor pattern 133 can remain in an amorphous state during the programming operation and can remain in a crystalline state after the programming operation. In other words, the phase of the variable resistor pattern 133 can remain unchanged after the programming operation.

[0024] The variable resistor pattern 133 can be used simultaneously as a data storage device and a selection element. The variable resistor pattern 133 may contain a resistive material and may have the characteristic of reversibly changing between different resistance states according to the applied voltage or current. For example, the variable resistor pattern 133 may contain a variable resistive material whose resistance changes without a phase transition, and may include chalcogenide elements. The variable resistor pattern 133 may contain germanium (Ge), antimony (Sb), arsenic (As), silicon (Si), indium (In), tin (Sn), gallium (Ga), etc., or may contain combinations thereof.

[0025] The variable resistance pattern 133 may contain a phase change material and may contain chalcogenides. The variable resistance pattern 133 may contain chalcogenide glass, chalcogenide alloys, etc. The phase of the variable resistance pattern 133 can be changed according to a programming operation. For example, the variable resistance pattern 133 can have a low-resistance crystalline state through a set operation. Furthermore, the variable resistance pattern 133 can have a high-resistance amorphous state through a reset operation. Therefore, data can be stored in the storage unit 130 using the resistance difference based on the phase of the variable resistance pattern 133.

[0026] The variable resistance pattern 133 may contain metal oxides (transition metal oxides) or metal oxides such as perovskite materials. Therefore, data can be stored in the storage cells as electrical paths are generated or disappear in the variable resistance pattern 133.

[0027] The variable resistor pattern 133 may have an MTJ structure and may include a magnetization fixed layer, a magnetization free layer, and a tunnel blocking layer therebetween. For example, the magnetization fixed layer and the magnetization free layer may include magnetic materials, and the tunnel blocking layer may contain oxides such as magnesium (Mg), aluminum (Al), zinc (Zn), or titanium (Ti). Here, the magnetization direction of the magnetization free layer can be changed by the spin torque of electrons in the applied current. Therefore, data can be stored in the storage unit 130 according to the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0028] Furthermore, the variable resistor pattern 133 may have a metal-insulator-metal (MIM) structure comprising metal oxides. In this case, data can be stored in the storage unit 130 by utilizing the resistance change of the metal oxides caused by applying a short electrical pulse.

[0029] For reference, although not shown in the figure, the semiconductor device may also include an intermediate electrode pattern and a switch pattern. For example, the semiconductor device may include a structure in which a lower electrode pattern 131, a switch pattern, an intermediate electrode pattern, a variable resistor pattern 133, and an upper electrode pattern 135 are sequentially stacked. In this case, the lower electrode pattern 131, the switch pattern, and the intermediate electrode pattern can constitute a selection element. The selection element may be a diode, a PNP diode, a transistor, a vertical transistor, a bipolar junction transistor (BJT), a metal-insulator transition (MIT) element, a hybrid ion-electron conduction (MIEC) element, a bidirectional threshold switch (OTS) element, etc. For example, the switch pattern 123 may include a chalcogenide material. Furthermore, the intermediate electrode pattern, the variable resistor pattern 133, and the upper electrode pattern 135 can constitute a memory element. The memory element and the selection element may share the intermediate electrode pattern.

[0030] The first liner pattern 140 may surround the sidewall of the storage cell 130 adjacent in the second direction II along the outline of the storage cell 130. For example, the first liner pattern 140 may cover the sidewall of the storage cell 130 along the outline of the storage cell 130, wherein the storage cell 130 is adjacent to the first liner pattern 140 in the second direction II. The second liner pattern 150 may be located on the first liner pattern 140 and may extend along the sidewall of the first guide wire 110. Specifically, the second liner pattern 150 may be located on the first liner pattern 140 and extend along the sidewall of the first guide wire 110. For example, the second liner pattern 150 may extend along the sidewall of the first guide wire 110 adjacent in the second direction II.

[0031] The paired first liner pattern 140 and second liner pattern 150 may include a first bent portion V1 covering the lower surface of the second portion 135B of the upper electrode pattern 135. Here, the first bent portion V1 may refer to the region in which the outline of the storage cell 130 is changed due to the second portion 135B of the upper electrode pattern 135, which is the region adjacent to the upper surface of the variable resistor pattern 133. For reference, the region adjacent to the upper surface of the variable resistor pattern 133 may refer to the region adjacent to the upper electrode pattern 135 relative to the middle portion of the variable resistor pattern 133.

[0032] The paired first inner liner pattern 140 and second inner liner pattern 150 may have a first thickness T1 in the region adjacent to the upper electrode pattern 135, and may have a second thickness T2 at the first bending portion V1 that is greater than the first thickness T1. Here, the first thickness T1 and the second thickness T2 may refer to the thickness of the paired first inner liner pattern 140 and second inner liner pattern 150 extending in the second direction II. That is, because the paired first inner liner pattern 140 and second inner liner pattern 150 are formed along the contour of the memory cell 130, the paired first inner liner pattern 140 and second inner liner pattern 150 may have a relatively large second thickness T2 at the first bending portion V1 along the second direction II.

[0033] The third liner pattern 170 may cover the sidewall of the storage cell 130 along the outline of the storage cell 130. For example, the third liner pattern 170 may correspondingly cover the sidewall of the storage cell 130 adjacent in the first direction I.

[0034] The third liner pattern 170 may include a second bent portion V2 covering the lower surface of the second portion 135B of the upper electrode pattern 135. Here, the second bent portion V2 may refer to the portion in which the outline of the storage cell 130 is changed due to the third portion 135C of the upper electrode pattern 135, which is a region adjacent to the upper surface of the variable resistor pattern 133. The third liner pattern 170 may have a third thickness T3 in the region adjacent to the upper electrode pattern 135, and may have a fourth thickness T4 at the second bent portion V2 that is greater than the third thickness T3. Here, the third thickness T3 and the fourth thickness T4 may refer to the thickness of the third liner pattern 170 extending in the first direction I.

[0035] The first inner liner pattern 140, the second inner liner pattern 150, and the third inner liner pattern 170 can protect the memory cell 130 during the manufacture of the semiconductor device. At least one of the first inner liner pattern 140, the second inner liner pattern 150, or the third inner liner pattern 170 may include a nitride. The nitride can withstand compressive forces. Therefore, because the paired first inner liner patterns 140 and 150 may have a second thickness T2 at the first bend portion V1 that is relatively larger than the area adjacent to the upper electrode pattern 135, the paired first inner liner patterns 140 and 150 can be subjected to relatively large compressive forces, and because the third inner liner pattern 170 may have a fourth thickness T4 at the second bend portion V2 that is relatively larger than the area adjacent to the upper electrode pattern 135, the third inner liner pattern 170 can be subjected to relatively large compressive forces.

[0036] In conventional semiconductor devices, when a memory cell repeatedly performs programming and erasing operations, the material contained in the variable resistor pattern may diffuse to the outside, potentially degrading the reliability of the memory cell. For example, the volume of the region adjacent to the upper surface of the variable resistor pattern may expand during repeated operations. As another example, chalcogenide elements included in the variable resistor pattern may separate from the pattern and move towards the upper electrode pattern. Specifically, the chalcogenide elements may separate in a region adjacent to the upper surface of the variable resistor pattern. In this case, the chalcogenide elements may move along the interface between the upper electrode pattern and the first / third liner patterns, which comprise different materials, potentially weakening the adhesion between the upper electrode pattern and the first / third liner patterns, resulting in gaps between them.

[0037] According to one embodiment of this disclosure, the upper electrode pattern 135 may cover a region adjacent to the upper surface of the variable resistor pattern 133 in a cap-like manner. For example, the upper electrode pattern 135 may have a substantially trapezoidal shape in cross-section. The upper surface of the variable resistor pattern 133 may be covered by a first portion 135A, and the sidewalls of the region adjacent to the upper surface of the variable resistor pattern 133 may be covered by a second portion 135B and a third portion 135C. Therefore, because the upper electrode pattern 135 covers the region adjacent to the upper surface of the variable resistor pattern 133 in a cap-like manner, volume expansion of the region adjacent to the upper surface of the variable resistor pattern 133 can be prevented or reduced.

[0038] When the second portion 135B / third portion 135C of the upper electrode pattern 135 is absent, the first portion 135A can contact the first inner liner pattern 140 / third inner liner pattern 170, and the chalcogenide element can move along the interface between the upper electrode pattern 135 and the first inner liner pattern 140 / third inner liner pattern 170 via a relatively short path. On the other hand, according to one embodiment of this disclosure, because the chalcogenide element needs to move along the interface between the second portion 135B / third portion 135C and the variable resistor pattern 133, and then move to the interface between the second portion 135B / third portion 135C and the first inner liner pattern 140 / third inner liner pattern 170, the chalcogenide element needs to move along a relatively long path. By increasing the movement path of the chalcogenide element as described above, the separation of the chalcogenide element from the variable resistor pattern 133 can be reduced. Therefore, the degradation of the reliability of the memory cell 130 can be prevented or reduced.

[0039] Furthermore, according to one embodiment of this disclosure, the first inner lining pattern 140 and the second inner lining pattern 150 may have a relatively large second thickness T2 at the first bending portion V1, and the third inner lining pattern 170 may have a relatively large fourth thickness T4 at the second bending portion V2. Additionally, the first inner lining pattern 140, the second inner lining pattern 150, and the third inner lining pattern 170 may include nitrides, and the nitrides may apply compressive force. In this case, the first inner lining pattern 140 and the second inner lining pattern 150 may apply a relatively large compressive force at the first bending portion V1, and the third inner lining pattern 170 may apply a relatively large compressive force at the second bending portion V2. In other words, because the first inner lining pattern 140, the second inner lining pattern 150, and the third inner lining pattern 170 can apply a relatively large compressive force to the upper electrode pattern 135 in the region adjacent to the upper surface of the variable resistor pattern 133, the adhesive force between the upper electrode pattern 135 and the first inner lining pattern 140 and the third inner lining pattern 170 can be increased. Therefore, the first inner lining pattern 140, the second inner lining pattern 150 and the third inner lining pattern 170 can prevent or reduce gaps between the upper electrode pattern 135 and the first inner lining pattern 140 and the third inner lining pattern 170.

[0040] The first gap-filling pattern 160 may be located between the memory cells 130. For example, the first gap-filling pattern 160 may be located between adjacent memory cells 130 in the second direction II. The first liner pattern 140 and the second liner pattern 150 may be located between the first gap-filling pattern 160 and the memory cells 130. The first gap-filling pattern 160 may include an insulating material such as an oxide.

[0041] The second gap fill pattern 180 may be located between the memory cells 130. For example, the second gap fill pattern 180 may be located between adjacent memory cells 130 in the first direction I. The third liner pattern 170 may be located between the second gap fill pattern 180 and the memory cells 130. The second gap fill pattern 180 may include an insulating material such as an oxide.

[0042] According to the above structure, the upper electrode pattern 135 can cover the area adjacent to the upper surface (or upper portion) of the variable resistor pattern 133 in a cap-like shape. As a result, the path that the chalcogenide elements included in the variable resistor pattern 133 need to move through can be increased by the shape of the upper electrode pattern 135. In addition, the expansion of the area adjacent to the upper surface of the variable resistor pattern 133 can be limited, and gaps between the upper electrode pattern 135 and the first inner liner pattern 140 / third inner liner pattern 170 can be prevented or reduced.

[0043] Furthermore, the first inner liner pattern 140, the second inner liner pattern 150, and the third inner liner pattern 170 may include nitrides and may have relatively large second thicknesses T2 and fourth thicknesses T4 in the region adjacent to the upper surface of the variable resistor pattern 133. Therefore, gaps between the upper electrode pattern 135 and the first inner liner pattern 140 / third inner liner pattern 170 can be prevented or reduced.

[0044] Figures 2A to 9C This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A It is a floor plan, and Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 9B They are along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 9A The cross-sectional view taken by line CC′. Figure 8B and Figure 9C They are along Figure 8A and Figure 9A The cross-sectional view taken by line DD′. For the sake of brevity, content overlapping with the above may be omitted in the following text.

[0045] refer to Figure 2A and Figure 2B A storage layer 220A, including a variable resistance layer 223A, can be formed on the first conductive layer 210A. First, a lower electrode layer 221A can be formed on the first conductive layer 210A. Then, a variable resistance layer 223A can be formed on the lower electrode layer 221A. Subsequently, an upper electrode layer 225A can be formed on the variable resistance layer 223A.

[0046] The upper electrode layer 225A may include a material different from that of the variable resistance layer 223A. The upper electrode layer 225A may include a material selective relative to the variable resistance layer 223A. Specifically, the upper electrode layer 225A may include a material having a lower etching rate than the variable resistance layer 223A. For example, the upper electrode layer 225A may include carbon, and the variable resistance layer 223A may include a chalcogenide material.

[0047] For reference, although not shown in the figure, the storage layer 220A can be formed by sequentially stacking the lower electrode layer 221A, the switch layer, the intermediate electrode layer, the variable resistor layer 223A, and the upper electrode layer 225A.

[0048] Subsequently, a first hard mask pattern HM1 can be formed on the memory layer 220A. Here, the first hard mask pattern HM1 can be formed as a single layer or multiple layers. For example, the first hard mask pattern HM1 can be formed as multiple layers by sequentially stacking nitrides, oxides, and nitrides. The first hard mask pattern HM1 can serve as a protective pattern to prevent or reduce damage to the memory layer 220A in subsequent processes.

[0049] refer to Figure 3A and Figure 3B The upper electrode layer 225A can be etched to form upper electrode lines 225L extending in the first direction I. For example, the upper electrode layer 225A can be etched using a first hard mask pattern HM1 to form respective upper electrode lines 225L extending in the first direction I.

[0050] Subsequently, the variable resistance layer 223A can be etched to a partial thickness. For example, the variable resistance layer 223A can be etched to a partial thickness using a first hard mask pattern HM1 to form trenches extending in the first direction I. Specifically, the variable resistance layer 223A can be partially etched to form trenches of a given depth. The variable resistance layer 223A can be etched in a region adjacent to the upper surface. Here, the region adjacent to the upper surface of the variable resistance layer 223A can refer to the region adjacent to the upper electrode line 225L relative to the middle portion of the variable resistance layer 223A. The variable resistance layer 223A can be etched to a desired thickness by controlling the process environment (such as the time used for etching the variable resistance layer 223A).

[0051] refer to Figure 4A and Figure 4B A first additional electrode layer 225E1 can be formed. For example, the first additional electrode layer 225E1 can be formed along the contour of the variable resistance layer 223A and the upper electrode line 225L. The first additional electrode layer 225E1 can extend on the sidewalls of the upper electrode line 225L adjacent to the second direction II and on the trench formed in the variable resistance layer 223A.

[0052] The first additional electrode layer 225E1 may include a material selective relative to the variable resistance layer 223A. For example, the first additional electrode layer 225E1 may include carbon. The first additional electrode layer 225E1 may include the same material as the upper electrode layer 225A. In other words, the first additional electrode layer 225E1 may include the same material as the upper electrode layer 225A. Therefore, there may be no interface between the first additional electrode layer 225E1 and the upper electrode line 225L, and the first additional electrode layer 225E1 can be used as a single upper electrode layer integrated with the upper electrode line 225L.

[0053] refer to Figure 5A and Figure 5B The variable resistance line 223L can be formed. For example, the variable resistance layer 223A can also be etched to form the variable resistance line 223L. First, the portion of the first additional electrode layer 225E1 formed between two adjacent upper electrode lines 225L arranged along the second direction II can be etched to expose the variable resistance layer 223A. In other words, the portion of the first additional electrode layer 225E1 that contacts the upper surface of the variable resistance layer 223A can be etched to expose the variable resistance layer 223A. Subsequently, the variable resistance layer 223A can be selectively etched to form the variable resistance line 223L. Because the variable resistance layer 223A comprises a material that is selective relative to the upper electrode lines 225L (for example, the variable resistance layer 223A comprises a material whose etching rate is higher than that of the upper electrode lines 225L), the variable resistance layer 223A can be selectively etched. At this time, a portion of the first additional electrode layer 225E1 can be retained to cover the area adjacent to the upper surface of the variable resistance line 223L. In other words, the remaining portions of the etched first additional electrode layer 225E1 each cover the sidewalls of the upper portion of the variable resistance line 223L.

[0054] Subsequently, the lower electrode layer 221A can be etched to form the lower electrode line 221L. Thus, a memory line 220L including the lower electrode line 221L, the variable resistance line 223L, and the upper electrode line 225L can be formed.

[0055] Subsequently, the etching can be performed along the first additional electrode layer 225E1 (for example, after the portions of the first additional electrode layer 225E1 formed between adjacent pairs of upper electrode lines 225L have been etched as described above), Figure 4BThe first inner liner layer 230A is formed by the outlines of the remaining portion of the first additional electrode layer 225E1, the variable resistance line 223L, the lower electrode line 221L, and the first conductive layer 210A. Here, the first inner liner layer 230A may have a bent portion that covers the remaining portion of the upper surface of the first additional electrode layer 225E1 adjacent to the variable resistance line 223L. The first inner liner layer 230A may include a nitride.

[0056] refer to Figure 6A and Figure 6B The first conductive layer 210A can be etched to form first conductive lines 210 extending in the first direction I. First, the first inner liner layer 230A can be etched to form a first inner liner pattern 230. For example, the first inner liner pattern 230 can be formed by etching the portion of the first inner liner layer 230A that contacts the upper surface of the first conductive layer 210A and the portion of the first inner liner layer 230A that contacts the upper surface of the first hard mask pattern HM1. Subsequently, the portion of the first conductive layer 210A exposed between the first inner liner patterns 230 can be etched to form the first conductive lines 210 extending in the first direction I.

[0057] Subsequently, a second inner liner layer 240A extending along the first conductor 210 can be formed on the first inner liner pattern 230. For example, the second inner liner layer 240A can extend on the sidewalls of both the first inner liner pattern 230 and the first conductor 210. Here, because the second inner liner layer 240A is formed on the first inner liner pattern 230, the second inner liner layer 240A can have a bent portion covering the region adjacent to the upper surface of the first additional electrode layer 225E1 and the variable resistance line 223L. The second inner liner layer 240A can include a material that is the same as or different from the material of the first inner liner layer 230A. For example, the second inner liner layer 240A can include a nitride.

[0058] refer to Figure 7A and Figure 7B A first gap-filling layer 250A can be formed to fill the space between the storage lines 220L. Here, the first gap-filling layer 250A may include an insulating material such as an oxide.

[0059] Subsequently, planarization can be performed to expose the upper surface of the upper electrode line 225L. For example, planarization can be performed to remove the first gap filler layer 250A, the second liner layer 240A, and the first hard mask pattern HM1, thereby exposing the upper surface of the upper electrode line 225L. At this time, the second liner layer 240A can be separated into a second liner pattern 240, and the first gap filler layer 250A can be separated into a first gap filler pattern 250.

[0060] refer to Figure 8A and Figure 8B Second conductive lines 260 extending in a second direction II, intersecting the first direction I, can be formed on the upper electrode line 225L. First, a second conductive layer 260A can be formed on the upper electrode line 225L. Then, a second hard mask pattern HM2 can be formed on the second conductive layer 260A. Here, the second hard mask pattern HM2 can have substantially the same shape as the first hard mask pattern HM1 and can include the same material as the first hard mask pattern HM1. Subsequently, the second conductive layer 260A can be etched through the second hard mask pattern HM2 to form the second conductive lines 260 extending in the second direction II.

[0061] Subsequently, the upper electrode line 225L can be etched to form the upper electrode pattern 225. For example, the upper electrode line 225L can be etched using a second hard mask pattern HM2 to form the upper electrode pattern 225.

[0062] Subsequently, the variable resistance line 223L can be etched to a partial thickness. For example, the variable resistance line 223L can be etched to a partial thickness using a second hard mask pattern HM2. Specifically, the variable resistance line 223L can be partially etched to form trenches, each with a given depth. Here, the method for etching the variable resistance line 223L to a partial thickness can be similar to... Figure 3A and Figure 3B The method of etching the variable resistance layer 223A to a certain thickness is basically the same.

[0063] Subsequently, a second additional electrode layer 225E2 can be formed along the contours of the second conductor 260, the upper electrode pattern 225, and the variable resistance line 223L. The second additional electrode layer 225E2 may include a material selective relative to the variable resistance layer 223A. For example, the second additional electrode layer 225E2 may include carbon. The second additional electrode layer 225E2 may include the same material as the upper electrode layer 225A. Therefore, an interface may not exist between the first additional electrode layer 225E1, the second additional electrode layer 225E2, and the upper electrode pattern 225. The first additional electrode layer 225E1 and the second additional electrode layer 225E2 can be used as a single upper electrode pattern integrated with the upper electrode layer 225A.

[0064] refer to Figure 9A and Figure 9BA variable resistance pattern 223 can be formed. For example, the variable resistance line 223L can be etched to form the variable resistance pattern 223. First, the portions of the second additional electrode layer 225E2 formed between two adjacent upper electrode patterns 225 arranged along the second direction II can be etched to expose the variable resistance line 223L. Subsequently, the variable resistance line 223L can be selectively etched to form the variable resistance pattern 223. At this time, a portion of the second additional electrode layer 225E2 can be retained and cover the area adjacent to the upper surface of the variable resistance pattern 223.

[0065] According to one embodiment of this disclosure, the first additional electrode layer 225E1 and the second additional electrode layer 225E2 may cover a region adjacent to the upper surface of the variable resistor pattern 223. For example, the first additional electrode layer 225E1 may partially cover the sidewall of the variable resistor pattern 223 adjacent in the second direction II, and the second additional electrode layer 225E2 may partially cover the sidewall of the variable resistor pattern 223 adjacent in the first direction I. In other words, the first additional electrode layer 225E1 and the second additional electrode layer 225E2 constituting a single upper electrode pattern, as well as the upper electrode pattern 225, may cover the region adjacent to the upper surface of the variable resistor pattern 223 in a cap-like manner. In this case, volume expansion of the region adjacent to the upper surface of the variable resistor pattern 223 due to repeated operation of the memory cell 220 can be prevented or reduced.

[0066] Furthermore, even if the chalcogenide element separates due to the repetitive operation of the memory cell 220, the chalcogenide element needs to move along the interface between the first additional electrode layer 225E1 and the second additional electrode layer 225E2 and the variable resistor pattern 223, and then move to the interface between the first additional electrode layer 225E1 and the second additional electrode layer 225E2 and the first liner pattern 230 and the third liner pattern 270, in order to move along a relatively long path. According to one embodiment of the present disclosure, by increasing the movement path of the chalcogenide element as described above, the separation of the chalcogenide element from the variable resistor pattern 223 can be reduced. Therefore, the degradation of the reliability of the memory cell 220 can be prevented or reduced.

[0067] Subsequently, the lower electrode line 221L can be etched to form the lower electrode pattern 221. Thus, a memory cell 220 including the lower electrode pattern 221, the variable resistor pattern 223, and the upper electrode pattern 225 can be formed.

[0068] Subsequently, along the second conductor 260, the etched second additional electrode layer 225E2 (for example, after the portions of the second additional electrode layer 225E2 formed between two adjacent upper electrode patterns 225 have been etched as described above) can be followed. Figure 8BThe remaining portion of the second additional electrode layer 225E2, the variable resistor pattern 223, the lower electrode pattern 221, and the outline of the first conductor 210 form a third inner liner layer 270A. Here, the third inner liner layer 270A may have a bent portion that covers the remaining portion of the upper surface of the second additional electrode layer 225E2 adjacent to the variable resistor pattern 223. The third inner liner layer 270A may include a nitride.

[0069] Subsequently, a second gap-filling layer 280A can be formed to fill the space between the storage cells 220. Here, the second gap-filling layer 280A may include an insulating material such as an oxide.

[0070] Subsequently, planarization can be performed to expose the upper surface of the second conductor 260. For example, the second gap filler layer 280A, the third inner liner layer 270A, and the second hard mask pattern HM2 can be removed to expose the upper surface of the second conductor 260. At this time, the third inner liner layer 270A can be separated into the third inner liner pattern 270, and the second gap filler layer 280A can be separated into the second gap filler pattern 280.

[0071] According to one embodiment of this disclosure, by forming a first additional electrode layer 225E1 on the upper electrode line 225L, the first inner liner layer 230A and the second inner liner layer 240A may include bent portions. Similarly, by forming a second additional electrode layer 225E2 on the upper electrode pattern 225, the third inner liner layer 270A may include bent portions. The first inner liner layer 230A, the second inner liner layer 240A, and the third inner liner layer 270A may include nitrides, and the nitrides may apply compressive forces. In other words, the paired first inner liner layer 230A and second inner liner layer 240A may apply relatively large compressive forces at the bent portions, and the third inner liner layer 270A may also apply relatively large compressive forces at the bent portions. In this case, the adhesive force between the first additional electrode layer 225E1 / second additional electrode layer 225E2 and the first inner liner layer 230A / third inner liner layer 270A can be increased. Therefore, the first inner liner 230A, the second inner liner 240A, and the third inner liner 270A can prevent or reduce the occurrence of gaps between the first additional electrode layer 225E1 / the second additional electrode layer 225E2 and the first inner liner 230A / the third inner liner 270A.

[0072] According to the manufacturing method described above, a first additional electrode layer 225E1 covering the region adjacent to the upper surface of the variable resistance line 223L can be formed on the upper electrode line 225L, and a second additional electrode layer 225E2 covering the region adjacent to the upper surface of the variable resistance pattern 223 can be formed on the upper electrode pattern 225. The first additional electrode layer 225E1 and the second additional electrode layer 225E2 can be used as a single upper electrode pattern integrated with the upper electrode pattern 225. Therefore, the upper electrode pattern is formed in a cap shape, which can cover the region adjacent to the upper surface of the variable resistance pattern 223. Therefore, even if the operation of the memory cell 220 is repeatedly performed, the expansion of the volume of the variable resistance pattern 223 can be limited, and the separation of the chalcogenide elements included in the variable resistance pattern 223 can be prevented, thus ensuring the reliability of the memory cell 220.

[0073] Furthermore, a first inner liner layer 230A and a second inner liner layer 240A, including bent portions, can be formed on the first additional electrode layer 225E1, and a third inner liner layer 270A, including bent portions, can be formed on the second additional electrode layer 225E2. Here, the first inner liner layer, the second inner liner layer, and the third inner liner layer 270A may include nitrides. Due to the formation of the first additional electrode layer 225E1 and the second additional electrode layer 225E2, the first inner liner layer, the second inner liner layer, and the third inner liner layer 270A can be formed to have a relatively large thickness at the bent portions, thus preventing or reducing gaps between the first additional electrode layer 225E1 / the second additional electrode layer 225E2 and the first inner liner layer 230A / the third inner liner layer 270A.

[0074] Although some embodiments of this disclosure have been described above with reference to the accompanying drawings, the various embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and changes to these embodiments.

Claims

1. A semiconductor device, comprising: A first conductor, the first conductor extending in a first direction; A second conductor, which is located on the first conductor and extends in a second direction that intersects the first direction; as well as A storage unit located between a first conductor and a second conductor, and comprising: a lower electrode pattern, an upper electrode pattern located on the lower electrode pattern, and a variable resistor pattern located between the lower electrode pattern and the upper electrode pattern. The upper electrode pattern includes: A first portion, the first portion being located between the variable resistor pattern and the second conductor; and A pair of second portions, the second portions extending on a first sidewall of the variable resistor pattern facing each other and arranged along the second direction, such that the interface between the first portion and the variable resistor pattern is located between the second portions.

2. The semiconductor device as claimed in claim 1, wherein, The upper electrode pattern further includes a pair of third portions that extend on the second sidewalls of the variable resistance pattern that face each other and are arranged along the first direction, such that the second portion and the third portion of the upper electrode pattern surround the interface between the first portion and the variable resistance pattern. as well as The third portion also extends on the sidewalls of the second conductors that face each other and are arranged along the first direction.

3. The semiconductor device as claimed in claim 2, wherein, Each of the third portions contacts a corresponding second sidewall in the second sidewall of the variable resistor pattern and a corresponding sidewall in the sidewall of the second conductor.

4. The semiconductor device of claim 2, wherein, Each of the second portions has a first height in a cross section located in a first plane defined by the second direction and the third direction; Wherein, each of the third portions has a second height greater than the first height in a cross-section located within a second plane defined by the first direction and the third direction; and The third direction intersects with the first direction and the second direction.

5. The semiconductor device as claimed in claim 1, wherein, The first portion contacts the upper surface of the variable resistor pattern, and Each of the second portions is in contact with a corresponding first sidewall in the first sidewall of the variable resistor pattern.

6. The semiconductor device of claim 1, further comprising: A first liner pattern covers the sidewall of the storage cell along the outline of the storage cell, the sidewall of the storage cell being adjacent to the first liner pattern in the second direction; as well as A second lining pattern is located on the first lining pattern and extends along the sidewall of the first guide wire.

7. The semiconductor device of claim 6, wherein, The paired first and second lining patterns include bent portions that cover the lower surface of the corresponding second portion of the second portion.

8. The semiconductor device of claim 7, wherein, The paired first and second liner patterns have a first thickness in the region adjacent to the upper electrode pattern, and The paired first lining pattern and second lining pattern have a second thickness in the bent portion, the second thickness being greater than the first thickness.

9. The semiconductor device of claim 6, wherein, At least one of the first lining pattern or the second lining pattern includes a nitride.

10. The semiconductor device of claim 1, wherein, The upper electrode pattern comprises a material that is selective relative to the variable resistance pattern.

11. The semiconductor device of claim 10, wherein, The upper electrode pattern comprises carbon, and The variable resistance pattern comprises chalcogenide material.

12. A semiconductor device, comprising: A first conductor, the first conductor extending in a first direction; A second conductor, which is located on the first conductor and extends in a second direction that intersects the first direction; as well as A storage unit located between a first conductor and a second conductor, and comprising: a lower electrode pattern, an upper electrode pattern located on the lower electrode pattern, and a variable resistor pattern located between the lower electrode pattern and the upper electrode pattern. The upper electrode pattern includes: The first part is located between the variable resistor pattern and the second conductor; A pair of second portions, the second portions extending on the first sidewalls of the variable resistor pattern facing each other and arranged along the second direction; and A pair of third portions, the third portions extending on the second sidewalls of the variable resistor pattern that face each other and are arranged along the first direction, and on the sidewalls of the second conductors that face each other and are arranged along the first direction, and The second and third portions of the upper electrode pattern surround the interface between the first portion and the variable resistor pattern.

13. The semiconductor device of claim 12, wherein, The first portion contacts the upper surface of the variable resistor pattern, and Each of the second portions is in contact with a corresponding first sidewall in the first sidewall of the variable resistor pattern.

14. The semiconductor device of claim 12, wherein, Each of the third portions contacts the corresponding sidewall of the sidewall of the second conductor.

15. The semiconductor device of claim 12, wherein, Each of the second portions has a first height in a cross-section located in a first plane defined by the second direction and the third direction. Wherein, each of the third portions has a second height greater than the first height in a cross-section located in a second plane defined by the second direction and the third direction, and The third direction intersects with the first direction and the second direction.

16. The semiconductor device of claim 12, further comprising: A first liner pattern covers the sidewall of the storage cell along the outline of the storage cell, the sidewall of the storage cell being adjacent to the first liner pattern in the second direction; as well as A second lining pattern is located on the first lining pattern and extends along the sidewall of the first guide wire.

17. The semiconductor device of claim 16, wherein, The paired first and second lining patterns include bent portions that cover the lower surface of the corresponding second portion of the second portion.

18. The semiconductor device of claim 17, wherein, The paired first and second liner patterns have a first thickness in the region adjacent to the upper electrode pattern, and The paired first lining pattern and second lining pattern have a second thickness in the bent portion, the second thickness being greater than the first thickness.

19. The semiconductor device of claim 16, wherein, At least one of the first lining pattern or the second lining pattern contains a nitride.

20. The semiconductor device of claim 12, wherein, The upper electrode pattern comprises a material that is selective relative to the variable resistance pattern.

21. The semiconductor device of claim 20, wherein, The upper electrode pattern comprises carbon, and The variable resistance pattern comprises chalcogenide material.

22. A method for manufacturing a semiconductor device, the method comprising: A lower electrode layer, a variable resistance layer, and an upper electrode layer are sequentially formed on the first conductive layer; Upper electrode lines extending in a first direction are formed by etching the upper electrode layer. The variable resistance layer is partially etched; A first additional electrode layer is formed along the contour of the upper electrode line and the variable resistance layer; as well as Variable resistance lines are formed by further etching the variable resistance layer.

23. The method of claim 22, wherein, The steps for forming the variable resistance wire include: The variable resistance layer is exposed by etching the portions of the first additional electrode layer formed between adjacent pairs of upper electrode lines; and The variable resistance lines are formed by selectively etching the variable resistance layer.

24. The method of claim 23, wherein, The first additional electrode layer comprises the same material as the upper electrode layer, and The first additional electrode layer contains a material that is selective relative to the variable resistance layer.

25. The method of claim 24, wherein, The first additional electrode layer comprises carbon, and The variable resistance layer comprises a chalcogenide material.

26. The method of claim 23, further comprising: The lower electrode line is formed by etching the lower electrode layer; A first inner liner layer is formed along the contour of the etched first additional electrode layer, the variable resistance line, the lower electrode line, and the first conductive layer. as well as The first liner pattern is formed by etching the first liner layer.

27. The method of claim 26, further comprising: First conductive lines extending in the first direction are formed by etching the first conductive layer. as well as A second liner layer is formed extending over the first conductor and the first liner pattern.

28. The method of claim 27, wherein, At least one of the first liner or the second liner contains a nitride.

29. The method of claim 27, further comprising: Second conductors are formed on the upper electrode lines, each extending in a second direction that intersects the first direction. The upper electrode pattern is formed by etching the upper electrode lines; The variable resistance line is partially etched; A second additional electrode layer is formed along the outline of the second conductor, the upper electrode pattern, and the variable resistance line; as well as The variable resistance pattern is formed by further etching the variable resistance lines.

30. The method of claim 29, further comprising: The variable resistance lines are exposed by etching the portions of the second additional electrode layer that are formed between adjacent pairs of the upper electrode patterns. as well as The variable resistance pattern is formed by selectively etching the variable resistance lines.

31. The method of claim 29, wherein, The second additional electrode layer comprises the same material as the upper electrode layer, and The second additional electrode layer comprises a material that is selective relative to the variable resistance layer.

32. The method of claim 31, wherein, The second additional electrode layer comprises carbon, and The variable resistance layer comprises a chalcogenide material.

33. The method of claim 30, further comprising: The lower electrode pattern is formed by etching the lower electrode lines; as well as A third inner liner is formed along the second conductor, the etched second additional electrode layer, the variable resistance pattern, the lower electrode pattern, and the outline of the first conductor.

34. The method of claim 33, wherein, The third inner liner contains nitrides.

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