Semiconductor element and manufacturing method thereof
By setting a first doped region with a high doping concentration and a second doped region with different conductivity types in a semiconductor device, the reverse leakage current and forward voltage of the Schottky diode are reduced, thereby improving the overall efficiency of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HON YOUNG SEMICON CORP
- Filing Date
- 2024-10-14
- Publication Date
- 2026-04-14
AI Technical Summary
Existing Schottky diodes suffer from a large reverse leakage current, which is difficult to effectively reduce while maintaining a low forward voltage.
A first doped region and a second doped region are provided in a semiconductor device. The first doped region has the same conductivity as the epitaxial layer and a high dopant concentration. The second doped region has a different conductivity than the epitaxial layer and extends partially below the first doped region to form an ohmic contact to reduce the height of the Schottky barrier.
This effectively reduces the reverse leakage current of the Schottky diode, decreases conduction losses, and improves overall efficiency.
Smart Images
Figure CN121865637A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor element and a method for manufacturing the same. Background Technology
[0002] Schottky barrier diodes (SBDs) are characterized by fast switching speed and high forward voltage (V). F Schottky diodes have gained significant attention in recent years due to their advantages such as low power density, high power density, and ability to operate at high temperatures. However, they also suffer from reverse leakage current (If). R This has significant drawbacks. Therefore, how to reduce reverse leakage current while maintaining a low forward voltage is one of the problems that the industry urgently needs to address through research and development. Summary of the Invention
[0003] In view of this, one object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.
[0004] One aspect of the present invention relates to a method of manufacturing a semiconductor device, comprising performing a first implantation process to form a first doped region in an epitaxial layer. The epitaxial layer and the first doped region have a first conductivity type. The manufacturing method further comprises performing a second implantation process to form a first portion of a second doped region located in the epitaxial layer. The first portion of the second doped region has a second conductivity type different from the first conductivity type and is adjacent to the first doped region. The manufacturing method further comprises performing a third implantation process to form a second portion of the second doped region having the second conductivity type located in the epitaxial layer. The second portion of the second doped region is vertically located below the first doped region. The manufacturing method further comprises forming an electrode structure. The electrode structure is electrically connected to the first doped region and the second doped region.
[0005] Another aspect of the present invention relates to a semiconductor device comprising an epitaxial layer, a first doped region, a second doped region, a first conductive layer, and a second conductive layer. The epitaxial layer has a first conductivity type. The first doped region is located in the epitaxial layer and has the first conductivity type. The second doped region is located in the epitaxial layer and has a second conductivity type different from the first conductivity type. The second doped region extends from a sidewall of the first doped region to below the bottom surface of the first doped region. The first conductive layer is located above the epitaxial layer and is electrically connected to the first doped region. The second conductive layer is located above the epitaxial layer and is electrically connected to the second doped region.
[0006] In summary, in some embodiments of the semiconductor device and its manufacturing method of the present invention, a first doped region (such as an n-type doped region) is provided between the conductive layer forming the Schottky contact and the epitaxial layer. This first doped region has the same conductivity as the epitaxial layer and a higher dopant concentration, which reduces the Schottky barrier height and helps to reduce the forward voltage. Furthermore, providing a second doped region (such as a p-type doped region) with a different conductivity than the epitaxial layer, electrically connecting it to the conductive layer forming the ohmic contact, and extending partially below the first doped region, helps to reduce the reverse leakage current. Compared to common semiconductor devices and their manufacturing methods, this reduces the conduction losses of the semiconductor device and improves the overall efficiency.
[0007] These and other aspects of the invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, but variations and modifications may be made therein without departing from the spirit and scope of the novel concept of the invention. Attached Figure Description
[0008] The accompanying drawings illustrate one or more embodiments of the invention and, together with the written description, serve to explain the principles of the invention. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein:
[0009] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.
[0010] Figures 2 to 5 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor device according to some embodiments of the present invention.
[0011] Figure 6 and Figure 7 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor device according to other embodiments of the present invention. Detailed Implementation
[0012] The following disclosure will be described more fully with reference to the accompanying drawings and reference data, some of which illustrate exemplary embodiments. The invention may be embodied in different forms and should not be limited to the embodiments mentioned below. However, these embodiments are provided to aid in a more complete understanding of the invention and to fully convey the scope of the invention to those skilled in the art.
[0013] Please refer to Figure 1 This is a cross-sectional schematic diagram of a semiconductor element 10 according to some embodiments of the present invention.
[0014] Semiconductor device 10 includes a substrate 104, an epitaxial layer 106, a first doped region 108, and a second doped region 110. The epitaxial layer 106 is located above the substrate 104. The first doped region 108 and the second doped region 110 are located in the epitaxial layer 106. The first doped region 108 and the second doped region 110 are adjacent to each other and alternately arranged.
[0015] like Figure 1 As shown, the second doped region 110 extends from the sidewall of the first doped region 108 to below the bottom surface of the first doped region 108. In other words, the bottom depth of the second doped region 110 is greater than the bottom depth of the first doped region 108. For example, the bottom depth of the first doped region 108 can be a distance between 0.005 micrometers and 0.5 micrometers extending downwards from the top surface of the epitaxial layer 106, while the bottom depth of the second doped region 110 can be a distance between 0.05 micrometers and 0.5 micrometers extending downwards from the top surface of the epitaxial layer 106.
[0016] Furthermore, the second doped region 110 has a first portion 110-1 and a second portion 110-2. The first portion 110-1 is adjacent to and contacts the sidewall of the first doped region 108. The second portion 110-2 is located below the bottom surface of the first doped region 108. In some embodiments, such as Figure 1 As shown, the bottom depth of the first portion 110-1 is greater than the bottom depth of the second portion 110-2. In other embodiments, the bottom surface of the first portion 110-1 may be flush with the bottom depth of the second portion 110-2. Furthermore, in some embodiments, the second portion 110-2 is spaced from the bottom surface of the first doped region 108 in a vertical direction (e.g., a direction perpendicular to the surface of the substrate 104). For example, as... Figure 1 As shown, a portion of the epitaxial layer 106 is located between the second portion 110-2 and the bottom surface of the first doped region 108. In other embodiments, the second portion 110-2 may contact the bottom surface of the first doped region 108. In some embodiments, the second portions 110-2 of two adjacent second doped regions 110 are separated by the epitaxial layer 106.
[0017] The substrate 104, epitaxial layer 106, and first doped region 108 have a first conductivity type. For example, the substrate 104, epitaxial layer 106, and first doped region 108 are n-type semiconductor layers. In some embodiments, the substrate 104, epitaxial layer 106, and first doped region 108 have the same n-type dopant. The dopant concentration of the substrate 104 is greater than the dopant concentration of the epitaxial layer 106. In other words, the substrate 104 is relatively heavily doped, while the epitaxial layer 106 is relatively lightly doped. For example, the dopant concentration of the substrate 104 is 10... 18 # / cm 3 With 10 19 # / cm3 The doping concentration of the epitaxial layer 106 is between 2 × 10⁻⁶ and 2 × 10⁻⁶. 15 # / cm 3 With 10 16 # / cm 3 The dopant concentration in the first doped region 108 is greater than that in the epitaxial layer 106. For example, the dopant concentration in the first doped region 108 is between 5 × 10⁻⁶ and 10⁻⁶. 17 # / cm 3 With 5×10 18 # / cm 3 Between. The epitaxial layer 106 can be formed as a drift region of the semiconductor device 10.
[0018] The second doped region 110 has a second conductivity type different from the first conductivity type. For example, the second doped region 110 is a p-type semiconductor layer, i.e., it has p-type dopants. In some embodiments, the dopant concentration of the second doped region 110 is 5 × 10⁻⁶. 17 # / cm 3 With 5×10 18 # / cm 3 between.
[0019] The semiconductor device 10 also includes an electrode structure. The electrode structure includes a conductive layer 102, a conductive layer 112, and a conductive layer 114. For example... Figure 1 As shown, conductive layer 102 is located below substrate 104. Conductive layer 102 can be formed as an ohmic contact. Conductive layers 112 and 114 are located above epitaxial layer 106. Conductive layer 114 contacts and is electrically connected to the first portion 110-1 of the second doped region 110, and is formed as an ohmic contact. In some embodiments, conductive layer 114 may comprise a metal compound of the material of epitaxial layer 106. For example, epitaxial layer 106 comprises silicon (Si) or silicon carbide (SiC), while conductive layer 114 comprises a metal silicide material such as nickel silicide (NiSi). x The conductive layer 112 contacts and is electrically connected to the first doped region 108, forming a Schottky contact. The conductive layer 112 is located between two adjacent conductive layers 114 and extends above the upper surface of the conductive layer 114 to protect the structure of the conductive layer 114 and ensure its electrical properties. In some embodiments, the conductive layer 112 comprises a metallic material such as titanium (Ti) or nickel (Ni).
[0020] As previously mentioned, the dopant concentration of the first doped region 108 is greater than that of the epitaxial layer 106. Therefore, the Schottky barrier height between the conductive layer 112 and the epitaxial layer 106 in contact with the first doped region 108 can be reduced, which helps to lower the forward voltage. On the other hand, the second portion 110-2 of the second doped region 110 located below the first doped region 108 helps to reduce the increased reverse leakage current due to the reduced Schottky barrier height. In this way, the conduction losses of the semiconductor device 10 can be reduced and the overall efficiency improved.
[0021] Furthermore, the semiconductor element 10 may also include a passivation layer 116 located above the epitaxial layer 106 and on opposite sides of the conductive layer 114. In some embodiments, the passivation layer 116 is partially located above and in contact with the second doped region 110.
[0022] In some embodiments, semiconductor element 10 is a type of Schottky diode. However, in other embodiments, semiconductor element 10 can be any type of semiconductor element with a Schottky contact, such as a metal oxide semiconductor field-effect transistor (MOSFET).
[0023] Please refer to Figures 2 to 5 These are cross-sectional schematic diagrams of intermediate stages in the manufacturing method of a semiconductor element 10 according to some embodiments of the present invention.
[0024] In the manufacturing method of semiconductor element 10, such as Figure 2 As shown, a first implantation process is performed on a substrate structure via masks 120 and 122. The substrate structure includes a substrate 104 and an epitaxial layer 106. As previously described, the substrate 104 and the epitaxial layer 106 have a first conductivity type. For example, the substrate 104 and the epitaxial layer 106 are n-type semiconductor layers or have n-type dopants. The first implantation process is performed to form a first doped region 108A in the epitaxial layer 106. The first doped region 108A has a first conductivity type. The dopant concentration of the first doped region 108A is greater than the dopant concentration of the epitaxial layer 106.
[0025] In some embodiments, mask 120 and mask 122 comprise the same material. In other embodiments, mask 120 and mask 122 comprise different materials; for example, mask 120 comprises polysilicon, while mask 122 comprises silicon dioxide (SiO2).
[0026] Next, as Figure 3As shown, the patterns of masks 120 and 122 are adjusted, and a second implantation process is performed through masks 120 and 122 to form a plurality of second doped regions 110A and a plurality of first doped regions 108 in the epitaxial layer 106. Further, the second implantation process forms a plurality of spaced second doped regions 110A, such that the first doped regions 108 and second doped regions 110A are adjacent and alternately arranged. The bottom depth of the second doped regions 110A is greater than the bottom depth of the first doped regions 108. The second implantation process causes the second doped regions 110A to have a second conductivity type different from the first conductivity type. For example, the second doped region 110 is a p-type semiconductor layer or has p-type dopants. It is worth noting that in some embodiments, since the location where the second doped regions 110A are formed is exposed in the first implantation process, the n-type dopant concentration in the portion of the second doped region 110A near the top surface is greater than the n-type dopant concentration in the remaining portion of the second doped region 110A. In other words, the n-type dopant concentration of the first portion 110-1 varies with vertical depth. In addition, Figure 3 In the embodiment shown, the doping range of the second doped region 110A is substantially equivalent to the doping range of the first portion 110-1 of the second doped region 110.
[0027] Next, as Figure 4 As shown, after the second implantation process is completed, the patterns of mask 120 and mask 122 are adjusted again, and a third implantation process is performed through mask 120 and mask 122 to form the second portion 110-2 of the second doped region 110 in the epitaxial layer 106. After the third implantation process, the second doped region 110 includes a first portion 110-1 and a second portion 110-2. The second portion 110-2 is vertically located below the first doped region 108. In some embodiments, the third implantation process is performed such that the second portion 110-2 is vertically separated from the bottom surface of the first doped region 108 by the epitaxial layer 106. In other embodiments, the second portion 110-2 may contact the bottom surface of the first doped region 108. Furthermore, since... Figure 3 The location of the second doped region 110A remains exposed during the third implantation process. Therefore, the first region 110-1 formed has a larger p-type dopant concentration at the same horizontal height as the second region 110-2. In other words, the p-type dopant concentration of the first region 110-1 also varies with vertical depth.
[0028] Next, as Figure 5 As shown, a conductive layer 114 is formed above the epitaxial layer 106. Furthermore, the conductive layer 114 is formed such that it contacts the first portion 110-1 of the second doped region 110 and is electrically connected to the second doped region 110 to form an ohmic contact.
[0029] Next, please return to Figure 1 A conductive layer 112 is formed above the epitaxial layer 106, such that the conductive layer 112 contacts and is electrically connected to the first doped region 108 to form a Schottky contact. Simultaneously, the conductive layer 112 extends over and covers the conductive layer 114. Furthermore, a conductive layer 102 is formed below the substrate 104 to form an ohmic contact. In some embodiments, the method of manufacturing the semiconductor element 10 further includes forming a passivation layer 116 above the epitaxial layer 106 and located on opposite sides of the conductive layer 114.
[0030] In some implementations, the process sequence can be adjusted so that the third injection process is performed before the second injection process. For example, please refer to... Figure 6 and Figure 7 These are schematic cross-sectional views of intermediate stages in the manufacturing method of a semiconductor element 10 according to other embodiments of the present invention. Figure 6 As shown, after performing the first implantation process, a third implantation process is performed first to form a second doped region 110A below the first doped region 108A. The bottom depth of the second doped region 110A is greater than the bottom depth of the first doped region 108A, and the second doped region 110A and the first doped region 108A are spaced apart in the vertical direction. In these embodiments, the doping range of the second doped region 110A includes the doping range of the second portion 110-2 of the second doped region 110. Next, as... Figure 7 As shown, after performing the third implantation process, a second implantation process is performed to form a first portion 110-1 of the second doped region 110 in the epitaxial layer 106. In these embodiments, after performing the second implantation process, the second doped region 110 includes a first portion 110-1 and a second portion 110-2.
[0031] From the detailed description of specific embodiments of the present invention above, it is evident that in some embodiments of the semiconductor device and its manufacturing method, by providing a first doped region (e.g., an n-type doped region) between the conductive layer forming the Schottky contact and the epitaxial layer, and by making the first doped region have the same conductivity type as the epitaxial layer and a larger dopant concentration, the Schottky barrier height can be reduced, which helps to reduce the forward voltage. Furthermore, by providing a second doped region (e.g., a p-type doped region) with a different conductivity type than the epitaxial layer, electrically connecting it to the conductive layer forming the ohmic contact, and partially extending below the first doped region, reverse leakage current can be reduced. Compared to common semiconductor devices and their manufacturing methods, the conduction losses of the semiconductor device can be reduced and the overall efficiency improved.
[0032] The foregoing description is only intended to illustrate and describe exemplary embodiments of the present invention and is not intended to exhaustively describe or limit the precise forms of the invention disclosed herein. The above teachings may be modified or varied.
[0033] The selected and illustrated embodiments are intended to explain the content of the invention and its practical application, thereby encouraging those skilled in the art to utilize the invention and its various embodiments, and to make various modifications to suit specific intended uses. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the appended claims, and not by the foregoing description and the exemplary embodiments described therein.
[0034] [Symbol Explanation]
[0035] 10: Semiconductor components
[0036] 102, 112, 114: Conductive layer
[0037] 104: Substrate
[0038] 106: Epitaxial layer
[0039] 108, 108A: First doped region
[0040] 110, 110A: Second doped region
[0041] 110-1: First part
[0042] 110-2: Second part
[0043] 116: Passivation layer
[0044] 120,122: Masking.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: A first implantation process is performed to form a first doped region in the epitaxial layer, wherein the epitaxial layer and the first doped region have a first conductivity type; A second implantation process is performed to form a first portion of a second doped region having a second conductivity type different from the first conductivity type located in the epitaxial layer, wherein the first portion of the second doped region is adjacent to the first doped region; A third implantation process is performed to form a second portion of the second doped region having the second conductivity type located in the epitaxial layer, wherein the second portion of the second doped region is vertically located below the first doped region; as well as An electrode structure is formed, which is electrically connected to the first doped region and the second doped region.
2. The manufacturing method as described in claim 1, characterized in that, The second implantation process is performed such that the bottom depth of the first portion of the second doped region is greater than the bottom depth of the first doped region.
3. The manufacturing method as described in claim 1, characterized in that, The third injection process is performed before the second injection process is performed.
4. The manufacturing method as described in claim 1, characterized in that, After performing the second injection process, the third injection process is performed.
5. The manufacturing method as described in claim 1, characterized in that, The third implantation process is performed such that a portion of the epitaxial layer is vertically located between the second portion of the second doped region and the first doped region.
6. The manufacturing method as described in claim 1, characterized in that, The electrode structure includes ohmic contacts and Schottky contacts.
7. The manufacturing method as described in claim 6, characterized in that, The ohmic contact contacts the first portion of the second doped region, and the Schottky contact contacts the first doped region and extends to the upper surface of the ohmic contact.
8. A semiconductor element, characterized in that, Include: The epitaxial layer has a first conductivity type; The first doped region is located in the epitaxial layer and has the first conductivity type; The second doped region is located in the epitaxial layer and has a second conductivity type different from the first conductivity type, wherein the second doped region extends from the sidewall of the first doped region to below the bottom surface of the first doped region. A first conductive layer is located above the epitaxial layer and electrically connected to the first doped region; as well as The second conductive layer is located above the epitaxial layer and is electrically connected to the second doped region.
9. The semiconductor device as claimed in claim 8, characterized in that, The second doped region has a portion extending below the bottom surface of the first doped region and spaced apart from the bottom surface in the vertical direction.
10. The semiconductor device as claimed in claim 8, characterized in that, The first conductive layer is a metallic material, and the second conductive layer is a metal silicide material.