Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and forming at least two first openings in the first mask layer; performing first ion implantation on the substrate to form at least two first body regions; forming a second mask layer on the side wall of the first opening, wherein the width of the second mask layer is the first width; second ion implantation is carried out, and a first source region is formed in the first body region; forming a dielectric layer filling the first opening; removing the first mask layer between the first body regions to form a second opening; forming a third mask layer on the side wall of the second opening; third ion implantation is carried out, and a second body region is formed in the substrate; a fourth mask layer is formed on the side wall of the third mask layer, the width of the fourth mask layer is a second width, and the second width is larger than or smaller than the first width; and performing fourth ion implantation, and forming a second source region in the second body region. According to the invention, channels with different lengths can be formed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] One of the main types of devices in the field of power semiconductors is the metal-oxide field-effect transistor (MOSFET). Among them, SiC material has the characteristics of large bandgap, high critical breakdown electric field, fast saturated electron drift velocity and high thermal conductivity, making it an ideal material for manufacturing high voltage, high power density and high temperature MOSFETs.

[0003] In linear-mode applications such as active loads, the switching speed of MOSFETs should be appropriately slowed down to limit inrush current. During switching, high current and high voltage can cause significant heat dissipation. After the switching process, the MOSFET continues to operate in the on-state, so a low on-resistance is required to reduce power consumption.

[0004] However, the low on-resistance, high gain, and fast switching speed of current SiC MOSFETs result in a smaller safe operating area, making SiC MOSFETs more susceptible to thermal runaway when operating in linear mode. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:

[0007] A substrate is provided, and a patterned first mask layer is formed on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate;

[0008] A first ion implantation is performed through the first opening to form at least two spaced-apart first body regions having a first conductivity type in the substrate;

[0009] A second mask layer is formed on the sidewall of the first opening, the width of the second mask layer being the first width;

[0010] A second ion implantation is performed on the exposed first body region to form a first source region having a second conductivity type in the first body region;

[0011] A dielectric layer is formed to fill the first opening;

[0012] Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate;

[0013] A third mask layer is formed on the sidewall of the second opening;

[0014] A third ion implantation is performed through the second opening to form a second body region having a first conductivity type in the substrate;

[0015] A fourth mask layer is formed on the sidewall of the third mask layer, the width of the fourth mask layer being a second width, which is greater than or less than the first width;

[0016] A fourth ion implantation is performed on the exposed second body region to form a second source region having a second conductivity type in the second body region.

[0017] For example, the width of the second body region is greater than or less than the width of the first body region.

[0018] For example, an oxidation process is used to form the third mask layer on the sidewall of the second opening.

[0019] For example, forming the second mask layer on the sidewall of the first opening includes: forming a first sidewall layer on the bottom and sidewall of the first opening; etching away a portion of the first sidewall layer located at the bottom of the first opening to retain a portion of the first sidewall layer located on the sidewall of the first opening, thereby obtaining the second mask layer;

[0020] Forming the fourth mask layer on the sidewall of the third mask layer includes: forming a second sidewall layer at the bottom and on the sidewall of the second opening; etching away a portion of the second sidewall layer at the bottom of the second opening to retain a portion of the second sidewall layer on the sidewall of the second opening, thereby obtaining the fourth mask layer.

[0021] For example, after performing a fourth ion implantation on the exposed second body region to form a second source region having a second conductivity type in the second body region, the method further includes:

[0022] Remove the remaining first mask layer, second mask layer, third mask layer, fourth mask layer and dielectric layer;

[0023] A patterned fifth mask layer is formed on the first surface of the substrate, the fifth mask layer exposing a portion of the surfaces of the first source region and the second source region;

[0024] A fifth ion implantation is performed on the exposed first source region and second source region to form a body contact region that penetrates the first source region and the second source region in the first body region and the second body region;

[0025] Remove the fifth mask layer.

[0026] Exemplarily, after removing the fifth mask layer, the method further includes:

[0027] A gate oxide layer is formed on a first surface of the substrate, and a gate electrode layer located between the first source region and the second source region is formed on the gate oxide layer;

[0028] An interlayer dielectric layer is formed on the gate electrode layer and the gate oxide layer;

[0029] Etching removes a portion of the interlayer dielectric layer to form a first contact hole in the interlayer dielectric layer that exposes the surfaces of the bulk contact region and a portion of the first source region and the second source region;

[0030] A first conductive layer is formed, which covers the interlayer dielectric layer and fills the first contact hole;

[0031] A passivation layer and a protective layer are sequentially formed on the first conductive layer;

[0032] Etching removes a portion of the passivation layer and the protective layer to expose a portion of the first conductive layer.

[0033] Exemplarily, after etching away the passivation layer and the protective layer to expose a portion of the first conductive layer, the method further includes:

[0034] The second surface of the substrate is thinned;

[0035] A drain electrode is formed on the second surface of the substrate.

[0036] For example, the substrate includes a SiC epitaxial layer.

[0037] This application also provides a semiconductor device, which is manufactured using the method described above.

[0038] In another aspect, this application provides an electronic device, which includes the semiconductor device described above.

[0039] The semiconductor device and its manufacturing method, and electronic device of the present application embodiments, by forming a second mask layer and a fourth mask layer with different widths, can form channels of different lengths in the first body region and the second body region. That is, channels of different lengths can be formed at different locations of the device. In this way, parallel current sharing can be achieved by controlling the channel distribution, which can realize dynamic control of switching speed and optimization of loss during switching and conduction processes. This makes the device more suitable for operation in linear mode and improves the device's shock resistance. Attached Figure Description

[0040] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0041] In the attached image:

[0042] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown;

[0043] Figures 2A-2R This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of this application. Detailed Implementation

[0044] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0050] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0051] From the perspective of device thermal stability, the rate of power generation should ideally be less than the rate of power dissipation. Therefore, thermal runaway tends to occur in the part of the die design where the current density is high but the thermal performance is poor. In other words, the current density distribution and temperature distribution when a device fails thermally are usually very uneven. The area near the source pad will occupy most of the current and also has a higher risk of thermal failure.

[0052] However, current SiC MOSFETs generally only have one channel length, making it impossible to achieve parallel current sharing by adjusting the channel distribution. At the same time, it is also difficult to optimize the losses during the switching and conduction processes by dynamically adjusting the switching speed. As a result, SiC MOSFETs are more susceptible to thermal runaway when operating in linear mode.

[0053] In related technologies, to achieve multiple channel length designs for SiC MOSFETs, multiple photolithography processes on multi-layer boards are required, which is a complex process.

[0054] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, as shown in Figure 2, which mainly includes the following steps:

[0055] Step S1: Provide a substrate and form a patterned first mask layer on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate;

[0056] Step S2: Perform first ion implantation through the first opening to form at least two spaced-apart first body regions with a first conductivity type in the substrate;

[0057] Step S3: A second mask layer is formed on the sidewall of the first opening, the width of the second mask layer being the first width;

[0058] Step S4: Perform a second ion implantation on the exposed first body region to form a first source region having a second conductivity type in the first body region;

[0059] Step S5: Form a dielectric layer that fills the first opening;

[0060] Step S6: Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate;

[0061] Step S7: A third mask layer is formed on the sidewall of the second opening;

[0062] Step S8: Perform third ion implantation through the second opening to form a second body region having a first conductivity type in the substrate;

[0063] Step S9: A fourth mask layer is formed on the sidewall of the third mask layer. The width of the fourth mask layer is a second width, which is greater than or less than the first width.

[0064] Step S10: Perform a fourth ion implantation on the exposed second body region to form a second source region having a second conductivity type in the second body region.

[0065] The semiconductor device manufacturing method of this application, by forming a second mask layer and a fourth mask layer with different widths, can form channels of different lengths in the first body region and the second body region. That is, it can form channels of different lengths at different locations of the device, and then achieve parallel current sharing by controlling the channel distribution. This can achieve dynamic control of switching speed and optimization of losses during switching and conduction processes, making the device more suitable for operation in linear mode, while improving the device's shock resistance.

[0066] Example 1

[0067] Below, for reference Figures 1 to 2RThe method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Figures 2A-2R This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0068] For example, the method for manufacturing the semiconductor device of this application includes the following steps:

[0069] First, step S1 is performed, providing a substrate and forming a patterned first mask layer on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate.

[0070] In one example, such as Figure 2A As shown, substrate 200 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, substrate 200 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 200 have been described herein, any material that can serve as substrate 200 falls within the spirit and scope of this application. Exemplarily, substrate 200 has a second conductivity type.

[0071] In one example, substrate 200 includes a substrate and a SiC epitaxial layer located on the substrate. Optionally, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Exemplarily, the semiconductor substrate and the epitaxial layer may have different doping concentrations; for example, the doping concentration of the epitaxial layer may be lower than that of the semiconductor substrate. Optionally, the epitaxial layer may serve as a drift region for the semiconductor device of this application, the presence of which provides the device's breakdown voltage and acts as a buffer.

[0072] In one example, such as Figure 2AAs shown, a first mask layer 201 can be formed on the first surface of the substrate 200 using various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD). The material of the first mask layer 201 includes, but is not limited to, one or more of polysilicon, silicon oxide, and silicon nitride; this application does not impose any limitations on this. Exemplarily, after forming the first mask layer 201, a photolithography process can be used to pattern the first mask layer 201 to form at least two first openings 202 exposing portions of the first surface of the substrate 200, with multiple first openings 202 spaced apart. For example, taking the multiple first openings 202 spaced apart along a first direction, the spacing between adjacent first openings 202 should be reasonably set according to the width of the subsequently formed second body region along the first direction and the distance between the second body region and the first body region.

[0073] Next, proceed to step S2, as follows: Figure 2B As shown, a first ion implantation is performed through a first opening 202 to form at least two spaced-apart first body regions 203 of a first conductivity type in a substrate 200, wherein the first body regions 203 extend from a first surface of the substrate 200 into the substrate 200. In this embodiment, the first conductivity type can be P-type and the second conductivity type can be N-type; in other embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. For example, the first body region 203 is of P-type conductivity, and the implanted ions in the first ion implantation include Al ions.

[0074] Next, proceed to step S3, as follows: Figure 2CAs shown, a second mask layer 204 is formed on the sidewall of the first opening 202, and the width of the second mask layer 204 is the first width. Exemplarily, the second mask layer can be formed on the sidewall of the first opening 202 using a self-aligned process employing a spacer process. Specifically, forming the second mask layer 204 on the sidewall of the first opening 202 using a spacer process includes: forming a first sidewall layer at the bottom and on the sidewall of the first opening; etching away a portion of the first sidewall layer located at the bottom of the first opening to retain a portion of the first sidewall layer on the sidewall of the first opening 202, resulting in the second mask layer 204, i.e., the second mask layer 204 is the remaining portion of the first sidewall layer on the sidewall of the first opening 202. Exemplarily, the material of the first sidewall layer can be pure silicon oxide, pure polysilicon, pure silicon nitride, a composite material of silicon nitride and silicon oxide, a composite material of polysilicon and silicon oxide, or other materials. In this embodiment, when the first sidewall layer is a composite material, silicon nitride and silicon oxide in the composite material can serve as stop layers when etching the first sidewall layer; when the first sidewall layer is a single material, it can be etched using a timed etching method. Exemplarily, the first width ranges from 0.3µm to 1µm, or it can be any other suitable width range, depending on the actual channel length requirements, which this application does not limit. Exemplarily, the width of the second mask layer 204 being the first width refers to the width of the second mask layer 204 in the horizontal direction being the first width; taking a plurality of first body regions 203 spaced apart along a first direction as an example, the width of the second mask layer 204 being the first width refers to the width of the second mask layer 204 in the first direction being the first width. In other embodiments, the second mask layer 204 can also be formed by an oxidation process.

[0075] Next, proceed to step S4, as follows: Figure 2C As shown, a second ion implantation is performed on the exposed first body region 203 to form a first source region 205 with a second conductivity type in the first body region 203. The distance from the edge of the first source region 205 to the edge of the first body region 203 located on the same side as the edge is the length of the channel in the first body region 203. The length of the channel in the first body region 203 is equal to the first width.

[0076] Next, proceed to step S5, as follows: Figure 2DAs shown, a dielectric layer 206 is formed to fill the first opening 202. The dielectric layer 206 can be formed by various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD). Exemplarily, the dielectric layer 206 can be made of silicon, polycrystalline silicon, or other materials; this application does not limit this. Exemplarily, when a sidewall process is used to form the second mask layer 204, the top of the formed second mask layer 204 has an arc-shaped structure, and the dielectric layer 206 formed in this step at least partially covers the top of the second mask layer 204.

[0077] Next, proceed to step S6, as follows: Figure 2E As shown, the first mask layer 201 located between adjacent first body regions 203 is removed to form a second opening 207 exposing a portion of the first surface of the substrate. Specifically, a patterned mask layer, such as a photoresist layer, can be formed, and then the first mask layer 201 located between adjacent first body regions 203 is etched away using the patterned mask layer as a mask to form the second opening 207 exposing a portion of the first surface of the substrate.

[0078] Next, proceed to step S7, as follows: Figure 2F As shown, a third mask layer 208 is formed on the sidewall of the second opening 207. Exemplarily, the third mask layer 208 is formed on the sidewall of the second opening 207 using a self-aligned process employing an oxidation process. Specifically, forming the third mask layer 208 on the sidewall of the second opening 207 using an oxidation process includes oxidizing the second mask layer 204 in an oxygen-containing atmosphere at a preset temperature for a preset time to obtain the third mask layer 208. The preset temperature range is 800℃-1500℃, and the preset time range is 2 hours to 4 hours. Exemplarily, when the second mask layer 204 is formed using a sidewall process and the third mask layer 208 is formed using an oxidation process, a portion of the third mask layer 208 is obtained by oxidizing the dielectric layer 206 located on top of the second mask layer 204, wherein the dielectric layer 206 and the second mask layer 204 are made of silicon or polysilicon. For example, a third mask layer 208 can also be formed on the sidewall of the second opening 207 using a sidewall process. Compared to the former, the oxidation process only requires one oxidation step to obtain the third mask layer 208, eliminating the need for deposition and etching processes. The sidewall process, on the other hand, allows for a smaller critical dimension (CD) and more precise width control. For example, the width of the third mask layer 208 ranges from 1µm to 3µm, or it can be any other width range; this application does not impose any limitations on this.

[0079] Next, proceed to step S8, as follows: Figure 2GAs shown, a third ion implantation is performed through the second opening 207 to form a second body region 209 having a first conductivity type in the substrate 200. Exemplarily, the implanted ions for the third ion implantation include Al ions. Exemplarily, the substrate region between the second body region 209 and the first body region 203 is a JFET (Junction Field-Effect Transistor) region.

[0080] Next, proceed to step S9, as follows: Figure 2H As shown, a fourth mask layer 210 is formed on the sidewall of the third mask layer 208. The width of the fourth mask layer 210 is a second width, which is greater than or less than the first width. Exemplarily, the fourth mask layer 210 can be formed on the sidewall of the third mask layer 208 using a self-aligned process employing a sidewall process. Specifically, forming the fourth mask layer 210 on the sidewall of the third mask layer 208 using a sidewall process includes: forming a second sidewall layer on the bottom and sidewall (i.e., the sidewall of the third mask layer 208) of the second opening 207; etching away a portion of the second sidewall layer at the bottom of the second opening 207 to retain a portion of the second sidewall layer on the sidewall of the second opening 207, thus obtaining the fourth mask layer 210, i.e., the fourth mask layer 210 is the remaining portion of the second sidewall layer on the sidewall of the second opening 207. Exemplarily, the material of the second sidewall layer can be pure silicon oxide, pure polycrystalline silicon, pure silicon nitride, a composite material of silicon nitride and silicon oxide, a composite material of polycrystalline silicon and silicon oxide, or other materials. When the second sidewall layer is a composite material, the silicon nitride and silicon oxide in the composite material can serve as stop layers when etching the first sidewall layer; when the second sidewall layer is a single material, the first sidewall layer can be etched using a timed etching method. Exemplarily, the second width ranges from 0.3µm to 3µm, or it can be any other suitable width range, depending on the actual channel length requirements, which this application does not limit. Exemplarily, the width of the fourth mask layer 210 being the second width refers to the width of the fourth mask layer 210 in the horizontal direction being the second width; taking the multiple body regions spaced apart along the first direction as an example, the width of the fourth mask layer 210 being the second width refers to the width of the fourth mask layer 210 in the first direction being the second width. In other embodiments, the fourth mask layer 210 can also be formed by an oxidation process.

[0081] Finally, proceed with step S10, as follows: Figure 2I As shown, a fourth ion implantation is performed on the exposed second body region 209 to form a second source region 211 with a second conductivity type in the second body region 209. The distance from the edge of the second source region 211 to the edge of the second body region 209 located on the same side as the edge is the length of the channel in the second body region 209, and the length of the channel in the second body region 209 is equal to the second width.

[0082] In this way, by forming a second mask layer with a width of the first width and a fourth mask layer with a width of the second width, channels of different lengths can be formed in the first and second body regions. The positions of the first and second body regions can be rationally set according to actual needs, forming channels of different lengths at different locations on the device. This allows for parallel current sharing by controlling the channel distribution, enabling dynamic control of switching speed and optimization of losses during switching and conduction processes. This makes the device more suitable for operation in linear mode and improves its shock resistance. It is worth noting that this application only illustrates the formation of two different channel lengths in the body region, but it does not mean that only two different channel lengths can be formed. Three or more different channel lengths can also be formed. Specific solutions can refer to the solution for forming two different channel lengths described above, which will not be repeated here.

[0083] In one example, the width of the second body region 209 is greater than or less than the width of the first body region 203. Since the widths of the first source region 205 and the second source region 211 need to be kept within a certain range, in order to form channels of different lengths within the first body region 203 and the second body region 209, the widths of the first body region 203 and the second body region 209 need to be reasonably set to meet the different length requirements of the channels. For example, taking the second width being greater than the first width, the width of the second body region 209 can be set to be greater than the width of the first body region 203. Exemplarily, the widths of the first body region 203 and the second body region 209 can be controlled by setting the widths of the first opening 202 and the second opening 207. Exemplarily, taking the arrangement of multiple body regions spaced apart along a first direction as an example, the width of the first body region 203 and the second body region 209 refers to the width of the first body region 203 and the second body region 209 along the first direction.

[0084] In one example, after performing a fourth ion implantation on the exposed second body region 209 to form a second source region 211 having a second conductivity type in the second body region 209, the method of this application further includes the following steps:

[0085] In one example, after the second source region 211 is formed in the second body region 209, the remaining first mask layer 201, second mask layer 204, third mask layer 208, fourth mask layer 210 and dielectric layer 206 can be removed using an etching process commonly used in the art (e.g., wet etching process).

[0086] Next, as Figure 2JAs shown, a patterned fifth mask layer 212 is formed on the first surface of the substrate 200, exposing a portion of the surface of the first source region 205 and the second source region 211. Exemplarily, the fifth mask layer 212 can be formed using various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD); the fifth mask layer 212 is then patterned using a photolithography process. Exemplarily, the material of the fifth mask layer 212 includes, but is not limited to, one or more of polysilicon, silicon oxide, and silicon nitride; this application does not impose any limitations on this.

[0087] Next, as Figure 2J As shown, a fifth ion implantation is performed on the exposed first source region 205 and second source region 211 to form a body contact region 213 penetrating the first source region 205 and the second source region 211 in the first body region 203 and the second body region 209. Exemplarily, the body contact region 213 has a first conductivity type, and the doping concentration of the body contact region 213 is greater than the doping concentration of the first body region 203 and the second body region 209.

[0088] Next, as Figure 2K As shown, the fifth mask layer 212 is removed. Exemplarily, the fifth mask layer 212 can be removed using an etching process commonly used in the art (e.g., wet etching process).

[0089] In one example, after removing the fifth mask layer 212, the method of this application further includes the following steps:

[0090] In one example, such as Figure 2L and 2M As shown, a gate oxide layer 214 is formed on the first surface of the substrate 200, and a gate electrode layer 215 is formed on the gate oxide layer 214 between the first source region 205 and the second source region 211. Exemplarily, the gate oxide layer 214 and the gate electrode layer 215 can be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The gate oxide layer 214 can also be formed by an oxidation process. Exemplarily, the gate oxide layer 214 is selected as an oxide layer, such as silicon dioxide, but is not limited to the above examples. Exemplarily, the gate electrode layer 215 is composed of polycrystalline silicon, but generally metals, metal nitrides, metal silicides, or similar compounds can also be used as the gate layer material.

[0091] Next, as Figure 2MAs shown, an interlayer dielectric layer 216 is formed on the gate electrode layer 215 and the gate oxide layer 214. The interlayer dielectric layer 216 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the interlayer dielectric layer 216 may include one or more of silicon silicate glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG), or other suitable materials; this application does not limit this to any particular material.

[0092] Next, as Figure 2N As shown, a portion of the interlayer dielectric layer 216 is etched away to form a first contact hole 217 in the interlayer dielectric layer 216, exposing the surfaces of the body contact region 213 and a portion of the first source region 205 and the second source region 211. Exemplarily, after forming the first contact hole 217, as... Figure 2O As shown, the method also includes the step of forming a second conductive layer 218 at the bottom of the first contact hole 217. Specifically, the second conductive layer can be formed by the following steps: depositing a conductive material layer, the material of which includes Ni; reacting the conductive material layer with the SiC at the bottom of the first contact hole 217 through rapid thermal annealing (RTA) to form a silicide contact; and removing the unreacted conductive material layer by wet etching to obtain the second conductive layer 218. Exemplarily, after forming the second conductive layer 218, the method further includes the step of etching the interlayer dielectric layer 216 to form a second contact hole (not shown) exposing a portion of the surface of the gate electrode layer 215.

[0093] Next, as Figure 2P As shown, a first conductive layer 219 is formed, which covers the interlayer dielectric layer 216 and fills the first contact hole 217. Exemplarily, the first conductive layer 219 can be formed by a sputtering process, and the material of the first conductive layer 219 includes Ti, TiN, and AlCu alloys.

[0094] Next, as Figure 2Q As shown, a passivation layer 220 and a protective layer 221 are sequentially formed on the first conductive layer 219. Exemplarily, the passivation layer 220 and the protective layer 221 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the passivation layer 220 is a protective thin film of organic or inorganic material, and the protective layer 221 is made of polyimide. Exemplarily, the passivation layer 220 and the protective layer 221 can be used to protect the device surface from external physical and chemical damage, improving the reliability and safety performance of the device.

[0095] Next, as Figure 2Q As shown, etching removes part of the passivation layer 220 and the protective layer 221 to expose part of the first conductive layer 219. Exemplarily, the exposed first conductive layer 219 can be connected to an external circuit and the source and gate are led out through the first contact hole and the second contact hole, respectively.

[0096] In one example, after etching away part of the passivation layer 220 and the protective layer 221 to expose part of the first conductive layer 219, the method of this application further includes the following steps: Figure 2R As shown, the second surface of the substrate 200 is thinned; a drain 222 is formed on the second surface of the substrate 200. Specifically, metallic Ni is deposited on the second surface of the substrate 200, and then laser annealing is performed to make the metallic Ni form an ohmic contact with the substrate 200. It is preferable to sputter TiNiAg to form the drain 222.

[0097] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. Other steps may also be included in the complete semiconductor device fabrication process, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0098] In summary, the semiconductor device manufacturing method of this application embodiment, by forming a second mask layer and a fourth mask layer with different widths, can form channels of different lengths in the first body region and the second body region. That is, it can form channels of different lengths at different locations of the device, and then achieve parallel current sharing by controlling the channel distribution. This can achieve dynamic control of switching speed and optimization of losses during the switching and conduction processes, making the device more suitable for operation in linear mode, while improving the device's shock resistance.

[0099] Example 2

[0100] This application also provides a semiconductor device prepared by the method described in Embodiment 1 above. Since the device of this application is prepared using the aforementioned method, it has the same advantages as the aforementioned method.

[0101] The semiconductor device of this application embodiment is manufactured using the above method. By forming a second mask layer and a fourth mask layer with different widths, channels of different lengths can be formed in the first body region and the second body region. That is, channels of different lengths can be formed at different locations of the device. In this way, parallel current sharing can be achieved by controlling the channel distribution. This can achieve dynamic control of switching speed and optimization of losses during the switching and conduction processes, making the device more suitable for operation in linear mode and improving the device's shock resistance.

[0102] Example 3

[0103] Another embodiment of this application also provides an electronic device, including the aforementioned semiconductor device.

[0104] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the semiconductor device described above. The electronic device in this embodiment has better performance because it uses the aforementioned semiconductor device.

[0105] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a patterned first mask layer is formed on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate; A first ion implantation is performed through the first opening to form at least two spaced-apart first body regions having a first conductivity type in the substrate; A second mask layer is formed on the sidewall of the first opening, the width of the second mask layer being the first width; A second ion implantation is performed on the exposed first body region to form a first source region having a second conductivity type in the first body region; A dielectric layer is formed to fill the first opening; Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate; A third mask layer is formed on the sidewall of the second opening; A third ion implantation is performed through the second opening to form a second body region having a first conductivity type in the substrate; A fourth mask layer is formed on the sidewall of the third mask layer, the width of the fourth mask layer being a second width, which is greater than or less than the first width; A fourth ion implantation is performed on the exposed second body region to form a second source region having a second conductivity type in the second body region.

2. The manufacturing method according to claim 1, characterized in that, The width of the second body region is greater than or less than the width of the first body region.

3. The manufacturing method according to claim 1, characterized in that, An oxidation process is used to form the third mask layer on the sidewall of the second opening.

4. The manufacturing method according to claim 1, characterized in that, Forming a second mask layer on the sidewall of the first opening includes: forming a first sidewall layer on the bottom and sidewall of the first opening; etching away a portion of the first sidewall layer located at the bottom of the first opening to retain a portion of the first sidewall layer located on the sidewall of the first opening, thereby obtaining the second mask layer. Forming the fourth mask layer on the sidewall of the third mask layer includes: forming a second sidewall layer at the bottom and on the sidewall of the second opening; etching away a portion of the second sidewall layer at the bottom of the second opening to retain a portion of the second sidewall layer on the sidewall of the second opening, thereby obtaining the fourth mask layer.

5. The manufacturing method according to claim 1, characterized in that, After performing a fourth ion implantation on the exposed second body region to form a second source region having a second conductivity type in the second body region, the method further includes: Remove the remaining first mask layer, second mask layer, third mask layer, fourth mask layer and dielectric layer; A patterned fifth mask layer is formed on the first surface of the substrate, the fifth mask layer exposing a portion of the surfaces of the first source region and the second source region; A fifth ion implantation is performed on the exposed first source region and second source region to form a body contact region that penetrates the first source region and the second source region in the first body region and the second body region; Remove the fifth mask layer.

6. The manufacturing method according to claim 5, further comprising, after removing the fifth mask layer: A gate oxide layer is formed on a first surface of the substrate, and a gate electrode layer located between the first source region and the second source region is formed on the gate oxide layer; An interlayer dielectric layer is formed on the gate electrode layer and the gate oxide layer; Etching removes a portion of the interlayer dielectric layer to form a first contact hole in the interlayer dielectric layer that exposes the surfaces of the bulk contact region and a portion of the first source region and the second source region; A first conductive layer is formed, which covers the interlayer dielectric layer and fills the first contact hole; A passivation layer and a protective layer are sequentially formed on the first conductive layer; Etching removes a portion of the passivation layer and the protective layer to expose a portion of the first conductive layer.

7. The manufacturing method according to claim 6, characterized in that, After etching away the passivation layer and the protective layer to expose a portion of the first conductive layer, the method further includes: The second surface of the substrate is thinned; A drain electrode is formed on the second surface of the substrate.

8. The manufacturing method according to any one of claims 1-7, characterized in that, The substrate includes a SiC epitaxial layer.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.

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