Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a substrate, forming a patterned first mask layer on the substrate, and forming at least two first openings which expose the first surface of the substrate in the first mask layer; performing first ion implantation through the first opening to form at least two first body regions arranged at intervals in the substrate; forming a first source region in the first body region; forming a dielectric layer filling the first opening; removing the first mask layer between the first body regions to form a second opening exposing a part of the first surface of the substrate; forming a second mask layer on the side wall of the second opening, wherein the width of the second mask layer is smaller than the first width; performing second ion implantation through the second opening to form a second body region in the substrate; a second source region is formed in the second body region. The second mask layer with the width smaller than the first width is formed, the cell width can be reduced, and the number of channels in unit area is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] One of the main types of devices in the field of power semiconductors is the metal-oxide-semiconductor field-effect transistor (MOSFET). Among them, SiC material has the characteristics of large bandgap, high critical breakdown electric field, fast saturated electron drift velocity and high thermal conductivity, making it an ideal material for fabricating high voltage, high power density and high temperature MOSFETs. This has made SiC material a research hotspot in power semiconductor devices internationally, and SiC devices are highly anticipated in high power applications such as high-speed railways, hybrid electric vehicles and intelligent high voltage direct current transmission.

[0003] Due to the influence of the gate oxide interface states (silicon carbide / silicon oxide), SiC MOSFETs have low channel electron mobility and high channel resistance, which in turn leads to increased on-resistance. To reduce the on-resistance, it is necessary to reduce the cell width and increase the number of channels per unit area.

[0004] However, in related technologies, an implantation mask is usually formed first through photolithography, and then ion implantation is performed to form the bulk region. The width of the JFET (junction field-effect transistor) region between the bulk regions is difficult to reduce, resulting in a large cell width of the device and a difficulty in increasing the number of channels per unit area. Consequently, the on-resistance of the device is difficult to decrease, and the device performance is low. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:

[0007] A substrate is provided, and a patterned first mask layer is formed on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate;

[0008] A first ion implantation is performed through the first opening to form at least two spaced-apart first body regions having a first conductivity type in the substrate;

[0009] A first source region having a second conductivity type is formed in the first body region;

[0010] A dielectric layer is formed to fill the first opening;

[0011] Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate;

[0012] A second mask layer is formed on the sidewall of the second opening, the width of the second mask layer being smaller than the first width;

[0013] A second ion implantation is performed through the second opening to form a second body region having a first conductivity type in the substrate. The region between the second body region and the first body region is a JFET region, and the width of the JFET region is equal to the width of the second mask layer.

[0014] A second source region having a second conductivity type is formed in the second body region.

[0015] For example, forming the second mask layer on the sidewall of the second opening includes: forming a first sidewall layer on the bottom and sidewall of the second opening; etching away a portion of the first sidewall layer located at the bottom of the second opening to retain a portion of the first sidewall layer located on the sidewall of the second opening, thereby obtaining the second mask layer.

[0016] For example, the first width is 1µm; and / or

[0017] The width of the second mask layer is greater than 0.05 μm.

[0018] For example, forming the first source region in the first body region includes: forming a third mask layer on the sidewall of the first opening; and performing a third ion implantation on the exposed first body region to form the first source region in the first body region.

[0019] Forming the second source region in the second body region includes: forming a fourth mask layer on the sidewall of the second mask layer; and performing a fourth ion implantation on the exposed second body region to form the second source region in the second body region.

[0020] For example, forming the third mask layer on the sidewall of the first opening includes: forming a second sidewall layer on the bottom and sidewall of the first opening; etching away a portion of the second sidewall layer located at the bottom of the first opening to retain a portion of the second sidewall layer located on the sidewall of the first opening, thereby obtaining the third mask layer;

[0021] Forming the fourth mask layer on the sidewall of the second mask layer includes: forming a third sidewall layer on the bottom and sidewall of the second opening; etching away a portion of the third sidewall layer at the bottom of the second opening to retain a portion of the third sidewall layer on the sidewall of the second opening, thereby obtaining the fourth mask layer.

[0022] For example, after forming the second source region having a second conductivity type in the second body region, the method further includes:

[0023] Remove the remaining first mask layer, second mask layer, and dielectric layer;

[0024] A patterned fifth mask layer is formed on the first surface of the substrate, the fifth mask layer exposing a portion of the surfaces of the first source region and the second source region;

[0025] A fifth ion implantation is performed on the exposed first source region and second source region to form a body contact region that penetrates the first source region and the second source region in the first body region and the second body region;

[0026] Remove the fifth mask layer.

[0027] Exemplarily, after removing the fifth mask layer, the method further includes:

[0028] A gate oxide layer is formed on a first surface of the substrate, and a gate electrode layer located between the first source region and the second source region is formed on the gate oxide layer;

[0029] An interlayer dielectric layer is formed on the gate electrode layer and the gate oxide layer;

[0030] Etching removes a portion of the interlayer dielectric layer to form a first contact hole in the interlayer dielectric layer that exposes the surfaces of the bulk contact region and a portion of the first source region and the second source region;

[0031] A first conductive layer is formed, which covers the interlayer dielectric layer and fills the first contact hole;

[0032] A passivation layer and a protective layer are sequentially formed on the first conductive layer;

[0033] Etching removes a portion of the passivation layer and the protective layer to expose a portion of the first conductive layer;

[0034] The second surface of the substrate is thinned;

[0035] A drain electrode is formed on the second surface of the substrate.

[0036] For example, the substrate includes a SiC epitaxial layer.

[0037] This application also provides a semiconductor device, which is manufactured using the method described above.

[0038] In another aspect, this application provides an electronic device, which includes the semiconductor device described above.

[0039] The semiconductor device and its manufacturing method, and electronic device of the present application embodiment form a second mask layer with a width smaller than a first width, thereby making the width of the JFET region located between the second body region and the first body region smaller than the first width, thereby reducing the cell width, increasing the number of channels per unit area, reducing the on-resistance of the device, and improving the device performance. Attached Figure Description

[0040] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0041] In the attached image:

[0042] Figure 1A-Figure 1B A cross-sectional schematic diagram of a semiconductor device in the related art is shown;

[0043] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown;

[0044] Figures 3A-3R This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of this application. Detailed Implementation

[0045] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0051] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0052] like Figures 1A to 1B As shown, in related technologies, a patterned mask layer 101 is generally formed first through photolithography. Multiple openings 102 are formed in the mask layer 101 to expose the surface of the substrate 100. Then, ion implantation is performed on the exposed surface of the substrate 100 using the mask layer 101 as a mask to form multiple bulk regions 103.

[0053] The mask layer 101 needs to reach a certain thickness to block ion implantation. The alignment error of the photolithography process is large, and the critical dimension (CD) of the mask layer 101 is difficult to reduce. This makes it difficult to reduce the width of the JFET region between the body regions 103 (for example, it is difficult to achieve a JFET region width of less than 1µm). This results in a large cell width of the device, making it difficult to increase the number of channels per unit area. Consequently, it is difficult to reduce the on-resistance of the device, resulting in lower device performance.

[0054] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:

[0055] Step S1: Provide a substrate and form a patterned first mask layer on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate;

[0056] Step S2: Perform first ion implantation through the first opening to form at least two spaced-apart first body regions with a first conductivity type in the substrate;

[0057] Step S3: Form a first source region having a second conductivity type in the first body region;

[0058] Step S4: Form a dielectric layer that fills the first opening;

[0059] Step S5: Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate;

[0060] Step S6: A second mask layer is formed on the sidewall of the second opening, the width of the second mask layer being smaller than the first width;

[0061] Step S7: Perform second ion implantation through the second opening to form a second body region with a first conductivity type in the substrate. The region between the second body region and the first body region is a JFET region. The width of the JFET region is equal to the width of the second mask layer.

[0062] Step S8: A second source region having a second conductivity type is formed in the second body region.

[0063] The semiconductor device manufacturing method of this application forms a second mask layer with a width smaller than a first width, thereby making the width of the JFET region located between the second body region and the first body region smaller than the first width, which can reduce the cell width, increase the number of channels per unit area, reduce the on-resistance of the device, and improve the device performance.

[0064] Example 1

[0065] Below, for reference Figures 2 to 3R The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application is shown. Figures 3A-3R This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of this application.

[0066] For example, the method for manufacturing the semiconductor device of this application includes the following steps:

[0067] First, step S1 is performed, providing a substrate and forming a patterned first mask layer on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate.

[0068] In one example, such as Figure 3A As shown, substrate 300 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, substrate 300 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), or germanium-on-insulator (GeOI), etc. Although several examples of materials that can form substrate 300 have been described herein, any material that can serve as substrate 300 falls within the spirit and scope of this application. Exemplarily, substrate 300 has a second conductivity type.

[0069] In one example, substrate 300 includes a substrate and a SiC epitaxial layer located on the substrate. Optionally, the semiconductor substrate and the SiC epitaxial layer may have the same conductivity type. Exemplarily, the semiconductor substrate and the SiC epitaxial layer may have different doping concentrations; for example, the doping concentration of the SiC epitaxial layer may be lower than the doping concentration of the semiconductor substrate. Optionally, the SiC epitaxial layer may serve as a drift region in the semiconductor device of the present invention, the presence of which provides the breakdown voltage of the device and acts as a buffer.

[0070] In one example, such as Figure 3A As shown, a first mask layer 301 can be formed on the first surface of the substrate 300 using various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD). The material of the first mask layer 301 includes, but is not limited to, one or more of polysilicon, silicon oxide, and silicon nitride; this application does not impose any limitations on this. Exemplarily, after forming the first mask layer 301, a photolithography process can be used to pattern the first mask layer 301 to form at least two first openings 302 exposing portions of the first surface of the substrate 300, with multiple first openings 302 spaced apart. For example, taking the multiple first openings 302 spaced apart along a first direction, the spacing between adjacent first openings 302 should be reasonably set according to the width of the subsequently formed JFET region along the first direction and the width of the second body region along the first direction.

[0071] Next, proceed to step S2, as follows: Figure 3BAs shown, a first ion implantation is performed through a first opening 302 to form at least two spaced-apart first body regions 303 with a first conductivity type in a substrate 300. The first body regions 303 extend from a first surface of the substrate 300 into the substrate 300. In this embodiment, the first conductivity type can be P-type and the second conductivity type can be N-type; in other embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. For example, the first body region 303 is P-type, and the implanted ions in the first ion implantation include Al ions.

[0072] Next, proceed to step S3, as follows: Figure 3C As shown, a first source region 305 having a second conductivity type is formed in the first body region 303. Specifically, as... Figure 3C As shown, forming a first source region 305 with a second conductivity type in a first body region 303 includes: forming a third mask layer 304 on the sidewall of the first opening 302; and performing a third ion implantation on the exposed first body region 303 to form the first source region 305 with the second conductivity type in the first body region 303. The distance from the edge of the first source region 305 to the edge of the first body region 303 located on the same side is the length of the channel in the first body region 303, and the length of the channel in the first body region 303 is equal to the width of the third mask layer 304.

[0073] In one example, a third mask layer 304 can be formed on the sidewall of the first opening 302 using a self-aligned process. This self-aligned process employs a spacer process. Specifically, forming the third mask layer 304 on the sidewall of the first opening 302 using a spacer process includes: forming a second sidewall layer on the bottom and sidewall of the first opening 302; etching away a portion of the second sidewall layer located at the bottom of the first opening 302 to retain a portion of the second sidewall layer located on the sidewall of the first opening 302, resulting in the third mask layer 304. That is, the third mask layer 304 is the remaining portion of the second sidewall layer located on the sidewall of the first opening 302. Exemplarily, the material of the second sidewall layer can be pure silicon oxide, pure polycrystalline silicon, pure silicon nitride, a composite material of silicon nitride and silicon oxide, a composite material of polycrystalline silicon and silicon oxide, or other materials. In this embodiment, when the second sidewall layer is a composite material, silicon nitride and silicon oxide in the composite material can serve as stop layers when etching the second sidewall layer; when the second sidewall layer is a single material, it can be etched using a timed etching method. Exemplarily, the width of the third mask layer 304 ranges from 0.3µm to 1µm, or it can be any other suitable width range, depending on the actual channel length requirements; this application does not impose any limitations on this. Exemplarily, the width of the third mask layer 304 refers to its width in the horizontal direction; taking a plurality of first body regions 303 spaced apart along a first direction as an example, the width of the third mask layer 304 refers to its width in the first direction. In other embodiments, the third mask layer 304 can also be formed by an oxidation process.

[0074] Next, proceed to step S4, as follows: Figure 3D As shown, a dielectric layer 306 is formed to fill the first opening 302. The dielectric layer 306 can be formed by various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD). Exemplarily, the dielectric layer 306 can be made of silicon, polycrystalline silicon, or other materials, and this application is not limited in this regard. Exemplarily, when a third mask layer 304 is formed on the sidewall of the first opening 302, the dielectric layer 306 fills the remaining portion of the first opening 302. Exemplarily, when the third mask layer 304 is formed using a sidewall process, the top of the formed third mask layer 304 has an arc-shaped structure, and the dielectric layer 306 formed in this step also at least partially covers the top of the third mask layer 304.

[0075] Next, proceed to step S5, as follows: Figure 3EAs shown, the first mask layer 301 located between adjacent first body regions 303 is removed to form a second opening 307 exposing a portion of the first surface of the substrate. Specifically, a patterned mask layer, such as a photoresist layer, can be formed, and then the first mask layer 301 located between adjacent first body regions 303 can be etched and removed using the patterned mask layer as a mask to form the second opening 307 exposing the first surface of the substrate.

[0076] Next, proceed to step S6, as follows: Figure 3F As shown, a second mask layer 308 is formed on the sidewall of the second opening 307, and the width of the second mask layer 308 is smaller than the first width. Exemplarily, the first width is 1 μm. Exemplarily, the width of the second mask layer 308 is also greater than 0.05 μm. Exemplarily, the second mask layer 308 can be formed on the sidewall of the second opening 307 using a self-aligned process employing a sidewall process. Specifically, forming the second mask layer 308 on the sidewall of the second opening 307 using a sidewall process includes: forming a first sidewall layer on the bottom and sidewall of the second opening 307; etching away a portion of the first sidewall layer located at the bottom of the second opening 307 to retain a portion of the first sidewall layer located on the sidewall of the second opening 307, thus obtaining the second mask layer 308, i.e., the second mask layer 308 is the remaining portion of the first sidewall layer located on the sidewall of the second opening 307. For example, the material of the first sidewall layer can be pure silicon oxide, pure polycrystalline silicon, pure silicon nitride, a composite material of silicon nitride and silicon oxide, a composite material of polycrystalline silicon and silicon oxide, or other materials. When the first sidewall layer is a composite material, the silicon nitride and silicon oxide in the composite material can serve as stop layers during etching of the first sidewall layer; when the first sidewall layer is a single material, a timed etching method can be used to etch the first sidewall layer. For example, by forming the second mask layer 308 through the sidewall process, the width of the second mask layer 308 can be precisely controlled, thereby forming a second mask layer 308 with a width smaller than the first width (e.g., 1µm). The width of the second mask layer 308 determines the width of the JFET region between the subsequently formed second body region and the first body region, thereby reducing the width of the JFET region to below the first width, resulting in a smaller-width JFET region. For example, the width of the second mask layer 308 refers to the width of the second mask layer 308 in the horizontal direction; taking a plurality of first body regions 303 spaced apart along a first direction as an example, the width of the second mask layer 308 refers to the width of the second mask layer 308 in the first direction. Next, step S7 is executed, as follows... Figure 3GAs shown, a second ion implantation is performed through the second opening 307 to form a second body region 309 with a second conductivity type in the substrate 300. The region between the second body region 309 and the first body region 303 is a JFET region, and the width of the JFET region is equal to the width of the second mask layer 308. Exemplarily, the width of the JFET region is the distance between adjacent second body regions 309 and first body regions 303. The width of the JFET region is a crucial factor affecting the cell width. Since a second mask layer 308 with a width smaller than the first width is formed in the aforementioned steps, the width of the JFET region is also smaller than the first width. A smaller JFET region width can reduce the cell width, thereby increasing the number of channels per unit area, which in turn reduces the on-resistance of the device and improves device performance. Exemplarily, the implanted ions in the third ion implantation include Al ions.

[0077] Finally, proceed with step S8, as follows: Figure 3I As shown, a second source region 311 having a second conductivity type is formed in the second body region 309. Specifically, as... Figure 3H and Figure 3I As shown, forming a second source region 311 with a second conductivity type in the second body region 309 includes: forming a fourth mask layer 310 on the sidewall of the second mask layer 308; and performing a fourth ion implantation on the exposed second body region 309 to form the second source region 311 with the second conductivity type in the second body region 309. The distance from the edge of the second source region 311 to the edge of the second body region 309 located on the same side as that edge is the length of the channel in the second body region 309, and the length of the channel in the second body region 309 is equal to the width of the fourth mask layer 310.

[0078] In one example, a fourth mask layer 310 can be formed on the sidewall of the second mask layer 308 using a self-aligned process. This self-aligned process employs a sidewall process. Specifically, forming the fourth mask layer 310 on the sidewall of the second mask layer 308 using a sidewall process includes: forming a third sidewall layer on the bottom and sidewall of the second opening 307 (i.e., the sidewall of the second mask layer 308); etching away a portion of the third sidewall layer at the bottom of the second opening 307 to retain a portion of the third sidewall layer on the sidewall of the second opening 307, thus obtaining the fourth mask layer 310. That is, the fourth mask layer 310 is the remaining portion of the third sidewall layer on the sidewall of the second opening 307. Exemplarily, the material of the third sidewall layer can be pure silicon oxide, pure polysilicon, pure silicon nitride, a composite material of silicon nitride and silicon oxide, a composite material of polysilicon and silicon oxide, or other materials. In this embodiment, when the third sidewall layer is a composite material, silicon nitride and silicon oxide in the composite material can serve as stop layers when etching the third sidewall layer; when the third sidewall layer is a single material, it can be etched using a timed etching method. Exemplarily, the width of the fourth mask layer 310 ranges from 0.3µm to 1µm, or it can be any other suitable width range, depending on the actual channel length requirements; this application does not impose any limitations on this. Exemplarily, the width of the fourth mask layer 310 refers to its width in the horizontal direction; taking a plurality of body regions spaced apart along a first direction as an example, the width of the fourth mask layer 310 refers to its width in the first direction. In other embodiments, the fourth mask layer 310 can also be formed by an oxidation process.

[0079] In one example, after forming a second source region 311 with a second conductivity type in the second body region 309, the method of this application further includes the following steps:

[0080] In one example, after the second source region 311 is formed in the second body region 309, the remaining first mask layer 301, second mask layer 308, and dielectric layer 306 can be removed using an etching process commonly used in the art (e.g., wet etching). Exemplarily, when the third mask layer 304 and fourth mask layer 310 are formed in the aforementioned steps, the third mask layer 304 and fourth mask layer 310 should also be removed in this step.

[0081] Next, as Figure 3JAs shown, a patterned fifth mask layer 312 is formed on the first surface of the substrate 300, exposing a portion of the surface of the first source region 305 and the second source region 311. Exemplarily, the fifth mask layer 312 can be formed using various deposition methods commonly used in the art, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition, or atomic layer deposition (ALD); the fifth mask layer 312 is then patterned using a photolithography process. Exemplarily, the material of the fifth mask layer 312 includes, but is not limited to, one or more of polysilicon, silicon oxide, and silicon nitride; this application does not impose any limitations on this.

[0082] Next, as Figure 3J As shown, a fifth ion implantation is performed on the exposed first source region 305 and second source region 311 to form a body contact region 313 penetrating the first body region 305 and second body region 309. Exemplarily, the body contact region 313 has a first conductivity type, and the doping concentration of the body contact region 313 is greater than the doping concentration of the first body region 303 and the second body region 309.

[0083] Next, as Figure 3K As shown, the fifth mask layer 312 is removed. Exemplarily, the fifth mask layer 312 can be removed using an etching process commonly used in the art (e.g., wet etching process).

[0084] In one example, after removing the fifth mask layer 312, the method of this application further includes the following steps:

[0085] In one example, such as Figure 3L and 3M As shown, a gate oxide layer 314 is formed on the first surface of the substrate 300, and a gate electrode layer 315 is formed on the gate oxide layer 314 between the first source region 305 and the second source region 311. Exemplarily, the gate oxide layer 314 and the gate electrode layer 315 can be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The gate oxide layer 314 can also be formed by an oxidation process. Exemplarily, the gate oxide layer 314 is selected as an oxide layer, such as silicon dioxide, but is not limited to the above examples. Exemplarily, the gate electrode layer 315 is composed of polycrystalline silicon, but generally metals, metal nitrides, metal silicides, or similar compounds can also be used as the gate layer material.

[0086] Next, as Figure 3MAs shown, an interlayer dielectric layer 316 is formed on the gate electrode layer 315 and the gate oxide layer 314. The interlayer dielectric layer 316 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the interlayer dielectric layer 316 may include one or more of materials such as USG, PSG, or BPSG, or other suitable materials; this application does not limit this to any particular material.

[0087] Next, as Figure 3N As shown, a portion of the interlayer dielectric layer 316 is etched away to form a first contact hole 317 in the interlayer dielectric layer 316, exposing the surfaces of the body contact region 313 and a portion of the first source region 305 and the second source region 311. Exemplarily, after forming the first contact hole 317, as... Figure 3O As shown, the method also includes the step of forming a second conductive layer 318 at the bottom of the first contact hole 317. Specifically, the second conductive layer can be formed by the following steps: depositing a conductive material layer, the material of which includes Ni; reacting the conductive material layer with the SiC at the bottom of the first contact hole 317 through rapid thermal annealing (RTA) to form a silicide contact; and removing the unreacted conductive material layer by wet etching to obtain the second conductive layer 318. Exemplarily, after forming the second conductive layer 318, the method further includes the step of etching the interlayer dielectric layer 316 to form a second contact hole (not shown) exposing a portion of the surface of the gate electrode layer 315.

[0088] Next, as Figure 3P As shown, a first conductive layer 319 is formed, which covers the interlayer dielectric layer 316 and fills the first contact hole 317. Exemplarily, the first conductive layer 319 can be formed by a sputtering process, and the material of the first conductive layer 319 includes Ti, TiN, and AlCu alloys.

[0089] Next, as Figure 3Q As shown, a passivation layer 320 and a protective layer 321 are sequentially formed on the first conductive layer 319. Exemplarily, the passivation layer 320 and the protective layer 321 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the passivation layer 320 is a protective thin film of organic or inorganic material, and the protective layer 321 is made of polyimide. Exemplarily, the passivation layer 320 and the protective layer 321 can be used to protect the device surface from external physical and chemical damage, improving the reliability and safety performance of the device.

[0090] Next, as Figure 3Q As shown, etching removes part of the passivation layer 320 and the protective layer 321 to expose part of the first conductive layer 319. Exemplarily, the exposed first conductive layer 319 can be connected to an external circuit and the source and gate are led out through the first contact hole and the second contact hole, respectively.

[0091] Next, as Figure 3R As shown, the second surface of the substrate 300 is thinned; a drain 322 is formed on the second surface of the substrate 300. Specifically, metallic Ni is deposited on the second surface of the substrate 300, and then laser annealing is performed to make the metallic Ni form an ohmic contact with the substrate 300. It is preferable to sputter TiNiAg to form the drain 322.

[0092] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. Other steps may also be included in the complete semiconductor device fabrication process, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0093] In summary, the semiconductor device manufacturing method of this application embodiment forms a second mask layer with a width smaller than a first width, thereby making the width of the JFET region located between the second body region and the first body region smaller than the first width, which can reduce the cell width, increase the number of channels per unit area, reduce the on-resistance of the device, and improve the device performance.

[0094] Example 2

[0095] This application also provides a semiconductor device prepared by the method described in Embodiment 1 above. Since the device of this application is prepared using the aforementioned method, it has the same advantages as the aforementioned method.

[0096] The semiconductor device of this application embodiment is manufactured using the above method, forming a second mask layer with a width smaller than the first width, thereby making the width of the JFET region located between the second body region and the first body region smaller than the first width, which can reduce the cell width, increase the number of channels per unit area, reduce the on-resistance of the device, and improve the device performance.

[0097] Example 3

[0098] Another embodiment of this application also provides an electronic device, including the aforementioned semiconductor device.

[0099] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the semiconductor device described above. The electronic device in this embodiment has better performance because it uses the aforementioned semiconductor device.

[0100] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a patterned first mask layer is formed on a first surface of the substrate, wherein at least two first openings are formed in the first mask layer that expose portions of the first surface of the substrate; A first ion implantation is performed through the first opening to form at least two spaced-apart first body regions having a first conductivity type in the substrate; A first source region having a second conductivity type is formed in the first body region; A dielectric layer is formed to fill the first opening; Remove the first mask layer located between adjacent first body regions to form a second opening exposing a portion of the first surface of the substrate; A second mask layer is formed on the sidewall of the second opening, the width of the second mask layer being smaller than the first width; A second ion implantation is performed through the second opening to form a second body region having a first conductivity type in the substrate. The region between the second body region and the first body region is a JFET region, and the width of the JFET region is equal to the width of the second mask layer. A second source region having a second conductivity type is formed in the second body region.

2. The manufacturing method according to claim 1, characterized in that, Forming the second mask layer on the sidewall of the second opening includes: forming a first sidewall layer on the bottom and sidewall of the second opening; etching away a portion of the first sidewall layer located at the bottom of the second opening to retain a portion of the first sidewall layer located on the sidewall of the second opening, thereby obtaining the second mask layer.

3. The manufacturing method according to claim 1, characterized in that, The first width is 1µm; and / or The width of the second mask layer is greater than 0.05 μm.

4. The manufacturing method according to claim 1, characterized in that, Forming the first source region in the first body region includes: forming a third mask layer on the sidewall of the first opening; and performing a third ion implantation on the exposed first body region to form the first source region in the first body region. Forming the second source region in the second body region includes: forming a fourth mask layer on the sidewall of the second mask layer; and performing a fourth ion implantation on the exposed second body region to form the second source region in the second body region.

5. The manufacturing method according to claim 4, characterized in that, Forming the third mask layer on the sidewall of the first opening includes: forming a second sidewall layer on the bottom and sidewall of the first opening; etching away a portion of the second sidewall layer located at the bottom of the first opening to retain a portion of the second sidewall layer located on the sidewall of the first opening, thereby obtaining the third mask layer. Forming the fourth mask layer on the sidewall of the second mask layer includes: forming a third sidewall layer on the bottom and sidewall of the second opening; etching away a portion of the third sidewall layer at the bottom of the second opening to retain a portion of the third sidewall layer on the sidewall of the second opening, thereby obtaining the fourth mask layer.

6. The manufacturing method according to claim 1, characterized in that, After forming the second source region having the second conductivity type in the second body region, the method further includes: Remove the remaining first mask layer, second mask layer, and dielectric layer; A patterned fifth mask layer is formed on the first surface of the substrate, the fifth mask layer exposing a portion of the surfaces of the first source region and the second source region; A fifth ion implantation is performed on the exposed first source region and second source region to form a body contact region that penetrates the first source region and the second source region in the first body region and the second body region; Remove the fifth mask layer.

7. The manufacturing method according to claim 6, further comprising, after removing the fifth mask layer: A gate oxide layer is formed on a first surface of the substrate, and a gate electrode layer located between the first source region and the second source region is formed on the gate oxide layer; An interlayer dielectric layer is formed on the gate electrode layer and the gate oxide layer; Etching removes a portion of the interlayer dielectric layer to form a first contact hole in the interlayer dielectric layer that exposes the surfaces of the bulk contact region and a portion of the first source region and the second source region; A first conductive layer is formed, which covers the interlayer dielectric layer and fills the first contact hole; A passivation layer and a protective layer are sequentially formed on the first conductive layer; Etching removes a portion of the passivation layer and the protective layer to expose a portion of the first conductive layer; The second surface of the substrate is thinned; A drain electrode is formed on the second surface of the substrate.

8. The manufacturing method according to any one of claims 1-7, characterized in that, The substrate includes a SiC epitaxial layer.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.

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