Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate; the gate electrode comprises a first gate electrode doped region, a fourth gate electrode doped region, a second gate electrode doped region and a third gate electrode doped region, the second gate electrode doped region is arranged at the second end of the first gate electrode doped region, and the third gate electrode doped region is arranged at the first end of the fourth gate electrode doped region; the doping type of the first gate electrode doped region is the same as that of the fourth gate electrode doped region, the doping type of the second gate electrode doped region is the same as that of the third gate electrode doped region, and the doping type of the second gate electrode doped region is opposite to that of the first gate electrode doped region; the gate metal wiring is electrically connected with the first gate electrode doped region and the third gate electrode doped region; and the gate metal bonding pad is electrically connected with the second gate electrode doped region and the fourth gate electrode doped region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Wide-bandgap power devices, such as silicon carbide (SiC) devices, have higher switching speeds than silicon-based power devices, thus offering lower switching losses. However, high switching speeds mean high gate voltage ramp-up and ramp rates, which in turn increases the risk of high gate overvoltage, posing a challenge to the reliability of SiC devices.

[0003] Therefore, it is necessary to provide a technical solution that simultaneously reduces switching losses and improves gate reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a technical solution that simultaneously reduces switching losses and improves gate reliability.

[0005] One aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate having a first insulating layer formed on its surface; a gate electrode located on the surface of the first insulating layer, the gate electrode including a first gate electrode doped region and a fourth gate electrode doped region; at least one of a second gate electrode doped region and a third gate electrode doped region, the second gate electrode doped region being disposed at a second end of the first gate electrode doped region, the third gate electrode doped region being disposed at a first end of the fourth gate electrode doped region, the first gate electrode doped region and the fourth gate electrode doped region having the same doping type, the second gate electrode doped region and the third gate electrode doped region having the same doping type, and the doping type of the second gate electrode doped region and the third gate electrode doped region being opposite to the doping type of the first gate electrode doped region and the fourth gate electrode doped region; a gate metal wiring electrically connecting the first gate electrode doped region and the third gate electrode doped region; and a gate metal pad electrically connecting the second gate electrode doped region and the fourth gate electrode doped region.

[0006] In some embodiments of this application, the gate electrode is made of polycrystalline silicon, and the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region and the fourth gate electrode doped region are formed by ion implantation of the gate electrode.

[0007] In some embodiments of this application, the first ends of the first gate electrode doped region and the fourth gate electrode doped region are connected.

[0008] In some embodiments of this application, the semiconductor structure further includes: a second insulating layer covering the first insulating layer and the gate electrode surface, wherein the gate metal wiring and the gate metal pad penetrate the second insulating layer.

[0009] In some embodiments of this application, the doping concentrations of the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region, and the fourth gate electrode doped region are the same.

[0010] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first insulating layer is formed on the surface of the semiconductor substrate; forming a gate electrode on the surface of the first insulating layer; forming a first gate electrode doped region and a fourth gate electrode doped region in the gate electrode; forming at least one of a second gate electrode doped region and a third gate electrode doped region, wherein the second gate electrode doped region is disposed at a second end of the first gate electrode doped region, and the third gate electrode doped region is disposed at a first end of the fourth gate electrode doped region, wherein the first gate electrode doped region and the fourth gate electrode doped region have the same doping type, and the second gate electrode doped region and the third gate electrode doped region have the same doping type, and the doping type of the second gate electrode doped region and the third gate electrode doped region is opposite to the doping type of the first gate electrode doped region and the fourth gate electrode doped region; forming a gate metal wiring electrically connecting the first gate electrode doped region and the third gate electrode doped region; and forming a gate metal pad electrically connecting the second gate electrode doped region and the fourth gate electrode doped region.

[0011] In some embodiments of this application, the gate electrode is made of polycrystalline silicon, and the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region and the fourth gate electrode doped region are formed by ion implantation of the gate electrode.

[0012] In some embodiments of this application, the first ends of the first gate electrode doped region and the fourth gate electrode doped region are connected.

[0013] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming a second insulating layer covering the first insulating layer and the gate electrode surface, wherein the gate metal wiring and the gate metal pad penetrate the second insulating layer.

[0014] In some embodiments of this application, the doping concentrations of the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region, and the fourth gate electrode doped region are the same.

[0015] This application provides a semiconductor structure and a method for forming the same, offering a technical solution that simultaneously reduces switching losses and improves gate reliability. Attached Figure Description

[0016] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0017] in:

[0018] Figures 1 to 3 This is a schematic diagram of the semiconductor structure described in some embodiments of this application;

[0019] Figure 4 This is a circuit diagram of the semiconductor structure described in some embodiments of this application;

[0020] Figure 5 This is a schematic diagram of the semiconductor structure described in some other embodiments of this application;

[0021] Figure 6 This is a circuit diagram of the semiconductor structure described in some other embodiments of this application;

[0022] Figure 7 This is a schematic diagram of the semiconductor structure described in other embodiments of this application;

[0023] Figure 8 The circuit diagrams are for other embodiments of the semiconductor structures described in this application. Detailed Implementation

[0024] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0025] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0026] Figures 1 to 3 This is a schematic diagram of the semiconductor structure described in some embodiments of this application. Figure 4 This is a circuit diagram of a semiconductor structure described in some embodiments of this application. Specifically, Figure 1 This is a top view of the semiconductor structure; Figure 2 For along Figure 1 Longitudinal section view at point AA (middle dashed line); Figure 3 For along Figure 1Longitudinal section view at the dashed line BB; Figure 4 This is a circuit diagram of the semiconductor structure. The method for forming the semiconductor structure 100 according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0027] Some embodiments of this application provide a semiconductor structure 100, see reference Figures 1 to 4 As shown, it includes: a semiconductor substrate 101, on which a first insulating layer 111 is formed; a gate electrode located on the surface of the first insulating layer 111, the gate electrode including a first gate electrode doped region 121 and a fourth gate electrode doped region 124; and at least one of a second gate electrode doped region 122 and a third gate electrode doped region 123 (wherein, Figures 1 to 4 The illustrated embodiment includes both a second gate electrode doped region 122 and a third gate electrode doped region 123. The second gate electrode doped region 122 is disposed at the second end of the first gate electrode doped region 121, and the third gate electrode doped region 123 is disposed at the first end of the fourth gate electrode doped region 124 (the first end and the second end refer to the attached...). Figure 1 The first gate electrode doped region 121 and the fourth gate electrode doped region 124 have the same doping type (e.g., N-type), the second gate electrode doped region 122 and the third gate electrode doped region 123 have the same doping type (e.g., P-type), and the doping type of the second gate electrode doped region 122 and the third gate electrode doped region 123 is opposite to that of the first gate electrode doped region 121 and the fourth gate electrode doped region 124; gate metal wiring 132 electrically connects the first gate electrode doped region 121 and the third gate electrode doped region 123; gate metal pad 131 electrically connects the second gate electrode doped region 122 and the fourth gate electrode doped region 124.

[0028] The semiconductor structure described in this application is, for example, a silicon carbide power semiconductor device.

[0029] In some embodiments of this application, the semiconductor substrate 101 may include a silicon carbide substrate and a silicon carbide epitaxial layer located on the surface of the silicon carbide substrate. The silicon carbide substrate is made of silicon carbide, and the silicon carbide epitaxial layer is also made of silicon carbide. In some embodiments of this application, the silicon carbide substrate and the silicon carbide epitaxial layer may contain doped ions, such as N-type doped ions. The thickness of the semiconductor substrate 101 is 10 to 500 micrometers. The doping concentration of the silicon carbide epitaxial layer is 1 x 10⁻⁶. 17 Up to 1x10 21 Atoms per cubic centimeter.

[0030] It should be noted that the semiconductor substrate 101 is used to form the active region. The focus of the technical solution in this application is on the gate electrode, therefore the structure located in the semiconductor substrate 101 is omitted.

[0031] In some embodiments of this application, the material of the first insulating layer 111 (as a field oxide layer) is, for example, any one or more of silicon dioxide, aluminum oxide, and silicon nitride; the thickness of the first insulating layer 111 is, for example, 0.5 micrometers to 5 micrometers.

[0032] In some embodiments of this application, the gate electrode is made of polycrystalline silicon. The thickness of the gate electrode is, for example, 0.1 micrometers to 1 micrometer. The first gate electrode doped region 121, the second gate electrode doped region 122, the third gate electrode doped region 123, and the fourth gate electrode doped region 124 are formed by ion implantation of the gate electrode.

[0033] In some embodiments of this application, the first gate electrode doped region 121, the second gate electrode doped region 122, the third gate electrode doped region 123, and the fourth gate electrode doped region 124 have the same doping concentration.

[0034] In the technical solution of this application, the first gate electrode doped region 121 and the second gate electrode doped region 122 are connected to form a first gate PN junction 125; the third gate electrode doped region 123 and the fourth gate electrode doped region 124 are connected to form a second gate PN junction 126.

[0035] In some embodiments of this application, the first ends of the first gate electrode doped region 121 and the fourth gate electrode doped region 124 are connected, which can play a current sharing role and avoid signal inconsistency between the first gate electrode doped region 121 and the fourth gate electrode doped region 124.

[0036] In some embodiments of this application, the semiconductor structure 100 further includes: a second insulating layer 112 (as an interlayer dielectric layer) covering the first insulating layer 111 and the gate electrode surface, wherein the gate metal wiring 132 and the gate metal pad 131 penetrate the second insulating layer 112.

[0037] In some embodiments of this application, the material of the second insulating layer 112 is, for example, any one or more of silicon dioxide, aluminum oxide, and silicon nitride; the thickness of the second insulating layer 112 is, for example, 0.1 micrometers to 5 micrometers.

[0038] In the technical solution of this application, the second insulating layer 112 covers the upper surface of the first insulating layer 111 and the upper surface of the gate electrode. The second insulating layer 112 provides openings only in the first gate electrode doped region contact area 121a, the second gate electrode doped region contact area 122a, the third gate electrode doped region contact area 123a, and the fourth gate electrode doped region contact area 124a on the gate electrode. The first gate electrode doped region contact area 121a and the third gate electrode doped region contact area 123a are connected and are on a straight line.

[0039] In some embodiments of this application, the gate metal pad 131 covers a portion of the upper surface of the second insulating layer 112 and is electrically connected to the second gate electrode doped region contact area 122a and the fourth gate electrode doped region contact area 124a, respectively. An ohmic contact is formed between the second gate electrode doped region contact area 122a and the second gate electrode doped region 122a, and an ohmic contact is formed between the fourth gate electrode doped region contact area 124a and the fourth gate electrode doped region 124a.

[0040] In some embodiments of this application, the gate metal pad 131 is made of materials such as aluminum, copper, titanium, nickel, silver, palladium, gold, tungsten, or alloys or stacks thereof; the thickness of the gate metal pad 131 is, for example, 1 micrometer to 10 micrometers.

[0041] In the technical solution of this application, the gate metal pad 131 is connected to the gate signal source 141, such as a gate driver, and the connection method is, for example, wire bonding.

[0042] In some embodiments of this application, the gate metal wiring 132 covers a portion of the upper surface of the second insulating layer 112 and the first gate electrode doped region contact region 121a and the third gate electrode doped region contact region 123a, and forms an ohmic contact between the first gate electrode doped region contact region 121a and the first gate electrode doped region 121; and forms an ohmic contact between the third gate electrode doped region contact region 123a and the third gate electrode doped region 123.

[0043] In some embodiments of this application, the gate metal wiring 132 is made of materials such as aluminum, copper, titanium, nickel, silver, palladium, gold, tungsten, or alloys or stacks thereof; the thickness of the gate metal wiring 132 is, for example, 1 micrometer to 10 micrometers.

[0044] In the technical solution of this application, the gate metal wiring 132 is connected to the semiconductor device cell gate 142. The gate 142 can be any type of gate, such as a trench gate or a planar gate.

[0045] refer to Figures 1 to 4As shown, in the first gate electrode doped region 121, the resistance between the first gate electrode doped region contact region 121a and the first gate PN junction 125 is the first gate electrode doped region resistance 121b; in the second gate electrode doped region 122, the resistance between the second gate electrode doped region contact region 122a and the first gate PN junction 125 is the second gate electrode doped region resistance 122b; in the third gate electrode doped region 123, the resistance between the third gate electrode doped region contact region 123a and the second gate PN junction 126 is the third gate electrode doped region resistance 123b; and in the fourth gate electrode doped region 124, the resistance between the fourth gate electrode doped region contact region 124a and the second gate PN junction 126 is the fourth gate electrode doped region resistance 124b.

[0046] Generally speaking, because silicon carbide transistor devices have a much faster switching speed than their silicon counterparts, meaning their gate voltage rise and fall rates are very high, silicon carbide MOS devices are prone to gate overvoltage spikes. Gate overvoltage can severely damage the lifespan of the gate dielectric layer or even destroy it. Typically, a resistor is placed at the device gate to slow down the rise and fall rate of the gate voltage. However, this inevitably increases the switching losses of the device, representing a trade-off between device reliability and performance.

[0047] Since the gate voltage rise and fall rates of transistor devices are not the same when they are turned on and off, in general, when only one gate resistor is set, the larger gate resistor is selected according to the one with the larger voltage rise and fall rate, with the premise of suppressing gate overvoltage. This will cause the one with the smaller voltage rise and fall rate to sacrifice too much switching speed, resulting in increased switching losses.

[0048] refer to Figures 1 to 4 In the technical solution provided in this application, a gate signal conditioning circuit is built into the gate electrode of a silicon carbide MOS device. The circuit includes two PN junctions connected in anti-parallel, namely, a first gate PN junction 125 and a second gate PN junction 126 connected in anti-parallel, and a first gate resistor 127 and a second gate resistor 128 connected in series with the first PN junction and the second PN junction, respectively. The gate signal conditioning circuit is connected to a gate signal source 141, such as a gate controller, and a device cell gate 142.

[0049] Continue to refer to Figures 1 to 4 The first gate resistor 127 is the sum of the first gate electrode doped region resistor 121b and the second gate electrode doped region resistor 122b; the second gate resistor 128 is the sum of the third gate electrode doped region resistor 123b and the fourth gate electrode doped region resistor 124b; the first gate resistor 127 and the second gate resistor 128 can be adjusted by changing the dimensions of the first to fourth gate electrode doped regions 121-124, including aspect ratio and thickness, as well as doping concentration.

[0050] When the device is turned on, the potential of the gate signal source 141 is higher than that of the device cell gate 142. Current flows from the gate signal source 141 to the device cell gate 142. At this time, the first gate PN junction 125 is forward biased and the second gate PN junction 126 is reverse biased. The gate current only passes through the first gate PN junction 125 and the first gate resistor 127. Therefore, the gate resistance when the device is turned on is the first gate resistor 127.

[0051] When the device is turned off, the potential of the gate signal source 141 is lower than that of the device cell gate 142. Current flows from the device cell gate 142 to the gate signal source 141. At this time, the first gate PN junction 125 is reverse biased and the second gate PN junction 126 is forward biased. The gate current only passes through the second gate PN junction 126 and the second gate resistor 128. Therefore, the gate resistance when the device is turned off is the second gate resistor 128.

[0052] The technical solution provided in this application provides different resistors for device turn-on and turn-off, so that the gate voltage rise and fall rate can be optimized independently in the two cases. This gives device and circuit designers more flexibility to adjust the gate resistance, so as to reduce device switching losses while ensuring device reliability.

[0053] The technical solution provided in this application integrates the gate signal conditioning circuit onto the power device chip, enabling circuit designers to achieve the effect of regulating the gate signal while reducing the number of components in the external gate signal circuit. Since gate overvoltage originates from the parasitic inductance of the gate signal loop, and the parasitic inductance is positively correlated with the coverage area of ​​the control gate signal loop, reducing the number of components in the external gate signal circuit is equivalent to reducing the loop area, i.e., the parasitic inductance. Therefore, this application design also provides the effect of fundamentally suppressing gate overvoltage, thereby further improving the device switching speed and further reducing device switching losses.

[0054] Figure 5 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. Figure 6 The circuit diagrams are for other embodiments of the semiconductor structures described in this application.

[0055] exist Figure 5 and Figure 6 In other embodiments shown, a second gate PN junction 126 is not provided, i.e., a third gate electrode doped region 123 is not provided.

[0056] When the device is turned on, the first gate PN junction 225 is forward biased, and the gate current passes through the first gate resistor 227 and the second gate resistor 228 connected in series. Therefore, the gate resistance when the device is turned on is the equivalent resistance of the first gate resistor 227 and the second gate resistor 228 connected in series.

[0057] When the device is turned off, the first gate PN junction 225 is reverse biased, and the gate current only passes through the second gate resistor 228. Therefore, the gate resistance when the device is turned off is the second gate resistor 228.

[0058] In this embodiment, since the second gate resistance 228 is always higher than the equivalent resistance of the first gate resistance 227 and the second gate resistance 228 connected in series, this embodiment is suitable for applications requiring a higher gate resistance when off than when on. This design reduces one structural point, lowers device complexity, and helps improve device yield.

[0059] Figure 7 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. Figure 8 The circuit diagrams are for other embodiments of the semiconductor structures described in this application.

[0060] exist Figure 7 and Figure 8 In other embodiments shown, the first gate PN junction 125 is not provided, that is, the second gate electrode doped region 122 is not provided.

[0061] When the device is turned on, the second gate PN junction 326 is reverse biased, and the gate current only passes through the first gate resistor 327. Therefore, the gate resistance when the device is turned on is the first gate resistor 327.

[0062] When the device is turned off, the second gate PN junction 326 is forward biased, and the gate current flows through the first gate resistor 327 and the second gate resistor 328 connected in series. Therefore, the gate resistance when the device is turned off is the equivalent resistance of the first gate resistor 327 and the second gate resistor 328 connected in series.

[0063] In this embodiment, since the first gate resistance 327 is always higher than the equivalent resistance of the first gate resistance 327 and the second gate resistance 328 connected in series, this embodiment is suitable for applications requiring a higher gate resistance during turn-on than during turn-off. This design also reduces a structural point, lowers device complexity, and helps improve device yield.

[0064] This application also provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate 100, wherein a first insulating layer 111 is formed on the surface of the semiconductor substrate 100; forming a gate electrode on the surface of the first insulating layer 111; forming a first gate electrode doped region 121 and a fourth gate electrode doped region 124 in the gate electrode using a first ion implantation process; forming at least one of a second gate electrode doped region 122 and a third gate electrode doped region 123 using a second ion implantation process, wherein the second gate electrode doped region 122 is disposed at a second end of the first gate electrode doped region 121, and the third gate electrode doped region 123 is disposed at a third end of the fourth gate electrode doped region 124. At one end, the first gate electrode doped region 121 and the fourth gate electrode doped region 124 have the same doping type, the second gate electrode doped region 122 and the third gate electrode doped region 123 have the same doping type, and the doping type of the second gate electrode doped region 122 and the fourth gate electrode doped region 124 is opposite to the doping type of the first gate electrode doped region 121 and the third gate electrode doped region 123; a gate metal wiring 132 is formed to electrically connect the first gate electrode doped region 121 and the third gate electrode doped region 123; and a gate metal pad 131 is formed to electrically connect the second gate electrode doped region 122 and the fourth gate electrode doped region 124.

[0065] It should be noted that the focus of this application is on the semiconductor structure, and the specific process for forming the semiconductor structure can be selected from suitable processes well known to those skilled in the art, and will not be elaborated further. For a description of the semiconductor structure, please refer to the preceding section on semiconductor structure.

[0066] This application provides a semiconductor structure and a method for forming the same, offering a technical solution that simultaneously reduces switching losses and improves gate reliability.

[0067] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0068] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0069] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0070] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a first insulating layer is formed on the surface of the semiconductor substrate; A gate electrode is located on the surface of the first insulating layer, and the gate electrode includes a first gate electrode doped region and a fourth gate electrode doped region; At least one of a second gate electrode doped region and a third gate electrode doped region, wherein the second gate electrode doped region is disposed at a second end of the first gate electrode doped region, and the third gate electrode doped region is disposed at a first end of the fourth gate electrode doped region; the first gate electrode doped region and the fourth gate electrode doped region have the same doping type; the second gate electrode doped region and the third gate electrode doped region have the same doping type; and the doping type of the second gate electrode doped region and the third gate electrode doped region is opposite to the doping type of the first gate electrode doped region and the fourth gate electrode doped region. A gate metal wiring is provided to electrically connect the first gate electrode doped region and the third gate electrode doped region. The gate metal pad is electrically connected to the second gate electrode doped region and the fourth gate electrode doped region.

2. The semiconductor structure as described in claim 1, characterized in that, The gate electrode is made of polycrystalline silicon, and the first, second, third, and fourth gate electrode doped regions are formed by ion implantation of the gate electrode.

3. The semiconductor structure as described in claim 1, characterized in that, The first ends of the first gate electrode doped region and the fourth gate electrode doped region are connected.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second insulating layer covers the first insulating layer and the gate electrode surface, and the gate metal wiring and gate metal pad penetrate the second insulating layer.

5. The semiconductor structure as described in claim 1, characterized in that, The doping concentrations of the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region, and the fourth gate electrode doped region are the same.

6. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a first insulating layer is formed on the surface of the semiconductor substrate; A gate electrode is formed on the surface of the first insulating layer; A first gate electrode doped region and a fourth gate electrode doped region are formed in the gate electrode; At least one of a second gate electrode doped region and a third gate electrode doped region is formed. The second gate electrode doped region is disposed at the second end of the first gate electrode doped region, and the third gate electrode doped region is disposed at the first end of the fourth gate electrode doped region. The first gate electrode doped region and the fourth gate electrode doped region have the same doping type, the second gate electrode doped region and the third gate electrode doped region have the same doping type, and the doping type of the second gate electrode doped region and the third gate electrode doped region is opposite to the doping type of the first gate electrode doped region and the fourth gate electrode doped region. A gate metal wiring is formed that electrically connects the first gate electrode doped region and the third gate electrode doped region; A gate metal pad is formed that electrically connects the second gate electrode doped region and the fourth gate electrode doped region.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The gate electrode is made of polycrystalline silicon, and the first, second, third, and fourth gate electrode doped regions are formed by ion implantation of the gate electrode.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first ends of the first gate electrode doped region and the fourth gate electrode doped region are connected.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: A second insulating layer is formed covering the first insulating layer and the gate electrode surface, with the gate metal wiring and gate metal pad penetrating through the second insulating layer.

10. The method for forming a semiconductor structure as described in claim 6, characterized in that, The doping concentrations of the first gate electrode doped region, the second gate electrode doped region, the third gate electrode doped region, and the fourth gate electrode doped region are the same.

Images