Gallium nitride transistor and preparation method thereof, and bidirectional switch

Abstract

The invention discloses a gallium nitride transistor and a preparation method thereof, and a bidirectional switch, and relates to the technical field of semiconductor devices. The gallium nitride transistor comprises a substrate, and a buffer layer, a channel layer and a first barrier layer which are sequentially positioned on one side of the substrate, comprising a first gate trench and a second gate trench, the gate trench is located in the first barrier layer, and the thickness of the first barrier layer below the bottom of the gate trench is not zero; a gate structure including a first gate and a second gate, a source structure including a first source and a second source; the first grid electrode is located in the first grid electrode groove, and the second grid electrode is located in the second grid electrode groove; the source structure is located on one side, deviating from the channel layer, of the first barrier layer; the first source electrode and the second source electrode are positioned on two opposite sides of the gate structure; and the gate dielectric layers are at least located between the first gate and the first barrier layer and between the second gate and the first barrier layer. According to the invention, the conduction performance and the current driving capability of the gallium nitride transistor are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium nitride transistor and its fabrication method, as well as a bidirectional switch. Background Technology

[0002] Gallium nitride (GaN) two-dimensional electron gas transistors, as third-generation wide-bandgap semiconductor devices, have been widely used in modern power electronic systems due to their excellent characteristics such as high breakdown voltage, low on-resistance, and high frequency response, and are especially suitable for high-density, high-efficiency power conversion scenarios.

[0003] In recent years, with the evolution of power electronic devices towards miniaturization and high performance, new application demands such as solid-state circuit breakers with bidirectional current regulation capabilities and AC power management have emerged. To meet these bidirectional current control application requirements, various monolithic bidirectional switch (MBS) structures based on GaN transistors have been proposed in existing technologies. Among them, the dual-gate common-drain MBS device has become a current research hotspot due to its advantages of high structural symmetry, good current control capability, and adaptability to power density.

[0004] To ensure safer driving characteristics for dual-gate common-drain MBS devices in power electronic systems, existing technologies typically employ a p-type doped GaN layer above the barrier layer to deplete the two-dimensional electron gas in the channel, ensuring the device remains normally off when there is no gate voltage. However, the pGaN gate structure exhibits significant drawbacks under long-term high-temperature and high-pressure operating conditions, such as a narrow gate voltage window, unstable threshold voltage, large gate leakage current, and poor reliability, thus limiting the widespread application of the device in high-reliability scenarios. Summary of the Invention

[0005] This invention provides a gallium nitride transistor and its fabrication method, as well as a bidirectional switch. By setting a gate trench portion that penetrates the first barrier layer, the conduction performance and current driving capability of the gallium nitride transistor are improved while ensuring that the gallium nitride transistor has normally-off characteristics.

[0006] The first aspect of the present invention provides a gallium nitride transistor, the gallium nitride transistor comprising:

[0007] Substrate;

[0008] A buffer layer is located on one side of the substrate;

[0009] A channel layer is located on the side of the buffer layer opposite to the substrate;

[0010] The first barrier layer is located on the side of the channel layer opposite to the buffer layer;

[0011] A gate trench, comprising a first gate trench and a second gate trench, wherein the first gate trench and the second gate trench are arranged sequentially along a direction parallel to the plane of the substrate; the gate trench is located within the first barrier layer, and the thickness of the first barrier layer below the bottom of the gate trench is not zero;

[0012] A gate structure and a source structure are provided, wherein the gate structure includes a first gate and a second gate, and the source structure includes a first source and a second source; the first gate is located in a first gate trench, and the second gate is located in a second gate trench; the source structure is located on the side of the first barrier layer away from the channel layer; in the arrangement direction of the gate structure and the source structure, the first source and the second source are located on opposite sides of the gate structure;

[0013] A gate dielectric layer, wherein the gate dielectric layer is located at least between the first gate and the first barrier layer, and between the second gate and the first barrier layer.

[0014] Optionally, the gallium nitride transistor further includes: a second barrier layer;

[0015] The second barrier layer is located between the channel layer and the first barrier layer;

[0016] The first barrier layer is an AlGaN barrier layer, and the second barrier layer is an AlN barrier layer.

[0017] Optionally, the gallium nitride transistor further includes: a cap layer;

[0018] The cap layer covers the first barrier layer;

[0019] The gate trench extends through the cap layer; the source structure is located on the side of the cap layer opposite to the first barrier layer.

[0020] Optionally, the gate dielectric layer is also located on the side of the first barrier layer away from the channel layer;

[0021] The gate dielectric layer further includes a first opening structure and a second opening structure;

[0022] The first source electrode is located within the first opening structure, and the second source electrode is located within the second opening structure.

[0023] Optionally, the thickness L1 of the first barrier layer is in the range of 24nm≤L1≤26nm;

[0024] The thickness L2 of the first barrier layer below the bottom of the gate trench is in the range of 6nm ≤ L2 ≤ 8nm.

[0025] A second aspect of the present invention provides a method for fabricating a gallium nitride transistor, the method comprising:

[0026] Provide substrate;

[0027] A buffer layer, a channel layer, and a first barrier layer are sequentially formed on one side of the substrate;

[0028] The first barrier layer is patterned to form a gate trench; the gate trench includes a first gate trench and a second gate trench, the first gate trench and the second gate trench are arranged sequentially along a direction parallel to the plane of the substrate; the gate trench is located within the first barrier layer, and the thickness of the first barrier layer below the bottom of the gate trench is not zero.

[0029] A source structure, a gate dielectric layer, and a gate structure are formed; the gate structure includes a first gate and a second gate, and the source structure includes a first source and a second source; the first gate is located in a first gate trench, and the second gate is located in a second gate trench; the source structure is located on the side of the first barrier layer away from the channel layer; in the arrangement direction of the gate structure and the source structure, the first source and the second source are located on opposite sides of the gate structure; the gate dielectric layer is located at least between the first gate and the first barrier layer, and between the second gate and the first barrier layer.

[0030] Optionally, before forming the first barrier layer, the following is also included:

[0031] A second barrier layer is formed on the side of the channel layer opposite to the buffer layer;

[0032] The first barrier layer is an AlGaN barrier layer, and the second barrier layer is an AlN barrier layer.

[0033] Optionally, the first barrier layer is patterned to form a gate trench, including:

[0034] The first barrier layer is patterned using an inductively coupled plasma etching process to form an initial gate trench;

[0035] The initial gate trench is patterned using an atomic layer lift-off process to form the gate trench;

[0036] The value range of k, which is the ratio of the depth of the initial gate trench to the depth of the gate trench, is: 4 / 9 ≤ k ≤ 5 / 9.

[0037] Optionally, a source structure, a gate dielectric layer, and a gate structure are formed, including:

[0038] A source structure is formed on the side of the first barrier layer away from the channel layer;

[0039] The gate dielectric layer is formed; the gate dielectric layer covers the source structure and the first barrier layer;

[0040] The gate dielectric layer is patterned to form a first opening structure and a second opening structure; the first source is located within the first opening structure, and the second source is located within the second opening structure.

[0041] The gate structure is formed within the gate trench.

[0042] A third aspect of the present invention provides a bidirectional switch, the bidirectional switch comprising: a gallium nitride transistor as described above.

[0043] The technical solution of this invention, by sequentially depositing a buffer layer, a channel layer, and a first barrier layer on one side of the substrate in a gallium nitride (GaN) transistor, enables the formation of a high-mobility current-carrying channel between the first barrier layer and the channel layer. By sequentially arranging the first gate trench and the second gate trench in the gate trench along a direction parallel to the plane of the substrate, a foundation is provided for forming a dual-gate control structure in a bidirectional switching device. By placing the gate trench within the first barrier layer and ensuring that the thickness of the first barrier layer below the bottom of the gate trench is not zero, the conduction performance and current drive capability of the GaN transistor are improved while ensuring its normally-off characteristics. By placing the first gate in a first gate trench and the second gate in a second gate trench, and placing the source structure on the side of the first barrier layer away from the channel layer, and by placing the first source and the second source in the source structure on opposite sides of the gate structure in the arrangement direction of the gate and source structures, a bidirectional switching device based on a gallium nitride transistor can be constructed. This enables the gallium nitride transistor to have bidirectional conductivity, making it suitable for circuit scenarios such as high-frequency alternating control and symmetrical drive. Furthermore, by placing gate dielectric layers between the first gate and the first barrier layer, and between the second gate and the first barrier layer, the thermal stability and reliability of the gallium nitride transistor can be improved while effectively suppressing gate leakage current.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a gallium nitride transistor device structure provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of another gallium nitride transistor device structure provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic flowchart of a method for fabricating a gallium nitride transistor according to an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the fabrication process of a gallium nitride transistor provided in an embodiment of the present invention;

[0050] Figure 5 This is a unidirectional output characteristic curve of the gallium nitride transistor provided in the embodiment of the present invention;

[0051] Figure 6 This is a bidirectional output characteristic curve of a gallium nitride transistor provided in an embodiment of the present invention;

[0052] Figure 7 This is the transfer characteristic curve of a gallium nitride transistor in a single direction corresponding to the linear coordinate system provided in the embodiments of the present invention;

[0053] Figure 8 This is the transfer characteristic curve of a gallium nitride transistor in a single direction in the logarithmic coordinate system provided in the embodiments of the present invention;

[0054] Figure 9 This is the breakdown characteristic curve of the gallium nitride transistor in a single transmission direction provided in the embodiments of the present invention;

[0055] Figure 10 This is the off-state leakage current characteristic curve of the gallium nitride transistor in a single transmission direction provided in the embodiments of the present invention;

[0056] Figure 11 This is a schematic diagram of the AC chopper characterization circuit provided in an embodiment of the present invention;

[0057] Figure 12 This is a graph showing the AC chopping characterization results of the gallium nitride transistor provided in this embodiment of the invention. Detailed Implementation

[0058] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] Figure 1 This is a schematic diagram of a gallium nitride transistor device structure provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the gallium nitride transistor includes: a substrate 1; a buffer layer 2 located on one side of the substrate 1; a channel layer 3 located on the side of the buffer layer 2 away from the substrate 1; a first barrier layer 4 located on the side of the channel layer 3 away from the buffer layer 2; a gate trench 5, which includes a first gate trench 51 and a second gate trench 52, arranged sequentially along a direction parallel to the plane of the substrate 1; the gate trench 5 is located within the first barrier layer 4, and the thickness of the first barrier layer 4 below the bottom of the gate trench 5 is not zero; a gate structure 6 and a source structure 7. The gate structure 6 includes a first gate 61 and a second gate 62, and the source structure 7 includes a first source 71 and a second source 72. The first gate 61 is located in the first gate trench 51, and the second gate 62 is located in the second gate trench 52. The source structure 7 is located on the side of the first barrier layer 4 away from the channel layer 3. In the arrangement direction of the gate structure 6 and the source structure 7, the first source 71 and the second source 72 are located on opposite sides of the gate structure 6. The gate dielectric layer 8 is located at least between the first gate 61 and the first barrier layer 4, and between the second gate 62 and the first barrier layer 1.

[0061] In this design, substrate 1 specifically supports the entire gallium nitride transistor device structure. The material of substrate 1 may include silicon, and its thickness may be, for example, 1 mm. Buffer layer 2 is located on one side of substrate 1 and is specifically used to address defects caused by lattice mismatch, preventing impurities in substrate 1 from being conducted upwards and suppressing leakage current. The material of buffer layer 2 may include C-doped GaN, and its thickness may be, for example, 5 μm. Channel layer 3 is located on the side of buffer layer 2 away from substrate 1 and is specifically used to provide a two-dimensional electron gas (2DEG) channel. The material of channel layer 3 may include undoped GaN or lightly doped GaN, and its thickness may be, for example, 300 nm. A first barrier layer 4 is located on the side of channel layer 3 away from buffer layer 2 and is specifically used to form a heterojunction with channel layer 3, thereby inducing and controlling the concentration and distribution of 2DEG. The material of barrier layer 4 may include an AlGaN barrier layer with an Al composition of 25%. The high-energy band discontinuity of the first barrier layer 4 helps to induce a large number of 2DEGs at the heterojunction interface, forming a high-mobility current-carrying channel, thereby effectively improving the on-state conductivity of the gallium nitride transistor and reducing the on-resistance of the gallium nitride transistor.

[0062] The gate trench 5 is specifically used to define the gate region in the gallium nitride transistor. The gate trench 5 includes a first gate trench 51 and a second gate trench 52, which are arranged sequentially along a direction parallel to the plane of the substrate 1, thus providing a basis for forming a dual-gate control structure in a bidirectional switching device. The gate trench 5 is located within the first barrier layer 4, and the thickness of the first barrier layer 4 below the bottom of the gate trench 5 is not zero; that is, the gate trench 5 only partially penetrates the first barrier layer 4, and the gate trench 5 is not etched to the channel layer 3. It is understandable that if the first barrier layer 4 is not etched to form the gate trench 5, the gate and channel in the gallium nitride transistor are still separated by a complete AlGaN barrier layer, making it impossible to effectively control the polarization charge and forming a high-density 2DEG in the channel. This makes it difficult to achieve a positive threshold voltage, and the gallium nitride transistor remains in a normally-on state with poor safety. It is also understandable that if the gate trench 5 completely penetrates the first barrier layer 4, the polarization charge will be completely shielded and the 2DEG below the gate will be excessively depleted. Although a gallium nitride transistor (GaN) in a normally off state can be achieved, the electron concentration in the GaN transistor's on state will be significantly reduced, leading to a significant increase in on-resistance and a decrease in the output efficiency and power density of the GaN transistor. Therefore, the gate trench 5, which only partially penetrates the first barrier layer 4, can introduce appropriate polarization regulation and create a threshold voltage rise, thereby achieving the normally off characteristic of the GaN transistor. At the same time, it can maintain an appropriate concentration of 2DEG channels when the GaN transistor is on, thereby reducing on-resistance and improving the output current and energy conversion efficiency of the GaN transistor. This achieves the goal of improving the conduction performance and current drive capability of the GaN transistor while ensuring its normally off characteristic, significantly improving the performance of the GaN transistor in high-voltage, high-frequency power electronics applications.

[0063] Optional, continue to refer to Figure 1 The thickness L1 of the first barrier layer 4 has a range of 24nm≤L1≤26nm; the thickness L2 of the first barrier layer 4 below the bottom of the gate trench 5 has a range of 6nm≤L2≤8nm.

[0064] Specifically, the thickness L1 of the first barrier layer 4 ranges between 24nm and 26nm, and the thickness L2 of the first barrier layer 4 below the bottom of the gate trench 5 ranges between 6nm and 8nm. That is, the depth of the gate trench 5 in the first barrier layer 4 is approximately 18nm, only partially penetrating the first barrier layer 4. It can be understood that if the depth of the gate trench 5 in the first barrier layer 4 is too deep, that is, when L2 approaches 0, the gate trench 5 completely penetrates the first barrier layer 4, and the 2DEG below the gate region may be excessively depleted, resulting in an increase in the on-resistance of the gallium nitride transistor and a decrease in output capability. If the depth of the gate trench 5 in the first barrier layer 4 is too shallow, for example, when L2 is greater than 10nm, the modulation capability of the gate control on the first barrier layer 4 will be weakened, making it difficult to fully deplete the electrons in the channel region, thus failing to achieve a positive threshold voltage and causing the device to remain in the normally on state. Therefore, by precisely setting the values ​​of L1 and L2 within a reasonable range, the threshold control capability and output performance of gallium nitride transistors in the on state are balanced, which is beneficial to improving the on-state performance and current driving capability of gallium nitride transistors, while ensuring the consistency and repeatability of the fabrication process.

[0065] The gate structure 6 includes a first gate 61 and a second gate 62, and the source structure 7 includes a first source 71 and a second source 72. The first gate 61 is located in the first gate trench 51, and the second gate 62 is located in the second gate trench 52. The source structure 7 is located on the side of the first barrier layer 4 away from the channel layer 3. In the arrangement direction of the gate structure 6 and the source structure 7, the first source 71 and the second source 72 are located on opposite sides of the gate structure 6. Thus, a bidirectional switching device based on a gallium nitride transistor can be formed by the first gate 61, the second gate 62, the first source 71, and the second source 72. In the actual operation of this bidirectional switching device, the first source 71 and the second source 72 can alternately act as the source or drain according to the device's operating mode, so that the gallium nitride transistor has bidirectional conductivity and is suitable for circuit scenarios such as high-frequency alternating control and symmetrical driving. Understandably, during the actual operation of a gallium nitride (GaN) transistor, the conduction state of the device is controlled by the gate-source voltage on the same side. For example, if the voltage between the first gate 61 and the first source 71 is greater than the threshold voltage of the GaN transistor, a 2DEG is formed in the channel region, the device is turned on, and current can flow from the first source S1 to the second source S2; if the voltage between the first gate 61 and the first source 71 is less than the threshold voltage of the GaN transistor, the channel is depleted, and the device is turned off. The second gate 62 and the second source 72 also have the same regulatory relationship. Therefore, the GaN transistor can achieve bidirectional symmetrical control and conduction path switching. For example, the materials of the first source 71 and the second source 72 may include a Ti / Al / Ni / TiN metal stack structure or a Ti / Al / Ni / Au metal stack structure, which have good ohmic contact performance and thermal stability; the materials of the first gate 61 and the second gate 62 may include metal stacks such as Ni / TiN, Ni / Au, Ti / TiN, or Ti / Au to achieve the required gate control characteristics, electrochemical stability, and process compatibility.

[0066] Furthermore, a gate dielectric layer 8 is disposed between the first gate 61 and the first barrier layer 4, and between the second gate 62 and the first barrier layer 1. The material of the gate dielectric layer 8 may include Al2O3 or SiO2, and the thickness of the gate dielectric layer 8 may be 15nm-20nm. Specifically, the gate dielectric layer 8 is used to provide electrical isolation between the gate structure 6 and the first barrier layer 4 to suppress gate leakage current. At the same time, by introducing the gate dielectric layer 8 between the gate structure 6 and the first barrier layer 4, a metal-insulator-semiconductor (MIS) gate structure can be formed. It is understood that traditional gate structures with p-type GaN gate control structures are prone to high gate leakage current and unstable threshold voltage due to their limited bandgap engineering and doping stability, resulting in poor long-term device reliability and easy operating point drift. Therefore, by implementing the MIS gate structure through the gate dielectric layer 8, the thermal stability of the threshold voltage can be improved, and the power consumption and breakdown risk at the gate can be reduced while effectively suppressing the gate leakage current. This significantly improves the thermal stability and reliability of gallium nitride transistors, making them suitable for applications under harsh working conditions such as long-term operation, high power, and high temperature.

[0067] In this embodiment, a buffer layer, a channel layer, and a first barrier layer are sequentially disposed on one side of the substrate in the gallium nitride transistor (GaN) to form a high-mobility current-carrying channel between the first barrier layer and the channel layer. By arranging the first and second gate trenches in the gate trench sequentially along a direction parallel to the plane of the substrate, a foundation is provided for forming a dual-gate control structure in a bidirectional switching device. By placing the gate trench within the first barrier layer and ensuring that the thickness of the first barrier layer below the bottom of the gate trench is not zero, the conduction performance and current drive capability of the GaN transistor are improved while maintaining its normally-off characteristics. By placing the first gate in a first gate trench and the second gate in a second gate trench, and placing the source structure on the side of the first barrier layer away from the channel layer, and by placing the first source and the second source in the source structure on opposite sides of the gate structure in the arrangement direction of the gate and source structures, a bidirectional switching device based on a gallium nitride transistor can be constructed. This enables the gallium nitride transistor to have bidirectional conductivity, making it suitable for circuit scenarios such as high-frequency alternating control and symmetrical drive. Furthermore, by placing gate dielectric layers between the first gate and the first barrier layer, and between the second gate and the first barrier layer, the thermal stability and reliability of the gallium nitride transistor can be improved while effectively suppressing gate leakage current.

[0068] Optional, Figure 2 This is a schematic diagram of another gallium nitride transistor device structure provided in an embodiment of the present invention. Figure 2As shown, the gallium nitride transistor further includes: a second barrier layer 9; the second barrier layer 9 is located between the channel layer 3 and the first barrier layer 4; wherein the first barrier layer 4 is an AlGaN barrier layer and the second barrier layer 9 is an AlN barrier layer.

[0069] Specifically, the second barrier layer 9 is located between the channel layer 3 and the first barrier layer 4. The first barrier layer 4 is an AlGaN barrier layer, and the second barrier layer 9 is an AlN barrier layer. It can be understood that AlN is a wide bandgap semiconductor material, with a larger bandgap than AlGaN and a lattice constant closer to GaN. Therefore, the second barrier layer 9 helps to alleviate the lattice mismatch stress between the first barrier layer 4 and the channel layer 3. By setting the second barrier layer 9, it can serve as a lattice transition layer between the first barrier layer 4 and the channel layer 3, effectively mitigating defects caused by lattice mismatch. Furthermore, it can enhance the 2DEG concentration at the interface in the heterostructure, helping to improve the device's on-state current and the overall polarization effect of the barrier, thus facilitating higher current carrying capacity of the gallium nitride transistor in the on-state.

[0070] Optional, continue to refer to Figure 2 The gallium nitride transistor also includes: a cap layer 10; the cap layer 10 covers the first barrier layer 4; a gate trench 5 penetrates the cap layer 10; and a source structure 7 is located on the side of the cap layer 10 away from the first barrier layer 4.

[0071] Specifically, the cap layer 10 covers the first barrier layer 4, and the gate trench 5 penetrates the cap layer 10 to form a gate trench 5 that partially penetrates the first barrier layer 4. The source structure 7 is located on the side of the cap layer 10 facing away from the first barrier layer 4; that is, the cap layer 10 is the uppermost layer structure of the gallium nitride transistor. The material of the cap layer 10 may include GaN to enable an effective ohmic contact interface between the cap layer 10 and the source structure 7. The cap layer 10 specifically provides shielding and buffering for the gallium nitride transistor. During subsequent metal sputtering, etching, and cleaning processes, the cap layer 10 effectively prevents the direct erosion of the first barrier layer 4 and the channel layer 3 by process plasmas and chemical solutions, thereby ensuring the structural stability of the gallium nitride transistor. The thickness of the cap layer 10 can be, for example, 1 nm.

[0072] Optional, continue to refer to Figure 2 The gate dielectric layer 8 is also located on the side of the first barrier layer 4 away from the channel layer 3; the gate dielectric layer 8 also includes a first opening structure 81 and a second opening structure 82; the first source 71 is located in the first opening structure 81 and the second source 72 is located in the second opening structure 82.

[0073] Specifically, the gate dielectric layer 8 is not only located between the first gate 61 and the first barrier layer 4, and between the second gate 62 and the first barrier layer 4, but also extends further to the side of the first barrier layer 4 away from the channel layer 3, forming a capping layer. Simultaneously, the gate dielectric layer 8 has a first opening structure 81 and a second opening structure 82, which respectively accommodate the first source 71 through the first opening structure 81 and the second source 72 through the second opening structure 82, thereby ensuring effective electrical contact between the source structure 7 and the cap layer 10. Furthermore, the complete coverage of the first barrier layer 4 by the gate dielectric layer 8 effectively prevents current leakage caused by surface states, charge accumulation, or environmental factors, further enhancing the electrical insulation and long-term stability of the gallium nitride transistor.

[0074] Based on the same inventive concept, this invention also provides a method for fabricating a gallium nitride transistor. Figure 3 This is a schematic flowchart of a gallium nitride transistor fabrication method provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the fabrication process of a gallium nitride transistor according to an embodiment of the present invention, combined with... Figure 3 and Figure 4 As shown, the method for fabricating this gallium nitride transistor includes:

[0075] S101, Provide substrate.

[0076] Specifically, substrate 1 is used to support the entire device structure of the gallium nitride transistor. The material of substrate 1 may include silicon, and the thickness of substrate 1 may be, for example, 1 mm.

[0077] S102, A buffer layer, a channel layer, and a first barrier layer are sequentially formed on one side of the substrate.

[0078] Specifically, using epitaxial growth technology, a buffer layer 2, a channel layer 3, and a first barrier layer 4 are sequentially formed on one side of a substrate 1. The buffer layer 2, located on one side of the substrate 1, is specifically used to address defects caused by lattice mismatch, preventing impurities in the substrate 1 from being conducted upwards and suppressing leakage current. The material of the buffer layer 2 may include C-doped GaN, and its thickness may be, for example, 5 μm. The channel layer 3, located on the side of the buffer layer 2 away from the substrate 1, is specifically used to provide a two-dimensional electron gas (2DEG) channel. The material of the channel layer 3 may include undoped GaN or lightly doped GaN, and its thickness may be, for example, 300 nm. The first barrier layer 4, located on the side of the channel layer 3 away from the buffer layer 2, is specifically used to form a heterojunction with the channel layer 3, thereby inducing and controlling the concentration and distribution of 2DEG. The material of the barrier layer 4 may be an AlGaN barrier layer with an Al composition of 25%. The high-energy band discontinuity of the first barrier layer 4 helps to induce a large number of 2DEGs at the heterojunction interface, forming a high-mobility current-carrying channel, thereby effectively improving the on-state conductivity of the gallium nitride transistor and reducing the on-resistance of the gallium nitride transistor.

[0079] Optionally, before forming the first barrier layer 4, the method further includes forming a second barrier layer 9 on the side of the channel layer 3 away from the buffer layer 2; wherein the first barrier layer 4 is an AlGaN barrier layer and the second barrier layer 9 is an AlN barrier layer.

[0080] Specifically, before forming the first barrier layer 4, a second barrier layer 9 can be formed on the side of the channel layer 3 away from the buffer layer 2 using epitaxial growth technology. That is, the buffer layer 2, the channel layer 3, the second barrier layer 9, and the first barrier layer 4 are sequentially stacked on one side of the substrate 1. The first barrier layer 4 is an AlGaN barrier layer, and the second barrier layer 9 is an AlN barrier layer. It can be understood that AlN is a wide bandgap semiconductor material, with a larger bandgap than AlGaN and a lattice constant closer to GaN. Therefore, the second barrier layer 9 helps to alleviate the lattice mismatch stress between the first barrier layer 4 and the channel layer 3. By setting the second barrier layer 9, it can serve as a lattice transition layer between the first barrier layer 4 and the channel layer 3, effectively mitigating the defects caused by lattice mismatch and further enhancing the 2DEG concentration at the interface in the heterostructure. This helps to improve the conduction current of the device, enhance the overall polarization effect of the barrier, and facilitate higher current carrying capacity of the gallium nitride transistor in the on-state.

[0081] Furthermore, after the buffer layer 2, channel layer 3, second barrier layer 9, and first barrier layer 4 are sequentially formed on one side of the substrate 1, a mesa etching process can be used to pattern and etch the area on the substrate 1 other than the active region. Specifically, the layer structures forming 2DEG, such as the buffer layer 2, channel layer 3, second barrier layer 9, and first barrier layer 4, are completely etched away in the non-active region. This can suppress the formation of polarization-induced 2DEG in the non-active region, avoid the generation of parasitic conductive channels or leakage current at the edge of the gallium nitride transistor, and effectively improve the turn-off performance, breakdown voltage, and overall electrical isolation capability of the gallium nitride transistor.

[0082] S103. Pattern the first barrier layer to form a gate trench.

[0083] The gate trench 5 includes a first gate trench 51 and a second gate trench 52, which are arranged sequentially along a direction parallel to the plane of the substrate 1. The gate trench 5 is located in the first barrier layer 4, and the thickness of the first barrier layer 4 below the bottom of the gate trench 5 is not zero.

[0084] Specifically, inductively coupled plasma (ICP) etching or atomic layer etch (ALE) etching can be used to anisotropically etch the first barrier layer 4 with the aid of an etching mask to form a gate trench 5 including a first gate trench 51 and a second gate trench 52. The first gate trench 51 and the second gate trench 52 are arranged sequentially along a direction parallel to the plane of the substrate 1, and the etching depth is controlled to be within the first barrier layer 4, that is, the gate trench 5 is located within the first barrier layer 4, and the thickness of the first barrier layer 4 below the bottom of the gate trench 5 is not zero. It can be understood that the gate trench 5, which only partially penetrates the first barrier layer 4, can introduce appropriate polarization control and form a threshold voltage rise, thereby realizing the normally-off characteristic of the gallium nitride transistor, and can also maintain an appropriate concentration of 2DEG channels when the gallium nitride transistor is turned on, so as to reduce the on-resistance and improve the output current and energy conversion efficiency of the gallium nitride transistor. This achieves the goal of improving the conduction performance and current drive capability of gallium nitride transistors while ensuring their normally-off characteristics, thus significantly improving their performance in high-voltage and high-frequency power electronics applications.

[0085] Optionally, patterning the first barrier layer 4 to form the gate trench 5 includes: patterning the first barrier layer 4 using an inductively coupled plasma etching process to form an initial gate trench; and patterning the initial gate trench using an atomic layer lift-off process to form the gate trench 5; wherein the value range of k, which is the ratio of the depth of the initial gate trench to the depth of the gate trench 5, is: 4 / 9 ≤ k ≤ 5 / 9.

[0086] Specifically, when forming the gate trench 5, the first barrier layer 4 can be patterned using an ICP etching process to form an initial gate trench. The depth of this initial gate trench is approximately 4 / 9 to 5 / 9 of the total depth of the gate trench 5, allowing for rapid etching and removal of most of the first barrier layer 4 using the ICP etching process. After forming the initial gate trench, the initial gate trench can be further patterned using an ALE process to fill in the remaining etching depth until the gate trench 5 of the required etching depth is formed. It is understood that by using the ICP etching process, with an etching rate much higher than that of the ALE process, in the initial stage of etching the gate trench 5, most of the first barrier layer 4 can be removed quickly, shortening the overall etching time. After forming the initial gate trench, a shallow, fine etching process using the ALE process, which has extremely high anisotropic control capabilities, is performed to effectively avoid surface damage or bottom roughness. By combining ICP etching with ALE etching, the gate trench 5 is formed, avoiding the impact of reaction accumulation on etching depth and morphology consistency when patterning is performed entirely with ALE. This ensures both etching efficiency and gate trench 5 quality, which helps improve the reliability and performance stability of gallium nitride transistors.

[0087] S104, forming the source structure, the gate dielectric layer, and the gate structure.

[0088] The gate structure 6 includes a first gate 61 and a second gate 62, and the source structure 7 includes a first source 71 and a second source 72. The first gate 61 is located in the first gate trench 51, and the second gate 62 is located in the second gate trench 52. The source structure 7 is located on the side of the first barrier layer 4 away from the channel layer 6. In the arrangement direction of the gate structure 9 and the source structure 7, the first source 71 and the second source 72 are located on opposite sides of the gate structure 6. The gate dielectric layer 8 is located at least between the first gate 61 and the first barrier layer 4, and between the second gate 62 and the first barrier layer.

[0089] Specifically, after forming the gate trench 5, the source structure 7 can be formed sequentially by electron beam evaporation, the gate dielectric layer 8 can be formed by atomic layer deposition (ALD) process, and the gate structure 6 can be formed by electron beam evaporation process. The gate structure 6 includes a first gate 61 and a second gate 62, and the source structure 7 includes a first source 71 and a second source 72. The first gate 61 is located in the first gate trench 51, and the second gate 62 is located in the second gate trench 52. The source structure 7 is located on the side of the first barrier layer 4 away from the channel layer 3. In the arrangement direction of the gate structure 6 and the source structure 7, the first source 71 and the second source 72 are located on opposite sides of the gate structure 6. Thus, a bidirectional switching device based on a gallium nitride transistor can be formed by the first gate 61, the second gate 62, the first source 71, and the second source 72. In the actual operation of this bidirectional switching device, the first source 71 and the second source 72 can alternately act as the source or drain according to the device's operating mode, so that the gallium nitride transistor has bidirectional conductivity and is suitable for circuit scenarios such as high-frequency alternating control and symmetrical driving. Understandably, during the actual operation of a gallium nitride (GaN) transistor, the conduction state of the device is controlled by the gate-source voltage on the same side. For example, if the voltage between the first gate 61 and the first source 71 is greater than the threshold voltage of the GaN transistor, a 2DEG is formed in the channel region, the device is turned on, and current can flow from the first source S1 to the second source S2. If the voltage between the first gate 61 and the first source 71 is less than the threshold voltage of the GaN transistor, the channel is depleted, and the device is turned off. The second gate 62 and the second source 72 also have the same regulatory relationship. Therefore, the GaN transistor can achieve bidirectional symmetrical control and conduction path switching.

[0090] Furthermore, the gate dielectric layer 8 is located at least between the first gate 61 and the first barrier layer 4, and between the second gate 62 and the first barrier layer. The material of the gate dielectric layer 8 may include Al2O3 or SiO2, and the thickness of the gate dielectric layer 8 may be 15nm-20nm. Specifically, the gate dielectric layer 8 is used to provide electrical isolation between the gate structure 6 and the first barrier layer 4 to suppress gate leakage current. Simultaneously, by introducing the gate dielectric layer 8 between the gate structure 6 and the first barrier layer 4, a MIS gate structure can be formed, thereby effectively suppressing gate leakage current while improving the thermal stability and reliability of the gallium nitride transistor.

[0091] Optionally, forming a source structure 7, a gate dielectric layer 8, and a gate structure 6 includes: forming a source structure 7 on the side of the first barrier layer 4 away from the channel layer 3; forming a gate dielectric layer 8; the gate dielectric layer 8 covering the source structure 7 and the first barrier layer 4; patterning the gate dielectric layer 8 to form a first opening structure 81 and a second opening structure 82; a first source 71 located within the first opening structure 81, and a second source 72 located within the second opening structure 82; and forming a gate structure 6 within a gate trench 5.

[0092] Specifically, before forming the source structure 7 on the side of the first barrier layer 4 away from the channel layer 3, photoresist can be first coated on the surface of the first barrier layer 4, and a patterned structure can be formed by exposure and development to form an opening only in the preset source region. Then, the source region can be treated with low-power oxygen plasma to further remove organic residues and oxide layers from the surface of the source region, improving the metal contact quality. Afterwards, an electron beam evaporation process can be used to sequentially deposit a Ti / Al / Ni / TiN metal stack structure or a Ti / Al / Ni / Au metal stack structure. After metal deposition, acetone can be used to dissolve the photoresist, thereby removing excess metal from non-source regions and retaining only the metal structure in the source region. To further reduce contact resistance, a rapid thermal annealing (RTA) furnace can be used to heat-treat the metal structure in a nitrogen atmosphere. The specific temperature can be selected according to the type of metal. For example, TiN structures are usually annealed at temperatures above 950°C, while if the outermost layer is Au material, the annealing temperature should not be lower than 875°C. This ensures that a low-resistance ohmic contact is formed between the source metal and the underlying AlGaN material, thereby improving the conductivity of the gallium nitride transistor.

[0093] After forming the source structure 7, an Al2O3 or SiO2 gate dielectric layer 8 with a thickness of 15nm-20nm can be deposited on the device surface using an ALD process. This gate dielectric layer 8 covers not only the exposed first barrier layer 4 but also the source structure 7. To re-expose the source electrode region, the gate dielectric layer 8 needs to be further patterned. For example, photoresist can be coated again, and after forming the patterned structure by exposure and development, wet etching can be performed using an alkaline solution to form the first opening structure 81 and the second opening structure 82 at the positions of the gate dielectric layer 8 corresponding to the source electrode region, thereby exposing the first source 71 and the second source 72. Subsequently, the gate dielectric layer 8 can be subjected to RTA annealing in a nitrogen environment to repair the interface defects between the gate dielectric layer 8 and the first barrier layer 4, improve the interface quality, and enhance the reliability of the gate region. After forming the gate dielectric layer 8, a Ni / TiN metal structure or a Ti / Au metal structure can be deposited in the gate trench 5 using a method similar to source metal deposition to form the gate structure 6.

[0094] The above-described method for fabricating gallium nitride (GaN) transistors can be used to fabricate the GaN transistors provided in any embodiment of the present invention, which possess the corresponding functions and beneficial effects of GaN transistors. Technical details not described in detail in this embodiment can be found in the GaN transistors provided in any embodiment of the present invention.

[0095] Since the gallium nitride (GaN) transistor fabrication method described above can be used to fabricate the GaN transistor in the embodiments of this invention, those skilled in the art can understand the specific implementation methods and various variations of the GaN transistor fabrication method described in these embodiments based on the GaN transistor. Therefore, how the GaN transistor fabrication method is implemented to fabricate the GaN transistor in the embodiments of this invention will not be described in detail here. Any method used by those skilled in the art to fabricate the GaN transistor in the embodiments of this invention falls within the scope of protection of this application.

[0096] To verify the performance of the gallium nitride transistor in the embodiments of the present invention, the following experimental tests can be performed on the gallium nitride transistor. Figure 5 This is a unidirectional output characteristic curve of the gallium nitride transistor provided in an embodiment of the present invention. In this experimental test, only one gate is turned on and a voltage is applied between the source and the gate. The results show that the gallium nitride transistor exhibits different gate-source voltages V. gs The output current changes under certain conditions. For example... Figure 5 As shown, with the gradual increase of the gate-source voltage, the 2DEG in the channel is gradually controlled and recovered, and the conduction capability of the gallium nitride transistor is significantly improved, with its saturation current density showing a clear upward trend. When the gate-source voltage increases to 6V, the gallium nitride transistor can achieve a unidirectional saturation current density of approximately 500mA / mm, indicating that the gallium nitride transistor has low on-resistance and good current carrying capacity in the on-state.

[0097] Figure 6 This is a bidirectional output characteristic curve of the gallium nitride transistor provided in an embodiment of the present invention. In this experimental test, the gates on both sides are synchronously driven with their corresponding sources. By alternately changing the potentials of the two source terminals, the gallium nitride transistor is subjected to forward and reverse biases respectively. Figure 6 As can be seen, gallium nitride transistors exhibit clear conduction characteristics in both forward and reverse directions, with a symmetrically distributed output current, indicating good bidirectional current control capability. In the on-state, the current density can reach up to approximately 400 mA / mm², which, although slightly lower than the single-sided conduction mode, still provides sufficient current carrying capacity to meet the requirements of bidirectional switching devices in high-power operating environments.

[0098] Figure 7 This is the transfer characteristic curve of a gallium nitride transistor in a single direction corresponding to the linear coordinate system provided in the embodiments of the present invention. Figure 8 This is the transfer characteristic curve of a gallium nitride transistor in a single direction, corresponding to the logarithmic coordinate system provided in the embodiments of the present invention. For example... Figure 7 and Figure 8 As shown, with a drain voltage of 5V, the threshold voltage of the gallium nitride (GaN) transistor is approximately 0.9V, indicating that the GaN transistor is an enhancement-mode device. This enhancement-mode characteristic is due to the fact that the gate trench in the GaN transistor only partially penetrates the first barrier layer. Meanwhile, the transfer curves in logarithmic coordinates further demonstrate that the leakage current of the GaN transistor in the off-state is extremely low, reaching as low as 10V. -8 Below A, the excellent turn-off performance and breakdown suppression capability of gallium nitride transistors are demonstrated.

[0099] Figure 9 This is the breakdown characteristic curve of the gallium nitride transistor provided in an embodiment of the present invention in a single transmission direction. The total channel length of the gallium nitride transistor is 16 μm, of which the length of the structure used for voltage bearing is 12 μm, as shown below. Figure 9 As shown, when the drain voltage gradually increases to above 530V, the leakage current of the device increases sharply, indicating that the device has undergone hard breakdown. The breakdown voltage of up to 530V indicates that the gallium nitride transistor has good high voltage withstand capability, which can meet the application requirements of high power load circuits, and is especially suitable for power switching applications requiring high withstand voltage and low leakage current.

[0100] Figure 10 This is the off-state leakage current characteristic curve of a gallium nitride transistor in a single transmission direction provided in an embodiment of the present invention, with the test condition being a drain voltage of 5V. Figure 10 As shown, the gate leakage current of a gallium nitride (GaN) transistor is only about 40 nA when the gate voltage is 5V, while it is as low as 1.66 × 10⁻⁶ when the gate voltage is -1.3V. -11 A further demonstrates that gallium nitride transistors exhibit extremely low leakage current levels in the off-state. This characteristic is primarily attributed to the introduction of the MIS gate structure, which effectively enhances the gate's insulation capability and suppresses gate leakage current, thus benefiting high-reliability and low-power power device applications.

[0101] Figure 11 This is a schematic diagram of the AC chopper characterization circuit provided in an embodiment of the present invention, as shown below. Figure 11 As shown, this AC chopper characterization circuit is used to characterize the switching capability of the gallium nitride transistor provided in this embodiment of the invention under AC conditions. The AC chopper characterization circuit is powered by an AC power supply with an amplitude of ±5V and a frequency of 1.2kHz, and is driven by two fully synchronized gate drive signals V. G1 and V G2 Two reverse-connected device units S1 and S2 are alternately controlled at a switching frequency of 50kHz to achieve bidirectional current switching. Figure 12 This is a graph showing the AC chopping characterization results of the gallium nitride transistor provided in this embodiment of the invention, such as... Figure 12 As shown, the upper figure compares the waveforms of the AC power supply and the load voltage, indicating that the chopped output still follows the low-frequency sinusoidal envelope well. The lower figure shows the conduction voltage waveforms of the two devices in the positive and negative half-cycles, demonstrating good synchronous conduction and turn-off capabilities. Experimental results show that gallium nitride transistors can achieve stable chopping control at a frequency of 50kHz in a bidirectional current path, verifying their feasibility and excellent performance in bidirectional AC high-frequency control scenarios.

[0102] Based on the same inventive concept, this invention also provides a bidirectional switch, which includes a gallium nitride transistor as described in the above embodiments.

[0103] Therefore, the bidirectional switch provided in this embodiment has the structure and operation provided by the gallium nitride crystal in the above embodiment, and can achieve the effect of the gallium nitride transistor in the above embodiment. The similarities can be referred to the above description, and will not be repeated here.

[0104] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gallium nitride transistor, characterized in that, include: Substrate; A buffer layer is located on one side of the substrate; A channel layer is located on the side of the buffer layer opposite to the substrate; The first barrier layer is located on the side of the channel layer opposite to the buffer layer; A gate trench, comprising a first gate trench and a second gate trench, wherein the first gate trench and the second gate trench are arranged sequentially along a direction parallel to the plane of the substrate; the gate trench is located within the first barrier layer, and the thickness of the first barrier layer below the bottom of the gate trench is not zero; A gate structure and a source structure, wherein the gate structure includes a first gate and a second gate, and the source structure includes a first source and a second source; The first gate is located in the first gate trench, and the second gate is located in the second gate trench; The source structure is located on the side of the first barrier layer away from the channel layer; In the arrangement direction of the gate structure and the source structure, the first source and the second source are located on opposite sides of the gate structure; A gate dielectric layer, wherein the gate dielectric layer is located at least between the first gate and the first barrier layer, and between the second gate and the first barrier layer.

2. The gallium nitride transistor according to claim 1, characterized in that, Also includes: Second barrier layer; The second barrier layer is located between the channel layer and the first barrier layer; The first barrier layer is an AlGaN barrier layer, and the second barrier layer is an AlN barrier layer.

3. The gallium nitride transistor according to claim 1, characterized in that, Also includes: Cap layer; The cap layer covers the first barrier layer; The gate trench extends through the cap layer; The source structure is located on the side of the cap layer away from the first barrier layer.

4. The gallium nitride transistor according to claim 1, characterized in that, The gate dielectric layer is also located on the side of the first barrier layer away from the channel layer; The gate dielectric layer further includes a first opening structure and a second opening structure; The first source electrode is located within the first opening structure, and the second source electrode is located within the second opening structure.

5. The gallium nitride transistor according to claim 1, characterized in that, The thickness L1 of the first barrier layer has a range of 24nm≤L1≤26nm; The thickness L2 of the first barrier layer below the bottom of the gate trench is in the range of 6nm ≤ L2 ≤ 8nm.

6. A method for fabricating a gallium nitride transistor, characterized in that, include: Provide substrate; A buffer layer, a channel layer, and a first barrier layer are sequentially formed on one side of the substrate; The first barrier layer is patterned to form a gate trench; The gate trench includes a first gate trench and a second gate trench, which are arranged sequentially along a direction parallel to the plane of the substrate; the gate trench is located within the first barrier layer, and the thickness of the first barrier layer below the bottom of the gate trench is not zero. A source structure, a gate dielectric layer, and a gate structure are formed; the gate structure includes a first gate and a second gate, and the source structure includes a first source and a second source; the first gate is located in the first gate trench, and the second gate is located in the second gate trench; The source structure is located on the side of the first barrier layer away from the channel layer; In the arrangement direction of the gate structure and the source structure, the first source and the second source are located on opposite sides of the gate structure; the gate dielectric layer is located at least between the first gate and the first barrier layer, and between the second gate and the first barrier layer.

7. The method for fabricating a gallium nitride transistor according to claim 6, characterized in that, Before the formation of the first barrier layer, it also includes: A second barrier layer is formed on the side of the channel layer opposite to the buffer layer; The first barrier layer is an AlGaN barrier layer, and the second barrier layer is an AlN barrier layer.

8. The method for fabricating a gallium nitride transistor according to claim 6, characterized in that, Patterning the first barrier layer to form a gate trench includes: The first barrier layer is patterned using an inductively coupled plasma etching process to form an initial gate trench; The initial gate trench is patterned using an atomic layer lift-off process to form the gate trench; The value range of k, which is the ratio of the depth of the initial gate trench to the depth of the gate trench, is: 4 / 9 ≤ k ≤ 5 / 9.

9. The method for fabricating a gallium nitride transistor according to claim 6, characterized in that, Forming a source structure, a gate dielectric layer, and a gate structure, including: A source structure is formed on the side of the first barrier layer away from the channel layer; The gate dielectric layer is formed; the gate dielectric layer covers the source structure and the first barrier layer; The gate dielectric layer is patterned to form a first opening structure and a second opening structure; the first source is located within the first opening structure, and the second source is located within the second opening structure. The gate structure is formed within the gate trench.

10. A bidirectional switch, characterized in that, include: The gallium nitride transistor as described in any one of claims 1-6.

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