Semiconductor element and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, an epitaxial layer, a well, a dielectric layer, a gate electrode layer and a source pad. The substrate comprises an array area and a peripheral area which are adjacent to each other. The epitaxial layer is over the substrate. The well is located in the epitaxial layer. The dielectric layer is disposed over the epitaxial layer and over the array region and the peripheral region. The gate electrode layer is disposed over the dielectric layer and over the array region and the peripheral region. The gate electrode layer has at least one opening above the peripheral region. The source electrode connecting pad is arranged above the gate electrode layer and extends from the upper part of the array region to the upper part of the peripheral region. The source electrode connecting pad is provided with at least one first extending part which extends downwards to the well through the at least one opening of the gate electrode layer. The parasitic capacitance can be reduced, and the switching characteristic is improved.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As semiconductor manufacturing technology matures and the feature size of semiconductor devices shrinks, the requirements for switching speeds are also increasing. Among these requirements, gate parasitic capacitance, which leads to charge accumulation, is one factor affecting switching speed and stability. Therefore, developing a semiconductor device and its manufacturing method that can reduce gate parasitic capacitance is one of the problems that the industry urgently needs to address through research and development. Summary of the Invention

[0003] In view of this, one objective of this disclosure is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.

[0004] According to some embodiments disclosed herein, a semiconductor device includes a substrate, an epitaxial layer, a well, a dielectric layer, a gate electrode layer, and a source pad. The substrate includes an adjacent array region and a peripheral region. The epitaxial layer is located above the substrate. The well is located within the epitaxial layer. The dielectric layer is located above the epitaxial layer and above the array region and the peripheral region. The gate electrode layer is located above the dielectric layer and above the array region and the peripheral region. The gate electrode layer has at least one opening located above the peripheral region. The source pad is located above the gate electrode layer and extends from above the array region to above the peripheral region. The source pad has at least one first extension portion extending downward through the at least one opening in the gate electrode layer to the well.

[0005] According to other embodiments of this disclosure, a method of manufacturing a semiconductor device includes forming an epitaxial layer over a substrate, wherein the substrate includes adjacent array regions and peripheral regions. The manufacturing method further includes forming a first well in the epitaxial layer and over the peripheral regions. The manufacturing method further includes forming a first dielectric layer over the epitaxial layer and over the array regions and peripheral regions. The manufacturing method further includes forming a gate electrode layer on the first dielectric layer and over the array regions and peripheral regions. The manufacturing method further includes forming a via over the peripheral regions, wherein the via passes through the gate electrode layer and the first dielectric layer and exposes the first well. The manufacturing method further includes forming a source pad over the gate electrode layer and contacting the first well through the via.

[0006] In summary, in some embodiments of the semiconductor device and its manufacturing method disclosed herein, by forming multiple openings in the gate electrode layer located above the peripheral region, the overlap area between the gate electrode layer and the underlying dielectric layer can be reduced. This reduces the parasitic capacitance of the formed device, thereby improving its switching characteristics, enhancing forward conduction capability, and increasing switching stability. Furthermore, extending the source pad into the aforementioned openings increases the source contact area and reduces the source-drain voltage (V0). sd).

[0007] These and other aspects of this disclosure will become apparent from the following description of preferred embodiments in conjunction with the accompanying drawings, but variations and modifications may be made therein without departing from the spirit and scope of the novel concept of this disclosure. Attached Figure Description

[0008] The accompanying drawings illustrate one or more embodiments of this disclosure and, together with the written description, serve to explain the principles of this disclosure. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein:

[0009] Figure 1 and Figure 2 This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 3 This is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 4 According to some embodiments disclosed herein Figure 3 A partial enlarged view of the semiconductor device in box 4.

[0012] Figure 5 This is a top view of a semiconductor element according to some other embodiments of the present disclosure.

[0013] Figure 6 This is a partial cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure.

[0014] Figure 7 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following disclosure will be described more fully with reference to the accompanying drawings and reference data, some of which illustrate exemplary embodiments. This disclosure may be implemented in various forms and should not be limited to the embodiments mentioned below. However, these embodiments are provided to aid in a more complete understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0016] Please refer to Figures 1 to 4 . Figure 1 This is a partial cross-sectional view of a semiconductor element 10 according to some embodiments of the present disclosure. Figure 2 This is a partial cross-sectional view of semiconductor device 10 along another section. Figure 3 This is a top view of semiconductor element 10. Figure 4 for Figure 3A partially enlarged view of block 4 of the semiconductor element 10. More specifically, Figure 1 Along Figure 4 Draw the line segment A-A'. Figure 2 Then along Figure 4 Draw the line segment B-B'.

[0017] Please refer to Figure 1 and Figure 2 Semiconductor device 10 includes a substrate 100, an epitaxial layer 102, a well 104, a source doped region 106, a body contact doped region 108, and a well 110. The substrate 100 includes adjacent array regions AR and peripheral regions PR. The epitaxial layer 102 is located above the substrate 100. The well 104 is located in the epitaxial layer 102 and above the array region AR of the substrate 100. The source doped region 106 and the body contact doped region 108 are located in the well 104 and above the array region AR of the substrate 100. The well 110 is located in the epitaxial layer 102 and above the peripheral region PR of the substrate 100. The well 110 and well 104 are separate from each other, or they may be connected. In some embodiments, the width of well 104 is smaller than the width of well 110, such as... Figure 1 and Figure 2 As shown.

[0018] In some embodiments, the substrate 100, epitaxial layer 102, and source doped region 106 have a first conductivity type. For example, the substrate 100, epitaxial layer 102, and source doped region 106 are n-type semiconductor layers. In some embodiments, the substrate 100, epitaxial layer 102, and source doped region 106 have the same n-type dopant. In some embodiments, the dopant concentration of the source doped region 106 is greater than the dopant concentration of the epitaxial layer 102.

[0019] In some embodiments, well 104, body contact doped region 108, and well 110 have a second conductivity type different from the first conductivity type. For example, well 104, body contact doped region 108, and well 110 are p-type semiconductor layers. In some embodiments, well 104, body contact doped region 108, and well 110 have the same p-type dopant. In some embodiments, the dopant concentration of body contact doped region 108 is greater than that of well 104, and the overall dopant concentration of well 110 may be substantially equal to the dopant concentration of well 104 or body contact doped region 108, or other dopant concentrations. In other words, the dopant concentration at any location in well 110 is not limited to any single dopant concentration. In some embodiments, well 110 does not substantially contain the n-type dopant of source doped region 106. In other embodiments, the dopant concentration of the n-type dopant in well 110 is equal to or less than the dopant concentration of the n-type dopant in source doped region 106.

[0020] like Figure 1 and Figure 2 As shown, the semiconductor device 10 also includes a first dielectric layer 112, a gate electrode layer 114, and a second dielectric layer 116. The first dielectric layer 112 is located above the epitaxial layer 102 and above the array region AR and peripheral region PR of the substrate 100. Specifically, the first dielectric layer 112a is located above the peripheral region PR, and the first dielectric layer 112a may comprise a stack of dielectric materials formed by multiple processes, and has the following characteristics: Figure 1The thickness variation shown is illustrated (e.g., a smaller thickness on the side closer to the array region AR). The first dielectric layer 112b is located above both the array region AR and the peripheral region PR. The first dielectric layer 112c is located above the array region AR. The gate electrode layer 114 is located above the first dielectric layer 112 and above both the array region AR and the peripheral region PR of the substrate 100. Specifically, the gate electrode layer 114a is located above the peripheral region PR. In some embodiments, the gate electrode layer 114a may extend towards the array region AR above the portion of the first dielectric layer 112a with a smaller thickness; this disclosure is not limited thereto. The gate electrode layer 114b is located above both the array region AR and the peripheral region PR. The gate electrode layer 114c is located above the array region AR. The second dielectric layer 116 covers both the gate electrode layer 114 and the first dielectric layer 112. Specifically, the second dielectric layer 116a covers the gate electrode layer 114a and the first dielectric layer 112a, the second dielectric layer 116b covers the gate electrode layer 114b and the first dielectric layer 112b, and the second dielectric layer 116c covers the gate electrode layer 114c and the first dielectric layer 112c. The first dielectric layer 112c, the gate electrode layer 114c, and the second dielectric layer 116c can be used as the gate structure of the transistor TR in the array region AR, wherein the first dielectric layer 112c serves as the gate dielectric layer, and the second dielectric layer 116c serves as the inter-layer dielectric (ILD). In some embodiments, the first dielectric layer 112 and the second dielectric layer 116 may include dielectric materials such as silicon dioxide (SiO2), aluminum oxide (Al2O3), or other suitable materials. In some embodiments, the gate electrode layer 114 may include a polysilicon gate, a conductive metal, or other suitable materials.

[0021] It is worth noting that the transistor TR in the array region AR of the semiconductor element disclosed herein can be any transistor structure, and is not limited to the structure disclosed in the accompanying drawings.

[0022] like Figure 1 and Figure 2As shown, the semiconductor device 10 also includes a source pad 118, a gate pad 120, and a drain pad 122. The source pad 118 is located above the gate electrode layer 114 and the second dielectric layer 116 and extends from above the array region AR to above the peripheral region PR. The source pad 118 has a pad region SP and multiple extensions. For example, the pad region SP of the source pad 118 is a horizontal portion located above the second dielectric layer 116. Extensions 118a and 118b of the source pad 118 extend downward from the pad region SP through the second dielectric layer 116c, the gate electrode layer 114c, and the first dielectric layer 112c. In some embodiments, extension 118a is above the peripheral region PR and extends to contact the well 110. Extension 118a is located on the side of the gate electrode layer 114a near the array region AR and is located between the gate electrode layer 114a and the gate electrode layer 114b. In some embodiments, the extension portion 118b is above the array region AR and extends to contact the source doped region 106 and the body contact doped region 108, and is electrically connected to the source doped region 106. In some embodiments, the source pad 118 also has an extension portion 118c. The extension portion 118c is above the peripheral region PR, located on the side of the gate electrode layer 114 (such as gate electrode layer 114a) away from the array region AR, and extends downward from the pad region SP of the source pad 118 through the second dielectric layer 116 to contact the well 110. The gate pad 120 is located above the peripheral region PR and contacts the gate electrode layer 114 (such as gate electrode layer 114a). The drain pad 122 is located on the side of the substrate 100 away from the epitaxial layer 102.

[0023] Please refer to Figure 3 For clarity, Figure 3 Only the substrate 100, gate electrode layer 114, and source pad 118 of semiconductor device 10 are shown. The gate electrode layer 114 has a connected pad region GP and an annular portion GR above the peripheral region PR. The annular portion GR can also be called the gate bus. The source pad 118 is located above the gate electrode layer 114 and has an extending annular portion SR. (The remaining text appears to be unrelated and possibly machine-generated.) Figure 3 As shown, the source pad 118 partially covers and surrounds the pad region GP of the gate electrode layer 114, and is also partially surrounded by the annular portion GR. Furthermore, the annular portion SR of the source pad 118 further completely surrounds the gate electrode layer 114 therein.

[0024] Please refer to Figure 4 For clarity, Figure 4 The top view omits the pad region SP of the second dielectric layer 116 and the source pad 118 of the semiconductor element 10. (As shown...) Figure 4As shown, the gate electrode layer 114 has a plurality of openings arranged at intervals above the peripheral region PR and along the outer edge of the array region AR. Specifically, the gate electrode layer 114 has openings OP1 and OP1', and extensions 118a and 118a' of the source pad 118 extend into openings OP1 and OP1', respectively. Opening OP1 can have a rectangular top view profile. Consequently, the extensions 118a formed in opening OP1 can also have a rectangular top view profile. Since the openings of the gate electrode layer 114 are arranged along the outer edge of the array region AR, opening OP1' can have an L-shaped top view profile. Consequently, the extensions 118a' formed in opening OP1' can also have an L-shaped top view profile.

[0025] In addition, such as Figure 4 As shown, the strip-shaped portion between any two openings OP1 / OP1' of the gate electrode layer 114 connects the gate electrode layers 114b and 114c in the array region AR to the gate electrode layer 114a in the peripheral region PR. These strip-shaped portions can also be referred to as gate lines GL. Specifically, the gate line GL connects the gate electrode portion GE (including gate electrode layers 114b and 114c) located above the array region AR to the pad region GP and the annular portion GR (including gate electrode layer 114a) located above the peripheral region PR. Simultaneously, the gate line GL is located between two adjacent extension portions 118a / 118a'. In this way, the number, shape, and size of the gate lines GL can be controlled by adjusting the number, shape, and size of the openings OP1 / OP1', thereby adjusting the internal gate resistance of the semiconductor device 10 to improve device operational stability.

[0026] The gate electrode layer 114 has multiple openings OP2 above the array region AR, and the extension portion 118b of the source pad 118 extends into the openings OP2. It is worth noting that those skilled in the art can adjust the shapes of the openings OP1, OP2, extension portions 118a, and 118b to, for example, circular, square, triangular, hexagonal, octagonal, or irregular shapes, and may have rounded corners. Simultaneously, the openings OP2 in the array region AR can be arranged in a general array, an interlaced array, or a vertical and horizontal line arrangement. Furthermore, this disclosure is not intended to limit the number, size, or area of ​​the openings OP1, OP1', OP2, extension portions 118a, 118a', and 118b; those skilled in the art can adjust these according to requirements such as the internal resistance of the component to further improve switching stability.

[0027] By forming multiple openings in the gate electrode layer 114 above the peripheral region PR, the area of ​​the gate electrode layer 114 can be reduced, thereby reducing the overlap area between the gate electrode layer 114 and the first dielectric layer 112. This reduces the parasitic capacitance of the semiconductor device 10, thereby improving switching characteristics and enhancing forward conduction capability and switching stability. Furthermore, extending the source pad 118 into the openings increases the source contact area and reduces the source-drain voltage (V0). sd ).

[0028] In some embodiments, by positioning the extension of the source pad 118 within an opening above the peripheral region PR, the area of ​​the source contact is increased, thus allowing the peripheral portion of the source pad 118 to be removed (e.g., ...). Figure 1 , Figure 2 The extension portion 118c and Figure 3 The annular region SR corresponds to the region.

[0029] For example, please refer to Figure 5 and Figure 6 . Figure 5 A top view of a semiconductor element 10' according to other embodiments of this disclosure is shown. Figure 6 A partial cross-sectional view of semiconductor element 10' corresponding to line segment A-A' is shown. As shown, the difference between semiconductor element 10' and semiconductor element 10 is that semiconductor element 10' does not have a portion where the source pad 118 is located on the periphery. Specifically, as... Figure 5 As shown, semiconductor element 10' does not have the annular portion SR of the source pad 118 of semiconductor element 10. Meanwhile, as... Figure 6 As shown, semiconductor element 10' does not have the extension portion 118c of the source pad 118 of semiconductor element 10. In this way, the width of the peripheral region PR can be shortened, so that the outer edge dimension of semiconductor element 10' is smaller than the outer edge dimension of semiconductor element 10.

[0030] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to some embodiments of this disclosure. Figure 7 As shown, the manufacturing method includes steps S201 to S210. Next, it will be paired with... Figure 1 and Figure 4 Explain each step of the manufacturing process.

[0031] First, in step S201, an epitaxial layer 102 is formed over a substrate 100. The substrate 100 includes adjacent array regions AR and peripheral regions PR. In some embodiments, the substrate 100 and the epitaxial layer 102 have a first conductivity type (e.g., n-type). In step S202, wells 104 and 110 having a second conductivity type (e.g., p-type) are formed in the epitaxial layer 102. Wells 104 and 110 are separated from each other. Well 104 is located over the array region AR, while well 110 is located over the peripheral region PR. In some embodiments, the dopant of well 110 is substantially the same as that of well 104, and the dopant concentrations of both are also substantially the same. In step S203, a source doped region 106 and a body contact doped region 108 are formed in well 104. In some embodiments, the source doped region 106 has a first conductivity type (e.g., n-type), while the body contact doped region 108 has a second conductivity type (e.g., p-type). In some embodiments, the dopant of the well 110 is substantially the same as the dopant of the body contact doped region 108 and the dopant concentrations of the two are also substantially the same.

[0032] Next, in step S204, a first dielectric layer 112 is formed over the epitaxial layer 102 and over the array region AR and the peripheral region PR. In step S205, a conductive material is formed on the first dielectric layer 112 and over the array region AR and the peripheral region PR. In step S206, the conductive material is patterned to form a gate electrode layer 114 on the first dielectric layer 112. In some embodiments, the patterning causes the gate electrode layer 114 to have, for example, a... Figure 4 The openings OP1, OP1', and OP2 are shown. In step S207, a second dielectric layer 116 is formed to cover the gate electrode layer 114 and the first dielectric layer 112. In step S208, a hole TH is formed in the second dielectric layer 116 and the first dielectric layer 112. The hole TH is distributed above the peripheral region PR and the array region AR. The hole TH passes through the second dielectric layer 116, the gate electrode layer 114, and the first dielectric layer 112 and partially exposes the source doped region 106, the body contact doped region 108, and the top surface of the well 110.

[0033] Next, in step S209, source pad 118 and gate pad 120 are formed. Specifically, source pad 118 is formed above gate electrode layer 114 and multiple extension portions (e.g., conductive pillars) are formed to fill vias TH. For example, such as... Figure 1 The extension portions 118a, 118b, and 118c are shown. Finally, in step S210, the drain pad 122 is formed.

[0034] In summary, in some embodiments of the semiconductor device and its manufacturing method disclosed herein, by forming multiple openings in the gate electrode layer located above the peripheral region, the overlap area between the gate electrode layer and the underlying dielectric layer can be reduced. This reduces the parasitic capacitance of the formed device, thereby improving its switching characteristics and enhancing forward conduction capability and switching stability. Furthermore, extending the source pad into the aforementioned openings increases the source contact area and reduces the source-drain voltage.

[0035] The foregoing description is only intended to illustrate and describe exemplary embodiments of the present disclosure and is not intended to exhaustively describe or limit the precise form of the invention disclosed herein. The above teachings may be modified or varied.

[0036] The selected and illustrated embodiments are intended to explain the content of this disclosure and their practical application, thereby inspiring those skilled in the art to utilize this disclosure and various embodiments, and to make various modifications to suit a particular intended use. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure is defined by the appended claims, and not by the foregoing description and the exemplary embodiments described therein.

[0037] [Symbol Explanation]

[0038] 4: Box

[0039] 10,10': Semiconductor element

[0040] 100: Substrate

[0041] 102: Epitaxial layer

[0042] 104,110: Trap

[0043] 106: Source doped region

[0044] 108: Bulk contact doped region

[0045] 112, 112a, 112b, 112c: First dielectric layer

[0046] 114, 114a, 114b, 114c: Gate electrode layers

[0047] 116, 116a, 116b, 116c: Second dielectric layer

[0048] 118: Source terminal pad

[0049] 118a, 118a', 118b, 118c: Extensions

[0050] 120: Gate pad

[0051] 122: Drain pad

[0052] A-A',B-B': line segment

[0053] AR: Array Area

[0054] GP, SP: Pad Area

[0055] GL: Gate line

[0056] GR,SR: Annular region

[0057] GE: Gate electrode area

[0058] OP1, OP1', OP2: Opening

[0059] PR: Surrounding Area

[0060] S201, S202, S203, S204, S205, S206, S207, S208, S209, S210: Steps

[0061] TH: Kong

[0062] TR: Transistor.

Claims

1. A semiconductor element characterized by comprising: Include: The substrate includes adjacent array areas and peripheral areas; An epitaxial layer is located above the substrate; The well is located in the epitaxial layer; A dielectric layer is located above the epitaxial layer and above the array region and the peripheral region; A gate electrode layer is located above the dielectric layer and above the array region and the peripheral region, wherein the gate electrode layer has at least one opening located above the peripheral region; as well as A source pad is located above the gate electrode layer and extends from above the array region to above the peripheral region, and the source pad has at least one first extension portion extending downward through the at least one opening in the gate electrode layer to the well.

2. The semiconductor device according to claim 1, characterized in that, The source pad also has a second extension portion that extends downward into the array region.

3. The semiconductor device according to claim 1, characterized in that, In a top-down view, the at least one first extension has a rectangular top-down profile.

4. The semiconductor device according to claim 1, characterized in that, In a top-down view, the at least one first extension has an L-shaped top-down profile.

5. The semiconductor device according to claim 1, characterized in that, The top view of the at least one opening is rectangular or L-shaped.

6. The semiconductor device according to claim 1, characterized in that, The at least one opening of the gate electrode layer includes a plurality of openings, and the at least one first extension of the source pad includes a plurality of first extensions, wherein the plurality of first extensions extend downward to the well via corresponding openings.

7. The semiconductor element according to claim 6, characterized in that, The gate electrode layer further includes gate lines located between adjacent portions of the plurality of first extensions.

8. The semiconductor element according to claim 1, characterized in that, The gate electrode layer further includes a pad region, an annular portion, a plurality of gate lines, and a plurality of gate electrode portions, wherein the pad region is connected to the annular portion and is located above the peripheral region, the plurality of gate electrode portions are located above the array region, and the plurality of gate electrode portions are connected to the pad region and the annular portion through the plurality of gate lines.

9. A method for manufacturing a semiconductor device, characterized in that, Include: An epitaxial layer is formed on a substrate, wherein the substrate includes an adjacent array region and a peripheral region; A first well is formed in the epitaxial layer and above the peripheral region; A first dielectric layer is formed above the epitaxial layer and above the array region and the peripheral region; A gate electrode layer is formed on the first dielectric layer and above the array region and the peripheral region; An aperture is formed above the peripheral region, wherein the aperture passes through the gate electrode layer and the first dielectric layer and exposes the first well; as well as A source pad is formed above the gate electrode layer and contacts the first well through the hole.

10. The manufacturing method according to claim 9, characterized in that, Also includes: A second well is formed in the epitaxial layer and located above the array region, wherein the second well and the first well have a first conductivity type; and A source doped region is formed in the second well, wherein the source doped region has a second conductivity type different from the first conductivity type.

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