Terminal expansion structure of high-voltage power device and preparation method thereof

Abstract

The invention relates to the field of semiconductor devices, in particular to a terminal expansion structure of a high-voltage power device and a preparation method of the terminal expansion structure. The structure is arranged on the periphery of an active region and comprises a JTE region with an optimized doping concentration gradient and a plurality of field rings which are arranged on the periphery of the JTE region, are in a curve polygon shape and have gradually reduced occupied areas. The key point of the preparation method is that the doping concentration of the JTE region is stabilized by adopting multiple times of ion implantation. By combining the optimized JTE and field ring design, the technical problems that the traditional field ring terminal area is too large and the JTE electric field distribution is not uniform are cooperatively solved, the terminal area is remarkably reduced, the electric field distribution is uniform, and the local peak value and the field plate tail end electric field peak are avoided, so that the voltage resistance, the stability and the reliability of the terminal structure are greatly enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a terminal extension structure for a high-voltage power device and its fabrication method. Background Technology

[0002] High-voltage power devices require termination structures designed around their active regions to alleviate electric field congestion at the PN junction edges, enabling the devices to withstand high reverse voltages. Common termination techniques include field-limiting rings (FCRs) and junction extension regions (JTEs). FCRs extend the depletion region through a series of concentric ring-shaped doped regions, thereby reducing the peak electric field. However, traditional equal-width, equal-spacing FCR designs are inefficient, requiring a large chip area to achieve the desired breakdown voltage, resulting in low termination efficiency (i.e., breakdown voltage per unit area). JTEs smooth the electric field distribution through a low-concentration doped region. However, the uniformity of its electric field distribution is highly dependent on precise control of the implantation dose. Inappropriate doses can easily lead to localized electric field peaks within or at the end of the JTE, causing premature breakdown. Furthermore, JTE technology is highly sensitive to process fluctuations; even small dose deviations can cause a significant drop in breakdown voltage, resulting in poor stability and reliability. Therefore, existing technologies have two prominent drawbacks: first, the field-limiting ring termination area is too large; second, the JTE electric field distribution is uneven, leading to poor reliability. There is an urgent need for a new terminal structure that can solve the above problems simultaneously. Summary of the Invention

[0003] The purpose of this invention is to provide a termination structure for a power device and its fabrication method, to solve the problems of excessively large field ring termination area and uneven JTE electric field distribution easily forming local peaks in existing technologies. To achieve the above objective, this invention adopts the following technical solution: A termination structure for a power device, disposed around the active region, includes: a JTE region surrounding the active region, whose doping concentration gradient is adjusted and high stability is achieved through a specific implantation process to ensure uniform electric field distribution and avoid the occurrence of local peaks; multiple field rings located around the JTE region, whose shape is designed as irregular curved polygons (such as rounded rectangles or octagons), rather than simple circles. More importantly, the area occupied by these field rings (which can be understood as a combination of the ring width and circumference) decreases progressively from the inside out. This design can achieve efficient electric field expansion with fewer rings and a smaller total area.

[0004] Furthermore, the doping concentration gradient of the JTE region is optimized so that the local peak change of the surface electric field intensity in the depletion region under reverse bias does not exceed 15%.

[0005] Furthermore, the corners of the field ring of the curved polygon are rounded, and its radius of curvature is optimized to further smooth the electric field distribution.

[0006] Furthermore, the width of the field ring and the spacing between adjacent field rings both decrease progressively from the inside to the outside.

[0007] Furthermore, the ratio of the width of the field ring to the spacing between adjacent field rings remains constant throughout the terminal region. Furthermore, it also includes at least one isolation trench disposed on the outermost side of the plurality of field rings, the depth of which is greater than or equal to the junction depth of the outermost field ring.

[0008] Furthermore, the isolation trench is filled with a dielectric material to completely terminate the surface electric field.

[0009] A method for fabricating the terminal structure includes the following steps: providing a semiconductor substrate; An active region and a termination region are defined on the semiconductor substrate; The JTE region is formed by ion implantation, and a stable doping concentration distribution is achieved through multiple combinations of energy and dose implantation. Multiple field rings with optimized shapes and occupancy areas are formed through ion implantation. The key lies in the implantation process of the JTE region. A multi-implantation method is employed, for example, performing a primary implantation to establish a baseline concentration, followed by a lower-dose implantation to precisely adjust and stabilize the concentration gradient. Specifically, the dose of the second implantation is 1 / 2 to 1 / 5 of the dose of the first implantation, to precisely control the concentration gradient and thus significantly improve the process tolerance and stability of the dose.

[0010] Specifically, it also includes the steps of: after forming the field ring, forming an isolation trench on the outermost side of the terminal structure by etching, and filling the trench with a dielectric material.

[0011] Compared with the prior art, the present invention has the following significant advantages: 1. Small terminal area and high efficiency: By adopting an optimized field ring shape with progressively decreasing area, the total area of ​​the terminal structure is significantly reduced while ensuring voltage resistance, thus improving chip utilization.

[0012] 2. Uniform electric field distribution and high reliability: By optimizing the injection dose stability of JTE, the surface electric field distribution is made more uniform, which effectively avoids premature breakdown caused by local electric field peaks and enhances the stability and reliability of the device.

[0013] 3. Excellent withstand voltage performance: The synergistic effect of JTE and optimized field ring, combined with isolation trench, improves the overall withstand voltage level of the terminal structure and avoids electric field spikes at the end of the field plate.

[0014] 4. Large process tolerance: JTE's multiple injection method improves tolerance to process fluctuations, which is beneficial to improving production yield and consistency. Attached Figure Description

[0015] Figure 1 is a schematic planar view of the terminal structure according to an embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures: 1- Semiconductor substrate; 2- Active region; 3- JTE region; 4- Field ring (4a, 4b, 4c, with progressively decreasing display area and rounded corners); 5- Isolation trench. Detailed Implementation

[0017] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] Example 1: The terminal extension structure of the high-voltage power device includes a P-type doped JTE region 3; a pattern of multiple concentric field rings 4a, 4b, 4c; and an isolation trench 5. The shapes of these field rings 4a, 4b, 4c are designed as octagons with rounded corners (i.e., curved polygons), rather than simple circles or squares, to effectively smooth the electric field concentration at the corners.

[0019] Specifically, P-type field rings are formed via ion implantation (e.g., boron implantation). The width and spacing of the field rings are optimized: the innermost field ring 4a is designed to be 10 μm wide, with a spacing of 8 μm between it and the edge of JTE region 3. The middle field ring 4b is designed to be 7 μm wide, with a spacing of 5 μm between it and field ring 4a. The outermost field ring 4c is designed to be 4 μm wide, with a spacing of 3 μm between it and field ring 4b. This "gradually decreasing width and spacing" design significantly reduces the overall area occupied by the field ring group, achieving the withstand voltage level that traditional designs require five field rings with only three field rings, greatly improving terminal efficiency.

[0020] Example 2: This example details a specific fabrication method for the termination extension structure of the high-voltage power device described in this invention. This method is fully compatible with semiconductor planar processes, exhibiting high feasibility and good repeatability. The specific fabrication steps include: Step S101: Provide a semiconductor substrate. An N-type doped single-crystal silicon wafer is provided as semiconductor substrate 1. Before proceeding to subsequent steps, semiconductor substrate 1 is subjected to standard RCA cleaning to remove surface contaminants.

[0021] Step S102: Growing a field oxide layer and forming the JTE region 3. First, a silicon dioxide layer with a thickness of approximately 5000 Å to 10000 Å is grown on the surface of the semiconductor substrate 1 by a thermal oxidation process, which serves as a shielding layer and field oxide layer for subsequent ion implantation.

[0022] The first step of the photolithography process is photoresist coating and exposure: photoresist is coated onto the oxide layer, and exposure is performed through a mask to define the pattern window of JTE region 3. Development: After development, the photoresist in the window area is removed to expose the underlying silicon dioxide.

[0023] First ion implantation: Boron ion implantation was performed using photoresist as a mask. The implantation parameters were: dose 1.0 × 10⁻⁶. 13 cm -2 The energy is 100 keV. This step aims to form the basic doped profile of the JTE region.

[0024] Second ion implantation: Following this, a second boron ion implantation was performed to optimize doping stability. The implantation parameters were: dose 2.0 × 10⁻⁶. 12 cm -2 The energy is 60 keV. This injection allows for precise adjustment of the near-surface concentration gradient, widening the process window and ensuring a uniform electric field distribution.

[0025] Photoresist removal and advancement: After injection, the photoresist is thoroughly removed by ashing and wet chemical cleaning.

[0026] Subsequently, high-temperature annealing is performed at 1150°C for 30 minutes in an inert gas (such as nitrogen) environment to activate the injected impurity atoms and advance the junction depth to the target depth (such as 2-3 μm).

[0027] Step S103: Forming the optimized field ring shape. Perform the second photolithography process: apply new photoresist, expose and develop through another mask that defines the irregular curved polygonal field ring pattern (such as a rounded octagon). Perform a third boron ion implantation to form P-type field rings 4a, 4b, 4c. The implantation dose and energy must ensure that the junction depth and conductivity type of the field ring meet the design expectations. After implantation, remove the photoresist. The implantation annealing of the field ring can be performed simultaneously with the annealing of the JTE region, or it can be completed in the annealing of step S102 (if the field ring pattern is formed in one photolithography step with the JTE region), or it can be performed separately at a later time.

[0028] Step S104: Deposit a surface passivation layer. A passivation layer with a thickness of approximately 1 μm is deposited on the entire surface of the semiconductor substrate 1 using chemical vapor deposition. The passivation layer is made of phosphosilicate glass due to its excellent surface passivation and planarization effects.

[0029] Step S105: Forming the isolation trench 5. Perform the third photolithography process: apply photoresist, and expose and develop using a mask that defines the location of the annular isolation trench 5. The specific process includes using the photoresist as a mask to first etch through the passivation layer and field oxide layer using reactive ion etching; then, using a high aspect ratio silicon etching process based on SF6 and C4F8 gases, etching downwards into the semiconductor substrate 1 itself to form the isolation trench 5 with a depth of approximately 5 μm. This depth must be greater than the junction depth of the JTE region and the field ring. After etching, the photoresist is completely removed.

[0030] Step S106: Filling the isolation trench. Silicon dioxide is deposited in the isolation trench 5 using high-density plasma chemical vapor deposition (HDPCVD) to achieve complete filling. HDPCVD has excellent step coverage and filling capabilities, effectively preventing voids within the trench. After filling, excess silicon dioxide on the wafer surface can be removed using chemical mechanical polishing (CMP) to achieve surface planarization.

[0031] Step S107: Complete subsequent device manufacturing processes. Thereafter, standard subsequent processes for power device manufacturing are performed, including but not limited to: front-end metallization (such as deposition and patterning of aluminum or copper as electrodes), back-end thinning and back metal deposition, alloying, and final passivation layer opening and testing. These processes are well known to those skilled in the art and will not be described in detail here.

[0032] Example 3: Enhanced structure including isolation trench 5. This example adds isolation trench 5 to Example 2 to further improve terminal reliability. Formation of isolation trench 5: After forming field ring 4c, a layer of silicon nitride is deposited as a hard mask by plasma-enhanced chemical vapor deposition; photolithography defines the pattern of isolation trench 5 surrounding the outermost field ring 4c.

[0033] Specifically, an inductively coupled plasma etching process is used to etch the semiconductor substrate 1 on the outermost side of the terminal region, forming an annular isolation trench 5 with a depth of approximately 5 μm. This depth is greater than the junction depth of the JTE region 3 and the field ring 4 to ensure effective termination of the laterally expanding depletion region. A silicon dioxide layer of approximately 5000 Å is grown on the inner wall of the trench using a high-temperature thermal oxidation method as a passivation layer. Then, high-density plasma chemical vapor deposition is used to completely fill the trench with silicon dioxide dielectric material. Finally, a chemical mechanical polishing process is used to remove excess dielectric material from the surface to achieve planarization.

[0034] Example 4: A variant of the JTE region 3 implantation process. This example primarily demonstrates another feasible configuration of the JTE region 3 implantation process to illustrate the flexibility of the invention. The structure of this example is the same as that of Example 2 or 3, the only difference being the ion implantation step for forming the JTE region 3.

[0035] Specifically, the procedure also involves two boron ion implantations, but with the following parameter adjustments: First implantation: dose 1.2 × 10⁻⁶ 13 cm -2 The energy was 120 keV. Second injection: dose was 3.0 × 10⁻⁶. 12 cm -2 The energy is 80 keV. This parameter combination can also achieve a wide-window, highly stable doping concentration gradient. The key is the use of a combination of "high-energy main injection + lower-energy auxiliary injection" to precisely control the concentration distribution, avoid local peaks in the electric field, and thus obtain a smooth electric field distribution.

[0036] The electric field curve of this invention is smooth without obvious peaks; while the curve of a conventional JTE exhibits dangerous local peaks at certain locations, which is precisely the defect overcome by this invention. The terminal structures of Embodiments 1 and 2 of this invention were simulated using semiconductor device simulation software (such as SentaurusTCAD) and compared with conventional equal-spaced field ring spacing designs and single JTE designs. Simulation results show that, at the same breakdown voltage of 1200V, the total length of the terminal structure of this invention is shortened by approximately 40% compared to the conventional equal-spaced field ring design; compared to the single JTE structure, the electric field distribution curve of this invention is very smooth, with no obvious local electric field peaks in either the JTE region or the field ring region, and the breakdown point occurs stably within the bulk, demonstrating its excellent reliability and stability. The isolation trench added in Embodiment 2 further reduces the electric field peak at the outermost edge by approximately 20%, ensuring the long-term reliability of the terminal under harsh conditions. The above-described fabrication method enables the effective fabrication of a high-voltage power chip terminal structure. This terminal structure exhibits excellent voltage withstand performance and electrical isolation, while effectively mitigating the stress mismatch between the active region and the terminal region, thereby improving the chip's reliability and stability.

[0037] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A termination extension structure for a high-voltage power device, disposed around the active region on a semiconductor substrate, characterized in that, include: A JTE region surrounds the active region, the doping concentration of the JTE region being configured to make the surface electric field uniformly distributed; Multiple field rings are located outside the JTE region and are concentrically arranged therewith; wherein, the multiple field rings are irregular curved polygons, and the area occupied by the field rings decreases stepwise from the side closer to the JTE region to the side farther away.

2. The terminal extension structure of the high-voltage power device according to claim 1, characterized in that, The doping concentration gradient of the JTE region is optimized so that the local peak variation of the surface electric field intensity in the depletion region under reverse bias does not exceed 15%.

3. The terminal extension structure of the high-voltage power device according to claim 1, characterized in that, The corners of the field ring of the curved polygon are rounded, and its radius of curvature is optimized to further smooth the electric field distribution.

4. The terminal extension structure of the high-voltage power device according to claim 1, characterized in that, The width of the field ring and the spacing between adjacent field rings both decrease progressively from the inside to the outside.

5. The terminal extension structure of the high-voltage power device according to claim 4, characterized in that, The ratio of the width of the field ring to the spacing between adjacent field rings remains constant throughout the entire terminal extension structure.

6. The terminal extension structure of the high-voltage power device according to claim 1, characterized in that, It also includes at least one isolation trench disposed on the outermost side of the plurality of field rings, wherein the depth of the isolation trench is greater than or equal to the junction depth of the outermost field ring.

7. The terminal extension structure of the high-voltage power device according to claim 6, characterized in that, The isolation trench is filled with a dielectric material to completely terminate the surface electric field.

8. A method for preparing a termination extension structure for a high-voltage power device as described in any one of claims 1-7, characterized in that, Includes the following steps: Provide a semiconductor substrate; An active region and a termination region are defined on the semiconductor substrate; The JTE region is formed by ion implantation, and a stable doping concentration distribution is achieved through multiple combinations of energy and dose implantation. The terminal extension structure is obtained by forming multiple field rings with optimized shapes and occupies area through ion implantation.

9. The preparation method according to claim 8, characterized in that, In the step of forming the JTE region, at least two ion implantations with different doses are performed, and the dose of the second implantation is 1 / 2 to 1 / 5 of the dose of the first implantation, in order to precisely control the concentration gradient.

10. The preparation method according to claim 9, characterized in that, It also includes the steps of: after forming the field ring, forming an isolation trench on the outermost side of the terminal extension structure by etching, and filling the isolation trench with a dielectric material.

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