Manufacturing method of semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: providing a substrate including an element region and a scribe region; forming a first mask pattern on the element region of the substrate, and forming a spacer on a side surface of the first mask pattern; forming a mask film extending along the first mask pattern, the spacer, and the substrate, in which the mask film includes a step portion on the scribe line region of the substrate; forming a sacrificial pattern filling the step portion; forming a second mask pattern by etching the mask film to expose the first mask pattern and the spacer; removing the spacer and the sacrificial pattern; and forming a gate trench inside the substrate using the first mask pattern and the second mask pattern as etching masks.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device comprising a plurality of word lines buried in a substrate of a buried channel array transistor (BCAT). Background Technology

[0002] As the integration density of semiconductor components increases, the individual circuit patterns become more refined to accommodate more semiconductor components within the same area. For example, as the integration density of semiconductor components increases, the design rules associated with the components of the semiconductor components may decrease.

[0003] However, in highly scaled-down semiconductor devices, the process of forming multiple gate electrodes and contacts connected to these gate electrodes can become increasingly complex and difficult. Summary of the Invention

[0004] A method for manufacturing a semiconductor device is provided that protects the key pattern and improves the patterning defects of the gate trench.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented.

[0006] According to one aspect of this disclosure, a method for manufacturing a semiconductor device includes: providing a substrate including a component region and a scribing region; forming a first mask pattern on the component region of the substrate and forming spacers on the side surfaces of the first mask pattern; forming a mask film extending along the first mask pattern, the spacers, and the substrate, wherein the mask film includes a stepped portion on the scribing region of the substrate; forming a sacrificial pattern filling the stepped portion; forming a second mask pattern by etching the mask film to expose the first mask pattern and the spacers; removing the spacers and the sacrificial pattern; and forming a gate trench inside the substrate using the first mask pattern and the second mask pattern as an etching mask.

[0007] According to one aspect of this disclosure, a method for manufacturing a semiconductor device includes: providing a substrate including a scribing region, wherein the scribing region includes a first region and a second region; forming a first mask pattern on the first region of the substrate and forming spacers on the side surfaces of the first mask pattern; forming a mask film on the first mask pattern, the spacers, and the substrate, wherein the mask film includes a stepped portion on a second region of the substrate; forming a sacrificial pattern that fills the stepped portion; patterning the mask film to form a second mask pattern; removing the sacrificial pattern and the spacers; and forming a trench inside the substrate using the first mask pattern and the second mask pattern as an etching mask.

[0008] According to one aspect of this disclosure, a method for manufacturing a semiconductor device includes: providing a substrate including a device region and a bonding region; forming a first mask pattern on the device region of the substrate and forming spacers on the side surfaces of the first mask pattern; forming a mask film extending along the first mask pattern, the spacers, and the substrate, wherein the mask film includes stepped portions on the bonding regions of the substrate; forming a sacrificial film filling the stepped portions on the mask film; performing a planarization process on the sacrificial film and the mask film to form a sacrificial pattern; patterning the mask film to form a second mask pattern; removing the sacrificial pattern and the spacers; forming a third mask pattern on the bonding regions, wherein the third mask pattern exposes the device region; forming a gate trench inside the substrate using the first mask pattern, the second mask pattern, and the third mask pattern as etch masks; forming a gate insulating film along the gate trench; and forming a gate electrode layer and a gate cap layer on the gate insulating film. Attached Figure Description

[0009] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a diagram illustrating a substrate on which semiconductor devices are integrated, according to an embodiment;

[0011] Figure 2 According to the embodiments Figure 1 A magnified view of region R1;

[0012] Figure 3 According to the embodiments Figure 1 A magnified view of region R2;

[0013] Figure 4 According to the embodiments Figure 1 A magnified view of region R3;

[0014] Figure 5 It is according to the embodiment along Figure 4 A cross-sectional view taken from A-A';

[0015] Figure 6 It is according to the embodiment along Figure 4 A cross-sectional view taken at B-B';

[0016] Figure 7 It is according to the embodiment along Figure 4 A cross-sectional view taken at C-C';

[0017] Figures 8 to 22 These are diagrams used to explain a method for manufacturing a semiconductor device according to an embodiment; and

[0018] Figure 23This is a diagram used to explain a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0019] Figure 1 This is a diagram illustrating a substrate on which a semiconductor device according to an embodiment can be integrated.

[0020] Reference Figure 1 The substrate 100 may include the element region ER and scribing region SLR in which the semiconductor chips are respectively formed.

[0021] The substrate 100 may be at least one of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, and a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

[0022] According to an embodiment, the first direction D1, the second direction D2, and the third direction D3 can be directions parallel to the upper surface of the substrate 100. The first direction D1 can be orthogonal to the second direction D2. The third direction D3 can form an angle (e.g., any angle) with respect to the first direction D1 and the second direction D2. The fourth direction D4 can be orthogonal to the first direction D1, the second direction D2, and the third direction D3. The fourth direction D4 can be a direction perpendicular to the upper surface of the substrate 100.

[0023] Component areas ER can be arranged two-dimensionally along a first direction D1 and a second direction D2. Each component area ER can be surrounded by a scribing area SLR. For example, scribing areas SLR can be set between component areas ER that are adjacent to each other in the first direction D1, and between component areas ER that are adjacent to each other in the second direction D2. Scribing areas SLR can also be set around component areas ER. For example, scribing areas SLR can be around component areas ER and between each component area ER and adjacent component areas ER.

[0024] After the semiconductor process is completed, the scribing region SLR can be cut to separate the component region ER into each die. When the substrate 100 is cut into chips, the scribing region SLR can be partially or completely lost through cutting.

[0025] Figure 2 According to the embodiments Figure 1 A magnified view of region R1.

[0026] Reference Figure 2 In some embodiments, the scribing area SLR may include the key area KR and the dummy area DR.

[0027] The key area KR can be an area in which a key pattern KP is set. The key pattern KP can be at least one of an alignment key and an overlay key. The number and shape of the key patterns KP are not limited to... Figure 2 The example shown. The position and number of key regions (KR) in the scribbled SLR are not limited to... Figure 2 The example shown. A dummy area DR can be an area where a key pattern KP is not set. A dummy area DR can also be an area where a dummy pattern is set.

[0028] Figure 3 yes Figure 1 A magnified view of region R2. Figure 4 yes Figure 1 A magnified view of region R3. Figure 5 It is along Figure 4 A cross-sectional view taken from line A-A'. Figure 6 It is along Figure 4 A cross-sectional view taken from the B-B' line. Figure 7 It is along Figure 4 A cross-sectional view taken from the C-C' line.

[0029] Reference Figure 3 and Figure 4 In some embodiments, the component area ER may include a cell area CR and a peripheral area PR. The cell area CR may be an area in which storage cells are disposed. The peripheral area PR may be disposed around the cell area CR. The peripheral area PR may be disposed between the cell area CR and the scribing area SLR. At least one peripheral component PST may be disposed in the peripheral area PR. The location and number of peripheral components PST are not limited to these embodiments. Figure 3 and Figure 4 Example shown in the diagram.

[0030] The cell region CR may include multiple cell active regions ACT. The cell active regions ACT may be defined by a device isolation film 105 formed in the substrate 100. As the design specifications of semiconductor memory devices decrease, the cell active regions ACT may be configured as diagonal or oblique stripes, as shown. For example, the cell active regions ACT may extend in the third direction D3.

[0031] Multiple gate electrodes may extend across the cell active region ACT in the first direction D1. The multiple gate electrodes may extend parallel to each other. The multiple gate electrodes may be, for example, multiple word lines WL. The word lines WL may be arranged at equal intervals. The width of the word lines WL or the spacing between word lines WL may be determined according to design rules. Conductive lines included in the cell gate structure 110 may be word lines WL.

[0032] Each active cell region ACT can be divided into three parts by two word lines WL extending in a first direction D1. The active cell region ACT may include a bit line connection region and a memory connection region. The bit line connection region may be located in the central part of the active cell region ACT, and the memory connection region may be located at the end of the active cell region ACT.

[0033] Multiple bit lines BL extending in a second direction D2 orthogonal to the word line WL can be set on the word line WL. The multiple bit lines BL can extend parallel to each other. The bit lines BL can be set at equal intervals. At least one of the width of the bit line BL and the interval between the bit lines BL can be determined according to design rules.

[0034] Semiconductor memory devices according to some embodiments may include contact arrangements formed on cell active regions ACT. Contact arrangements may include, for example, direct contacts DC, buried contacts BC, and landing pads LP.

[0035] Here, direct contact DC can refer to the contact that electrically connects the cell active region ACT to the bit line BL. Buried contact BC can refer to the contact that connects the cell active region ACT to the lower electrode 191 of the data storage pattern 190. The contact area between the buried contact BC and the cell active region ACT may be small due to the layout structure. Therefore, conductive landing pads LP can be introduced to increase the contact area with the cell active region ACT and the contact area with the lower electrode 191.

[0036] The landing pad LP can be disposed between the cell active region ACT and the buried contact BC, or between the buried contact BC and the lower electrode 191. In a semiconductor memory device according to some embodiments, the landing pad LP can be disposed between the buried contact BC and the lower electrode of the data storage pattern 190. By introducing the landing pad LP to increase the contact area, the contact resistance between the cell active region ACT and the lower electrode of the capacitor can be reduced.

[0037] Direct contact DC can be connected to the bit line connection area. Buried contact BC can be connected to the memory connection area. Because the buried contact BC is located at both ends of the cell active area ACT, the landing pad LP can be configured to partially overlap with the buried contact BC to be adjacent to both ends of the cell active area ACT. For example, the buried contact BC can be formed to overlap with the cell active area ACT and the component isolation film 105 between the adjacent word line WL and the adjacent bit line BL.

[0038] The word line WL can be formed as a structure buried within the substrate 100. The word line WL can be positioned across the cell active region ACT between the direct contact DC and the buried contact BC. For example... Figure 3 and Figure 4 As shown, two word lines WL can be configured to intersect a cell active region ACT. When the cell active region ACT extends along the third direction D3, the word line WL can have an angle of less than 90 degrees with the cell active region ACT.

[0039] The direct contact DC and the buried contact BC can be arranged symmetrically. As a result, the direct contact DC and the buried contact BC can be arranged on a straight line along the first direction D1 and the second direction D2.

[0040] However, unlike the direct contact DC and buried contact BC, the landing pad LP can be arranged in a zigzag pattern in the second direction D2 of the bit line BL. Furthermore, the landing pad LP can be configured to overlap the same side portion of each bit line BL in the first direction D1 of the word line WL.

[0041] For example, each of the landing pads LP of the first line may overlap with the left side of the corresponding bit line BL, and each of the landing pads LP of the second line may overlap with the right side of the corresponding bit line BL.

[0042] According to an embodiment, a semiconductor memory device may include a cell active region ACT, a plurality of cell gate structures 110, a plurality of cell conductive lines 140, a plurality of memory pads 160, and a data storage pattern 190. In some embodiments, the semiconductor memory device may include a plurality of cell gate plugs.

[0043] Multiple cell gate structures 110, multiple bit line structures 140ST, multiple memory pads 160, and data storage patterns 190 can be set in the cell region CR.

[0044] The device isolation film 105 can be formed inside the substrate 100 of the cell region CR. The device isolation film 105 can have a shallow trench isolation (STI) structure, which has excellent device isolation characteristics.

[0045] The element isolation film 105 can define the active cell region ACT inside the cell region CR. The active cell region ACT defined by the element isolation film 105 can have an island shape including a short axis and a long axis.

[0046] The active cell region ACT can have a diagonal shape, with an angle of less than 90 degrees relative to the word line WL disposed in the element isolation film 105. The active cell region ACT can have a diagonal shape, with an angle of less than 90 degrees relative to the bit line BL formed on the element isolation film 105.

[0047] For example, the active cell region ACT may have a diagonal shape with an angle of less than 90 degrees relative to the cell gate structure 110 disposed inside the device isolation film 105. The active cell region ACT may have a diagonal shape with an angle of less than 90 degrees relative to the bit line structure 140ST formed on the device isolation film 105.

[0048] The component isolation film 105 may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon nitride film, but the embodiments are not limited thereto. Although an example of the component isolation film 105 being formed of an insulating film is shown, this is only for illustrative purposes, and the implementation is not limited thereto. Depending on the width of the component isolation film 105, the component isolation film 105 may be formed of one or more insulating films.

[0049] Although an example is shown where the upper surface of the element isolation film 105 and the upper surface of the substrate 100 are placed on the same plane, this is only for illustrative purposes and the embodiments are not limited thereto.

[0050] Multiple cell gate structures 110 may be disposed within the cell region CR. Each cell gate structure 110 may be formed within the substrate 100 and the device isolation film 105. The cell gate structure 110 may be formed across the device isolation film 105 and the cell active region ACT defined by the device isolation film 105.

[0051] The cell gate structure 110 may include a cell gate trench 115, a cell gate insulating film 111, a cell gate electrode 112, a cell gate cap pattern 113, and a cell gate cap conductive film 114 disposed within the substrate 100 and the element isolation film 105. Here, the cell gate electrode 112 may correspond to a word line WL. In some embodiments, the cell gate structure 110 may not include the cell gate cap conductive film 114.

[0052] The cell gate trench 115 can be relatively deep within the device isolation film 105 and relatively shallow within the cell active region ACT. The bottom surface of the cell gate electrode 112 can be curved. For example, the depth of the cell gate trench 115 inside the device isolation film 105 can be greater than the depth of the cell gate trench 115 in the cell active region ACT.

[0053] The cell gate insulating film 111 may extend along the sidewalls and bottom surface of the cell gate trench 115. The cell gate insulating film 111 may extend along at least a portion of the contour of the cell gate trench 115. The cell gate insulating film 111 may include at least one of, for example, silicon oxide, silicon nitride, silicon nitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0054] A cell gate electrode 112 may be disposed on a cell gate insulating film 111. The cell gate electrode 112 may fill a portion of a cell gate trench 115. A cell gate cap conductive film 114 may extend along the upper surface of the cell gate electrode 112. In semiconductor memory devices according to some embodiments, the cell gate cap conductive film 114 may cover the entire upper surface of the cell gate electrode 112, but the embodiments are not limited thereto.

[0055] The unit gate electrode 112 may include a conductive material, such as at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy. The unit gate cap conductive film 114 may include, for example, polysilicon or polysilicon-germanium, but the embodiments are not limited thereto.

[0056] A cell gate cap pattern 113 may be disposed on the cell gate electrode 112 and the cell gate cap conductive film 114. The cell gate cap pattern 113 may fill the cell gate trench 115 retained after the cell gate electrode 112 and the cell gate cap conductive film 114 are formed. Although an example is illustrated where the cell gate insulating film 111 extends along the sidewall of the cell gate cap pattern 113, the implementation is not limited thereto.

[0057] The cell gate cover pattern 113 may include at least one of, for example, silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxy carbon nitride (SiOCN), and combinations thereof.

[0058] In some embodiments, an impurity-doped region may be formed on at least one side of the cell gate structure 110. The impurity-doped region may be the source / drain region of a transistor. The impurity-doped region may be formed in the memory connection region and the bit line connection region.

[0059] The bit line structure 140ST may include a unit conductive line 140 and a unit line cover film 144. The unit conductive line 140 may be disposed on a substrate 100 on which a unit gate structure 110 is disposed and on a device isolation film 105.

[0060] The unit conductive line 140 may extend in the second direction D2. The unit conductive line 140 may intersect with the element isolation film 105 and the unit active region ACT defined by the element isolation film 105. Here, the unit conductive line 140 may correspond to the bit line BL.

[0061] The unit conductive line 140 can be a multilayer film. The unit conductive line 140 may include, for example, a first unit conductive film 141, a second unit conductive film 142, and a third unit conductive film 143. The first to third unit conductive films 141, 142, and 143 may be sequentially stacked on the substrate 100 and the element isolation film 105. Although an example in which the unit conductive line 140 is a triple film is illustrated, the embodiments are not limited thereto.

[0062] Each of the first to third conductive films 141, 142, and 143 may include at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, a metal, and a metal alloy. In a semiconductor memory device according to some embodiments, the 2D material may be at least one of a metallic material and a semiconductor material. The 2D material may comprise a 2D allotrope or a 2D compound, and may comprise at least one of, for example, graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). The 2D materials discussed above are listed by way of example only, and the embodiments are not limited thereto.

[0063] A cell line capping film 144 may be disposed on the cell conductive line 140. The cell line capping film 144 may extend along the upper surface of the cell conductive line 140 in a second direction D2. The cell line capping film 144 may include at least one selected from, for example, a silicon nitride film, a silicon oxide nitride, a silicon carbon nitride, and a silicon oxycarbon nitride. In semiconductor memory devices according to some embodiments, the cell line capping film 144 may include a silicon nitride film. Although an example in which the cell line capping film 144 is a single film is illustrated, the embodiments are not limited thereto.

[0064] Bit line contact 146 may be disposed between unit conductive line 140 and substrate 100. For example, unit conductive line 140 may be disposed on bit line contact 146. For example, bit line contact 146 may be disposed at the point where unit conductive line 140 intersects with the central portion of unit active region ACT having an island shape. Bit line contact 146 may be disposed between bit line connection region of unit active region ACT and unit conductive line 140. Bit line contact 146 may be connected to bit line connection region.

[0065] Multiple bit line contacts 146 can be arranged along the second direction D2. Each unit conductive line 140 can be arranged on the multiple bit line contacts 146 and extend along the second direction D2.

[0066] Bit line contact 146 can electrically connect unit conductive line 140 to substrate 100. Here, bit line contact 146 can correspond to direct contact DC. Bit line contact 146 can include at least one of, for example, doped semiconductor material, conductive silicide compound, conductive metal nitride, and metal.

[0067] In the region overlapping with the upper surface of the bit line contact 146, the unit conductive line 140 may include a second unit conductive film 142 and a third unit conductive film 143. In the region not overlapping with the upper surface of the bit line contact 146, the unit conductive line 140 may include a first unit conductive film to a third unit conductive film 141, 142 and 143.

[0068] The cell insulating film 130 may be disposed on the substrate 100 and the device isolation film 105. For example, the cell insulating film 130 may be disposed on the substrate 100 and the device isolation film 105 on which the bit line contacts 146 are not formed. The cell insulating film 130 may be disposed between the substrate 100 and the cell conductive line 140, and between the device isolation film 105 and the cell conductive line 140. In a semiconductor memory device according to some embodiments, the upper surface of the bit line contact 146 may be higher than the upper surface of the cell insulating film 130, based on the upper surface of the substrate 100.

[0069] Although the illustration shows a multilayer film comprising a first unit insulating film 131 and a second unit insulating film 132 as an example, the implementation is not limited thereto, and in some embodiments, the unit insulating film 130 may be a single film. For example, the first unit insulating film 131 may comprise a silicon oxide film, and the second unit insulating film 132 may comprise a silicon nitride film, but the embodiments are not limited thereto. In some embodiments, the unit insulating film 130 may comprise three or more insulating films. If the unit insulating film 130 includes a third unit insulating film, the third unit insulating film may be a silicon oxide film.

[0070] The unit line spacer 150 can be disposed on the sidewalls of the unit conductive line 140 and the unit line cover film 144. In the portion of the unit conductive line 140 where the bit line contact 146 is formed, the unit line spacer 150 can be formed on the substrate 100 and the element isolation film 105. The unit line spacer 150 can be disposed on the sidewalls of the unit conductive line 140, the sidewalls of the unit line cover film 144, and the sidewalls of the bit line contact 146.

[0071] In the remaining portion of the unit conductive line 140 where the bit line contact 146 is not formed, a unit line spacer 150 may be disposed on the unit insulating film 130. The unit line spacer 150 may be disposed on the sidewall of the unit conductive line 140 and the sidewall of the unit line cover film 144.

[0072] Although the illustration shows an example where the unit line spacer 150 is a single film, this is for illustrative purposes only, and the embodiments are not limited thereto. For example, in some embodiments, the unit line spacer 150 may have a multilayer film structure. The unit line spacer 150 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxide nitride film (SiON), a silicon oxide carbon nitride film (SiOCN), air, and combinations thereof, but the embodiments are not limited thereto.

[0073] The gate pattern 170 can be disposed on the substrate 100 and the device isolation film 105. The gate pattern 170 can be disposed to overlap with the cell gate structure 110 and the device isolation film 105 formed inside the substrate 100. The gate pattern 170 can be disposed on the cell gate cap pattern 113.

[0074] The fence pattern 170 may be disposed between the bit line structures 140ST extending along the second direction D2. The fence pattern 170 may include at least one of, for example, silicon oxide, silicon nitride, silicon nitride, and combinations thereof.

[0075] Multiple storage contacts 120 may be disposed between adjacent cell conductive lines 140 in the first direction D1. Storage contacts 120 may be disposed between adjacent fence patterns 170 in the second direction D2. Storage contacts 120 may overlap with the substrate 100 and the element isolation film 105 between adjacent cell conductive lines 140 in the fourth direction D4. Storage contacts 120 may be connected to the storage connection region of the cell active region ACT. Here, storage contacts 120 may correspond to buried contacts BC.

[0076] Storage contact 120 may include, for example, at least one of impurity-doped semiconductor material, conductive silicide compound, conductive metal nitride, and metal.

[0077] Storage pads 160 can be provided on each storage contact 120. Storage pads 160 can be electrically connected to storage contacts 120. Storage pads 160 can be connected to the storage connection area of ​​the cell active area ACT. Here, storage pads 160 can correspond to landing pads LP.

[0078] The storage pad 160 may overlap a portion of the upper surface of the unit conductive line 140. The storage pad 160 may include at least one of, for example, an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0079] A pad isolation insulating film 180 can be disposed on the storage pads 160 and the unit conductive lines 140. For example, the pad isolation insulating film 180 can be disposed on the unit line cover film 144. The pad isolation insulating film 180 can define the storage pads 160 forming multiple isolation zones. The pad isolation insulating film 180 may not cover the upper surface of the storage pads 160. The pad isolation insulating film 180 can fill the pad isolation recesses. The pad isolation recesses can isolate adjacent storage pads 160.

[0080] The pad isolation insulating film 180 may include an insulating material and may electrically isolate the storage pads 160 from each other. For example, the pad isolation insulating film 180 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, a silicon oxycarbon nitride film, and a silicon carbon nitride film, but the embodiments are not limited thereto.

[0081] An upper etch stop film 295 may be disposed on the upper surface of the storage pad 160 and the upper surface of the pad isolation insulating film 180. The upper etch stop film 295 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), silicon carbon oxide (SiOC), and silicon boron nitride (SiBN).

[0082] Data storage pattern 190 can be disposed on storage pad 160. Data storage pattern 190 is connected to storage pad 160. A portion of data storage pattern 190 can be disposed inside upper etch stop film 295.

[0083] As an example, the data storage pattern 190 may be a capacitor. The data storage pattern 190 may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. For example, the upper electrode 193 may be a plate-shaped upper electrode.

[0084] A lower electrode 191 may be disposed on a storage pad 160. The lower electrode 191 may have, for example, a cylindrical shape. A capacitor dielectric film 192 may be disposed on the lower electrode 191. The capacitor dielectric film 192 may be formed along the contour of the lower electrode 191. An upper electrode 193 may be disposed on the capacitor dielectric film 192. The upper electrode 193 may cover the outer wall of the lower electrode 191, but the embodiment is not limited thereto. Although an example of the upper electrode 193 being a single film is illustrated, this is only for illustrative purposes, and the embodiment is not limited thereto. For example, in some embodiments, the lower electrode 191 may have a cylindrical shape with an opening on one side.

[0085] Each of the lower electrode 191 and the upper electrode 193 may include at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide), but the embodiments are not limited thereto.

[0086] The capacitor dielectric film 192 may include, for example, one of silicon oxide, silicon nitride, silicon oxide nitride, high dielectric constant materials, and combinations thereof, but the embodiments are not limited thereto. In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 may include a dielectric film containing hafnium (Hf). In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 may have a laminated film structure having a ferroelectric material film and a paraelectric material film.

[0087] Conversely, the data storage pattern 190 can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern 190 may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material, wherein the crystallization state changes according to the amount of current.

[0088] Figures 8 to 22 These are diagrams used to explain methods for manufacturing semiconductor devices according to some embodiments. For reference, Figure 8 yes Figure 2 A magnified view of region R1, and Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 and Figure 22 It is along Figure 8 The cross-sectional view taken by line D-D'.

[0089] refer to Figures 8 to 10 A substrate 100 may be provided. The substrate 100 may include a component region ER and a scribing region SLR. The component region ER includes a cell region CR and a peripheral region PR. The scribing region SLR includes a bond region KR and a dummy region DR.

[0090] A dummy region DR may include a first dummy region DR1 and a second dummy region DR2. For example, a key region KR may be located between the first dummy region DR1 and the second dummy region DR2. The position and number of each of the first dummy region DR1 and the second dummy region DR2 are not limited to the examples shown in the accompanying drawings.

[0091] The bond pattern KP can be formed on the bond region KR of the substrate 100.

[0092] The device isolation film 105 can be formed inside the cell region CR of the substrate 100. The device isolation film 105 can define the cell active region ACT. The device isolation film 105 can be formed inside the dummy region DR of the substrate 100. The device isolation film 105 can be formed inside the bond region KR of the substrate 100.

[0093] The oxide layer 210, the mask layer 220, and the etch stop layer 230 may be sequentially formed on the cell region CR and the scribing region SLR of the substrate 100.

[0094] The oxide layer 210 may include oxides such as silicon oxide, but the embodiments are not limited thereto. The mask layer 220 may include carbon-based materials, but the embodiments are not limited thereto. For example, the mask layer 220 may include a spin-on hard mask (SOH), but the embodiments are not limited thereto. For example, the etch stop layer 230 may include a nitride, but the embodiments are not limited thereto. For example, the etch stop layer 230 may include SiON, but the embodiments are not limited thereto.

[0095] A first mask pattern 240 can be formed on the etch stop layer 230 of the cell region CR, the first dummy region DR1, and the second dummy region DR2. The first mask pattern 240 may not be formed on the bond region KR to protect the bond pattern KP. The first mask pattern 240 may extend, for example, in the first direction D1.

[0096] Spacers 250 may be formed on the first mask pattern 240. Spacers 250 may be formed on the side of the first mask pattern 240.

[0097] For example, preliminary spacers can be conformally formed along the first mask pattern 240 and the etch stop layer 230. An atomic layer deposition (ALD) process can be used to form the preliminary spacers. After the preliminary spacers are formed, the preliminary spacers on the upper surface of the first mask pattern 240 and the upper surface of the etch stop layer 230 can be removed by an etch-back process. Therefore, spacers 250 can be formed on the side surface of the first mask pattern 240.

[0098] The first mask pattern 240 may include, for example, polysilicon. The spacer 250 may include, for example, oxide.

[0099] Reference Figure 11 and Figure 12A mask film 260 can be formed on the etch stop layer 230. The mask film 260 can cover the etch stop layer 230, the first mask pattern 240, and the spacers 250, but the embodiments are not limited thereto. The mask film 260 can fill the gaps between the spacers 250. The mask film 260 can be formed on the cell region CR, the bond region KR, and the dummy region DR.

[0100] The mask 260 includes a stepped portion ST. The stepped portion ST can be formed by the width between adjacent first mask patterns 240. The stepped portion ST can be formed on the bond region KR.

[0101] For example, the height H of the stepped portion ST can be 400 angstroms (Å). For example, the bottom surface ST_BS of the stepped portion ST can be located above the upper surface 240_US of the first mask pattern 240. In one embodiment, the lowest surface of the stepped portion ST (e.g., the bottom surface ST_BS of the stepped portion ST) can be above the highest surface of the first mask pattern 240 (e.g., the upper surface 240_US of the first mask pattern 240).

[0102] The mask 260 may include, for example, polycrystalline silicon.

[0103] Reference Figure 13 and Figure 14 A sacrificial film 270 can be formed to fill the stepped portion ST and cover the mask film 260. The sacrificial film 270 can be formed on the cell region CR, the bond region KR, and the dummy region DR. The sacrificial film 270 on the stepped portion ST may include a portion recessed toward the substrate 100. The recess may be caused by the shape of the stepped portion ST.

[0104] The sacrificial membrane 270 may also include an insulating material. For example, the sacrificial membrane 270 may include oxides or nitrides, such as TEOS. In some embodiments, the sacrificial membrane 270 may be a single membrane. In some embodiments, the sacrificial membrane 270 may be a multilayer membrane.

[0105] Reference Figure 15 and Figure 16 A planarization process can be performed on the mask film 260 and the sacrificial film 270. For example, a chemical mechanical polishing (CMP) process can be performed on the mask film 260 and the sacrificial film 270. As a result, at least a portion of the sacrificial film 270 can be removed. A planarization process can be performed on the sacrificial film 270 to form a sacrificial pattern 272. The sacrificial pattern 272 may not be formed in the remaining area except for the stepped portion ST. At this time, at least a portion of the mask film 260 can also be removed. The upper surface of the mask film 260 may be substantially coplanar with the upper surface of the sacrificial pattern 272.

[0106] Process conditions associated with planarization may include, for example, the type of slurry, the slurry supply flow rate, the polishing pressure, and the rotation speed.

[0107] The paste can be selective. Selectivity can be the ratio of the amount of a particular film removed when a planarization process is performed using the paste. For example, the paste can be a composition that polishes a sacrificial film 270 made of an insulating material to a relatively large extent and a mask film 260 made of polycrystalline silicon to a relatively small extent. For example, the selectivity of the paste composition for the insulating film to the polycrystalline silicon film can be a ratio of about 2:1 or greater.

[0108] The slurry supply flow rate can refer to the amount of slurry required for the planarization process. For example, the slurry can be sprayed through a supply nozzle. The flow rate of the slurry sprayed through the supply nozzle can be selected according to the purpose. For example, the slurry supply flow rate can be from about 50 ml / min to about 1000 ml / min, but the embodiments are not limited to this.

[0109] Polishing pressure can refer to the pressure applied when bringing the polishing head into contact with the semiconductor substrate. The polishing pressure can be selected depending on the purpose of polishing. For example, the polishing pressure can be from about 0.3 pounds per square inch (psi) to about 7 psi, but the examples are not limited to this.

[0110] Rotational speed can refer to the speed at which the semiconductor substrate and the polishing head rotate while in contact with each other. According to embodiments, the rotation directions of the semiconductor substrate and the polishing head can be the same or opposite directions. The rotational speed of the polishing head can be selected according to the purpose. For example, the rotational speed can be from about 10 revolutions per minute (rpm) to about 140 rpm, but embodiments are not limited to this.

[0111] The upper surface of the mask film 260 on the cell region CR may have a stepped shape due to the first mask pattern 240. The upper surface of the mask film 260 may be uneven along the first mask pattern 240. This may result in patterning defects in the cell gate trench 115 that can be formed later. However, in a method for manufacturing a semiconductor device according to some embodiments, planarization may be performed on the mask film 260. Therefore, the patterning defects in the cell gate trench 115 may be improved, for example, by reduction or elimination.

[0112] refer to Figures 15 to 18 It can form a second mask pattern 262 and remove spacers 250 and sacrificial pattern 272.

[0113] For example, the mask film 260 can be patterned to form a second mask pattern 262. The second mask pattern 262 can be extended in the first direction D1. The second mask pattern 262 can be formed, for example, by a trimming process.

[0114] If the sacrificial pattern 272 is not formed, the mask 260 of the bond region KR may also be patterned during the patterning of the mask 260 due to the step portion ST of the mask 260. The bond pattern KP may also be etched together, and the bond pattern KP may be damaged. However, because the step portion ST can be filled with the sacrificial pattern 272 in the method for manufacturing a semiconductor device according to some embodiments, damage to the bond pattern KP can be prevented. Therefore, a semiconductor device with improved patterning defects and / or yield can be formed.

[0115] Next, a third mask pattern 280 can be formed covering the second dummy region DR2. The third mask pattern 280 can fill the gap between the first mask pattern 240 and the second mask pattern 262 of the second dummy region DR2. The third mask pattern 280 can cover both the first mask pattern 240 and the second mask pattern 262 of the second dummy region DR2, but the embodiment is not limited thereto. The third mask pattern 280 can extend to a portion of the key region KR.

[0116] Reference Figure 19 and Figure 20 The cell gate trench 115 and the dummy gate trench 215 can be formed using the first mask pattern 240 and the second mask pattern 262 as etching masks. The cell gate trench 115 can be formed by etching the etch stop layer 230, the mask layer 220, the oxide layer 210, and a portion of the substrate 100 of the cell region CR. The dummy gate trench 215 can be formed by etching the etch stop layer 230, the mask layer 220, the oxide layer 210, and a portion of the substrate 100 of the first dummy region DR1. The cell gate trench 115 and the dummy gate trench 215 can be formed using the same process.

[0117] Because of the third mask pattern 280, the dummy gate trench 215 may not be formed in the first dummy region DR1. For example, the first dummy region DR1 may be a region patterned in a manner similar to the cell region CR, and the second dummy region DR2 may be a region not patterned in a manner similar to the cell region CR.

[0118] Next, the first mask pattern 240, the second mask pattern 262, and the third mask pattern 280 can be removed.

[0119] Reference Figure 21 and Figure 22The unit gate insulating film 111, unit gate electrode 112, unit gate cap pattern 113, and unit gate cap conductive film 114 can be formed inside the unit gate trench 115. The dummy gate insulating film 211, dummy gate electrode 212, dummy gate cap pattern 213, and dummy gate cap conductive film 214 can also be formed inside the dummy gate trench 215. Each of the dummy gate insulating film 211, dummy gate electrode 212, dummy gate cap pattern 213, and dummy gate cap conductive film 214 can be formed using the same process as each of the unit gate insulating film 111, unit gate electrode 112, unit gate cap pattern 113, and unit gate cap conductive film 114. Each of the dummy gate insulating film 211, dummy gate electrode 212, dummy gate cap pattern 213, and dummy gate cap conductive film 214 may include the same material as each of the unit gate insulating film 111, unit gate electrode 112, unit gate cap pattern 113, and unit gate cap conductive film 114.

[0120] Reference Figures 3 to 7 It can form a unit insulating film 130, a bit line contact 146, a bit line structure 140ST, a storage pad 160, a fence pattern 170, a pad isolation insulating film 180, an upper etch stop film 295, and a data storage pattern 190.

[0121] Figure 23 These are diagrams used to explain methods for manufacturing semiconductor devices according to some embodiments. For reference, Figure 23 It is along Figure 8 The cross-sectional view taken from D-D', and is Figure 10 The following image.

[0122] refer to Figure 23 In some embodiments, the bottom surface ST_BS of the stepped portion ST may be located above the upper surface 240_US of the first mask pattern 240. In another embodiment, the lowermost surface of the stepped portion ST (e.g., the bottom surface ST_BS of the stepped portion ST) may be lower than the uppermost surface of the first mask pattern 240 (e.g., the upper surface 240_US of the first mask pattern 240). Next, references can be implemented. Figures 13 to 22 The manufacturing method described.

[0123] This disclosure is not limited to the specific embodiments described above, and can be made in various different forms. Those skilled in the art will understand that this disclosure can be embodied in other specific forms without altering the technical spirit or essential features of the disclosure. Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive.

[0124] Cross-references to related applications

[0125] This application is based on and claims priority to Korean Patent Application No. 10-2024-0137314, filed on October 10, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Provide a substrate including component areas and scribing areas; A first mask pattern is formed on the element region of the substrate, and spacers are formed on the side of the first mask pattern; A mask film is formed, the mask film extending along the first mask pattern, the spacer and the substrate, wherein the mask film includes a stepped portion on the scribing area of ​​the substrate; A sacrificial pattern is formed to fill the stepped portion; The second mask pattern is formed by etching the mask film to expose the first mask pattern and the spacer; Remove the spacers and the sacrificial pattern; and The first mask pattern and the second mask pattern are used as etching masks to form gate trenches inside the substrate.

2. The method according to claim 1, The sacrificial pattern mentioned above includes insulating material.

3. The method according to claim 1, The sacrifice pattern includes a first membrane and a second membrane that is different from the first membrane.

4. The method according to claim 1, wherein, The scribing area includes a key area and a dummy area, and The stepped portion is formed on the key region.

5. The method according to claim 1, wherein, The formation of the sacrificial pattern includes: A sacrificial film is formed on the mask film, wherein the sacrificial film fills the stepped portion, and A planarization process is performed on the mask film and the sacrificial film to form the sacrificial pattern.

6. The method according to claim 1, further comprising: A gate electrode is formed inside the gate trench.

7. The method of claim 1, wherein the lowermost surface of the stepped portion is above the uppermost surface of the first mask pattern.

8. The method of claim 1, wherein the lowermost surface of the stepped portion is lower than the uppermost surface of the first mask pattern.

9. A method for manufacturing a semiconductor device, the method comprising: A substrate is provided that includes a scribing region, wherein the scribing region includes a first region and a second region; A first mask pattern is formed on the first region of the substrate, and spacers are formed on the side of the first mask pattern; A mask film is formed on the first mask pattern, the spacer, and the substrate, wherein the mask film includes a stepped portion on the second region of the substrate; A sacrificial pattern is formed to fill the stepped portion; Pattern the mask film to form a second mask pattern; Remove the sacrificial pattern and the spacers; and The first mask pattern and the second mask pattern are used as etching masks to form trenches inside the substrate.

10. The method according to claim 9, wherein, The formation of the sacrificial pattern includes: A sacrificial film is formed on the mask film, wherein the sacrificial film fills the stepped portion, and A planarization process is performed on the mask film and the sacrificial film to form the sacrificial pattern. The sacrificial film is selective for the mask film during the planarization process.

11. The method of claim 9, further comprising: A bond pattern is formed on the second region of the substrate.

12. The method according to claim 9, The scribed area also includes a third area, and The method further includes forming the first mask pattern and the spacer on the third region of the substrate.

13. The method of claim 12, further comprising: After the spacer is removed, a third mask pattern is formed on the third region, wherein the third mask pattern exposes the first region.

14. The method of claim 9, further comprising: A gate electrode is formed inside the trench.

15. The method according to claim 9, wherein, The sacrificial pattern comprises a material different from the mask film.

16. The method according to claim 9, wherein, The sacrificial pattern includes insulating material.

17. A method for manufacturing a semiconductor device, the method comprising: Provide a substrate including component regions and bond regions; A first mask pattern is formed on the element region of the substrate, and spacers are formed on the side of the first mask pattern; A mask film is formed, the mask film extending along the first mask pattern, the spacer and the substrate, wherein the mask film includes a stepped portion on the bond region of the substrate; A sacrificial film filling the stepped portion is formed on the mask film; A planarization process is performed on the sacrificial film and the mask film to form a sacrificial pattern; Pattern the mask film to form a second mask pattern; Remove the sacrificial pattern and the spacers; A third mask pattern is formed on the key area, wherein the third mask pattern exposes the component area; The first mask pattern, the second mask pattern, and the third mask pattern are used as etching masks to form gate trenches inside the substrate; A gate insulating film is formed along the gate trench; and A gate electrode layer and a gate cap layer are formed on the gate insulating film.

18. The method according to claim 17, The mask film mentioned above comprises polycrystalline silicon.

19. The method according to claim 17, The sacrificial membrane comprises an oxide.

20. The method according to claim 17, The sacrificial film is selective relative to the mask film in the planarization process.

Images