Semiconductor structure and forming method thereof

Abstract

The method includes forming a first semiconductor layer and a second semiconductor layer overlapping the first semiconductor layer. The second semiconductor layer is spaced apart from the first semiconductor layer by a dielectric isolation layer. The method further includes performing a first epitaxial process to form a lower source / drain region alongside the first semiconductor layer, forming a dummy contact etch stop layer over the lower source / drain region, forming a dummy interlayer dielectric over the dummy contact etch stop layer, and forming a second semiconductor layer over the dummy interlayer dielectric. And performing a second epitaxial process to form an upper source / drain region aside the second semiconductor layer, the upper source / drain region over the dummy interlayer dielectric. The dummy interlayer dielectric and the dummy contact etch stop layer are removed to form a gap between the upper source / drain region and the lower source / drain region. A dielectric region is formed to fill the gap. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements on the material layers.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] One embodiment of this application provides a method for forming a semiconductor structure, comprising: forming a first semiconductor layer and a second semiconductor layer overlapping the first semiconductor layer, wherein the second semiconductor layer is spaced apart from the first semiconductor layer by a dielectric isolation layer; performing a first epitaxial process to form a lower source / drain region next to the first semiconductor layer; forming a pseudo-contact etch stop layer above the lower source / drain region; forming a pseudo-interlayer dielectric above the pseudo-contact etch stop layer; performing a second epitaxial process to form an upper source / drain region next to the second semiconductor layer, wherein the upper source / drain region is located above the pseudo-interlayer dielectric; removing the pseudo-interlayer dielectric and the pseudo-contact etch stop layer to form a gap between the upper source / drain region and the lower source / drain region; and forming a dielectric region to fill the gap.

[0005] Another aspect of this application provides a method for forming a semiconductor structure, comprising: forming a lower source / drain region adjacent to a first semiconductor layer; forming a dummy region above the lower source / drain region; forming an upper source / drain region adjacent to a second semiconductor layer, wherein the second semiconductor layer overlaps with and is spaced apart from the first semiconductor layer; removing the dummy region to form a gap between the upper source / drain region and the lower source / drain region; forming a first contact etch stop layer and a second contact etch stop layer, wherein the first contact etch stop layer is located between the upper source / drain region and the lower source / drain region. The second contact etch stop layer is located above the upper source / drain region; a first interlayer dielectric and a second interlayer dielectric are formed, wherein the first interlayer dielectric is located in the first contact etch stop layer, and the second interlayer dielectric is located above the second contact etch stop layer; an etching process is performed to form a contact opening, wherein the second interlayer dielectric, the second contact etch stop layer, the first interlayer dielectric, and the first contact etch stop layer are etched; a pre-cleaning process is performed to clean the contact opening; silicide layers are formed on the upper source / drain region and the lower source / drain region; and the contact opening is filled with a contact plug.

[0006] This application provides another aspect of a semiconductor structure, comprising: a first semiconductor layer; a second semiconductor layer overlapping the first semiconductor layer; a lower source / drain region located next to the first semiconductor layer; an upper source / drain region located next to the second semiconductor layer; a first contact etch stop layer located between the lower source / drain region and the upper source / drain region, wherein, in a vertical cross-section of the first contact etch stop layer, the first contact etch stop layer forms a ring; a first interlayer dielectric surrounded by the ring; a second contact etch stop layer located above the upper source / drain region; and a second interlayer dielectric located above the second contact etch stop layer.

[0007] Embodiments of this application provide an ILD with high etch selectivity for forming contact plugs. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0009] Figure 1 A perspective view of an example complementary field-effect transistor (CFET) according to some embodiments is shown.

[0010] Figures 2 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a view of an intermediate stage in the fabrication of a CFET according to some embodiments.

[0011] Figure 17 A process flow for manufacturing a CFET is shown according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] A complementary field-effect transistor (CFET) and a method for forming the same are provided. According to some embodiments, a lower source / drain region, a pseudo-contact etch-stop layer (CESL), a pseudo-interlayer dielectric (ILD), and an upper source / drain region are formed. The pseudo-ILD is formed of a first dielectric material such as silicon oxide. The pseudo-CESL and pseudo-ILD are then removed. A first CESL and a second CESL are then formed, followed by the formation of a first ILD and a second ILD. The first ILD and the second ILD are formed of a second dielectric material different from the first dielectric material of the pseudo-ILD. The second dielectric material is more resistant to the chemicals used in the subsequent pre-cleaning process (performed prior to the formation of the silicide layer). Therefore, bending (protrusion) of the source / drain contact plug into the first ILD is avoided.

[0015] It should be understood that while gate-all-around (GAA) transistors (such as nanostructured FETs) have been discussed as examples, the concepts of this disclosure can also be applied to the formation of other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), etc. Throughout the description, the terms "FET" and "transistor" are used interchangeably.

[0016] Figure 1 Examples of CFET 10 (including FET (transistor) 10U and 10L) according to some embodiments are shown. Figure 1 This is a 3D view, in which some components of the CFET are omitted for clarity.

[0017] A CFET comprises multiple vertically stacked FETs. For example, a CFET may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type), opposite to the first device type. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U.

[0018] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26'. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Depending on the context, the source / drain regions may individually or collectively refer to the source or drain. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0019] Figure 1 Reference cross sections used in subsequent figures are also shown. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26' of the CFET and in the direction of current flow, for example, between the source / drain regions 62 of the CFET. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 80 of the CFET. For clarity, subsequent figures may refer to these reference cross sections.

[0020] Figures 2 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B A cross-sectional view of an intermediate stage in the formation of a CFET according to some embodiments is shown (e.g.) Figure 1 (Illustrative representation). The corresponding processes are also schematically reflected in, for example... Figure 17 The process flow shown is 200. In the following discussion, unless otherwise stated, the figures followed by the letter "A" indicate a path along the... Figure 1 A vertical cross-sectional view of a cross-section similar to the vertical reference cross-section A-A' in the diagram. The figure following the number with the letter "B" shows a view along the same... Figure 1 A cross-sectional view of a cross-section similar to the vertical reference cross-section B-B' in the diagram.

[0021] exist Figure 2The image shows a wafer 2 including a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The SOI substrate can include a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 20 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or combinations thereof.

[0022] A multilayer stack 22 is formed over the substrate 20. The corresponding process is shown as follows. Figure 17 Process 202 in the process flow 200 shown. The multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (including a lower semiconductor layer 26L and an upper semiconductor layer 26U). The lower semiconductor layer 26L and the upper semiconductor layer 26U are used to form the lower FET and the upper FET, respectively.

[0023] Suitable wells (not shown separately) can be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, semiconductor layers 26L and 26U can be in-situ doped (when epitaxially grown) and / or implanted with the desired conductivity type.

[0024] In such Figure 2 In the example shown, the multilayer stack 22 includes three lower semiconductor layers 26L and two upper semiconductor layers 26U. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24A and semiconductor layers 26U and 26L. For example, Figure 5 An example is shown, wherein, as an example, the multilayer stack 22 includes a lower semiconductor layer 26L and an upper semiconductor layer 26U, which is consistent with... Figure 4 The differences are shown. Each layer of the multilayer stack 22 can be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0025] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the dummy semiconductor layer 24B can be removed at a faster rate than the dummy semiconductor layer 24A.

[0026] Semiconductor layer 26 (including lower semiconductor layer 26L and upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor material may be selected from candidate semiconductor materials of substrate 20. Lower semiconductor layer 26L and upper semiconductor layer 26U may be formed of the same semiconductor material or may be formed of different semiconductor materials.

[0027] In some embodiments, the pseudo-semiconductor layer 24A is formed of or includes silicon germanium, the semiconductor layer 26 is formed of silicon, and the pseudo-semiconductor layer 24B may be formed of germanium or silicon germanium with a higher percentage of germanium atoms than that in the semiconductor layer 24A.

[0028] exist Figure 3 In this process, a multilayer stack 22 and a substrate 20 are patterned to form a semiconductor strip 28. The corresponding process is shown as follows: Figure 17 Process 204 in the process flow 200 shown. Each semiconductor strip 28 includes a semiconductor strip 20' (a portion of the original substrate 20) and a multilayer stack 22', which is the remainder of the multilayer stack 22. The remainder 22' of the multilayer stack 22 is referred to hereinafter as a nanostructure, indicated by the corresponding reference numeral followed by an apostrophe. Thus, the multilayer stack 22' includes pseudo-nanostructures 24'A, 24'B, a lower semiconductor nanostructure 26'L, an intermediate semiconductor nanostructure 26'M, and a upper semiconductor nanostructure 26'U. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Pseudo-nanostructures 24'A and 24'B can also be collectively referred to as pseudo-nanostructure 24'. The lower semiconductor nanostructure 26'L and the upper semiconductor nanostructure 26'U can also be collectively referred to as semiconductor nanostructure 26'.

[0029] The lower semiconductor nanostructure 26'L will be used as the channel region for the lower nanostructure FET used in the CFET. The upper semiconductor nanostructure 26'U will be used as the channel region for the upper nanostructure FET used in the CFET. The intermediate semiconductor nanostructure 26'M is a semiconductor nanostructure 26' immediately above / below (e.g., in contact with) the pseudo nanostructure 24'B. The intermediate semiconductor nanostructure 26'M can be used for isolation and may or may not be used as the channel region for the CFET. Subsequently, the pseudo nanostructure 24'B will be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 26'M can define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0030] exist Figure 4 In this configuration, an isolation region 32 is formed above the substrate 20 and between adjacent semiconductor strips 28. The corresponding process is shown as follows: Figure 17 Process 206 in the illustrated process flow 200. The isolation region 32 may include a dielectric liner and a dielectric material located above the dielectric liner. The isolation region 32 is then recessed. Some upper portions of the semiconductor strip 28 (including multilayer stack 22') protrude higher than the remaining isolation region 32 to form protruding fins 34.

[0031] Then, a pseudo-dielectric layer 36 is formed on the protruding fin 34. The corresponding process is shown as follows. Figure 17 Process 208 in the process flow 200 shown. The pseudo-dielectric layer 36 may be formed or comprise, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques.

[0032] A dummy gate layer 38 is formed above the dummy dielectric layer 36. The corresponding process is shown as follows. Figure 17 Process 210 in the illustrated process flow 200. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), etc. A mask layer 40 is formed over the planarized dummy gate layer 38 and can include, for example, silicon nitride, silicon oxynitride, etc.

[0033] Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38 and possibly the dummy dielectric layer 36. Figure 5 The resulting structure is shown in the figure. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42. The multilayer stack 22' may include any number of dummy semiconductor layers 24'A and semiconductor layers 26'U and 26'L.

[0034] exist Figure 5 In this configuration, a gate spacer 44 is formed over the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0035] refer to Figure 6A and Figure 6B Source / drain trenches 46 are formed in semiconductor strip 28. The corresponding process is shown as follows. Figure 17 Process 212 in the process flow 200 shown. Figure 6B As shown Figure 6A The cross-section shown is 6B-6B. The source / drain recess 46 is formed by etching and can extend through the multilayer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain recess 46 can be located in the isolation region 32 ( Figure 4 Above, below, or at the same level as the top surface of the semiconductor strip 28. During the etching process, the gate spacer 44 and the dummy gate stack 42 mask portions of the semiconductor strip 28. Etching may include a single etching process or multiple etching processes.

[0036] refer to Figure 7A and Figure 7B The pseudo-nanostructure 24'A is laterally recessed, and dielectric material is filled into the corresponding recesses to form internal spacers 54, which are dielectric spacers. A dielectric isolation layer 56 is also formed to replace the pseudo-nanostructure 24'B. The corresponding process is shown as follows. Figure 17 Process 214 in the process flow 200 shown.

[0037] Next, as Figure 8A and Figure 8B As shown, a lower source / drain region 62L is formed in the lower portion of the source / drain groove 46. Figure 5 The corresponding process is shown as follows. Figure 17 Process 216 in the process flow 200 shown. The lower source / drain region 62L is in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U. The internal spacer 54 electrically insulates the lower source / drain region 62L from the pseudo-nanostructure 24'A, which will be replaced by a replacement gate in a subsequent process.

[0038] The lower (epitaxical) source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon, doped with n-type dopants such as phosphorus or arsenic. When the lower source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon-germanium, doped with p-type dopants such as boron or indium. The lower source / drain region 62L can be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants.

[0039] According to some embodiments, a pseudo-contact etch stop layer (CESL) 66 can be formed above the lower source / drain region 62L. The corresponding process is shown as follows. Figure 17Process 218 in the process flow 200 shown. Pseudo-CESL 66 can be formed from silicon nitride, silicon oxide, silicon oxynitride, etc., and they can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0040] A pseudo-ILD 68 is formed on top of the pseudo-CESL 66. The corresponding process is shown as follows. Figure 17 Process 220 in the illustrated process flow 200. The pseudo-ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as FCVD, plasma-enhanced CVD (PECVD), or CVD. Suitable dielectric materials for the pseudo-ILD 68 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. The pseudo-ILD 68 and pseudo-CESL 66 together form a pseudo-dielectric region, which will be removed in a subsequent process.

[0041] The formation process of the pseudo ILD 68 and pseudo CESL 66 may include depositing a conformal CESL layer, depositing material for the ILD 68, followed by a planarization process, and then an etch-back process. According to some embodiments, the pseudo ILD 68 is first etched, leaving the pseudo CESL 66 unetched. An isotropic etch process is then performed to remove the portion of the pseudo CESL 66 above the recessed pseudo ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26'U are exposed.

[0042] According to an optional embodiment, instead of forming pseudo-CESL 66 and pseudo-ILD 68, a homogeneous dielectric material is formed as the pseudo-dielectric region. The homogeneous dielectric material may be selected from the same group of materials used to form the pseudo-ILD 68.

[0043] Next, an upper source / drain region 62U is formed in the upper portion of the source / drain recess 46. The corresponding process is shown as follows. Figure 17 Process 222 in the process flow 200 shown. The material for the upper source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L.

[0044] The conductivity type of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. In other words, the upper source / drain region 62U can be doped in the opposite way to the lower source / drain region 62L. The upper source / drain region 62U can be doped in situ and / or can be implanted with n-type or p-type dopants.

[0045] refer to Figure 9A and Figure 9BAn etching process is performed to remove the pseudo-CESL 66 and pseudo-ILD 68. The corresponding process is shown as follows. Figure 17 Process 224 in the process flow 200 shown. Etching may include an isotropic etching process, which may be a dry etching process and / or a wet etching process. After etching, a void (also called a gap or air gap) 63 is formed to separate the upper source / drain region 62U from the corresponding lower source / drain region 62L.

[0046] According to some embodiments, pseudo-ILD 68 and pseudo-CESL 66 are completely removed. According to an alternative embodiment, some residual portions of pseudo-CESL 66 may remain at the corner area 65, such as... Figure 9A As shown.

[0047] Next, as Figure 10A and Figure 10B As shown, CESL 70A and 70B are formed. The corresponding process is shown as follows. Figure 17 Process 226 in the process flow 200 shown. CESL 70 is also called replacement CESL. CESL 70A and 70B are formed in the same formation process and can be formed from a dielectric material with high etch selectivity for etching the subsequently formed ILD 72A and 72B. For example, CESL 70A and 70B can be formed from or include silicon nitride, silicon oxide, silicon oxynitride, etc., and they can be formed by any suitable conformal deposition process, such as CVD, ALD, etc.

[0048] refer to Figure 10A and Figure 10B CESL 70A can be formed as a full ring, including a top portion (which may be a horizontal portion) that contacts the bottom surface of the upper source / drain region 62U and a bottom portion (which may be a horizontal portion) that contacts the corresponding lower source / drain region 62L.

[0049] refer to Figure 11A and Figure 11B After forming CESL 70A and 70B, ILD 72A and 72B are formed. The corresponding process is shown as follows. Figure 17 Process 228 in the process flow 200 shown. ILDs 72A and 72B can be formed from a dielectric material that can be deposited by any suitable conformal or bottom-up method, such as ALD, CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for ILDs 72A and 72B may include SiOC, SiOCN, SiC, etc.

[0050] ILD 72A and 72B are formed by sharing a common forming process and are formed from the same materials. Figure 11B In the diagram, dashed lines are drawn to schematically mark the connection points of ILD 72A and 72B. It should be understood that since ILD 72A and 72B can be formed in the same continuous process, there may not be any distinguishable interface between ILD 72A and 72B.

[0051] According to optional embodiments, ILD 72A and 72B are formed in different forming processes and can be formed from different materials. Therefore, in Figure 11B In the diagram, dashed lines 75 (and 73) are drawn to schematically mark the possible location of the interface between ILD 72A and 72B.

[0052] The formation of CESL 70A and 70B, and ILD 72A and 72B, includes depositing the respective dielectric layers and performing a planarization process, such as CMP or mechanical polishing, to remove excess portions of the dielectric layers. According to some embodiments, the mask layer 40 is removed during the planarization process. Figure 10A ).

[0053] According to some embodiments, the outer portions of ILDs 72A and 72B can be pre-sealed with the inner portions, and the gap (also referred to as a slit or air gap) 120 can remain in the center of ILD 72A. Figure 11A The gap 120 can be located in the middle between the top and bottom portions of the CESL 70A. The gap 120 can be an elongation ( Figure 11B It extends horizontally in its longitudinal direction and may have a maximum lateral dimension (maximum width) and a maximum vertical dimension (maximum height) smaller than the maximum lateral dimension. According to an alternative embodiment, no gap is formed in ILD 72A. Gap 121 may or may not be formed in ILD 72B. Figure 11A When a void 121 is formed in ILD 72B, the void 121 (which may be a slit) may be elongated and have a vertically extending longitudinal direction.

[0054] Figure 12A and Figure 12B The formation of the replacement gate stack 90 is shown. The corresponding process is shown as follows. Figure 17 Process 230 in the process flow 200 shown. In the formation of the replacement gate stack 90, the dummy gate stack 42 is first removed in one or more etching processes to form a recess (not shown, e.g.) Figure 12A As shown, it is occupied by the gate stack 90.

[0055] Then the pseudo-nanostructure 24'A was removed by etching. Figure 11AThe remaining portion of the spacer allows the grooves to extend between the semiconductor nanostructures 26'. In the etching process, the pseudo-nanostructures 24'A are etched at a faster rate than the semiconductor nanostructures 26', the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the pseudo-nanostructures 24'A are formed of silicon-germanium and the semiconductor nanostructures 26' are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0056] A gate dielectric 78 is formed on the exposed surface of the exposed portion including the semiconductor nanostructure 26' and the gate spacer 44. The gate dielectric 78 encloses all (e.g., four) sides of the semiconductor nanostructure 26'. Each gate dielectric 78 may include an interface layer, which may include an oxide, such as silicon oxide. The interface layer may be formed by a thermal oxidation process, a chemical oxidation process, and / or a deposition process. The gate dielectric 78 may also include a high-k dielectric layer having a high dielectric constant (high-k) value greater than, for example, about 7.0. The high-k dielectric layer may be formed of a metal oxide or silicate of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof, or may include a metal oxide or silicate of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof.

[0057] Gate electrodes 80L and 80U are also formed. In the formation process, a conductive layer is first formed on a high-k dielectric layer, and the remaining portion of the trench is filled. Each of the gate electrodes 80L and 80U may include a metallic material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. Gate electrodes 80L and 80U can provide a work function suitable for the resulting lower FET (lower transistor) 10L and upper FET (upper transistor) 10U. Gate electrodes 80L and 80U may be a common gate electrode formed in the same formation process, or they may be electrically disconnected from each other and formed in separate formation processes.

[0058] The gate dielectric 78 and the gate electrode 80L together form a gate stack 90L. The gate dielectric 78 and the gate electrode 80U together form a gate stack 90U. This forms a CFET 10 including an upper FET 10U and a lower FET 10L.

[0059] Then, an etch stop layer 122 and an ILD 124 are formed. The etch stop layer 122 may be formed from or include AlO, AlN, SiOC, or a multilayer thereof. The ILD 124 may be formed from or include SiO, SiOC, SiOCN, or a multilayer thereof.

[0060] refer to Figure 13A and Figure 13B A patterned etch mask 126 is formed over the ILD 124 and the etch mask 126 is patterned. The patterned etch mask 126 may include photoresist and may include a bottom anti-reflective coating (BARC).

[0061] Then, the etch stop layer 122 and ILD 124 are patterned by etching using a patterned etch mask 126 to define the pattern. This forms contact openings 130 and 132. The corresponding process is shown as follows. Figure 17 Process 232 in the illustrated process flow 200. In the formation of contact openings 130 and 132, the second ILD 72B and the second CESL 70B are etched to expose the upper source / drain region 62U. In the formation of contact opening 132, a portion of the upper source / drain region 62U is also etched, followed by the etching of the lower first ILD 72A and the first CESL 70A. The etching for forming contact opening 132 stops at the top surface of the lower epitaxial source / drain region 62L.

[0062] Although an etching mask 126 is shown, etching can be performed using one or more etching masks to achieve the desired pattern. For example, an etching mask (such as the etching mask 126 shown) can be used to etch portions of the second ILD 72B and the second CESL 70B, thereby exposing the top surface of portions of the upper source / drain region 62U. Another etching mask (not shown) can be used to etch through the upper source / drain region 62U, stopping at the lower source / drain region 62L. After etching, the etching mask 126 can be removed.

[0063] Further reference Figure 13A and Figure 13B This forms a dielectric liner 134. The corresponding process is shown as follows. Figure 17 Process 234 in the process flow 200 shown. Although Figure 13A and Figure 13B The same figure shows the etch mask 126 and the dielectric liner 134, but the etch mask 126 may have been removed when the dielectric liner 134 was formed.

[0064] According to some embodiments, the formation of the dielectric liner 134 includes depositing a first conformal layer by a first conformal deposition process, such as ALD, CVD, PVD, etc. Then, an anisotropic etching process is performed to remove the horizontal portion of the first conformal layer, leaving the vertical portion as the dielectric liner 134. The material of the dielectric liner 134 may include SiN, SiON, metal oxides of metals such as Hf, Ti, Al, W, Nb, Re, etc., metal nitrides of metals such as Hf, Ti, Al, W, Nb, Re, etc., or combinations thereof.

[0065] refer to Figure 14A and Figure 14B After the contact openings 130 and 132 are formed, a (wet) pre-cleaning process 140 is performed. The corresponding process is shown as follows: Figure 17 Process 236 in the process flow 200 shown. A pre-cleaning process 140 can be performed using a chemical substance that effectively removes residues from contact openings 130 and 132 without corroding the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. For example, diluted aqueous hydrofluoric acid can be used.

[0066] The chemical will not corrode the second ILD 72B and the first ILD 72A. It should be understood that a portion of the first ILD 72A (in the dashed region 125) has sidewalls exposed to the contact opening 132. If the dummy ILD 66 is not replaced by ILD 72A, the chemical will corrode the material of ILD 66 (which will not be dummy), such as silicon oxide. Therefore, during the pre-cleaning process 140, the (dummy) ILD 66 will undergo lateral etching, and the contact opening 132 will adversely extend laterally in region 125. As a result of this lateral etching, the subsequently formed contact plug 144A will undesirably extend laterally in the dashed region 125.

[0067] By removing the pseudo ILD 66 and replacing it with the first ILD 72A, the first ILD 72A can be formed from material (such as SiOC) that was not etched during the pre-cleaning process 140. Thus, unfavorable lateral etching is avoided or mitigated.

[0068] Figure 14A and Figure 14B The structure after removing the etched mask 126 is shown. (Reference) Figure 15A and Figure 15B A silicide layer 142A is formed on the top surface of the lower source / drain region 62L and the upper source / drain region 62U, and a silicide layer 142B is formed on the sidewall of the upper source / drain region 62U. The corresponding process is shown as follows. Figure 17 Process 238 in the process flow 200 shown.

[0069] The formation process may include depositing a metal layer (not shown), for example, using a conformal deposition process such as physical vapor deposition (PVD). An annealing process is then performed to react the metal layer with silicon (and silicon-germanium) in the upper source / drain region 62U and the lower source / drain region 62L. This forms source / drain silicide layers 142A and 142B. The annealing process can be performed by rapid thermal annealing (RTA), furnace annealing, etc. The remaining metal layer can then be removed, for example, in an anisotropic etching process.

[0070] According to some embodiments, the upper source / drain region 62U on the right side of the rightmost silicide layer 142B shown is... Figure 15B The portion of the upper source / drain region 62U can be completely silicided. This may occur when the thickness of the corresponding portion of the upper source / drain region 62U is small, for example, less than about 3 nm. Alternatively, when the portion of the upper source / drain region 62U on the right side of the rightmost silicide layer 142B has a larger thickness, for example, greater than about 3 nm, the corresponding portion of the upper source / drain region 62U may have some remaining portion after silicided.

[0071] Next, as Figure 16A and Figure 16B As shown, contact plugs 144A and 144B are formed, and contact plugs 144A and 144B are individually and collectively referred to as contact plug 144. The corresponding process is shown as follows. Figure 17 Process 240 in the process flow 200 shown. According to some embodiments, contact plugs 144A and 144B comprise metals such as tungsten, molybdenum, ruthenium, iridium, or alloys thereof.

[0072] According to some embodiments, contact plugs 144A and 144B have a single-layer structure, wherein the entire contact plugs 144A and 144B are formed of a homogeneous material as described above. According to an alternative embodiment, the formation of contact plugs 144A and 144B may include forming a barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Next, a metallic material is deposited over the barrier layer, and the metallic material is in contact with the barrier layer. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, etc., or combinations thereof.

[0073] Further reference Figure 16A and Figure 16BAfter depositing the material used to form contact plugs 144A and 144B, a planarization process, such as CMP or mechanical polishing, is performed to remove excess material, leaving contact plugs 144A and 144B. Therefore, the top portions of contact plugs 144B and 144A are surrounded by a dielectric liner 134. Contact plugs 144A and 144B are coplanar with the top surface of the dielectric liner 134 and may also be coplanar with the top surface of the dielectric layer 124.

[0074] Contact plug 144B is electrically connected to the upper source / drain region 62U. Contact plug 144A serves as a local interconnect that electrically interconnects the lower source / drain region 62L and the upper source / drain region 62U. The formation of the sidewall silicide layer 142B can cause a portion of contact plug 144A to be narrower than other portions, a phenomenon known as necking of contact plug 144A. Necking may be caused by the nature of silicide formation, where the central portion of the silicon-containing layer can silicide faster than the edge portions. According to some embodiments, the necked portion of contact plug 144A can have a width in the range of about 10 nm to about 13 nm, and the portions of contact plug 144A above and below the necked portion can have a width in the range of about 15 nm to about 20 nm.

[0075] In the cross-sections of the upper source / drain region 62U and the lower source / drain region 62L, as shown... Figure 16A As shown, contact plugs 144A and 144B are formed, such that gap 121 ( Figure 12A The ) no longer exist. However, contact plugs 144A and 144B may not extend to the full length of these upper source / drain regions 62U and lower source / drain regions 62L. Therefore, Figure 12A A cross-section of the final structure is also shown. Figure 16A and Figure 16B The final structure is shown in the figure. Figure 12A cross section and Figure 16A The cross-sections are parallel, except that contact plugs 144A and 144B do not extend to the like Figure 12A In the cross-section shown, and therefore in Figure 12A The void 121 can still be seen in the cross-section.

[0076] In the embodiment where some remnants of pseudo-CESL 66 remain at corner region 65 (also refer to...) Figure 9A The residual portion of the pseudo CESL 66 may contact the lower source / drain region 62L and the first CESL 70A, and may contact the internal spacer 54 and / or the intermediate semiconductor nanostructure 26'M. The material of the residual portion of the pseudo CESL 66 may be the same as or different from the material of the first CESL 70A.

[0077] The embodiments of this disclosure have several advantageous features. By forming a pseudo-ILD and using a different dielectric material than that of the pseudo-ILD to form the lower (first) ILD, the lower ILD can be formed from a material (such as SiOC) that is not etched during the pre-cleaning process. Therefore, undesirable lateral etching of the lower ILD is less likely to occur.

[0078] According to some embodiments of this disclosure, a method includes: forming a first semiconductor layer and a second semiconductor layer overlapping the first semiconductor layer, wherein the second semiconductor layer is spaced apart from the first semiconductor layer by a dielectric isolation layer; performing a first epitaxial process to form a lower source / drain region adjacent to the first semiconductor layer; forming a dummy contact etch stop layer over the lower source / drain region; forming a dummy interlayer dielectric over the dummy contact etch stop layer; performing a second epitaxial process to form an upper source / drain region adjacent to the second semiconductor layer, wherein the upper source / drain region is located above the dummy interlayer dielectric; removing the dummy interlayer dielectric and the dummy contact etch stop layer to form a gap between the upper source / drain region and the lower source / drain region; and forming a dielectric region to fill the gap. In embodiments, the dielectric region includes the first contact etch stop layer; and the first interlayer dielectric, wherein in a cross-section of the first interlayer dielectric, the first interlayer dielectric is surrounded by the first contact etch stop layer.

[0079] In an embodiment, the method further includes: forming a second contact etch stop layer over the upper source / drain region, wherein the second contact etch stop layer is formed in the same process as for forming the first contact etch stop layer; and forming the second interlayer dielectric in the same process as for forming the first interlayer dielectric. In an embodiment, the pseudo interlayer dielectric is formed of a first dielectric material, and the first interlayer dielectric is formed of a second dielectric material different from the first dielectric material.

[0080] In one embodiment, the method further includes: forming a contact opening, wherein a portion of the contact opening in the first interlayer dielectric has a first width; and performing a pre-cleaning process to clean the contact opening using chemical substances, wherein after the pre-cleaning process, a portion of the contact opening in the first interlayer dielectric has a second width equal to the first width. In another embodiment, the method further includes: after the pre-cleaning process, forming silicide layers on an upper source / drain region and a lower source / drain region; and filling the contact opening with contact plugs.

[0081] In one embodiment, the dummy interlayer dielectric comprises silicon oxide, and the dielectric region comprises silicon carbide. In another embodiment, forming the dummy contact etch stop layer and forming the dielectric region comprises a flowable chemical vapor deposition process. In yet another embodiment, the method further comprises: after forming the dielectric region, removing the dummy semiconductor layer between the first semiconductor layer and the second semiconductor layer to leave a space; and forming a replacement gate stack in that space.

[0082] According to some embodiments of this disclosure, a method includes: forming a lower source / drain region adjacent to a first semiconductor layer; forming a dummy region above the lower source / drain region; forming an upper source / drain region adjacent to a second semiconductor layer, wherein the second semiconductor layer overlaps with and is spaced apart from the first semiconductor layer; removing the dummy region to form a gap between the upper source / drain region and the lower source / drain region; forming a first contact etch stop layer and a second contact etch stop layer, wherein the first contact etch stop layer is located between the upper source / drain region and the lower source / drain region, and the second contact etch stop layer is located above the upper source / drain region.

[0083] Then, a first interlayer dielectric and a second interlayer dielectric are formed, wherein the first interlayer dielectric is located in the first contact etch stop layer and the second interlayer dielectric is located above the second contact etch stop layer; an etching process is performed to form a contact opening, wherein the second interlayer dielectric, the second contact etch stop layer, the first interlayer dielectric, and the first contact etch stop layer are etched; a pre-cleaning process is performed to clean the contact opening; silicide layers are formed on the upper source / drain region and the lower source / drain region; and the contact opening is filled with a contact plug.

[0084] In an embodiment, forming the dummy region includes depositing a dummy contact etch stop layer over the lower source / drain region; and depositing a dummy interlayer dielectric over the dummy contact etch stop layer. In an embodiment, the dummy region and the first interlayer dielectric are formed of different dielectric materials. In an embodiment, a pre-cleaning process is performed using chemicals configured to etch the dummy region without etching the first interlayer dielectric.

[0085] In one embodiment, hydrofluoric acid is used to perform a pre-cleaning process, and the dummy regions comprise silicon oxide, and the first interlayer dielectric comprises silicon carbide. In another embodiment, in a cross-sectional view of the first contact etch stop layer, the first contact etch stop layer forms a ring surrounding the first interlayer dielectric.

[0086] According to some embodiments of this disclosure, a structure includes: a first semiconductor layer; a second semiconductor layer overlapping the first semiconductor layer; a lower source / drain region located next to the first semiconductor layer; an upper source / drain region located next to the second semiconductor layer; a first contact etch stop layer located between the lower source / drain region and the upper source / drain region, wherein the first contact etch stop layer forms a ring in a vertical cross-section; a first interlayer dielectric surrounded by the ring; a second contact etch stop layer located above the upper source / drain region; and a second interlayer dielectric located above the second contact etch stop layer.

[0087] In an embodiment, the first contact etch stop layer and the second contact etch stop layer comprise the same first dielectric material, and the first interlayer dielectric and the second interlayer dielectric comprise the same second dielectric material. In an embodiment, the first contact etch stop layer comprises an upper horizontal portion contacting the bottom surface of the upper source / drain region; and a lower horizontal portion contacting the top surface of the lower source / drain region. In an embodiment, the first interlayer dielectric includes voids. In an embodiment, the voids are located in the middle of the interlayer dielectric.

[0088] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A first semiconductor layer and a second semiconductor layer overlapping the first semiconductor layer are formed, wherein the second semiconductor layer is spaced apart from the first semiconductor layer by a dielectric isolation layer; Perform a first epitaxial process to form a lower source / drain region next to the first semiconductor layer; A pseudo-contact etch stop layer is formed above the lower source / drain region; A pseudo-interlayer dielectric is formed above the pseudo-contact etch stop layer; A second epitaxial process is performed to form an upper source / drain region next to the second semiconductor layer, wherein the upper source / drain region is located above the pseudo interlayer dielectric; Remove the pseudo-interlayer dielectric and the pseudo-contact etch stop layer to form a gap between the upper source / drain region and the lower source / drain region; and A dielectric region is formed to fill the gap.

2. The method according to claim 1, wherein, The dielectric region includes: First contact etch stop layer; and The first interlayer dielectric, wherein, in the cross-section of the first interlayer dielectric, the first interlayer dielectric is surrounded by the first contact etch stop layer.

3. The method according to claim 2, further comprising: A second contact etch stop layer is formed above the upper source / drain region, wherein the second contact etch stop layer is formed in the same process as that used to form the first contact etch stop layer; and The second interlayer dielectric is formed in the same process as that used to form the first interlayer dielectric.

4. The method according to claim 2, wherein, The pseudo interlayer dielectric is formed of a first dielectric material, and the first interlayer dielectric is formed of a second dielectric material different from the first dielectric material.

5. The method according to claim 2, further comprising: A contact opening is formed, and a portion of the contact opening in the first interlayer dielectric has a first width; as well as A pre-cleaning process is performed to clean the contact opening using chemicals, wherein, after the pre-cleaning process, the portion of the contact opening in the first interlayer dielectric has a second width that is the same as the first width.

6. The method of claim 5, further comprising, after the pre-cleaning process: A silicide layer is formed on the upper source / drain region and the lower source / drain region; and The contact opening is filled with a contact plug.

7. The method according to claim 1, wherein, The pseudo-interlayer dielectric comprises silicon oxide, and the dielectric region comprises silicon oxide carbon.

8. The method according to claim 1, wherein, The formation of the pseudo-contact etch stop layer and the formation of the dielectric region include a flowable chemical vapor deposition process.

9. A method for forming a semiconductor structure, comprising: A lower source / drain region is formed next to the first semiconductor layer; A pseudo-region is formed above the lower source / drain region; An upper source / drain region is formed next to the second semiconductor layer, wherein the second semiconductor layer overlaps with and is spaced apart from the first semiconductor layer; Remove the pseudo-region to form a gap between the upper source / drain region and the lower source / drain region; A first contact etch stop layer and a second contact etch stop layer are formed, wherein the first contact etch stop layer is located between the upper source / drain region and the lower source / drain region, and the second contact etch stop layer is located above the upper source / drain region; A first interlayer dielectric and a second interlayer dielectric are formed, wherein the first interlayer dielectric is located in the first contact etch stop layer, and the second interlayer dielectric is located above the second contact etch stop layer; An etching process is performed to form a contact opening, wherein the second interlayer dielectric, the second contact etch stop layer, the first interlayer dielectric, and the first contact etch stop layer are etched. Perform a pre-cleaning process to clean the contact openings; A silicide layer is formed on the upper source / drain region and the lower source / drain region; and The contact opening is filled with a contact plug.

10. A semiconductor structure comprising: First semiconductor layer; The second semiconductor layer overlaps with the first semiconductor layer; The lower source / drain region is located next to the first semiconductor layer; The upper source / drain region is located next to the second semiconductor layer; A first contact etch stop layer is located between the lower source / drain region and the upper source / drain region, wherein the first contact etch stop layer forms a ring in a vertical cross-section; The first interlayer dielectric is surrounded by the ring; A second contact etch stop layer is located above the upper source / drain region; and The second interlayer dielectric is located above the second contact etch stop layer.

Images