Method of forming semiconductor structure

Abstract

In one embodiment, a method includes providing a structure including a bottom device and a top device over the bottom device, forming a trench extending through the top device and into the bottom device, and forming a conductive plug in the trench. The trench includes a bottom portion having a first width and a top portion having a second width, the first width being less than the second width. Forming the conductive plug in the trench includes depositing a metal precursor over the structure, thereby forming a metal layer in top and bottom portions of the trench, performing an etch-back process on the top portion of the metal layer, filling the trench with a metal fill layer, and performing a planarization process on the structure. The embodiment of the invention relates to a method for forming a semiconductor structure.

Description

Technical Field

[0001] This application relates to a method for forming a semiconductor structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of handling and manufacturing ICs, and similar developments in IC handling and manufacturing are needed to achieve these advancements. For example, stacked device structures have been introduced to further reduce the density of advanced IC technology nodes. However, manufacturing such stacked device structures presents additional challenges. Therefore, existing implementations are not satisfactory in all aspects. Summary of the Invention

[0004] One embodiment of this application provides a method for forming a semiconductor structure, including:

[0005] A structure is provided, the structure comprising: a bottom source / drain component; a bottom contact etch stop layer (CESL) disposed above the bottom source / drain component; a bottom interlayer dielectric (ILD) layer disposed above the bottom contact etch stop layer, wherein the thickness of the bottom contact etch stop layer is less than the thickness of the bottom interlayer dielectric layer; a top source / drain component disposed above the bottom interlayer dielectric layer; a top contact etch stop layer disposed above the top source / drain component and the bottom interlayer dielectric layer; and a top interlayer dielectric layer disposed above the top source / drain component, wherein the thickness of the top contact etch stop layer is less than the thickness of the top interlayer dielectric layer;

[0006] Trenches are formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trenches expose the top source / drain components and the bottom source / drain components;

[0007] A silicide layer is formed on the top source / drain component and the bottom source / drain component;

[0008] A metal deposition process is performed to form a metal layer on the sidewalls and bottom surface of the trench;

[0009] Perform a metal self-etching process to remove the top portion of the metal layer; and

[0010] A metal filling layer is formed in the trench.

[0011] Another aspect of this application provides a method for forming a semiconductor structure, including:

[0012] A structure is provided, the structure comprising: a bottom active region including a bottom channel region and a bottom source / drain region adjacent to the bottom channel region; a bottom gate structure located above the bottom channel region; a bottom contact etch stop layer (CESL) located above the bottom source / drain region; a bottom interlayer dielectric (ILD) layer located above the bottom contact etch stop layer; a top active region including a top channel region and a top source / drain region adjacent to the top channel region; a top gate structure located above the top channel region; a top contact etch stop layer located above the top source / drain region; and a top interlayer dielectric layer located above the top contact etch stop layer;

[0013] A trench is formed extending through the top interlayer dielectric layer, the top contact etch stop layer, the top source / drain region, the bottom contact etch stop layer, and the bottom interlayer dielectric layer to expose the bottom source / drain region;

[0014] A metal precursor is provided to the structure to form a metal layer in the trench;

[0015] A bottom antireflective coating (BARC) layer is formed above the metal layer and in the top portion of the trench above the top source / drain region;

[0016] An etching process is performed to remove the top portion of the metal layer above the bottom anti-reflective coating;

[0017] Remove the bottom anti-reflective coating; and

[0018] A metal filler layer is formed over the remaining portion of the metal layer and in the trench.

[0019] Another aspect of this application provides a method for forming a semiconductor structure, including:

[0020] A structure is provided, the structure including a bottom device and a top device located above the bottom device;

[0021] A trench is formed extending through the top device and into the bottom device, wherein the trench includes a bottom portion having a first width and a top portion having a second width, wherein the first width is smaller than the second width; and

[0022] Forming a conductive plug in the trench includes: depositing a metal precursor over the structure to form a metal layer in the top and bottom portions of the trench; performing an etch-back process on the top portion of the metal layer; filling the trench with a metal filler layer; and performing a planarization process on the structure. Attached Figure Description

[0023] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0024] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0025] Figure 2 , Figure 3 , Figure 4A , Figure 8 and Figure 9 This illustrates one or more aspects of the present disclosure. Figure 1 Partial cross-sectional views of exemplary semiconductor structures during various manufacturing stages of the method.

[0026] Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7A and Figure 7B This illustrates one or more aspects of the present disclosure. Figure 1 Partial schematic cross-sectional views of exemplary semiconductor structures during various manufacturing stages in the method.

[0027] Figure 10 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0028] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B This illustrates one or more aspects of the present disclosure. Figure 10Partial schematic cross-sectional views of exemplary semiconductor structures during various manufacturing stages in the method. Detailed Implementation

[0029] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact.

[0030] Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components may be formed between the components so that the components are not in direct contact. Furthermore, for the convenience of describing the relationship between one component and another, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially relative terms are intended to cover different orientations of devices including components. Also, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., these terms are intended to cover values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with that value, the value or range of values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of “about 5 nm” can cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those skilled in the art to be + / - 15%.

[0031] Stacked transistor structures can provide further density reductions for advanced integrated circuit (IC) technology nodes (especially as they advance to 3nm (N3) and below), particularly when the stacked transistor structure includes multi-gate devices such as fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors comprising nanowires and / or nanosheets, and other types of multi-gate devices. Stacked transistor structures include vertically stacked transistors. For example, a stacked transistor structure may include a first transistor (i.e., an upper / top transistor) positioned above a second transistor (i.e., a lower / bottom transistor). When the first and second transistors have opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the transistor stack can provide a complementary field-effect transistor (CFET).

[0032] Stacked transistor structures may include source / drain contacts. In some cases, stacked n-type and p-type transistors share a common source / drain contact. The common source / drain contact can be a local interconnect used to connect the n-type and p-type source / drain epitaxial components together. Because the n-type and p-type epitaxial components are stacked perpendicularly to each other, the local interconnect may need to penetrate the top epitaxial component until it lands on the bottom epitaxial component. However, forming source / drain contacts in stacked devices involves various challenges, such as higher resistance. Therefore, while existing stacked device structures (e.g., CFET structures) and their associated fabrication processes are generally sufficient for their intended purposes, they are not entirely satisfactory in every respect.

[0033] This disclosure generally relates to semiconductor structures (e.g., stacked transistor structures) having common source / drain contacts. In an example process, a structure (e.g., a CFET structure) is provided. This structure includes a bottom transistor disposed above a substrate and a top transistor disposed above the bottom transistor. The bottom transistor includes bottom source / drain components, and the top transistor includes a top source / drain component vertically positioned above the bottom source / drain components. A trench is formed to expose the bottom source / drain components and the top source / drain components. A metal seed layer is deposited along the sidewalls and bottom surface of the trench. A deposition process is performed, including depositing a metal precursor and a reactant, thereby forming a metal layer in the trench. In some embodiments, a metal self-etching process is performed by flowing the metal precursor at an increased concentration over the structure to remove the top portion of the metal layer and the metal seed layer. The deposition process and the metal self-etching process may be repeated until the bottom portion of the trench is filled without gaps. In some other embodiments, a bottom anti-reflective coating (BARC) layer is deposited above the metal layer and in the top portion of the trench after the deposition process. A pull-back process is performed to remove portions of the metal layer and metal liner above the BARC layer. The BARC layer is then removed. A metal filler layer is then deposited in the trench, and a planarization process is performed to remove excess material, thereby forming the common source / drain contact. By forming the source / drain contact using the method of this disclosure, gaps can be avoided or the size of gaps in the source / drain contact assembly can be reduced, thus lowering the resistance of the source / drain contact.

[0034] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 9 Description method 100. Figures 2 to 4A and Figures 8 to 9 It is based on Figure 1 Partial cross-sectional views of structure 200 at different manufacturing stages of an embodiment of method 100. Figures 4B to 7B It is based on Figure 1 Partial schematic cross-sectional views of structure 200 at different manufacturing stages of an embodiment of method 100. Figure 10 This is a flowchart illustrating a method 300 for forming a semiconductor structure according to an embodiment of the present disclosure. The following will be combined with... Figures 11A to 14B Description method 300, Figures 11A to 14B It is based on Figure 10Partial schematic cross-sectional views of optional structures 200' at different manufacturing stages of embodiments of method 300. Method 100 (or 300) is merely an example and is not intended to limit this disclosure to what is explicitly shown in method 100 (or 300). Additional steps may be provided before, during, and after method 100 (or 300), and some steps described may be replaced, eliminated, or rearranged for additional embodiments of method 100 (or 300). For simplicity, not all steps are described in detail herein. Because structure 200 (or 200') will be manufactured as a semiconductor structure, structure 200 (or 200') may be referred to herein as semiconductor structure 200 (or 200') or semiconductor device 200 (or 200'), depending on the context. To avoid ambiguity, Figures 2 to 14B The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. In this disclosure, unless otherwise stated, the same reference numerals denote the same parts. That is, the material properties of the various numbered elements described in association with a method or drawing, and their comparisons, should be applied to the same numbered elements described in association with different methods or different drawings.

[0035] refer to Figures 1 to 3 Method 100 includes a frame 102 in which a structure 200 is formed or provided. Figure 3 It shows along Figure 2 A partial cross-sectional view of structure 200 intercepted by line A-A'. Figure 2 In some embodiments shown, structure 200 includes a front-end process (FEOL) CFET structure fabricated on substrate 202. In the depicted embodiments, the FEOL CFET structure includes a bottom device structure formed around a bottom channel member 2080B and a top device structure formed around a top channel member 2080T. Along the vertical direction (i.e., the Z direction), the bottom channel member 2080B is spaced apart from the top channel member 2080T by an intermediate dielectric layer 210 sandwiched between two intermediate semiconductor layers 2080M. The bottom channel member 2080B is disposed above a base fin 202B. The base fin 202B is disposed above a bottom silicon-germanium layer 206B above substrate 202. Isolation member 212 (e.g.) Figure 3(As shown) is disposed above substrate 202 and surrounding base fin 202B and bottom silicon-germanium layer 206B. In some embodiments, bottom silicon-germanium layer 206B is omitted. Bottom channel member 2080B forms a channel region extending horizontally between two bottom source / drain members 218B. Similarly, top channel member 2080T forms a channel region extending horizontally between two top source / drain members 218T. Depending on the context, bottom source / drain member 218B and top source / drain member 218T may be referred to collectively or individually as source / drain member 218. The bottom device structure includes a bottom gate structure 220B that surrounds each of the vertical stacks of bottom channel member 2080B, and the top device structure includes a top gate structure 220T that surrounds each of the vertical stacks of top channel member 2080T. Depending on the context, bottom gate structure 220B and top gate structure 220T may be referred to collectively or individually as gate structure 220.

[0036] Each top source / drain component 218T is directly disposed above one of the bottom source / drain components 218B. The bottom source / drain components 218B may be disposed on the substrate epitaxial region 226. Figure 2 As shown, the bottom source / drain component 218B is spaced apart from the top source / drain component 218T above it by a bottom contact etch stop layer (BCESL) 232B and a bottom interlayer dielectric (BILD) layer 234B. The BILD layer 234B is spaced apart from the intermediate semiconductor layer 2080M and the intermediate dielectric layer 210 by the BCESL 232B. The top contact etch stop layer (TCESL) 232T and the top interlayer dielectric (TILD) layer 234T are disposed above each top source / drain component 218T. The bottom channel components 2080B are stacked on top of each other along the Z-direction and staggered by internal spacer components 228. Similarly, the top channel components 2080T are stacked on top of each other along the Z-direction and staggered by internal spacer components 228. The gate spacer 222 extends along the sidewall of a portion of the top gate structure 220T above the top channel components 2080T. Due to the planarization process, the top surfaces of TCESL 232T, TILD layer 234T, gate spacer 222, and top gate structure 220T are coplanar. For example... Figure 2 As shown, the bottom channel component 2080B and the top channel component 2080T are located within the channel region 204C of the active region 204, and the bottom source / drain component 218B and the top source / drain component 218T are located within the source / drain region 204SD of the active region 204. The source / drain region 204SD is disposed between the two channel regions 204C, and the channel region 204C is disposed between the two source / drain regions 204SD.

[0037] In some embodiments, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer (such as a silicon oxide layer) to have a silicon-on-insulator (SOI) structure. Base fin 202B may share the same composition as substrate 202. In some embodiments, bottom channel member 2080B, intermediate semiconductor layer 2080M, and top channel member 2080T may include silicon (Si). Gate spacer 222, intermediate dielectric layer 210, and internal spacer component 228 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or suitable dielectric materials. BCESL 232B and TCESL 232T may include silicon nitride or aluminum nitride. BILD layer 234B and TILD layer 234T may include oxide-based dielectric materials such as silicon oxide, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. BCESL 232B and TCESL 232T may be thinner than BILD layer 234B and TILD layer 234T, respectively, along the X-direction. Isolation component 212 may include oxide-based dielectric materials such as silicon oxide, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0038] The epitaxial region 226 may include undoped semiconductor material. In the depicted embodiments, the epitaxial region 226 includes undoped silicon (Si), undoped silicon germanium (SiGe), or undoped germanium (Ge). The top surface of the epitaxial region 226 may be at the same level as the top surface of the substrate fin 202B. The epitaxial region 226 may reduce leakage into the substrate 202. In some embodiments, fin spacers 222f are disposed along the sidewalls of the epitaxial region 226. The fin spacers 222f and the gate spacers 222 may be formed of the same material.

[0039] In the embodiments shown in the accompanying drawings, the bottom source / drain component 218B is p-type and may comprise silicon germanium (SiGe) doped with a p-type dopant (such as boron (B)); the top source / drain component 218T is n-type and may comprise silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). In these depicted embodiments, the bottom source / drain component 218B may comprise boron-doped silicon germanium (SiGe:B), and the top source / drain component 218T may comprise phosphorus-doped silicon (Si:P). As used herein, source / drain region, source / drain component, epitaxial source / drain, epitaxial source / drain component, etc., may refer to the source of a device, the drain of a device, or the source and / or drain of multiple devices.

[0040] In some embodiments, each of the bottom gate structure 220B and the top gate structure 220T includes an interface layer 236 to be in contact with the bottom channel member 2080B, the top channel member 2080T, the intermediate semiconductor layer 2080M, and / or the base fin 202B. In some embodiments, each of the bottom gate structure 220B and the top gate structure 220T further includes a gate dielectric layer 238 above the interface layer 236 and a gate electrode 240 above the gate dielectric layer 238. The gate electrode 240 in the bottom gate structure 220B includes a p-type work function layer. The gate electrode 240 in the top gate structure 220T includes an n-type work function layer. In some embodiments, the interface layer 236 includes silicon oxide. The gate dielectric layer 238 is formed of a high-k dielectric material. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). The gate dielectric layer 238 may include hafnium oxide. Optionally, the gate dielectric layer 238 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zinc oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. In some embodiments, the dielectric constant of the gate dielectric layer 238 is greater than that of the isolation member 212, the internal spacer member 228, the intermediate dielectric layer 210, the gate spacer 222, the BCESL 232B, the BILD layer 234B, the TCESL 232T, and the TILD layer 234T. In some cases, the dielectric constant of the gate dielectric layer 238 is greater than twice that of the isolation component 212, the internal spacer component 228, the intermediate dielectric layer 210, the gate spacer 222, the BCESL 232B, the BILD layer 234B, the TCESL 232T, or the TILD layer 234T. Additionally, along the X-direction, the thickness of the gate dielectric layer 238 is less than the thickness of the gate spacer 222.

[0041] For example, the p-type work function layer in the gate electrode 240 of the bottom gate structure 220B may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function materials, or combinations thereof. The n-type work function layer in the gate electrode 240 of the top gate structure 220T may include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials, or combinations thereof. In one embodiment, the gate electrode 240 in the bottom gate structure 220B and the top gate structure 220T comprises a titanium-based material.

[0042] In some embodiments, reference Figure 3 Structure 200 includes a gate isolation structure 250. The gate isolation structure 250 may extend longitudinally along the X direction in a top view. In the depicted embodiment, the gate isolation structure 250 is disposed between two active regions 204. The gate isolation structure 250 may divide the gate structure 220 into two portions and electrically isolate these two portions. In some embodiments, the gate isolation structure 250 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbon oxynitride, or combinations thereof. In one embodiment, the gate isolation structure 250 includes a silicon nitride liner 252 and a dielectric filler 254 surrounded by the silicon nitride liner 252. The dielectric filler 254 may include silicon oxide.

[0043] refer to Figure 1 and Figure 4A Method 100 includes a frame 104 in which a trench 256 is formed to expose source / drain components 218. Figure 4A The following are shown at different manufacturing stages according to method 100. Figure 3 A partial cross-sectional view of part B of structure 200 in the diagram.

[0044] Trench 256 may extend vertically through TILD layer 234T, BILD layer 234B, TCESL 232T, and BCESL 232B to expose top source / drain component 218T and bottom source / drain component 218B. In some embodiments, trench 256 extends through top source / drain component 218T. The top surface and sidewalls of top source / drain component 218T and the top surface of bottom source / drain component 218B are exposed in trench 256. Therefore, trench 256 has a first depth D1 to the top surface of top source / drain component 218T and a second depth D2 to the top surface of bottom source / drain component 218B. D1 and D2 are along the Z direction, and D2 is greater than D1. In the depicted embodiment, trench 256 includes a top portion 256a having a width W1 and a first depth D1, and a bottom portion 256b having a width W2 and a second depth D2. W1 and W2 are along the Y direction. W1 is greater than W2. In some embodiments, in a cross-sectional view, the groove 256 has a "long and short leg" shape, which refers to a shape having a first depth (or a first height, e.g., D1) and a second depth (or a second height, e.g., D2) greater than the first depth, a first width (e.g., W1) of the top portion within the first depth, and a second width (e.g., W2) of the bottom portion between the first and second depths, the second width being less than the first width. The first and second depths are along a first direction (e.g., the Z direction), and the first and second widths are along a second direction perpendicular to the first direction (e.g., the Y direction).

[0045] In some embodiments, a patterning process is performed on dielectric layers (e.g., TILD layer 234T, BILD layer 234B, TCESL 232T, and BCESL 232B) to form trench 256. In some embodiments, a portion of the top source / drain component 218T is removed during the patterning process. Forming trench 256 may include more than one patterning process to extend trench 256 to a first depth and a second depth, respectively. The patterning process may include multiple photolithography and etching processes. The photolithography process may include forming a patterned mask layer 262 over the TILD layer 234T. The patterned mask layer 262 may include multiple dielectric layers, such as etch stop layers (ESL) 258 and ILD layers 260 stacked on top of each other as shown. The patterned mask layer 262 has an opening that, in a top view, partially overlaps with a corresponding source / drain region 204SD. The etching process may include transferring a pattern in the patterned mask layer 262 to the underlying dielectric layer and / or source / drain components 218, for example, by removing portions of the TILD layer 234T, BILD layer 234B, TCESL 232T, and BCESL 232B and / or source / drain components 218 exposed by openings. The etching process may include dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0046] Still referencing Figure 1 As shown in Figure 4, method 100 includes block 106, wherein a dielectric liner 264 is formed on the sidewalls of trench 256. The dielectric liner 264 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the dielectric liner 264 includes silicon nitride. For example, the dielectric liner 264 may be formed by conformally blanket-depositing a dielectric material layer over structure 200 using a process such as chemical vapor deposition (CVD), subatmospheric pressure CVD (SACVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the horizontal surface of trench 256. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof. In some embodiments, the etch-back process includes a directional etching process. After the etch-back process, a dielectric material layer may be retained as a dielectric liner 264 on the sidewalls of the trench 256. The dielectric liner 264 prevents diffusion between the metal filler layer (described below) and the dielectric layer (e.g., TILD layer 234T, TCESL 232T, BILD layer 234B, BCESL 232B).

[0047] Before proceeding to the next process, a cleaning process may be performed to remove any debris from the surface of trench 256. In some embodiments, the cleaning process includes purging a carrier gas (e.g., an inert gas) to clean the surface of structure 200.

[0048] Still referencing Figure 1 and Figure 4A Method 100 includes block 108, wherein a silicide layer 266 is formed on the exposed surfaces (e.g., top surfaces) of the bottom source / drain component 218B and the top source / drain component 218T. In some embodiments, one or more silicide processes are performed to form the silicide layer 266. Figure 4A In this configuration, a silicide layer 266 is disposed on each exposed top surface of the bottom source / drain component 218B and the top source / drain component 218T, and the silicide layer 266 has a crescent-shaped profile. The silicide process may include depositing a metal-containing layer over the source / drain component 218 by a suitable deposition process, and heating the structure 200 (e.g., by subjecting it to an annealing process) to react the components of the source / drain component 218 with the metal components in the metal-containing layer. In some embodiments, the silicide process consumes a portion of the source / drain component 218 and transforms it into the silicide layer 266. The metal-containing layer includes any metallic component suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The silicide layer 266 thus includes both the metallic components and the components of the source / drain component 218 (e.g., silicon and / or germanium). In some embodiments, the metal-containing layer is a titanium-containing layer, and the silicide layer 266 comprises titanium and silicon, and may be referred to as a titanium silicide layer. Any unreacted metal, such as the remainder of the metal-containing layer, is selectively removed by any suitable process. The silicide layer 266 formed on the bottom source / drain component 218B and the top source / drain component 218T may be formed separately and may comprise different compositions. For example, the silicide layer 266 is selectively formed on the bottom source / drain component 218B by a first silicide process to have a first composition, and then another silicide layer 266 is selectively formed on the top source / drain component 218T by a second silicide process to have a second composition. The first composition and the second composition may be different. For example, the silicide layer 266 on the bottom source / drain component 218B and the silicide layer 266 on the top source / drain component 218T may comprise different metals. The silicide layer 266 may reduce the resistance of the source / drain contacts (to be described).

[0049] Still referencing Figure 1 and Figure 4AMethod 100 includes frame 110, wherein a metal seed layer 268 (also referred to as metal liner 268) is formed in trench 256. The metal seed layer 268 is deposited over structure 200, including a dielectric liner 264, a patterned mask layer 262, and a silicide layer 266. In some embodiments, the metal seed layer 268 comprises molybdenum (Mo), ruthenium (Ru), iridium (Ir), alloys thereof, or combinations thereof. In some embodiments, the metal seed layer deposition is continuous, and the thickness of the metal seed layer 268 is no greater than about 5 nm. The thickness of the metal seed layer 268 may be equal to or less than about 5 nm, optionally less than about 2 nm. The metal seed layer 268 can be formed by a PVD process or an ALD process. In embodiments where the metal seed layer 268 is formed by a PVD process, the thickness of the metal seed layer 268 on a horizontal surface (e.g., a top surface) may be greater than the thickness of the metal seed layer 268 on the sidewalls of trench 256. In embodiments where the metal seed layer 268 is formed via an ALD process, the metal seed layer 268 can be deposited conformally. For ease of description, the term "conformally" may be used herein for the purpose of depicting a layer having a substantially uniform thickness over the various regions. The metal seed layer 268 can facilitate the growth or bonding of the metal layer (to be described) formed thereon.

[0050] For the purposes of simplicity and clarity, Figure 4B As shown Figure 4A A simplified schematic diagram of structure 200 is shown. Figure 4B In the dielectric structure 235, there are TILD layer 234T, TCESL 232T, BILD layer 234B, BCESL 232B, a patterned mask layer 262, and a dielectric liner 264. In the depicted embodiment, a metal seed layer 268 is disposed on the sidewalls and top surface of the dielectric structure 235, and on the top surface of the silicide layer 266. In the depicted embodiment, the metal seed layer 268 is thicker on the sidewalls than on the top surface of the dielectric structure 235 and the silicide layer 266. The metal seed layer 268 can be formed by a PVD process.

[0051] refer to Figure 1 and Figure 5AMethod 100 includes block 112, wherein a metal deposition process is performed on structure 200. The metal deposition process can be performed at a temperature of about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, the metal deposition process includes a suitable deposition process, such as a CVD process or an ALD process. In some embodiments, the metal deposition process includes a CVD process. In some embodiments, the metal deposition process includes flowing a mixture into a process chamber. The mixture may include a metal precursor (also referred to as a metal-containing precursor) and a reactant. In some embodiments, the metal precursor includes Mo(CO)6 (molybdenum hexacarbonyl), MoO2(thd)2 (dioxodibenzo(2,2,6,6-tetramethylheptane-3,5-dione)molybdenum(VI)), MoCl5 (molybdenum chloride(V)), MoO2Cl2 (molybdenum dichlorodioxide), [C2H5Ru(CO)2]2, Ru(CO)H2[P(C6H5)3]3, Ru(TMM)(CO)3 (ruthenium tricarbonyl(trimethylenemethane)), Ru3(CO) 12 (ruthenium dodecacarbonyltriruthenium), TICP(C) 18 H 27 IrO3 or tricarbonyl(1,2,3-η)-1,2,3-tris(tert-butyl)-cyclopropenyliridium) or combinations thereof. In some embodiments, the metal in the metal precursor is the same as the metal in the metal seed layer 268. For example, the metal precursor and the metal seed layer 268 comprise Mo. A reactant may interact (e.g., react) with the metal precursor to reduce it to an elemental metal (e.g., metal atoms not bonded to a nonmetallic element such as carbon or oxygen), thereby forming the metal layer 270. The reactant may include a reactive gas, plasma, or a combination thereof. In some embodiments, the reactant comprises a reactive gas, such as hydrogen (H2). The reactive gas may be referred to as a reducing agent. In some embodiments, the reactant comprises a plasma generated from a gas, such as an inert gas (e.g., argon (Ar)). The plasma can break the bonds in the metal precursor to convert it into an elemental metal. In such embodiments, the metal deposition process includes a plasma-enhanced CVD (PECVD) process.

[0052] In some embodiments, due to the dimensions (e.g., depth, width) and shape of the trench 256 and the inherent nature of the deposition process (e.g., CVD process), the metal layer 270 grows faster in the top portion 256a of the trench 256 than in the bottom portion 256b of the trench 256. The top portion of the metal layer 270 can prevent the mixture from flowing downwards into the portion of the trench 256 below it. In some embodiments, as shown, gaps 256s are formed and are clamped by the metal layer 270. The gaps 256s can extend from the top portion 256a to the bottom portion 256b of the trench 256. In some embodiments, the remaining portion of the trench 256 above the gaps 256s has a width W3 along the Y direction and a depth D3 along the Z direction. In some other embodiments, the operation at block 112 may not create gaps clamped between the metal layers 270.

[0053] refer to Figure 1 and Figures 5B to 6 Method 100 includes block 114, in which a metal self-etching process is performed. The metal self-etching process can remove the top portion of metal layer 270 and metal seed layer 268 via a metal precursor. Since the metal precursor can form a metal layer (e.g., metal layer 270) and can etch the metal layer, such a property can be referred to as the self-etching property.

[0054] The metal self-etching process can be performed at temperatures from about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, performing the metal self-etching process includes introducing an etching gas into a process chamber. The etching gas includes a metal precursor. The metal precursors used at boxes 114 and 112 may have the same composition. In some embodiments, the metal precursor converts metal layer 270 and / or metal seed layer 268 into a metal-containing gas (e.g., Mo(CO)4, Mo(CO2)5), which may be purged out of the process chamber (e.g., through unreacted etching gas). For example, each of metal layer 270 and metal seed layer 268 includes element Mo, the metal precursor includes Mo(CO)6, and Mo(CO)6 reacts with element Mo to form Mo(CO)4 and Mo(CO)5, which are in the gas phase under operating conditions. In some embodiments, the metal precursor has a first concentration in the mixture and a second concentration in the etching gas. The first concentration may be lower than the second concentration. In some embodiments, the second concentration is greater than about 95%. In some embodiments, the reactant as described above has a concentration of less than about 3% in the etching gas. In some embodiments, the etching gas further includes a carrier gas, such as an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, other suitable inert gases, or combinations thereof. In some embodiments, the carrier gas is used to deliver the metal precursor gas into the process chamber and / or to purge unreacted etching gas and product gas (e.g., metal-containing gas) out of the process chamber.

[0055] Compared to the bottom portions of metal layer 270 and metal seed layer 268, the top portions of metal layer 270 and metal seed layer 268 are closer to the opening of trench 256 and are more exposed to the etching gas, thus being removed at a faster rate. In some embodiments, after the metal self-etching process, metal layer 270 above the top surface of dielectric structure 235 is completely removed. In the depicted embodiment, metal seed layer 268 on the top surface of dielectric structure 235 is partially removed. The thickness of metal layer 270 in the top portion 256a of trench 256 (e.g., the horizontal portion above silicide layer 266 and / or the vertical portion along the sidewalls of metal seed layer 268) can be reduced. In some embodiments, the slots 256s do not extend further downward during the metal self-etching process. In some embodiments, after performing the metal self-etching process, access to slots 256s (e.g., the remaining portion of trench 256 above slots 256s) is wider. For example, after the metal self-etching process, the width W4 of the remaining portion of trench 256 along the Y direction is greater than W3. W3 and W4 are at the same depth or level as shown by the dashed lines. For example, after the metal self-etching process, the depth D4 of the remaining portion of trench 256 is greater than D3. Therefore, the vertical height of the slot 256s is reduced. Therefore, the profile of the metal layer 270 can be adjusted by the metal self-etching process.

[0056] The metal deposition process and the metal self-etching process can be performed in situ (e.g., in the same process chamber). In some embodiments, the metal deposition process and the metal self-etching process are repeated in cycles. For example, after the first cycle of the metal deposition process and the metal self-etching process, the gap 256s can be retained (e.g., as shown in the image). Figure 5B(As shown). Then, a second cycle of the metal deposition process and the metal self-etching process is performed. The metal deposition process of the second cycle may deposit an additional metal layer 270' over the metal layer 270. The additional metal layer 270' may fill the gaps 256s and / or reduce the size of the gaps 256s. In some embodiments, the additional metal layer 270' completely fills the gaps 256s. The additional metal layer 270' and the metal layer 270 may be merged. For simplicity, the merged layer of the additional metal layer 270' and the metal layer 270 is referred to as the merged metal layer 270 or metal layer 270, which has an increased thickness from the metal deposition process of the second cycle. The metal self-etching process of the second cycle may remove the top portion of the merged metal layer 270, including removing the top portion of the additional metal layer 270'. One or more cycles of the metal deposition process and the metal self-etching process may be performed. Similar to the above, the thickness of the metal layer 270 may be increased in each cycle, and the top portion of the metal layer 270 may be removed in that cycle. One or more cycles can be performed until the gap 256s is filled by the metal layer 270. In some embodiments, after one or more cycles, the gap 256s (e.g., Figure 6 (As shown by the dashed line in the image) is entirely composed of metal layer 270 (e.g., as shown by the dashed line in the image). Figure 6 (As shown) filling. In some other embodiments, one or more cycles of metal deposition and metal self-etching processes are performed until the gap 256s reaches the designed size. In such embodiments, the impact of the gap 256s on the resistance of the common source / drain contacts can be reduced.

[0057] Various parameters of the metal deposition process and the metal self-etching process can be adjusted to achieve the designed formation and / or etching of the metal layer 270, such as the composition of the mixture, the composition of the etching gas, temperature, duration, pressure, gas flow rate, source power, bias power, bias, number of cycles, other suitable parameters or combinations thereof.

[0058] refer to Figure 1 and Figures 7A to 7B Method 100 includes a frame 116, wherein a metal filler layer 272 is formed over structure 200 to fill trench 256. Figure 7A This illustrates an embodiment where the gap is retained for 256 seconds, and Figure 7BThis illustrates an embodiment where the gap 256s is completely filled. Due to a metal self-etching process (e.g., a metal self-etching process in the last cycle), the top portion of the metal layer 270 is removed, allowing the remaining portion of the trench 256 to be widened, and a metal filler layer 272 can be deposited without forming gaps in the metal filler layer 272. The metal filler layer 272 can be deposited over the dielectric structure 235. The metal filler layer 272 may include an elemental metal. In some embodiments, the metal filler layer 272 includes Mo, Ru, Ir, alloys thereof, or combinations thereof. In some embodiments, the metal filler layer 272 includes the same metal as the metal layer 270. In some embodiments, the metal filler layer 272, metal layer 270, and metal seed layer 268 include the same composition. The metal filler layer 272, metal layer 270, and metal seed layer 268 may be combined. The conductivity of the metal filler layer 271 is greater than the conductivity of the source / drain component 218. In some embodiments, the metal filler layer 272 is formed by CVD, PVD, metal-organic CVD (MOCVD), plating or other suitable processes.

[0059] refer to Figure 1 and Figures 8 to 9 Method 100 includes block 118, in which a planarization process (e.g., CMP process) is performed to remove excess material (e.g., portions of the metal filler layer 272 and metal seed layer 268 on the top surface of dielectric structure 235). The remaining portion of the metal filler layer 272 may be referred to as the remaining metal filler layer 272'. The remaining metal filler layer 272', metal layer 270, metal seed layer 268, and silicide layer 266 together form a first source / drain contact 276 (or common source / drain contact 276). The first source / drain contact 276 has a "long and short leg" shape as described above. A second source / drain contact 278 disposed above the top source / drain component 218T and connected to the top source / drain component 218T but not connected to the bottom source / drain component 218B can be formed by the same or different methods and may include similar components such as the silicide layer, metal seed layer, and metal filler layer. Although Figures 8 to 9 It is not explicitly described, but gap 256s can exist in the remaining metal filler layer 272', which is caused by Figure 7A The example shown is generated by... Figure 7B In some other embodiments resulting from the illustrated embodiment, the first source / drain contact 276 is seamless. Gaps in the first source / drain contact 276 can be reduced or avoided by performing one or more cycles of a metal deposition process and a metal self-etching process, thus reducing the resistance of the first source / drain contact 276.

[0060] Structure 200 can undergo further processes to form various components and regions known in the art. For example, subsequent processes may form additional interlayer dielectric (ILD) layers, contacts / vias / wires, and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) over substrate 202, configured to connect various components to form a functional circuit that may include one or more devices, including semiconductor device 200. In a further example, the multilayer interconnect components may include vertical interconnect components (such as vias or contacts) and horizontal interconnect components (such as metal lines). The various interconnect components may be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form a copper-associated multilayer interconnect structure.

[0061] refer to Figures 10 to 14B Method 300 can be used to manufacture optional structure 200'. (See reference) Figure 10 and Figures 2 to 4B Optional structure 200' can withstand the operations described above at boxes 102 to 110. (See reference) Figure 10 and Figure 5A Method 300 includes block 312, in which a metal deposition process is performed on structure 200', similar to the operation at block 112. Differences from the metal deposition process at block 112 include the following: In some embodiments, the pressure of the metal deposition process at block 312 is lower than that of the metal deposition process at block 112. Compared to the metal deposition process at block 112, in the metal deposition process at block 312, the mixture diffuses more towards the bottom portion 256b of the trench 256, thus avoiding the formation of gaps 256s or reducing the size of gaps 256s. In some embodiments, the metal deposition process at block 312 includes an ALD process. In some embodiments, a metal layer 270 is conformally deposited.

[0062] refer to Figure 10 and Figures 11A to 11B Method 300 includes block 314, wherein a bottom antireflective coating (BARC) layer 280 is deposited over a metal layer 270. The BARC layer material can be deposited over the metal layer 270 using CVD, spin coating, or other suitable processes. In some embodiments, the BARC layer material may include silicon oxynitride (SiON), silicon oxycarbide, polymers, or other suitable materials. After depositing the BARC layer material, as... Figure 11A The depicted process involves selectively etching back the BARC layer material to expose the top portion of the metal layer 270. Etching back may include using a dry etching process. A dry etching process may include using a plasma containing argon (Ar), oxygen (O2), nitrogen (N2), hydrogen (H2), or a combination thereof. The top surface of the remaining BARC layer material (i.e., BARC layer 280) may be below the top surface of the dielectric structure 235. Figure 11A In the depicted embodiment, the gap 256s is closed by a metal layer 270 and a BARC layer 280. In such... Figure 11B In some of the alternative embodiments shown, no gap is formed below the BARC layer 280.

[0063] refer to Figure 10 and Figures 12A to 12B Method 300 includes block 316, in which the top portion of the metal layer 270 and the metal seed layer 268 above the BARC layer 280 is removed. Figure 12A and Figure 12B The following are respectively shown by Figure 11A and Figure 11B The illustrated embodiment produces an embodiment. In some embodiments, the top portions of the metal layer 270 and the metal seed layer 268 above the top surface of the BARC layer 280 are etched back (or pulled back, for example, by a wet etching process). After the etch back, the topmost surfaces of the metal layer 270 and the metal seed layer 268 may be at the same level as the top surface of the BARC layer 280. Figures 12A to 12B As shown, etch-back removes the top portions of metal layer 270 and metal seed layer 268, while the bottom portions of metal layer 270 and metal seed layer 268 are retained. Etching-back provides a wider entry point for the deposited metal fill layer (to be described), thus avoiding the formation of additional gaps in the metal fill layer (e.g., above the top surface of the horizontal portion of metal layer 270 above silicide layer 266 in the top portion 256a of trench 256). Etching-back can include controlled selective etching of metal layer 270 and metal seed layer 268, while substantially not etching dielectric structure 235 and BARC layer 280. For example, as part of the etch-back process, etchant selectivity can be selected such that the metal is etched at a higher rate than the dielectric. In some embodiments, the etchant includes phosphoric acid (H3PO4), hydrochloric acid (HCl), sulfuric acid (H2SO4), nitric acid (HNO3), hydrogen peroxide (H2O2), acetic acid (CH3COOH), hydrogen fluoride (HF), ammonium hydroxide (NH4OH), water (H2O), or combinations thereof.

[0064] refer to Figure 10 and Figures 13A to 13B Method 300 includes block 318, wherein the BARC layer 280 is removed using processes such as ashing, wet etching, and / or dry etching. Figures 13A to 13B The following are respectively shown by Figure 12A and Figure 12BThe illustrated embodiments are examples of the resulting embodiments. In some embodiments, a wet etching process is used to remove the BARC layer 280. In some embodiments, the etchant includes CH3COOH, HF, NH4OH, H2O, H2O2, or combinations thereof. The duration of the etching process at box 318 may be less than the duration of the etch-back process at box 316. In some embodiments, as shown by the dashed lines, residue 280' of the BARC layer 280 remains on the metal layer 270. Residue 280' can be detected in the common source / drain components (to be described). In some embodiments, residue 280' has a thickness of less than about 3 nm. In some embodiments, no residue remains on the metal layer 270.

[0065] refer to Figure 10 and Figures 14A to 14B Method 300 includes frame 320, wherein a metal filler layer 272 is formed over metal layer 270. Figures 14A to 14B The following are respectively shown by Figures 13A to 13B The examples shown are examples that result from existing examples. (And...) Figure 7A and Figure 7B The differences in the illustrated embodiments include the following. Figure 14A and Figure 14B In this configuration, the top surfaces of the metal layer 270 and the metal seed layer 268 are lower than the top surface of the dielectric structure 235. In some embodiments, the metal layer 270 in the top portion 256a of the trench 256 has a uniform thickness. In some embodiments, the metal filler layer 272 is disposed directly on the top portion of the sidewalls and top surface of the dielectric structure 235. Residue 280' of the BARC layer 280 on the metal layer 270 is optional and is shown in dashed lines.

[0066] refer to Figure 10 and Figures 8 to 9 Method 300 includes a box 322 similar to box 118 in method 100 described above. The differences include the following: Because the metal seed layer 268 on the top surface of the dielectric structure 235 is removed at box 316, the operation at box 322 removes a portion of the metal filler layer 272 on the top surface of the dielectric structure 235. Gaps 256s may exist in the remaining metal filler layer 272', which is caused by… Figure 14A The examples shown are generated. In the embodiment represented... Figure 14B In some other embodiments resulting from the illustrated embodiment, the first source / drain contact 276 is seamless. Gaps in the first source / drain contact 276 can be reduced or avoided by forming the BARC layer 280 and performing an etch-back process, thus reducing the resistance of the first source / drain contact 276. Structure 200' can undergo further processes as described above to form various components and regions.

[0067] Although Figures 2 to 9 and Figures 11A to 14B A stacked transistor structure with GAA transistors is shown, but other examples of semiconductor devices (e.g., conductive parts with long and short leg shapes, conductive parts with high aspect ratios (e.g., greater than about 4), multi-gate devices, stacked transistor structures with any combination of transistors, such as planar transistors, FinFETs, nanosheet transistors, and nanowire transistors) can benefit from the aspects of this disclosure.

[0068] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures. For example, by depositing a metal layer for a common source / drain contact in a trench and etching the top portion of the metal layer as described above, gaps in the common source / drain contact can be reduced or eliminated, thereby reducing the resistance of the common source / drain contact. Consequently, the overall performance of the semiconductor device can be improved.

[0069] In one exemplary aspect, this disclosure relates to a method. The method includes providing a structure. The structure includes: a bottom source / drain component; a bottom contact etch stop layer (CESL) disposed over the bottom source / drain component; a bottom interlayer dielectric (ILD) layer disposed over the bottom CESL; a top source / drain component disposed over the bottom ILD layer; a top CESL disposed over the top source / drain component and the bottom ILD layer; and a top ILD layer disposed over the top source / drain component. The thickness of the bottom CESL is less than the thickness of the bottom ILD layer, and the thickness of the top CESL is less than the thickness of the top ILD layer. The method also includes forming trenches extending in the top ILD layer and the bottom ILD layer, the trenches exposing the top source / drain component and the bottom source / drain component. The method also includes forming silicide layers on the top source / drain components and the bottom source / drain components, performing a metal deposition process to form metal layers on the sidewalls and bottom of the trench, performing a metal self-etching process to remove the top portion of the metal layers, and forming a metal fill layer in the trench.

[0070] In some embodiments, performing a metal deposition process includes flowing a mixture comprising a metal precursor and a reactant onto a structure, and performing a metal self-etching process includes flowing an etching gas comprising the metal precursor over the structure. In some embodiments, the metal precursor includes Mo(CO)6, MoO2(thd)2, MoCl5, MoO2Cl2, [C2H5Ru(CO)2]2, Ru(CO)H2[P(C6H5)3]3, Ru(TMM)(CO)3, and Ru3(CO). 12TICP or a combination thereof. In some embodiments, the metal precursor has a first concentration in the mixture and a second concentration in the etching gas, the first concentration being lower than the second concentration. In some embodiments, the reactant includes a reactive gas, plasma, or a combination thereof. In some embodiments, the metal deposition process is a first metal deposition process, the metal self-etching process is a first metal self-etching process, and the metal layer is a first metal layer; the method further includes performing a second metal deposition process to form a second metal layer over the remaining portion of the first metal layer, and performing a second metal self-etching process to remove the top portion of the second metal layer. In some embodiments, prior to performing the second metal deposition process, the remaining portion of the first metal layer clamps a gap, and the second metal layer fills the gap. In some embodiments, the metal deposition process and the metal self-etching process are performed in the same chamber. In some embodiments, performing the metal self-etching process includes flowing a metal precursor over the structure, the metal precursor reacting with the top portion of the metal layer to form a gas, the gas comprising the metal of the metal layer.

[0071] In another exemplary aspect, this disclosure relates to a method. The method includes providing a structure. The structure includes: a bottom active region including a bottom channel region and a bottom source / drain region adjacent to the bottom channel region; a bottom gate structure located above the bottom channel region; a bottom contact etch stop layer (CESL) located above the bottom source / drain region; a bottom interlayer dielectric (ILD) layer located above the bottom CESL; a top active region including a top channel region and a top source / drain region adjacent to the top channel region; a top gate structure located above the top channel region; a top CESL located above the top source / drain region; and a top ILD layer located above the top CESL. The method also includes forming a trench extending through the top ILD layer, top CESL, top source / drain region, bottom CESL, and bottom ILD layer to expose the bottom source / drain region, providing a metal precursor to the structure to form a metal layer in the trench, forming a bottom anti-reflective coating (BARC) layer over the metal layer and in the top portion of the trench above the top source / drain region, performing an etching process to remove the top portion of the metal layer above the BARC layer, removing the BARC layer, and forming a metal filler layer over the remaining portion of the metal layer and in the trench.

[0072] In some embodiments, the metal precursor and the metal filler layer comprise the same metal. In some embodiments, the BARC layer and the metal layer close gaps in the bottom portion of the trench. In some embodiments, before providing the metal precursor to the structure, the method further includes forming a metal seed layer in the trench, forming a metal layer over the metal seed layer, and performing an etching process to remove the top portion of the metal seed layer above the BARC layer. In some embodiments, the etchant used in the etching process includes H3PO4, HCl, H2SO4, HNO3, H2O2, CH3COOH, HF, NH4OH, H2O, or combinations thereof. In some embodiments, removing the BARC layer leaves a residual BARC layer on the remaining portion of the metal layer.

[0073] In another exemplary aspect, this disclosure relates to a method. The method includes providing a structure including a bottom device and a top device located above the bottom device, forming a trench extending through the top device and into the bottom device. The trench includes a bottom portion having a first width and a top portion having a second width, the first width being smaller than the second width. The method further includes forming a conductive plug in the trench. Forming the conductive plug in the trench includes depositing a metal precursor over the structure to form a metal layer in the top and bottom portions of the trench, performing an etch-back process on the top portion of the metal layer, filling the trench with a metal filler layer, and performing a planarization process on the structure.

[0074] In some embodiments, the bottom device includes a bottom source / drain component and a bottom dielectric layer disposed above the bottom source / drain component, and the top device includes a top source / drain component and a top dielectric layer disposed above the top source / drain component. A conductive plug extends through the top dielectric layer and the bottom dielectric layer and electrically connects the top source / drain component and the bottom source / drain component. The conductivity of the conductive plug is greater than the conductivity of the top source / drain component and the bottom source / drain component. In some embodiments, the method further includes forming a silicide layer on the top source / drain component and the bottom source / drain component and between the top source / drain component and the conductive plug. In some embodiments, performing an etch-back process includes flowing a metal precursor over the structure. In some embodiments, performing an etch-back process includes forming a bottom anti-reflective coating (BARC) layer on the metal layer and in a trench, performing an etching process to remove a top portion of the metal layer, and removing the BARC layer. The top portion of the metal layer is located above the BARC layer.

[0075] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A structure is provided, the structure comprising: Bottom source / drain components; A bottom contact etch stop layer (CESL) is disposed above the bottom source / drain components; A bottom interlayer dielectric (ILD) layer is disposed above the bottom contact etch stop layer, wherein the thickness of the bottom contact etch stop layer is less than the thickness of the bottom interlayer dielectric layer; The top source / drain component is disposed above the bottom interlayer dielectric layer; A top contact etch stop layer is disposed above the top source / drain components and the bottom interlayer dielectric layer; and A top interlayer dielectric layer is disposed above the top source / drain component, wherein the thickness of the top contact etch stop layer is less than the thickness of the top interlayer dielectric layer; Trenches are formed extending in the top interlayer dielectric layer and the bottom interlayer dielectric layer, wherein the trenches expose the top source / drain components and the bottom source / drain components; A silicide layer is formed on the top source / drain component and the bottom source / drain component; a metal deposition process is performed to form a metal layer on the sidewalls and bottom surface of the trench; Perform a metal self-etching process to remove the top portion of the metal layer; and A metal filling layer is formed in the trench.

2. The method according to claim 1, wherein, Performing the metal deposition process involves flowing a mixture comprising a metal precursor and a reactant into the structure, and The metal self-etching process includes causing an etching gas containing the metal precursor to flow over the structure.

3. The method according to claim 2, wherein, The metal precursors include Mo(CO)6, MoO2(thd)2, MoCl5, MoO2Cl2, [C2H5Ru(CO)2]2, Ru(CO)H2[P(C6H5)3]3, Ru(TMM)(CO)3, and Ru3(CO). 12 TICP or a combination thereof.

4. The method according to claim 2, wherein, The metal precursor has a first concentration in the mixture and a second concentration in the etching gas. Wherein, the first concentration is lower than the second concentration.

5. The method according to claim 2, wherein, The reactants include reactive gases, plasma, or combinations thereof.

6. The method according to claim 1, wherein, The metal deposition process is a first metal deposition process, the metal self-etching process is a first metal self-etching process, and the metal layer is a first metal layer. The method further includes: A second metal deposition process is performed to form a second metal layer over the remaining portion of the first metal layer, and A second metal self-etching process is performed to remove the top portion of the second metal layer.

7. The method according to claim 6, wherein, Before the second metal deposition process is performed, the remaining portion of the first metal layer clamps the gap. The second metal layer fills the gap.

8. The method according to claim 1, wherein, The metal deposition process and the metal self-etching process are performed in the same chamber.

9. A method for forming a semiconductor structure, comprising: A structure is provided, the structure comprising: The bottom active region includes a bottom channel region and a bottom source / drain region adjacent to the bottom channel region; A bottom gate structure is located above the bottom channel region; A bottom contact etch stop layer (CESL) is located above the bottom source / drain region; A bottom interlayer dielectric (ILD) layer is located above the bottom contact etch stop layer; The top active region includes a top channel region and a top source / drain region adjacent to the top channel region; A top gate structure is located above the top channel region; The top contact etch stop layer is located above the top source / drain region; and A top interlayer dielectric layer is located above the top contact etch stop layer; A trench is formed extending through the top interlayer dielectric layer, the top contact etch stop layer, the top source / drain region, the bottom contact etch stop layer, and the bottom interlayer dielectric layer to expose the bottom source / drain region; A metal precursor is provided to the structure to form a metal layer in the trench; A bottom antireflective coating (BARC) layer is formed above the metal layer and in the top portion of the trench above the top source / drain region; An etching process is performed to remove the top portion of the metal layer above the bottom anti-reflective coating; Remove the bottom anti-reflective coating; and A metal filler layer is formed over the remaining portion of the metal layer and in the trench.

10. A method for forming a semiconductor structure, comprising: A structure is provided, the structure including a bottom device and a top device located above the bottom device; A trench is formed extending through the top device and into the bottom device, wherein the trench includes a bottom portion having a first width and a top portion having a second width, wherein the first width is smaller than the second width; and Forming a conductive plug in the trench includes: A metal precursor is deposited over the structure to form a metal layer in the top and bottom portions of the trench. An etch-back process is performed on the top portion of the metal layer. A metal filler layer is filled into the trench, and A planarization process is performed on the structure.

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