Semiconductor device and forming method thereof

Abstract

A top layer device of a complementary field effect transistor (CFET) device includes a plurality of first transistors. A first bonding layer is disposed over the top layer device. The first bonding layer includes a first dielectric layer and a plurality of first conductive elements embedded in the first dielectric layer. An underlying device of the CFET includes a plurality of second transistors. A second bonding layer is disposed over the second device. The second bonding layer includes a second dielectric layer and a plurality of second conductive components embedded in the second dielectric layer. Each first conductive component is aligned with and coupled to a respective one of the second conductive components. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs. For example, as device size shrinks, the alignment and bonding between different devices becomes more difficult. If devices are bonded but not properly aligned, device performance may not be optimal.

[0003] Therefore, while conventional methods of bonding IC structures are generally sufficient, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] One embodiment of this application provides a semiconductor device, including:

[0005] A first device, comprising: a plurality of first transistors; and a first bonding layer disposed above the first device, wherein the first bonding layer comprises a first dielectric layer and a plurality of first conductive components embedded in the first dielectric layer, wherein the first bonding layer is part of the middle-of-line (MEoL) interconnect structure of the first device;

[0006] The second device includes: a plurality of second transistors; and a second bonding layer disposed above the second device, wherein the second bonding layer includes a second dielectric layer and a plurality of second conductive components embedded in the second dielectric layer, wherein the second bonding layer is part of the mid-process interconnect structure of the second device, and wherein each of the first conductive components is aligned and coupled to a corresponding one of the second conductive components.

[0007] Another embodiment of this application provides a semiconductor device, including: a top portion of a complementary field-effect transistor (CFET) device, the top portion including a plurality of transistors having a first conductivity type; a bottom portion of the complementary field-effect transistor device, the bottom portion including a plurality of transistors having a second conductivity type different from the first conductivity type; and a bonding structure disposed between the top portion and the bottom portion of the complementary field-effect transistor in a cross-sectional side view, wherein the bonding structure includes at least a first bonding layer and a second bonding layer, the first bonding layer including a plurality of first bonding elements, the second bonding layer including a plurality of second bonding elements, wherein, in the cross-sectional side view, the first bonding elements are perpendicularly aligned with and directly bonded to the second bonding elements, and wherein, in a top view, each of the first bonding elements and the second bonding elements has a periodic distribution.

[0008] This application provides, in another aspect, a method for forming a semiconductor device, comprising: forming a first dielectric layer over a first portion of a complementary field-effect transistor (CFET) device; etching a plurality of first openings in the first dielectric layer; filling the first openings with a first conductive material to form a plurality of first bonding elements in the first openings; forming a second dielectric layer over a second portion of the CFET device; etching a plurality of second openings in the second dielectric layer; filling the second openings with a second conductive material to form a plurality of second bonding elements in the second openings; and electrically coupling the first portion of the CFET device and the second portion of the CFET device together at least partially through the first bonding elements and the second bonding elements. Attached Figure Description

[0009] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1A This is a perspective view of an IC device in the form of FinFET according to various aspects of this disclosure.

[0011] Figure 1B This is a plan view of an IC device in the form of a FinFET according to various aspects of this disclosure.

[0012] Figure 1C This is a cross-sectional side view of an IC device in the form of a GAA device according to various aspects of this disclosure.

[0013] Figure 1D This is a cross-sectional side view of a portion of a complementary field-effect transistor (CFET) according to various aspects of this disclosure.

[0014] Figures 2 to 8 A cross-sectional side view of an IC structure undergoing bonding processes according to various aspects of this disclosure is shown.

[0015] Figure 9 This is a plan view of an IC device according to various aspects of this disclosure.

[0016] Figures 10 to 16 A cross-sectional side view of an IC structure undergoing bonding processes according to various aspects of this disclosure is shown.

[0017] Figure 17 This is a plan view of an IC device according to various aspects of this disclosure.

[0018] Figure 18 This is a block diagram of an IC manufacturing facility based on various aspects of this disclosure.

[0019] Figure 19 This is a flowchart illustrating a method for bonding IC devices according to various aspects of this disclosure. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components may be formed between the components. Furthermore, for the convenience of describing the relationship between one component and another, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially relative terms are intended to cover different orientations of devices including components. Also, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., the term is intended to cover values ​​within a reasonable range including the described value, such as within + / - 10% of the described value or other values ​​understood by those skilled in the art. For example, the term “about 5 nm” covers a size range from 4.5 nm to 5.5 nm.

[0022] This disclosure generally relates to semiconductor manufacturing, and more specifically, to the bonding alignment of IC structures including field-effect transistors (FETs) such as three-dimensional fin field-effect transistors (FinFETs) or gate-all-around (GAA) devices. In this regard, FinFET devices are fin field-effect transistor devices, and GAA devices are multi-channel field-effect transistor devices. Both FinFET and GAA devices have recently gained increasing popularity in the semiconductor industry because they offer several advantages over conventional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (e.g., “planar” transistor devices). These advantages can include better chip area efficiency, improved carrier mobility, and manufacturing processes compatible with the fabrication processes of planar devices. Therefore, it may be desirable to design integrated circuit (IC) chips using either FinFET or GAA devices for parts or the entire IC chip.

[0023] However, despite the advantages of FinFET and / or GAA devices, certain challenges may still exist in IC applications employing FinFET or GAA devices. For example, modern IC manufacturing may require bonding different IC structures together. However, as device dimensions shrink proportionally, alignment between different IC structures can become more difficult. If devices are bonded but not properly aligned, device performance may not be optimal.

[0024] To address the problems discussed above, this disclosure employs an electrically assisted alignment scheme to improve the bonding alignment between different IC structures. In this regard, Figures 1A to 1D Example types of transistors that may be used as bonding targets for IC devices are shown, and Figures 2 to 17 Various aspects of the joint alignment scheme are shown, as discussed in more detail below.

[0025] Now for reference Figures 1A to 1D These figures illustrate the basic structures of example FinFET and GAA devices. For example, Figure 1A and Figure 1B Three-dimensional perspective and top view of portions of an integrated circuit (IC) device 100 are shown, respectively. The IC device 100 may be an intermediate device manufactured during the processing of the IC or portions thereof, and may include static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. Note that unless otherwise required, this disclosure is not limited to any particular number of devices or device regions, or any specific device configuration. For example, although the shown IC device 100 is a three-dimensional FinFET device, the concepts of this disclosure can also be applied to planar FET devices or GAA devices.

[0026] Now for reference Figure 1A and Figure 1B The figures show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 100, respectively. The IC device 100 may be an intermediate device manufactured during the processing of the IC or a portion thereof, and may include static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells.

[0027] exist Figure 1A and Figure 1BIn the example shown, IC device 100 is a three-dimensional fin FET (FinFET) device. In this respect, FinFET devices are fin field-effect transistor devices that have recently become increasingly popular in the semiconductor industry because they offer several advantages over traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (such as "planar" transistor devices). These advantages can include better chip area efficiency, improved carrier mobility, and manufacturing processes compatible with those of planar devices. Therefore, it may be desirable to use FinFET devices in the design of integrated circuit (IC) chips for parts or the entire IC chip.

[0028] refer to Figure 1A The IC device 100 includes a substrate 110. The substrate 110 may include elemental (single-element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Optionally, the substrate 110 may include multiple material layers with similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions (such as source / drain regions) may be formed in or on the substrate 110. Depending on design requirements, the doped regions can be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron). The doped regions can be formed directly on the substrate 110 in a p-well structure, n-well structure, double-well structure, or using a bump structure. The doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0029] A three-dimensional active region comprising nanostructures is formed on substrate 110. The active region is an elongated fin-like structure projecting upward beyond substrate 110. Hereinafter, the projecting structure 120 may be interchangeably referred to as fin structure 120. Fin structure 120 may be fabricated using a suitable process including photolithography and etching processes. The photolithography process may include forming a photoresist layer on substrate 110, exposing the photoresist to form a pattern, performing a post-exposure baking process, and developing the photoresist to form a masking element (not shown) comprising the photoresist. The masking element is then used to etch grooves in substrate 110, leaving fin structure 120 on substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, fin structure 120 may be formed by a dual-patterning or multi-patterning process. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. As an example, a layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 120.

[0030] The IC device 100 also includes a source / drain component 122 formed over the fin structure 120. The source / drain component 122 may include an epitaxial layer epitaxially grown on the fin structure 120. The IC device 100 also includes an isolation structure 130 formed over the substrate 110. The isolation structure 130 electrically isolates various components of the IC device 100. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 130 is formed by etching trenches in the substrate 110 during the formation of the fin structure 120. The trenches can then be filled with the aforementioned isolation material, followed by a chemical mechanical polishing (CMP) process. Other isolation structures, such as field oxide, localized oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as the isolation structure 130. Optionally, the isolation structure 130 may include a multilayer structure, for example, having one or more thermal oxide lining layers.

[0031] IC device 100 also includes a gate structure 140 formed over the fin structure 120 in the channel region of each fin structure 120 and bonded to the fin structure 120 on three sides. The gate structure 140 may be a dummy gate structure (e.g., comprising an oxide gate dielectric and a polysilicon gate electrode), or it may be an HKMG structure comprising a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown herein, the gate structure 140 may include additional material layers, such as an interface layer, a capping layer, other suitable layers, or combinations thereof, situated above the fin structure 120.

[0032] refer to Figure 1B Multiple fin structures 120 are longitudinally oriented along the X direction, and multiple gate structures 140 are longitudinally oriented along the Y direction (i.e., substantially perpendicular to the fin structures 120). In many embodiments, the IC device 100 includes additional components such as gate spacers disposed along the sidewalls of the gate structures 140, a hard mask layer disposed above the gate structures 140, and many other components.

[0033] Figure 1C A schematic cross-sectional side view of a portion of an IC device 5 manufactured according to embodiments of the present disclosure is shown, wherein the IC device 5 is a gate-all-around (GAA) device and may be referred to hereinafter as GAA device 5. It should be understood that in some embodiments, the GAA device 5 may be an NFET, or in other embodiments it may be a PFET.

[0034] refer to Figure 1C The cross-sectional view of GAA device 5 is taken along the XZ plane, where the X direction (and...) Figure 1A The X direction (which is the same as the X direction in the equation) is horizontal, and the Z direction (which is the same as the Z direction in the equation) is horizontal. Figure 1A The Z-direction is the same in both directions, and is the vertical direction. The GAA device 5 includes a fin structure 10, which may be similar to the fin structure 120 discussed above. In some embodiments, the fin structure 10 includes silicon. The GAA device 5 includes a source / drain component 20, which may be similar to the source / drain component 122 discussed above. In embodiments where the GAA device 5 is an NFET, the source / drain component 20 includes silicon-phosphorus (SiP). In embodiments where the GAA device 5 is a PFET, the source / drain component 20 includes silicon-germanium (SiGe).

[0035] GAA device 5 includes multiple channels, such as Figure 1CThe channels 30-33 are shown. Each of the channels 30-33 comprises a semiconductor material, such as silicon or a silicon compound. The channels 30-33 are nanostructures (e.g., having dimensions in the range of a few nanometers), and each channel may also have an elongated shape and extend in the X direction. In some embodiments, each of the channels 30-33 may have a nanowire shape, a nanosheet shape, a nanotube shape, etc. The cross-sectional profile of the nanowire, nanosheet, or nanotube may be circular / round, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0036] In some embodiments, the lengths of channels 30-33 (e.g., measured in the X direction) may differ from one another. For example, the length of channel 30 may be less than the length of channel 31, the length of channel 31 may be less than the length of channel 32, and the length of channel 32 may be less than the length of channel 33. In some embodiments, each channel 30-33 may not have a uniform thickness.

[0037] In some embodiments, the spacing (e.g., measured in the Z direction) between channels 30-33 (each channel from an adjacent channel) is in the range of about nanometers (nm) to about 12 nm. In some embodiments, the thickness (e.g., measured in the Z direction) of each channel 30-33 is in the range of about 5 nm to about 12 nm. In some embodiments, the width (e.g., in the Z direction) of each channel 30-33 is in the range of about 5 nm to about 12 nm. Figure 1A (Measured in the Y direction) in the range of approximately 15 nm to approximately 150 nm. Multiple interface layers (IL) 40 may also be formed on the upper and lower surfaces of channels 30-33.

[0038] The GAA device 5 also includes a gate structure disposed above and between channels 30-33. The gate structure may include a gate dielectric layer 50. In some embodiments, the gate dielectric layer 50 includes a high-k gate dielectric. The gate structure also includes one or more power function metal layers 60. In embodiments where the GAA device 5 is an NFET, the one or more power function metal layers 60 include an N-type power function metal layer, such as TiAlC. In embodiments where the GAA device 5 is a PFET, the one or more power function metal layers 60 include a P-type power function metal layer, such as TiN.

[0039] The gate structure also includes fill metal 80. In the portion of the gate structure formed above channels 30-33, fill metal 80 is formed above one or more function metal layers 60. The one or more function metal layers 60 are U-shaped and enclose the fill metal 80, and the gate dielectric layer 50 is also U-shaped and encloses the one or more function metal layers 60. In the portion of the gate structure formed between channels 30-33, fill metal 80 is circumferentially surrounded by one or more function metal layers 60 (in the cross-sectional view) and then circumferentially surrounded by the gate dielectric layer 50. It should be understood that the gate structure may also include an adhesive layer formed between the one or more function metal layers 60 and the fill metal 80 to increase adhesion. However, for simplicity, such an adhesive layer is not specifically shown herein.

[0040] The GAA device 5 also includes a gate spacer 90 and an internal spacer 95 disposed on the sidewalls of the gate dielectric layer 50. The internal spacer 95 is also disposed between channels 30-33. The gate spacer and the internal spacer 95 may include a dielectric material, such as a low-k material, such as SiOCN, SiON, SiN, or SiOC.

[0041] The GAA device 5 also includes a source / drain contact 96 formed above the source / drain component 20. The source / drain contact 96 may include a conductive material such as cobalt, copper, aluminum, tungsten, or a combination thereof. The source / drain contact 96 is surrounded by barrier layers, such as barrier layers 97A and 97B, which help prevent or reduce material diffusion from and into the source / drain contact 96. In some embodiments, barrier layer 97A comprises TiN, and barrier layer 97B comprises SiN. A silicide layer 98 may also be formed between the source / drain component 20 and the source / drain contact 96 to reduce the source / drain contact resistance. In some embodiments, the silicide layer 98 may comprise a metal silicide material, such as cobalt silicide.

[0042] GAA device 5 also includes an interlayer dielectric (ILD) 99. ILD 99 provides electrical isolation between the various components of GAA device 5, such as between the gate structure and the source / drain contacts 96.

[0043] GAA devices can also offer advantages such as better chip area efficiency and improved carrier mobility. Therefore, advanced IC chips can also be implemented using GAA devices. However, it should be understood that, unless otherwise required, this disclosure is not limited to any particular number of devices or device regions, or any specific device configuration. For example, while FinFET devices or GAA devices are described as potential transistors that can be used to implement IC chips or portions thereof, the concepts of this disclosure, discussed in more detail below, can also be applied to IC chips implemented using planar FET devices.

[0044] Figure 1D This is a cross-sectional side view of a portion of a complementary field-effect transistor (CFET) 200 shown along the XZ plane. In some embodiments, the portion of CFET 200 shown is a top-level device, which may include one or more GAA transistors (similar to those referenced above). Figure 1C The GAA device discussed below (5). In the bonding process of this disclosure discussed below, the top-level device can be bonded to the bottom-level device of the CFET. However, it should be understood that in some embodiments, the top-level device and the bottom-level device may have substantially similar or even identical structures (except for the conductivity type). In other embodiments, the top-level device may include an n-type transistor, while the bottom-level device may include a p-type transistor, and vice versa, but the remainder of their respective device configurations may be substantially similar or identical. In any case, it should be understood that, unless otherwise stated, the description of the top-level device of the CFET 200 also applies to the bottom-level device.

[0045] refer to Figure 1D A portion of the CFET 200 includes multiple semiconductor layers, such as semiconductor layer 210. The semiconductor layers 210 may be arranged perpendicularly to each other in a stack, and they may collectively serve as the channel components for the GAA transistors of a portion of the CFET 200. In some embodiments, each of the semiconductor layers 210 comprises silicon. In other embodiments, the semiconductor layers 210 may comprise another suitable type of semiconductor material.

[0046] This portion of the CFET 200 also includes multiple gate dielectric layers, such as gate dielectric layer 220. In some embodiments, each of the gate dielectric layers 220 includes a high-k dielectric layer, which may be a dielectric material with a dielectric constant greater than that of silicon dioxide (k≈3.9). For example, the high-k dielectric layer may use HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO. x The gate dielectric layer 220 may be implemented using ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, or combinations thereof. In the illustrated embodiment, the gate dielectric layer 220 may include a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer. It should be understood that the gate dielectric layer 220 may also include an interface layer comprising a dielectric material such as SiO2, SiGeO2, etc. xHfSiO, SiON, other dielectric materials or combinations thereof.

[0047] A portion of the CFET 200 also includes multiple gate electrode layers, such as gate electrode layer 230. Gate electrode layer 230 is formed on gate dielectric layer 220 and includes a conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or combinations thereof. In some embodiments, each of gate electrode layers 230 includes a work function layer and a filler metal layer. The work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function). The function layer includes function metals and / or alloys thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. Meanwhile, the filler metal layer is a conductive layer formed above the function layer, and it may include materials such as Al, W, Cu, Ti, Ta, TiN, TaN, polycrystalline silicon, alloys thereof, or combinations thereof. In some embodiments, the gate electrode layer 230 may also include a barrier layer. The barrier layer includes materials that prevent or eliminate the diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (such as between the function layer and the filler metal layer). In some embodiments, the barrier layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof.

[0048] The gate dielectric layer 220 and the gate electrode layer 230 can be formed via a gate replacement process, wherein the dummy gate structure is replaced by a functional gate structure comprising the gate dielectric layer 220 and the gate electrode layer 230. The location and / or size of the dummy gate structure (and therefore the functional gate structure) can be at least partially defined by a hard mask layer 240, which may include a dielectric material such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, or combinations thereof. In some other embodiments, the hard mask layer 240 may include metals and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HfO2), aluminum zirconium oxide (e.g., ZrAlO), or combinations thereof. It should be understood that the gate stack (or gate structure) can be formed from the gate dielectric layer 220 and the gate electrode layer 230.

[0049] Gate spacer 250 is disposed along the sidewall of a portion of the gate stack immediately adjacent to hard mask layer 240, and inner spacer 260 is disposed along the sidewall of the remaining portions of the gate stack. Gate spacer 250 and inner spacer 260 may comprise dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof; however, it should be understood that gate spacer 250 and inner spacer 260 may comprise different types of materials and / or different configurations (e.g., different numbers of layers). For example, in some embodiments, gate spacer 250 may comprise more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. Each set of spacers may have different compositions.

[0050] This portion of the CFET 200 also includes a plurality of source / drain regions 270 disposed on opposite sides of the gate stack. The source / drain regions 270 may be epitaxially grown, and they may be doped with n-type and / or p-type dopants. For example, the source / drain regions 270 may comprise silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C:P epitaxial source / drain). As another example, the source / drain regions 270 may comprise silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B epitaxial source / drain). The source / drain regions 270 may also include materials and / or dopants that achieve desired tensile and / or compressive stresses in adjacent channel regions (e.g., formed by semiconductor layer 210). As used herein, source / drain region 270 may refer to the source of a device (e.g., a particular transistor), the drain of a device, or the source and / or drain of multiple devices.

[0051] This portion of the CFET 200 also includes source / drain contacts, such as source / drain contacts 275, which are vertically disposed above or below the source / drain region 270 to provide electrical connection to the source / drain region 270. In some embodiments, at least some of the source / drain contacts 275 may be at least partially surrounded by a barrier layer or liner layer 278.

[0052] This portion of the CFET 200 may also include conductive vias, such as conductive via 280, which are vertically disposed above or below the source / drain contact 275 to further provide electrical connection to the source / drain contact 275 and by extending to electrically connect to the source / drain region 270. This portion of the CFET 200 may also include gate contacts (such as gate contact 285) and conductive vias (such as conductive via 290) configured to provide electrical connection to a particular gate structure. Each of the source / drain contact 275, gate contact 285, and conductive vias 280 and 290 may include one or more types of conductive materials, such as tungsten, aluminum, copper, cobalt, ruthenium, and / or combinations thereof.

[0053] This portion of the CFET 200 may also include an electrical isolation layer / structure configured to provide electrical isolation between various microelectronic components, such as gate electrode layer 230 or source / drain regions 270. For example, a portion of the CFET 200 may include an interlayer dielectric (ILD) 295 and one or more dielectric layers, such as dielectric layers 297 and 298. For example, the ILD and / or dielectric layers 297-298 may include dielectric materials such as silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), degelatin, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) materials, polyimide, other dielectric materials, or combinations thereof. ILD 295 can also be surrounded by a contact etch stop layer (CESL), which can have a different material composition than ILD 295.

[0054] This portion of the CFET 200 may also include bonding pads 299. Bonding pads 299 may comprise conductive materials such as Al, Ag, Au, Cu, Co, Ir, Mo, Ni, Pt, Ru, Si, Ta, Tu, W, Zr, or combinations thereof. Each bonding pad 299 may be electrically coupled to one or more other conductive components, such as conductive vias 280. Thus, bonding pads 299 can be used to provide electrical connections to microelectronic components of the CFET 200, such as electrical connections to the source / drain regions 270. Although not specifically shown here for simplicity, it should be understood that bonding pads similar to bonding pads 299 may also be implemented to provide electrical connections to the gate structure of the CFET 200.

[0055] For simplicity, this article does not discuss other components of the CFET 200 in detail. It should also be understood that... Figure 1DThe portion of CFET 200 shown is an embodiment of the top-level device, to which a bottom-level device having a substantially similar or identical structure may be bonded to form the CFET. In some embodiments, the top-level device may include n-type transistors, while the bottom-level device may include p-type transistors, or vice versa. In other embodiments, the top-level device and the bottom-level device may include the same type of transistors (e.g., both may include n-type transistors or both may include p-type transistors).

[0056] Regardless of how the transistors in the IC are implemented Figures 1A to 1B FinFET, Figure 1C GAA devices or Figure 1D CFET devices, as should be understood, can all benefit from the concepts disclosed herein. For example, the fabrication and / or packaging of IC devices may involve one or more bonding processes. Taking CFET devices as an example, a monolithic CFET architecture can fabricate top-layer and bottom-layer devices on the same wafer. However, the high aspect ratio of fabricating monolithic CFET devices leads to process challenges related to etching, thin film, diffusion, etc. To address the challenges of monolithic CFET fabrication, hybrid bonding can be used to form parallel CFET devices, where... Figure 1D The top-level device corresponding to a portion of the CFET 200 shown is bonded to the bottom-level device of the CFET, which may have a similar structure to the top-level device. In this hybrid bonding process, the conductive via 280 of the top-level device of the CFET 200 can be bonded to a similar conductive via of the bottom-level device of the CFET 200, the conductive via 290 of the top-level device of the CFET 200 can be bonded to a similar conductive via of the bottom-level device of the CFET 200, and the dielectric layer 298 of the top-level device of the CFET can be bonded to a similar dielectric layer of the bottom-level device of the CFET 200.

[0057] However, joining conductive vias together in this hybrid bonding process can involve a relatively high degree of alignment. If the conductive vias (e.g., conductive via 290 of the top device of CFET 200 and the corresponding conductive via from the bottom device of CFET 200) are not properly aligned, the intended electrical connection between the top and bottom devices may be interrupted, potentially leading to malfunctions (or at least degradation) in the operation of CFET 200. Furthermore, conductive vias 280 and / or 290 may not have a periodic distribution (e.g., in a planar top view). Therefore, pattern uniformity may not be optimal, and / or the planarization of the surfaces of the bonded top and bottom devices may also become problematic, potentially further degrading the quality of the bonding as part of the parallel CFET fabrication.

[0058] To address the issues discussed above, this disclosure implements one or more bonding layers (e.g., as part of a bonding structure) on the top and bottom devices of the CFET, wherein hybrid bonding is achieved by bonding the bonding layers together, as discussed in more detail below.

[0059] Figures 2 to 8 A series of schematic partial cross-sectional side views (e.g., along the XZ plane) according to different embodiments of the present disclosure are shown, corresponding to the process flow for bonding different IC structures together. For reasons of consistency and clarity, Figures 1A to 1D and Figures 2 to 8 Similar components appearing in the same context can be marked as identical.

[0060] refer to Figure 2 This shows a cross-sectional side view of the top-level device 300 of the CFET. The top-level device 300 can be compared with the one mentioned above. Figure 1D The top-level device of the CFET 200 discussed is basically similar. However, with Figure 2 Compared to the top-level device 300 shown, Figure 1D The top-level device of the CFET 200 is vertically flipped up and down (in the Z direction). In other words, in Figure 1D In the top-layer device of the CFET 200, the bonding pad 299 faces upward and the dielectric layer 298 faces downward. Figure 2 In the top-layer device 300, the bonding pads 299 face downwards, and the dielectric layer 298 faces upwards. In other words, the side 310 of the top-layer device 300 is... Figure 2 The middle is facing upward in the Z direction, and the side 311 of the top layer device 200 is in Figure 2 The center is facing downwards in the Z direction.

[0061] like Figure 2 As shown, the top-level device 300 includes not only transistor components such as channels (e.g., formed by semiconductor layer 210), source / drain regions 270, and gates (e.g., including gate dielectric layer 220 and gate electrode layer 230), but also various interconnect structures. For example, the top-level device 300 includes a back-to-line (BEoL) interconnect structure 320 located above side 311 of the transistor components, and a middle-to-line (MEoL) interconnect structure 321 located above side 310 of the transistor components.

[0062] The BEoL interconnect structure 320 may include one or more dielectric layers (such as dielectric layer 298) and conductive components, such as conductive vias 280 and / or bonding pads 299, which extend at least partially perpendicularly through the dielectric layers in the Z direction. For example, in some embodiments, dielectric layer 298 may be formed over the gate structure and over source / drain contacts 275 on side 311. One or more etching processes may then be performed to etch trenches in dielectric layer 298, and the trenches may be filled with one or more conductive materials via one or more deposition processes to form conductive vias. Similarly, bonding pads 299 may be formed by forming another dielectric layer 298 over conductive vias 280 on side 311, etching openings in dielectric layer 298, and filling the etched openings with one or more conductive materials to form bonding pads 299.

[0063] The formation of the MEoL interconnect structure 321 may involve a similar process to that used to form the BEoL interconnect structure 320. For example, an ILD 295 may be formed above side 310 of the transistor assembly, and an etching process may be performed to etch openings through the ILD 295, followed by filling the openings with one or more conductive materials through one or more deposition processes to form source / drain contacts 275, conductive vias, and conductive vias 290. These conductive components may be formed at different stages. For example, the source / drain contacts 275 may be formed first, followed by the formation of conductive vias 280 (used as source / drain vias) and 290 (used as gate vias). As will be discussed in more detail below, one aspect of this disclosure relates to performing a hybrid bonding process using the MEoL interconnect structure 321 instead of the BEoL interconnect structure 320. In other words, the top-level device 300 will be bonded to the bottom-level device (discussed below) via the MEoL interconnect structure 321 instead of the BEoL interconnect structure 320.

[0064] A dielectric layer 330 is formed over the MEoL interconnect structure 321 on side 310 of the top-layer device 300. For example, a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)) can be performed to form the dielectric layer 330 over the surfaces of the dielectric layer 298 and the conductive vias 280 and 290. In various embodiments, the dielectric layer 330 may include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, AlO x AlON, AlN, or combinations thereof.

[0065] Now for reference Figure 3One or more etching processes 340 are performed on the top-layer device 300 from side 310 to form a plurality of openings, such as openings 350 and 351, in the dielectric layer 330. For example, in some embodiments, the one or more etching processes 340 may include one or more dry etching processes, or in some other embodiments, one or more wet etching processes, to remove portions of the dielectric layer 330. As a result, openings 350 and 351 expose the upper surfaces of conductive vias 290 and 280 to side 310, respectively. Note that opening 350 may be wider in the X direction than conductive via 290, which may facilitate alignment between conductive via 290 and the corresponding conductive via of the underlying device, as will be discussed in more detail below.

[0066] It should also be noted that openings 350 and 351 do not need to have the same (or even similar) dimensions in the X direction. Instead, one can be much wider than the other. For example, opening 351 can be much wider than opening 350 in the X direction. The wider width of opening 351 can be configured to accommodate the location of another conductive via of a lower-level device to be coupled to the top-level device 300, which may not be aligned with conductive via 280, as will be discussed in more detail below.

[0067] Now for reference Figure 4 One or more deposition processes 370 can be performed on the top-layer device 300 to form bonding elements 380 and 381 in openings 350 and 351, respectively. In some embodiments, the one or more deposition processes 370 may include CVD, PVD, ALD, or combinations thereof. In some embodiments, the deposited material may include Al, Ag, Au, Cu, Co, Ir, Mo, Ni, Pt, Ru, Si, Ta, Tu, W, Zr, or combinations thereof. Table 1 includes a list of candidate materials for dielectric layer 330 and bonding elements 380-381, along with some associated physical properties:

[0068] Table 1

[0069]

[0070] It should be understood that planarization processes (such as CMP processes) can be performed on the deposited material to planarize the bonding elements 380 and 381 with the upper surface of the dielectric layer 330, for example, until the upper surfaces of the bonding elements 380-381 are substantially coplanar with the upper surface of the dielectric layer 330. It should also be understood that in some embodiments, one or more deposition processes 370 may also form a liner (e.g., as a barrier layer) around the bonding elements 380 and 381. However, for simplicity, the liner layer is not specifically shown here. It should be understood that the dielectric layer 330 and the bonding elements 380-381 can also be considered as part of the MEoL interconnect structure 321 of the top-layer device 300.

[0071] refer to Figure 5 The image shows a cross-sectional side view of the underlying device 400 of the CFET. The underlying device 400 may be structurally similar to the reference above. Figures 2 to 4 The top-level device 300 is discussed. However, in some embodiments, the transistors of the top-level device 300 and the transistors of the bottom-level device 400 have different types of conductivity. For example, in some embodiments, the top-level device 300 may include n-type transistors, while the bottom-level device 400 may include p-type transistors. Furthermore, the locations of various microelectronic components in the top-level device 300 and the bottom-level device 400 may differ. For example, in the top-level device 300, conductive vias 280 (e.g., source / drain vias) and conductive vias 290 (e.g., gate vias) may be relatively far apart in the X direction. In contrast, in the bottom-level device 400, conductive vias 280 (e.g., source / drain vias) and conductive vias 290 (e.g., gate vias) may be closer to each other in the X direction.

[0072] like Figure 5 As shown, the bonding pads 299 of the bottom device 400 face downwards, and the dielectric layer 298 faces upwards. In other words, the side 410 of the bottom device 400 is... Figure 5 The middle is facing upward in the Z direction, and the side 411 of the bottom device 400 is in Figure 5 The Z-axis faces downwards. Similar to the top-level device 300 discussed above, the bottom-level device 400 also includes a BEoL interconnect structure 420 and a MEoL interconnect structure 421. The BEoL interconnect structure 420 is located above the transistor assembly side 411 of the bottom-level device 400, and the MEoL interconnect structure 421 is located above the transistor assembly side 410 of the bottom-level device 400. Similar to the top-level device 300, the formation of the BEoL interconnect structure 420 and MEoL interconnect structure 421 for the bottom-level device 400 may also include various deposition processes for forming a dielectric layer, etching processes for etching trenches in the dielectric layer, and filling the trenches with conductive material to form various conductive components, such as the conductive via 280 and bonding pads of the BEoL interconnect structure 420, and the source / drain contacts 275, conductive via 280, and conductive via 290 of the MEoL interconnect structure 421. Similarly, one aspect of this disclosure relates to bonding the bottom device 400 to the top device 300 via MEoL interconnect structure 421 instead of via BEoL interconnect structure 420.

[0073] A dielectric layer 430 is formed over the MEoL interconnect structure 421 on side 410 of the underlying device 400. For example, deposition processes such as CVD, PVD, or ALD can be performed to form the dielectric layer 430 over the surfaces of the dielectric layer 298 and the conductive vias 280 and 290. In various embodiments, the dielectric layer 430 may include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, AlO x AlON, AlN, or combinations thereof. In some embodiments, the material list may include the same materials listed in Table 1 above for dielectric layer 330. In some embodiments, dielectric layer 430 formed on bottom device 400 may have the same dielectric material composition as dielectric layer 330 formed on top device 300.

[0074] Now for reference Figure 6 One or more etching processes 440 are performed on the underlying device 400 from side 410 to form a plurality of openings, such as openings 450 and 451, in the dielectric layer 430. For example, in some embodiments, the one or more etching processes 440 may include one or more dry etching processes, or in some other embodiments, one or more wet etching processes, to remove portions of the dielectric layer 430. As a result, openings 450 and 451 expose the upper surfaces of conductive vias 290 and 280 to side 410, respectively. Note that opening 450 may be wider than conductive via 290 in the X direction, which may facilitate the connection of conductive vias 290 and 280. Figure 5 The alignment between the conductive vias of the underlying device 400, as will be discussed in more detail below.

[0075] It should also be noted that openings 450 and 451 do not need to have the same (or even similar) dimensions in the X direction. Instead, one can be much wider than the other. For example, opening 451 can be much wider than opening 450 in the X direction. The wider width of opening 451 can be configured to accommodate the location of the conductive via 280 of the top-layer device 300 (see...). Figure 4 The conductive via 280 will be bonded to the underlying device 400 in a subsequent process.

[0076] Now for reference Figure 7One or more deposition processes 470 can be performed on the underlying device 400 to form bonding elements 480 and 481 in openings 450 and 451, respectively. In some embodiments, the one or more deposition processes 470 may include CVD, PVD, ALD, or combinations thereof. In some embodiments, the deposited material may include Al, Ag, Au, Cu, Co, Ir, Mo, Ni, Pt, Ru, Si, Ta, Tu, W, Zr, or combinations thereof. In some embodiments, the deposited material may include candidate materials for bonding elements listed in Table 1 above. In some embodiments, the deposited material forming bonding elements 480 and 481 of the underlying device 400 has the same material composition as bonding elements 380 and 381 of the top device 300. It should be understood that a planarization process (such as a CMP process) may be performed on the deposited material to planarize bonding elements 480 and 481 with the upper surface of dielectric layer 430, for example, until the upper surfaces of bonding elements 480-481 are substantially coplanar with the upper surface of dielectric layer 430. It should also be understood that in some embodiments, one or more deposition processes 470 may also form a liner (e.g., as a barrier layer) around the bonding elements 480 and 481. However, for simplicity, the liner layer is not specifically shown here. It should be understood that the dielectric layer 430 and the bonding elements 480-481 can also be considered as part of the MEoL interconnect structure 421 of the underlying device 400.

[0077] Now for reference Figure 8 A bonding process 490 is performed to bond the top-layer device 300 and the bottom-layer device 400 together to form a parallel CFET device 500. As part of the bonding process 490, the top-layer device 300 is vertically flipped so that side 310 ( Figure 5 (Middle-up) Figure 8 The top layer device 300 is now facing the bottom layer device 400 (e.g., facing the bottom device 400). At this point, the MEoL interconnect structure 321 of the top layer device 300 is now facing the MEoL interconnect structure 421 of the bottom layer device 400.

[0078] Then, dielectric layers 330 and 430 are bonded together, as are bonding elements 380-480 and bonding elements 381-481. The bonding of bonding elements 380 and 480 establishes an electrical connection between the conductive vias 290 of the top-layer device 300 and 290 of the bottom-layer device 400, and the bonding of bonding elements 381 and 481 establishes an electrical connection between the conductive vias 280 of the top-layer device 300 and 280 of the bottom-layer device 400. In this way, the top-layer device 300 and the bottom-layer device 400 are electrically coupled together. Note that dielectric layer 330 and bonding elements 380-381 can be considered as part of the MEoL interconnect structure 321 of the top-layer device 300, and dielectric layer 430 and bonding elements 480-481 can be considered as part of the MEoL interconnect structure 421 of the bottom-layer device 400. Therefore, it can be said that the top-level device 300 and the bottom-level device 400 are joined together via their respective MEoL interconnect structures 321 and 421 rather than via their BEoL interconnect structures 320 and 420.

[0079] Notice, Figure 8 An enlarged cross-sectional side view of portion 495 of the top-layer device 300 and the bottom-layer device 400 joined together is also shown. The enlarged view includes the source / drain regions 270, source / drain contacts 275, and conductive vias 280 of the top-layer device 300 and the bottom-layer device 400, as well as bonding elements 381 and 481, to provide a better visual understanding of how the bonding scheme of this disclosure is implemented. For simplicity, other components are not specifically shown in the enlarged view.

[0080] The bonding scheme disclosed herein offers inherent advantages. For example, if the top-layer device 300 is bonded to the bottom-layer device 400 without a bonding structure in between (consisting of dielectric layers 330 and 430 and bonding elements 380-381 and 480-481), alignment between the various components of the top-layer device 300 and the bottom-layer device 400 may become problematic. Figure 8 As shown, there is a significant lateral offset in the X direction between the conductive vias 280 of the top-layer device 300 and the conductive vias 280 of the bottom-layer device 400. This lateral offset may be due to the IC design or may be the result of suboptimal manufacturing processes that occur prior to the bonding process 490. In either case, the lateral offset between these conductive vias 280 makes their bonding (and the intended electrical connection) difficult or even impossible in some situations.

[0081] Here, the implementation of bonding elements 381 and 481 can accommodate the lateral offset between the conductive vias 280. In other words, bonding element 381 is long enough that its "right" portion (such as...) Figure 8(As shown) can extend to the bottom surface of the conductive via 280 of the top-layer device 300 and make electrical contact with the bottom surface of the conductive via 280 of the top-layer device 300. Simultaneously, the bonding element 481 is long enough that its "left" portion can extend to the top surface of the conductive via 280 of the bottom-layer device 400 and make electrical contact with the top surface of the conductive via 280 of the bottom-layer device 400. Since bonding elements 381 and 481 are much wider than the corresponding conductive vias 280 to which they are electrically coupled, the bonding of bonding elements 381 and 481 inherently has a larger tolerance. In other words, even if bonding elements 381 and 481 are not perfectly vertically aligned, their large size inherently makes it very likely that at least a portion of bonding element 381 will make electrical and physical contact with another portion of bonding element 481, allowing an electrical connection to be established between the conductive vias 280 of the top-layer device 300 and the bottom-layer device 400.

[0082] The advantages discussed above can also be applied to coupling elements 380 and 480, albeit to a lesser extent. For example, due to opening 350 (see... Figure 3 ) and 450 (see Figure 6 The vias 350 and 450 are formed to be wider than the conductive vias 290 of the top-layer device 300 and the bottom-layer device 400, respectively. Therefore, the bonding elements 380 and 480 filling these openings are also wider (in the X direction) than the conductive vias 290 of the top-layer device 300 and the bottom-layer device 400, respectively. Thus, the margin for aligning the bonding elements 380 and 480 together is still greater than aligning the conductive vias 290 of the top-layer device 300 and the bottom-layer device 400 together. In other words, while a sufficiently large lateral offset between the conductive vias 290 may result in electrical discontinuities between them, the same amount of lateral offset can still allow the bonding elements 380 and 480 to bond together and establish physical and electrical contact with each other, which in turn establishes an electrical connection between the conductive vias 290 of the top-layer device 300 and the bottom-layer device 400.

[0083] Figure 9 A top view of an example wafer 600 on which multiple IC dies 610 are implemented is shown. The top view is defined by an X-direction and a Y-direction perpendicular to the X-direction. The IC dies 610 are arranged in multiple rows along the X-direction and in multiple columns along the Y-direction. Although Figure 9 Each row and column in the diagram includes three such IC dies 610, but it should be understood that this is only for simplicity and each row and column may include a greater number of IC dies 610.

[0084] In some embodiments, each IC die 610 may include a parallel CFET device 500, as discussed above, which is formed by bonding a top-level device 300 and a bottom-level device 400 together. For example, a cut line A-A' is shown on one of the IC dies 610, and it should be understood that... Figure 8 A cross-sectional side view can be obtained corresponding to such a cutting line A-A'. It should also be understood that a planar top view can be obtained along a horizontal plane that cuts across (e.g., intersects with) the joining elements 480 and 481. In other words, Figure 9 The geometric pattern shown may include a top view of the joining elements 480-481, and Figure 8 Other joining elements are not specifically shown in the cross-sectional view. Finally, it should be understood that the top view of joining elements 380 and 381 (and other joining elements in this joining layer) can appear similar to... Figure 9 They are essentially similar. In other words, the top view of the bonding layer for the top-level device 300 can look essentially similar to the top view of the bonding layer for the bottom-level device 400.

[0085] The above text combined Figures 2 to 9 The manufacturing process discussed corresponds to the first embodiment of this disclosure. Figures 10 to 17 The following discussion describes a second embodiment of this disclosure. Similarly, for reasons of consistency and clarity, similar components appearing in the first embodiment will be labeled the same in the second embodiment.

[0086] Now for reference Figure 10 The second embodiment of this disclosure can also form a bonding structure, which includes a dielectric layer 330 and bonding elements 380-381 embedded in the dielectric layer 330 above the top-layer device 300. However, in Figure 10 In the second embodiment, the bonding element 381 can be significantly narrower. For example, while the bonding element 381 may still be wider than the conductive via 280 formed above it, Figure 10 The width of the bonding element 381 in the middle may be less than Figure 5 The bonding element 381 in the embodiment is wide.

[0087] A deposition process 620 is performed to form the dielectric layer 630 over the dielectric layer 330 and the bonding elements 380-381. In some embodiments, the deposition process 620 may include CVD, PVD, ALD, or a combination thereof, and the material composition of the dielectric layer 630 may be substantially similar to that of the dielectric layer 330. For example, the dielectric layer 330 may include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, AlO xIn embodiments using AlON and AlN, the dielectric layer 630 may also include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, and AlO. x AlON, AlN.

[0088] Now for reference Figure 11 One or more etching processes 640 are performed to etch openings in the dielectric layer 630 from side 310. In some embodiments, the one or more etching processes 640 may include one or more dry etching processes or one or more wet etching processes to remove portions of the dielectric layer 630. As a result of the etching processes 640, openings 650, 651, 652, and 653 are formed. Opening 650 exposes the upper surface of the bonding element 380, opening 651 exposes a portion of the upper surface of the dielectric layer 330, opening 652 exposes the upper surface of the bonding element 381, and opening 653 exposes another portion of the upper surface of the dielectric layer 330. In some embodiments, openings 650-653 have substantially the same width in the X direction, and they are also substantially the same width in the X direction (and in the... Figure 11 The openings (650-653) are spaced approximately the same distance apart on the perpendicular Y direction (not directly visible in the center). In this way, the openings can be said to have a periodic distribution.

[0089] Now for reference Figure 12 One or more deposition processes 670 may be performed to form bonding elements 680-683 in openings 650-653, respectively. In some embodiments, the one or more deposition processes 670 may include CVD, PVD, ALD, or combinations thereof. In some embodiments, the deposited material may include Al, Ag, Au, Cu, Co, Ir, Mo, Ni, Pt, Ru, Si, Ta, Tu, W, Zr, or combinations thereof. In some embodiments, the deposited material forming bonding elements 680-683 has the same material composition as bonding elements 380-381. A planarization process (such as a CMP process) may also be performed on the deposited material to planarize the upper surfaces of bonding elements 680-683 and dielectric layer 630, for example, until the upper surfaces of bonding elements 680-683 are substantially coplanar with the upper surface of dielectric layer 630. It should also be understood that in some embodiments, one or more deposition processes 670 may also form a liner (e.g., as a barrier layer) around each bonding element 680-683. However, for the sake of simplicity, the lining layer is not shown in detail here.

[0090] Now for reference Figure 13A second embodiment of this disclosure may further form a bonding structure including a dielectric layer 430 and bonding elements 480-481 embedded in the dielectric layer 430 above the underlying device 400. A deposition process 720 is performed to form the dielectric layer 730 over the dielectric layer 430 and the bonding elements 480-481. In some embodiments, the deposition process 720 may include CVD, PVD, ALD, or a combination thereof, and the material composition of the dielectric layer 730 may be substantially similar to that of the dielectric layer 430. For example, the dielectric layer 430 may include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, AlO x In embodiments using AlON and AlN, the dielectric material layer may also include SiN, SiON, SiCN, SiOC, SiOCN, BN, BCN, TiO2, TiON, TiN, and AlO. x AlON, AlN. In some embodiments, dielectric layer 430 may include candidate materials for dielectric layer 330 listed in Table 1 above.

[0091] Now for reference Figure 14 One or more etching processes 740 are performed to etch openings in the dielectric layer 730 from side 410. In some embodiments, the one or more etching processes 740 may include one or more dry etching processes or one or more wet etching processes to remove portions of the dielectric layer 730. As a result of the etching processes 740, openings 750, 751, 752, and 753 are formed. Opening 750 exposes the upper surface of the bonding element 480, opening 751 exposes a portion of the upper surface of the bonding element 481, opening 752 exposes another portion of the upper surface of the bonding element 481, and opening 753 exposes a portion of the upper surface of the dielectric layer 430. In some embodiments, openings 750-753 have substantially the same width in the X direction, and they are also substantially the same width in the X direction (and in the... Figure 11 The openings (750-753) are spaced approximately the same distance apart on the perpendicular Y direction (not directly visible in the center). In this way, the openings can be said to have a periodic distribution.

[0092] Now for reference Figure 15One or more deposition processes 770 may be performed to form bonding elements 780-783 in openings 750-753, respectively. In some embodiments, the one or more deposition processes 770 may include CVD, PVD, ALD, or combinations thereof. In some embodiments, the deposited material may include Al, Ag, Au, Cu, Co, Ir, Mo, Ni, Pt, Ru, Si, Ta, Tu, W, Zr, or combinations thereof. In some embodiments, the deposited material forming bonding elements 780-783 has the same material composition as bonding elements 480-481. A planarization process (such as a CMP process) may also be performed on the deposited material to planarize the upper surfaces of bonding elements 780-783 and dielectric layer 730, for example, until the upper surfaces of bonding elements 780-783 are substantially coplanar with the upper surface of dielectric layer 730. It should also be understood that in some embodiments, one or more deposition processes 770 may also form a liner (e.g., as a barrier layer) around each bonding element 780-783. However, for the sake of simplicity, the lining layer is not shown in detail here.

[0093] Now for reference Figure 16 According to a second embodiment of this disclosure, a bonding process 790 is performed to bond the top-layer device 300 and the bottom-layer device 400 together to form a parallel CFET device 500. As part of the bonding process 790, the top-layer device 300 is vertically flipped such that side 310 is... Figure 16 The top layer device 300 is now facing downwards. At this point, the MEoL interconnect structure 321 of the top layer device 300 is now facing the MEoL interconnect structure 421 of the bottom layer device 400. Then, dielectric layers 630 and 730 are bonded together, as are bonding elements 680 and 780, 681 and 781, 682 and 782, and 683 and 783. The bonding of bonding elements 680 and 780 establishes an electrical connection between the conductive vias 290 of the top layer device 300 and 290 of the bottom layer device 400, and the bonding of bonding elements 682 and 782 establishes an electrical connection between the conductive vias 280 of the top layer device 300 and 280 of the bottom layer device 400. In this way, the top layer device 300 and the bottom layer device 400 are electrically coupled together.

[0094] Note that dielectric layers 330 and 630, as well as bonding elements 380-381 and 680-683, can also be considered as part of the MEoL interconnect structure 321 of the top-layer device 300, and dielectric layers 430 and 730, as well as bonding elements 480-481 and 780-783, can also be considered as part of the MEoL interconnect structure 421 of the bottom-layer device 400. Therefore, it can be said that the top-layer device 300 and the bottom-layer device 400 are bonded together via their respective MEoL interconnect structures 321 and 421, rather than via their BEoL interconnect structures 320 and 420.

[0095] Meanwhile, bonding elements 681, 683, 781, and 783 are considered pseudo-conductive components because they do not establish electrical connections between the microelectronic components of the top-layer device 300 and the bottom-layer device 400. For example, although bonding elements 681 and 781 are coupled to the conductive via 280 via bonding element 481, they are not electrically coupled to any microelectronic components of the top-layer device 300 because they are coupled to the dielectric layer 330, which is an insulating material. As for bonding elements 683 and 783, they are located together between the dielectric layers 330 and 430, which are both insulating materials. Therefore, bonding elements 683 and 783 do not function as conductive components that facilitate the establishment of electrical connections between the top-layer device 300 and the bottom-layer device.

[0096] According to various aspects of this disclosure, the implementation of bonding elements 681, 683, 781, and 783 (e.g., pseudo-bonding elements) is not for establishing electrical connections, but for improving the bonding process 790 itself. More specifically, some challenges in performing the bonding process 790 may relate to the planarity of the bonding interface 795 between the top-layer device 300 and the bottom-layer device 400. The bonding interface 795 is defined by the downward-facing surfaces of the dielectric layer 630 and bonding elements 680-683, and the upward-facing surfaces of the dielectric layer 730 and bonding elements 780-783. The planarity (e.g., its flatness) of these surfaces is defined by the planarization process (e.g., CMP process) performed on the top-layer device 300 after forming bonding elements 680-683 to fill openings 650-653, and by the planarization process (e.g., CMP process) performed on the bottom-layer device 400 after forming bonding elements 780-783 to fill openings 750-753. Any curvature or topographic variation of these surfaces will result in nonplanarity of the bonding interface 795 (defined by these surfaces). As the nonplanarity of the bonding interface 795 increases, bonding of the top-layer device 300 and the bottom-layer device 400 may become more difficult. Unfortunately, the planarization process can be adversely affected by factors such as pattern uniformity, and a lack of pattern uniformity can lead to a concave effect, which may cause the resulting surfaces to exhibit curvature or topographic variations that result in nonplanarity of the bonding interface 795.

[0097] According to various aspects of this disclosure, the implementation of bonding elements 680-683 and 780-783 (including pseudo-bonding elements 681, 683, 781, and 783) contributes to improving the planarity of the bonding interface 795. As discussed above, openings 650-653 and 750-753 are formed with a periodic distribution. Therefore, bonding elements 680-683 and 780-783 also inherently have a periodic distribution. For example, bonding elements 680-683 and 780-783 may have substantially equal dimensions to each other and are also spaced substantially equally apart from each other. In this way, pattern uniformity (e.g., conductive elements 680-683 and 780-783 serve as a pattern) is enhanced, which minimizes the dent effect (or other defects in the planarization process associated with a lack of pattern uniformity).

[0098] It should also be noted that the implementation of pseudo-bonding elements 681, 683, 781, and 783 further improves the planarity of the bonding interface 795. For example, without the implementation of pseudo-bonding elements 681, 683, 781, and 783, there would be a larger spacing between adjacent bonding elements 680 and 682, and between adjacent bonding elements 780 and 782. Such a long spacing could degrade the quality of pattern uniformity, especially with increasing spacing length. In other words, if only a few functional bonding elements (such as bonding elements 680, 682, 780, and 782) are implemented as sparsely distributed within the bonding structure, the pattern density may be too low, which could be considered as causing pattern inhomogeneity. Here, by adding pseudo-bonding elements 681, 683, 781, and 783 throughout the bonding structure, the pattern density is enhanced, which in turn can contribute to pattern uniformity and can further reduce the dent effect of the planarization process. Therefore, the bonding interface 795 can have greater planarity, which further improves the bonding quality of the top device 300 and the bottom device 400.

[0099] Notice, Figure 8 An enlarged cross-sectional side view of portion 495 of the top-layer device 300 and the bottom-layer device 400 joined together is also shown. The enlarged view includes the source / drain regions 270, source / drain contacts 275, and conductive vias 280 of the top-layer device 300 and the bottom-layer device 400, as well as bonding elements 381 and 481, to provide a better visual understanding of how the bonding scheme of this disclosure is implemented. For simplicity, other components are not specifically shown in the enlarged view.

[0100] Figure 17A top view of an example wafer 800 is shown, on which multiple IC dies are implemented. The top view is defined by the X direction and a Y direction perpendicular to the X direction. In some embodiments, each IC die may include a parallel CFET device 500, which (as discussed above) is formed by bonding a top-layer device 300 and a bottom-layer device 400 together according to a second embodiment. For simplicity, Figure 17 The IC die is not shown separately. Instead, Figure 17 The top view shows the periodic distribution of the joining elements (such as joining elements 780-783) according to the embodiment. For example, joining elements 780-783 may have substantially the same size as each other, and they are spaced substantially equally apart from adjacent joining elements 780-883.

[0101] Figure 17 The diagram shows a dicing line A-A' on a portion of example wafer 800. It should be understood that... Figure 16 A cross-sectional side view can be obtained corresponding to such a cutting line A-A'. It should also be understood that a planar top view can be obtained along a horizontal plane that also cuts across (e.g., intersects with) the joining elements 780-783. In other words, Figure 17 The geometric pattern shown may include a top view of the joining elements 780-783, and Figure 16 Other joining elements are not specifically shown in the cross-sectional view. Finally, it should be understood that the top view of joining elements 680-683 (and other joining elements in this joining layer) can appear similar to... Figure 17 The top view is basically similar. In other words, the top view of the bonding layer for the top device 300 can look basically similar to the top view of the bonding layer for the bottom device 400.

[0102] Note that, for the sake of simplicity, Figure 17 The document does not specifically show the outline or boundaries of each IC die. Instead, Figure 17 The geometry and distribution pattern of the bonding elements (such as bonding elements 780-783) are shown. It should also be understood that the actual wafer 800 may include more than... Figure 17 The number of bonding elements shown is much greater, but for simplicity, they are not specifically shown herein.

[0103] Figure 18 An integrated circuit manufacturing system 900 according to an embodiment of the present disclosure is shown, which can be used to perform the above-described integrated circuit manufacturing process with reference to Figures 1 to 12. Figure 17The manufacturing process discussed (e.g., manufacturing and bonding parallel CFETs). Manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916…, N connected via a communication network 918. Network 918 can be a single network, or it can be various different networks, such as intranets and the Internet, and can include wired and wireless communication channels.

[0104] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring products of interest; entity 906 represents an engineer, such as a processing engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the conditions and settings of processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing photolithography processes or a bonding tool for bonding different IC structures together; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced processing control module associated with processing tool 910 and other other processing tools; and entity 916 represents a sampling module associated with processing tool 910.

[0105] Each entity can interact with other entities and can provide integrated circuit manufacturing, processing control, and / or computing capabilities to and / or receive these capabilities from other entities. Each entity may also include one or more computer systems for performing computations and implementing automation. For example, the advanced processing control module of entity 914 may include multiple computer hardware components in which software instructions are encoded. The computer hardware may include hard disk drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0106] The integrated circuit manufacturing system 900 enables interaction between entities to achieve integrated circuit (IC) manufacturing and advanced processing control of IC manufacturing. In an embodiment, advanced processing control includes adjusting processing conditions, settings, and / or recipes of a processing tool applicable to the relevant wafer based on metrological results.

[0107] In another embodiment, metrological results are measured from a subset of the processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrological results are measured from selected fields and points of a subset of the processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0108] One of the capabilities offered by the IC Manufacturing System 900 is the ability to enable collaboration and information access across areas such as design, engineering and processing, metrology, and advanced processing control. Another capability offered by the IC Manufacturing System 900 is the ability to integrate systems between facilities, such as between metrology tools and processing tools. This integration allows facilities to coordinate their activities. For example, integrating metrology tools and processing tools can more effectively integrate manufacturing information into the manufacturing process or APC module, and wafer data can be acquired from online or field measurements using metrology tools integrated into associated processing tools.

[0109] Figure 19 This is a flowchart of a method 1000 for bonding an IC device according to various aspects of this disclosure. Method 1000 includes step 1010, forming a first dielectric layer over a first portion of a complementary field-effect transistor (CFET) device.

[0110] Method 1000 includes step 1020, etching a plurality of first openings in a first dielectric layer.

[0111] Method 1000 includes step 1030, filling a first opening with a first conductive material to form a plurality of first bonding elements in the first opening.

[0112] Method 1000 includes step 1040, forming a second dielectric layer over a second portion of the CFET device.

[0113] Method 1000 includes step 1050, etching a plurality of second openings in a second dielectric layer. In some embodiments, the first and second openings are etched such that, in a cross-sectional side view, each first opening is perpendicularly aligned with a corresponding second opening. In some embodiments, the first and second openings are etched such that the first openings and each of the first openings have a periodic distribution in a top view.

[0114] Method 1000 includes step 1060, filling a second opening with a second conductive material to form a plurality of second bonding elements in the second opening. In some embodiments, filling a first opening and filling a second opening are performed such that the first conductive material and the second conductive material have the same material composition.

[0115] Method 1000 includes step 1070, electrically coupling a first portion of a CFET device and a second portion of a CFET device together, at least partially, via a first bonding element and a second bonding element. In some embodiments, the electrical coupling includes directly bonding the first bonding element to the second bonding element.

[0116] It should be understood that method 1000 may include additional steps that can be performed before, during, or after steps 1010-1070. For example, in some embodiments, prior to performing the electrical coupling in step 1070, method 1000 may include the following steps: forming a third dielectric layer over a first bonding element; etching a plurality of third openings in the third dielectric layer; filling the third openings with a third conductive material to form a plurality of third bonding elements in the third openings, wherein at least a subset of the third bonding elements are directly formed on at least a subset of the first bonding elements; forming a fourth dielectric layer over a second bonding element; etching a plurality of fourth openings in the fourth dielectric layer; and filling the fourth openings with a fourth conductive material to form a plurality of fourth bonding elements in the fourth openings, wherein at least a subset of the fourth bonding elements are directly formed on at least a subset of the second bonding elements. The electrical coupling in step 1070 includes directly bonding the third bonding elements to the fourth bonding elements. As another example, method 1000 may also include the following steps performed before forming the first dielectric layer and the second dielectric layer: forming one or more n-type transistors in a first portion of the CFET; and forming one or more p-type transistors in a second portion of the CFET. Other steps may include testing and packaging, etc.

[0117] In summary, this disclosure relates to a bonding alignment scheme. According to this scheme, one or more bonding structures can be formed over a top-level device of a parallel CFET, and one or more bonding structures can be formed over a bottom-level device of a parallel CFUT. Each bonding structure may include a dielectric layer and a plurality of conductive components (serving as bonding elements) embedded in the dielectric layer. The conductive components may have a wider lateral dimension than the conductive vias to which they are coupled. In some embodiments, the conductive components of the bonding structure are periodically distributed. The bonding of the top-level and bottom-level devices of the parallel CFET is achieved at least in part by bonding the bonding layers together such that the conductive components of the bonding structure of the top-level device are bonded to the conductive components of the bonding structure of the bottom-level device.

[0118] The embodiments disclosed herein offer advantages over conventional systems and methods of bonding. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. One advantage is greater margin for bonding alignment. In this regard, as device dimensions scale down at each technology node of semiconductor manufacturing, aligning vias from different IC structures can become increasingly difficult, such as between vias from the top-level device of a CFET and vias from the bottom-level device of a CFET. However, because this disclosure establishes bonding (and thus electrical connection) between the top-level and bottom-level devices of a CFET using bonding elements that are wider than the vias, there is greater tolerance for lateral misalignment between the top-level and bottom-level devices, and the bonding elements can still make electrical contact with each other, thereby achieving electrical connection between the top-level and bottom-level devices of the CFET. Another advantage is the improvement in bonding itself. In this regard, the quality of bonding can depend on the planarity of the bonding surfaces. By implementing the bonding elements as periodic structures (e.g., having substantially equal dimensions and / or spaced apart by substantially uniform distances), pattern uniformity is improved. Improved pattern uniformity can reduce denting effects and / or other potential planarization problems, thus improving the planarity of the planarized surface. In embodiments implementing pseudo-bonded elements, pattern uniformity can be further enhanced, which can further improve the planarity of the planarized surface. Therefore, the bonding surface (with better planarity) can achieve higher quality bonding, which is associated with better device performance and / or yield. Other advantages include compatibility with existing manufacturing processes, ease of implementation, and low cost.

[0119] One aspect of this disclosure relates to a device. The device includes: a first device including a plurality of first transistors; a first bonding layer disposed over the first device, wherein the first bonding layer includes a first dielectric layer and a plurality of first conductive components embedded in the first dielectric layer; a second device including a plurality of second transistors; and a second bonding layer disposed over the second device, wherein the second bonding layer includes a second dielectric layer and a plurality of second conductive components embedded in the second dielectric layer, and wherein each first conductive component is aligned with and coupled to a corresponding one of the second conductive components.

[0120] Embodiments of this disclosure also relate to a semiconductor device, including a first device and a second device. The first device includes: a plurality of first transistors; and a first bonding layer disposed above the first device, wherein the first bonding layer includes a first dielectric layer and a plurality of first conductive components embedded in the first dielectric layer, wherein the first bonding layer is part of a middle-process interconnect (MEoL) structure of the first device. The second device includes: a plurality of second transistors; and a second bonding layer disposed above the second device, wherein the second bonding layer includes a second dielectric layer and a plurality of second conductive components embedded in the second dielectric layer, wherein the second bonding layer is part of a middle-process interconnect structure of the second device, and wherein each of the first conductive components is aligned and coupled to a corresponding one of the second conductive components.

[0121] In some embodiments, the first device is the top device of a complementary field-effect transistor (CFET), and the second device is the bottom device of the CFET; or the first device is the bottom device of the CFET, and the second device is the top device of the CFET.

[0122] In some embodiments, the first transistor includes an n-type transistor; and the second transistor includes a p-type transistor.

[0123] In some embodiments, the semiconductor device further includes: a third bonding layer disposed over the first bonding layer, wherein the third bonding layer includes a third dielectric layer and a plurality of third conductive components embedded in the third dielectric layer; and a fourth bonding layer disposed over the second bonding layer, wherein the fourth bonding layer includes a fourth dielectric layer and a plurality of fourth conductive components embedded in the fourth dielectric layer; wherein: the third conductive components are directly bonded to the first conductive component; at least a subset of the third conductive components are electrically coupled to the first conductive component; and at least a subset of the fourth conductive components are electrically coupled to the second conductive component.

[0124] In some embodiments, at least another subset of the third conductive component is a pseudo-conductive component that is not electrically coupled to any of the first conductive components; or at least another subset of the fourth conductive component is a pseudo-conductive component that is not electrically coupled to any of the second conductive components.

[0125] In some embodiments, each of the first device and the second device further includes a back-end process interconnect (BEoL) structure, wherein the mid-end process interconnect structure and the back-end process interconnect structure of the first device are located on opposite sides of the first transistor, and wherein the mid-end process interconnect structure and the back-end process interconnect structure of the second device are located on opposite sides of the second transistor.

[0126] In some embodiments, the first conductive component and the second conductive component have the same outline in a top view.

[0127] In some embodiments, each of the first conductive component and the second conductive component has a periodic distribution pattern in a top view.

[0128] In some embodiments, a first side of one of the first conductive components is coupled to a first conductive via or a first conductive contact of the first device; a first side of one of the second conductive components is coupled to a second conductive via or a second conductive contact of the second device; a second side of one of the first conductive components is coupled to a second side of one of the second conductive components; and in a cross-sectional side view, the first conductive via or the first conductive contact is laterally offset from the second conductive via or the second conductive contact.

[0129] In some embodiments, the first dielectric layer and the second dielectric layer have the same dielectric material composition; and the first conductive component and the second conductive component have the same conductive material composition.

[0130] Another aspect of this disclosure relates to a device. The device includes: a top portion of a complementary field-effect transistor (CFET) device including a plurality of transistors having a first conductivity type; a bottom portion of the CFET device including a plurality of transistors having a second conductivity type different from the first conductivity type; and a bonding structure disposed between the top portion and the bottom portion of the CFET in a cross-sectional side view, wherein the bonding structure includes at least a first bonding layer and a second bonding layer, the first bonding layer including a plurality of first bonding elements, and the second bonding layer including a plurality of second bonding elements, wherein, in a cross-sectional side view, the first bonding elements are perpendicularly aligned with and directly bonded to the second bonding elements, and wherein, in a top view, each of the first and second bonding elements has a periodic distribution.

[0131] In some embodiments, the bonding structure further includes a third bonding layer and a fourth bonding layer; in the cross-sectional side view, the third bonding layer is disposed between the top portion of the complementary field-effect transistor and the first bonding layer; the third bonding layer includes a plurality of third bonding elements electrically coupled to at least a subset of the first bonding elements; in the cross-sectional side view, the fourth bonding layer is disposed between the bottom portion of the complementary field-effect transistor and the second bonding layer; the fourth bonding layer includes a plurality of fourth bonding elements electrically coupled to at least a subset of the second bonding elements; and at least one of the third bonding elements is electrically coupled to one of the fourth bonding elements, but is not aligned with said one of the fourth bonding elements.

[0132] In some embodiments, a subset of the first bonding elements is not electrically coupled to any microelectronic components of the top portion of the complementary field-effect transistor; or a subset of the second bonding elements is not electrically coupled to any microelectronic components of the bottom portion of the complementary field-effect transistor.

[0133] Another aspect of this disclosure relates to a method. The method includes: forming a first dielectric layer over a first portion of a complementary field-effect transistor (CFET) device; etching a plurality of first openings in the first dielectric layer; filling the first openings with a first conductive material to form a plurality of first bonding elements in the first openings; forming a second dielectric layer over a second portion of the CFET device; etching a plurality of second openings in the second dielectric layer; filling the second openings with a second conductive material to form a plurality of second bonding elements in the second openings; and electrically coupling the first portion of the CFET device and the second portion of the CFET device together at least partially through the first bonding elements and the second bonding elements.

[0134] In some embodiments, electrical coupling includes directly coupling the first bonding element to the second bonding element.

[0135] In some embodiments, the method further includes, prior to the electrical coupling: forming a third dielectric layer over the first bonding element; etching a plurality of third openings in the third dielectric layer; filling the third openings with a third conductive material to form a plurality of third bonding elements in the third openings, wherein at least a subset of the third bonding elements is formed directly on at least a subset of the first bonding elements; forming a fourth dielectric layer over the second bonding element; etching a plurality of fourth openings in the fourth dielectric layer; and filling the fourth openings with a fourth conductive material to form a plurality of fourth bonding elements in the fourth openings, wherein at least a subset of the fourth bonding elements is formed directly on at least a subset of the second bonding elements; wherein the electrical coupling includes directly bonding the third bonding elements to the fourth bonding elements.

[0136] In some embodiments, filling the first opening and filling the second opening are performed such that the first conductive material and the second conductive material have the same material composition.

[0137] In some embodiments, the method further includes, prior to forming the first dielectric layer and the second dielectric layer: forming one or more n-type transistors in the first portion of the complementary field-effect transistor; and forming one or more p-type transistors in the second portion of the complementary field-effect transistor.

[0138] In some embodiments, the first opening and the second opening are etched in such a manner that, in a cross-sectional side view, each of the first openings is perpendicularly aligned with a corresponding second opening.

[0139] In some embodiments, the first opening and the second opening are etched in such a manner that each of the first opening and the second opening has a periodic distribution in a top view.

[0140] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: The first device includes: Multiple first transistors; and A first bonding layer is disposed above the first device, wherein the first bonding layer includes a first dielectric layer and a plurality of first conductive components embedded in the first dielectric layer, wherein the first bonding layer is part of the middle-of-line (MEoL) interconnect structure of the first device. The second device includes: Multiple second transistors; and A second bonding layer is disposed above the second device, wherein the second bonding layer includes a second dielectric layer and a plurality of second conductive components embedded in the second dielectric layer, wherein the second bonding layer is part of the mid-process interconnect structure of the second device, and wherein each of the first conductive components is aligned and coupled to a corresponding one of the second conductive components.

2. The semiconductor device according to claim 1, wherein: The first device is the top device of the complementary field-effect transistor (CFET), and the second device is the bottom device of the complementary field-effect transistor; or The first device is the bottom device of the complementary field-effect transistor, and the second device is the top device of the complementary field-effect transistor.

3. The semiconductor device according to claim 1, wherein: The first transistor includes an n-type transistor; and The second transistor includes a p-type transistor.

4. The semiconductor device according to claim 1, further comprising: A third bonding layer is disposed above the first bonding layer, wherein the third bonding layer includes a third dielectric layer and a plurality of third conductive components embedded in the third dielectric layer; and A fourth bonding layer is disposed above the second bonding layer, wherein the fourth bonding layer includes a fourth dielectric layer and a plurality of fourth conductive components embedded in the fourth dielectric layer; in: The third conductive component is directly coupled to the fourth conductive component; At least a subset of the third conductive component is electrically coupled to the first conductive component; and At least a subset of the fourth conductive component is electrically coupled to the second conductive component.

5. The semiconductor device according to claim 4, wherein: At least another subset of the third conductive component are pseudo-conductive components that are not electrically coupled to any of the first conductive components; or At least another subset of the fourth conductive component is a pseudo-conductive component that is not electrically coupled to any of the second conductive components.

6. The semiconductor device according to claim 1, wherein, Each of the first device and the second device further includes a back-end process interconnect (BEoL) structure, wherein the mid-end process interconnect structure and the back-end process interconnect structure of the first device are located on opposite sides of the first transistor, and wherein the mid-end process interconnect structure and the back-end process interconnect structure of the second device are located on opposite sides of the second transistor.

7. The semiconductor device according to claim 1, wherein, The first conductive component and the second conductive component have the same outline in the top view.

8. The semiconductor device according to claim 1, wherein, Each of the first conductive component and the second conductive component has a periodic distribution pattern in the top view.

9. A semiconductor device, comprising: The top portion of a complementary field-effect transistor (CFET) device, the top portion comprising a plurality of transistors having a first conductivity type; The bottom portion of the complementary field-effect transistor device includes a plurality of transistors having a second conductivity type different from the first conductivity type; as well as A bonding structure, disposed in a cross-sectional side view between the top portion and the bottom portion of the complementary field-effect transistor, wherein the bonding structure includes at least a first bonding layer and a second bonding layer, the first bonding layer comprising a plurality of first bonding elements and the second bonding layer comprising a plurality of second bonding elements, wherein, in the cross-sectional side view, the first bonding elements are perpendicularly aligned with and directly bonded to the second bonding elements, and wherein, in a top view, each of the first bonding elements and the second bonding elements has a periodic distribution.

10. A method of forming a semiconductor device, comprising: A first dielectric layer is formed over a first portion of a complementary field-effect transistor (CFET) device; Multiple first openings are etched in the first dielectric layer; The first opening is filled with a first conductive material, thereby forming a plurality of first bonding elements in the first opening; A second dielectric layer is formed over the second portion of the complementary field-effect transistor device; Multiple second openings are etched in the second dielectric layer; The second opening is filled with a second conductive material, thereby forming a plurality of second bonding elements in the second opening; as well as The first portion of the complementary field-effect transistor device and the second portion of the complementary field-effect transistor device are electrically coupled together, at least partially, through the first bonding element and the second bonding element.

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