Film layer preparation method and system of back contact battery
By using a low-temperature CVD process to prepare an amorphous silicon layer in the back contact battery and then performing boron doping, the problems of thermal damage and efficiency instability of silicon wafers caused by traditional high-temperature processes were solved, thereby improving battery life and efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LAPLACE RENEWABLE ENERGY TECH CO LTD
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-14
AI Technical Summary
In the traditional BC battery manufacturing process, the high-temperature boron diffusion process causes thermal damage to the silicon wafer and uneven thickness of the tunnel oxide layer, which affects the stability of battery efficiency.
An amorphous silicon layer was prepared in the second region of a silicon wafer using a low-temperature CVD process, and boron doping was performed using the low-temperature CVD process to replace the traditional high-temperature diffusion furnace process, thus preparing the film layer for the back contact battery.
It significantly reduces thermal damage to silicon wafers caused by high temperatures, reduces the texturing and penetration phenomenon in thin areas of amorphous silicon layers, and improves the lifespan and efficiency stability of solar cells.
Smart Images
Figure CN121865732A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor or photovoltaic material processing, specifically to a method and system for preparing a film layer of a back contact battery. Background Technology
[0002] Back contact (BC) photovoltaic cells are a technology that improves photoelectric conversion efficiency by optimizing the cell structure. Its core feature is that the cell emitter region (i.e., P+ emitter) and base region (i.e., N+ back field) are alternately placed on the back of the cell in an interdigitated structure. The front of the cell is covered with an anti-reflection passivation film and an aluminum oxide passivation film to improve the passivation effect while reducing the shading of the metal grid electrode and increasing the effective light absorption area.
[0003] Currently, in traditional methods for fabricating the P+ emitter on the back of BC batteries, a tunneling oxide layer (molecular formula: ...) needs to be prepared using low-pressure chemical vapor deposition (LPCVD) technology. The silicon wafer is first coated with a polycrystalline silicon layer (Poly-Si), and then boron is diffused through a diffusion furnace to obtain a boron-doped polycrystalline silicon layer. Because the boron diffusion process is carried out at high temperatures, typically 950 ℃ and above, it can easily cause thermal damage to the silicon wafer, significantly impacting the cell lifespan. Furthermore, preparing a tunneling oxide layer on a textured surface can lead to uneven thickness of the tunneling oxide layer. At high temperatures, thinner areas of the tunneling oxide layer are prone to texturing penetration, affecting the stability of cell efficiency. Summary of the Invention
[0004] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a method and system for preparing a film layer in a back contact battery.
[0005] In a first aspect, one embodiment of this application provides a method for preparing a film layer for a back contact battery, used to prepare a film layer on a silicon wafer. The silicon wafer has a first side and a second side in a first direction. The second side of the silicon wafer has a first region and a second region arranged in an interdigitated manner. An intervening region is also provided between adjacent first regions and second regions. The method includes: sequentially preparing a tunneling oxide layer and a phosphorus-doped layer in the first region, the second region, and the intervening region. The phosphorus-doped layer includes a phosphorus-doped polycrystalline silicon layer; preparing a first mask layer on the side of the phosphorus-doped layer away from the silicon wafer; removing the first mask layer, the tunneling oxide layer, and the phosphorus-doped layer in the second region and the intervening region; texturing the second region and the intervening region; preparing an amorphous silicon layer in the second region, on the side of the phosphorus-doped layer away from the silicon wafer, and in the intervening region; boron-doping the amorphous silicon layer by a low-temperature CVD process to form a boron-doped amorphous silicon layer; and removing the boron-doped amorphous silicon layer on the side of the phosphorus-doped layer away from the silicon wafer and the boron-doped amorphous silicon layer in the intervening region.
[0006] In some embodiments, the amorphous silicon layer is prepared in the second region, the side of the heavily phosphorus-doped layer away from the silicon wafer, and the spacer region, comprising: preparing the amorphous silicon layer in the second region, the side of the heavily phosphorus-doped layer away from the silicon wafer, and the spacer region at a first process temperature, wherein the first process temperature ranges from 250 °C to 400 °C; and / or, boron doping is performed on the amorphous silicon layer by a low-temperature CVD process to form a boron-doped amorphous silicon layer, comprising: performing boron doping on the amorphous silicon layer by a low-temperature CVD process at a second process temperature, wherein the second process temperature ranges from 250 °C to 400 °C.
[0007] In some embodiments, the amorphous silicon layer is prepared in the second region, the side of the heavily phosphorus-doped layer away from the silicon wafer, and the spacer region by means of a low-temperature CVD process using a PECVD device; and / or, the amorphous silicon layer is boron-doped by means of a low-temperature CVD process to form a boron-doped amorphous silicon layer, including: the amorphous silicon layer is boron-doped by means of a low-temperature CVD process using a PECVD device to form a boron-doped amorphous silicon layer.
[0008] In some embodiments, preparing a first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer includes: depositing the first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer using a PECVD device, the first mask layer comprising silicon nitride.
[0009] In some embodiments, sequentially preparing a tunneling oxide layer and a heavily phosphorus-doped layer in a first region, a second region, and a spacer region includes: preparing a tunneling oxide layer in the first region, a second region, and a spacer region; preparing a polycrystalline silicon layer on the side of the tunneling oxide layer away from the silicon wafer; and doping phosphorus into the polycrystalline silicon layer to form a heavily phosphorus-doped layer.
[0010] In some embodiments, removing the first mask layer, tunneling oxide layer, and heavily phosphorus-doped layer from the second region and the spacer region includes: creating a groove in the first mask layer of the second region and the spacer region using a laser; and removing the first mask layer, heavily phosphorus-doped layer, and tunneling oxide layer of the second region and the spacer region using a wet etching process.
[0011] In some embodiments, removing the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region, includes: preparing a second mask layer on the side of the boron-doped amorphous silicon layer away from the silicon wafer at a third process temperature, wherein the third process temperature is in the range of 300 °C to 400 °C; creating grooves in the second mask layer of the first region and the spacer region using a laser; and removing the second mask layer and the boron-doped amorphous silicon layer of the first region and the spacer region by a wet etching process.
[0012] In some embodiments, after removing the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region, the method further includes: preparing conductive film layers on the side of the heavily phosphorus-doped layer away from the silicon wafer, the spacer region, and the side of the boron-doped amorphous silicon layer away from the silicon wafer; and removing the conductive film layer in the spacer region by laser.
[0013] In some embodiments, after preparing conductive film layers on the side of the heavily phosphorus-doped layer away from the silicon wafer, the spacer region, and the side of the boron-doped amorphous silicon layer away from the silicon wafer, the method further includes: preparing a first antireflection passivation layer on the side of the conductive film layer away from the silicon wafer; opening the first antireflection passivation layer in the spacer region using a laser; and / or preparing a second antireflection passivation layer on a first side of the silicon wafer.
[0014] In some embodiments, after preparing the first antireflection passivation layer on the side of the conductive film layer away from the silicon wafer, the method further includes: creating openings in the first antireflection passivation layer and the conductive film layer in the first region and the second region using a laser; and screen printing in the first region, the second region and the interval region using a paste at a preset temperature to form gate lines, wherein the preset temperature ranges from 200 ℃ to 400 ℃.
[0015] Secondly, one embodiment of this application provides a film preparation system for a back contact battery, used to prepare a film on a silicon wafer. The silicon wafer has a first side and a second side in a first direction. The second side of the silicon wafer has a first region and a second region arranged in an interdigitated manner. A spacer region is also provided between adjacent first regions and second regions. The system includes: a first preparation device configured to sequentially prepare a tunneling oxide layer and a heavily phosphorus-doped layer in the first region, the second region, and the spacer region. The heavily phosphorus-doped layer includes a phosphorus-doped polycrystalline silicon layer; and a second preparation device configured to prepare a film on the side of the heavily phosphorus-doped layer away from the silicon wafer. The equipment includes: a first mask layer; a first removal device configured to remove the first mask layer, tunneling oxide layer, and phosphorus-doped layer from the second region and the spacer region; a texturing device configured to texturize the second region and the spacer region; a third fabrication device configured to fabricate an amorphous silicon layer from the second region, the side of the phosphorus-doped layer away from the silicon wafer, and the spacer region, and to boron-dopant the amorphous silicon layer by a low-temperature CVD process to form a boron-doped amorphous silicon layer; and a second removal device configured to remove the boron-doped amorphous silicon layer from the side of the phosphorus-doped layer away from the silicon wafer and the boron-doped amorphous silicon layer from the spacer region.
[0016] The back contact cell film preparation method and system proposed in this application have advantages. Since the process temperature of the amorphous silicon layer is lower than that of the traditional LPCVD process for preparing the tunneling oxide layer and polycrystalline silicon layer, and the temperature for boron doping of the amorphous silicon layer using low-temperature CVD technology is lower than that for boron diffusion of the polycrystalline silicon layer using a diffusion furnace, this application embodiment prepares an amorphous silicon layer in the second region of the silicon wafer to replace the tunneling oxide layer and polycrystalline silicon layer in traditional BC cells. Furthermore, it uses a low-temperature CVD process to dope the amorphous silicon layer with boron, replacing the traditional method of boron diffusion of the polycrystalline silicon layer using a diffusion furnace. This significantly reduces high-temperature thermal damage to the silicon wafer, improves cell lifespan, and reduces the occurrence of texturing and tunneling phenomena in thinner areas of the amorphous silicon layer, improving the passivation effect in the second region and thus enhancing cell efficiency stability. Attached Figure Description
[0017] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.
[0018] Figure 1 The diagram shown is a schematic flowchart of a method for preparing a film layer of a back contact battery according to an exemplary embodiment of this application.
[0019] Figure 2 The diagram shown is a schematic diagram of the structure of a polished silicon wafer provided in an exemplary embodiment of this application.
[0020] Figure 3 The diagram shown is a schematic representation of the structure of a silicon wafer after removing the tunneling oxide layer and the phosphorus heavily doped layer of the second region and the spacer region, according to an exemplary embodiment of this application.
[0021] Figure 4 The diagram shown is a schematic diagram of the structure of a silicon wafer after preparing a boron-doped amorphous silicon layer according to an exemplary embodiment of this application.
[0022] Figure 5 The diagram shown is a schematic representation of the structure of a silicon wafer after removing the phosphorus-doped layer on the side of the silicon wafer away from the wafer, the boron-doped amorphous silicon layer in the intervening region, and an exemplary embodiment of this application.
[0023] Figure 6 The diagram shown is a schematic diagram of the structure of a cut silicon wafer provided in an exemplary embodiment of this application.
[0024] Figure 7The diagram shown is a schematic flowchart of the process for preparing a tunneling oxide layer and a heavily phosphorus-doped layer according to an exemplary embodiment of this application.
[0025] Figure 8 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a tunneling oxide layer according to an exemplary embodiment of this application.
[0026] Figure 9 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a polycrystalline silicon layer according to an exemplary embodiment of this application.
[0027] Figure 10 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a heavily phosphorus-doped layer according to an exemplary embodiment of this application.
[0028] Figure 11 The diagram shown is a flowchart illustrating a method for removing the tunneling oxide layer and the heavily phosphorus-doped layer in the second region and the spacer region according to an exemplary embodiment of this application.
[0029] Figure 12 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of the first mask layer, provided by an exemplary embodiment of this application.
[0030] Figure 13 The diagram shown is a schematic diagram of the structure for laser processing of the second region provided in an exemplary embodiment of this application.
[0031] Figure 14 The diagram shown is a flowchart illustrating a method for removing a boron-doped amorphous silicon layer on the side of the silicon wafer away from the heavily phosphorus-doped layer, as well as a boron-doped amorphous silicon layer in the intervening region, according to an exemplary embodiment of this application.
[0032] Figure 15 The diagram shown is a schematic diagram of the structure of a silicon wafer after the fabrication of the second mask layer, provided by an exemplary embodiment of this application.
[0033] Figure 16 The diagram shown is a schematic representation of the laser processing of a first region and an interval region provided in an exemplary embodiment of this application.
[0034] Figure 17 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a conductive film layer according to an exemplary embodiment of this application.
[0035] Figure 18 The diagram shown is a schematic diagram of the structure of a silicon wafer after the fabrication of the first antireflection passivation layer, provided by an exemplary embodiment of this application.
[0036] Figure 19 The diagram shown is a schematic diagram of the structure of a silicon wafer after the fabrication of the second antireflection passivation layer, provided by an exemplary embodiment of this application.
[0037] Figure 20The diagram shown is a flowchart illustrating a method for screen printing grid lines provided in an exemplary embodiment of this application.
[0038] Figure 21 The diagram shown is a schematic representation of a structure for laser processing of a first region, a second region, and an interval region, provided by an exemplary embodiment of this application.
[0039] Figure 22 The diagram shown is a schematic diagram of the structure of a silicon wafer after opening the first anti-reflection passivation layer and conductive film layer according to an exemplary embodiment of this application.
[0040] Figure 23 The diagram shown is a flowchart illustrating a specific method for preparing a film layer of a back contact battery according to an embodiment of this application.
[0041] Figure 24 The diagram shown is a schematic diagram of the film preparation system for a back contact battery provided in an exemplary embodiment of this application.
[0042] Figure 25 The diagram shown is a schematic diagram of the structure of a silicon wafer after the amorphous silicon layer has been prepared, according to an exemplary embodiment of this application.
[0043] Figure label: 200. Silicon wafer; 201. Tunneling oxide layer; 202. First side; 203. Second side; 204. Heavy phosphorus doped layer; 205. Amorphous silicon layer; 206. Boron-doped amorphous silicon layer; 207. Mechanically damaged layer; 208. Polycrystalline silicon layer; 209. First mask layer; 210. Second mask layer; 211. Conductive film layer; 212. First antireflection passivation layer; 213. Second antireflection passivation layer; 214. Through hole; 800. Film layer preparation system for back contact battery; 801. First preparation equipment; 802. Second preparation equipment; 803. First removal equipment; 804. Texturing equipment; 805. Third preparation equipment; 806. Second removal equipment. Detailed Implementation
[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0045] Figure 1 The diagram shown is a schematic flowchart of a method for preparing a film layer of a back contact battery according to an exemplary embodiment of this application. Figure 2 The diagram shown is a schematic representation of the structure of a polished silicon wafer provided in an exemplary embodiment of this application. Figure 3The diagram shown is a schematic representation of the structure of a silicon wafer after removing the tunneling oxide layer and the heavily doped phosphorus layer from the second region and the spacer region, according to an exemplary embodiment of this application. Figure 4 The diagram shown is a schematic representation of the structure of a silicon wafer after the preparation of a boron-doped amorphous silicon layer, according to an exemplary embodiment of this application. Figure 5 The diagram shown is a schematic representation of the silicon wafer structure after removing the phosphorus-doped layer on the side of the silicon wafer furthest from the wafer, and the boron-doped amorphous silicon layer in the intervening region, according to an exemplary embodiment of this application. Figure 25 The diagram shown is a schematic diagram of the structure of a silicon wafer after the amorphous silicon layer has been prepared, according to an exemplary embodiment of this application.
[0046] like Figures 1-5 and Figure 25 As shown, this application provides a method for preparing a film layer of a back contact battery, which is used to prepare a film layer on a silicon wafer 200. The silicon wafer 200 has a first side 202 and a second side 203 in a first direction (as shown in direction a in the figure). The second side 203 of the silicon wafer 200 has a first region (approximately located in region N in the figure) and a second region (approximately located in region P in the figure) arranged in an interdigitated manner. There is also a gap region (approximately located in region G in the figure) between adjacent first regions and second regions.
[0047] The method for preparing the film layer of the back contact battery provided in this application includes the following steps 101 to 106.
[0048] Step 101: Prepare a tunneling oxide layer and a phosphorus heavily doped layer sequentially in the first region, the second region, and the spacer region.
[0049] The phosphorus-doped layer 204 includes a phosphorus-doped polycrystalline silicon layer 208.
[0050] Step 102: Prepare a first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and remove the first mask layer, tunneling oxide layer and heavily phosphorus-doped layer from the second region and the spacer region.
[0051] Step 103: Fabricate the second region and the interval region.
[0052] By texturing the second region and the spacer region, photons can be reflected back to the PN junction position when they are transmitted to the texturized structure, thereby improving the photoelectric conversion efficiency of the back contact cell.
[0053] Step 104: Prepare an amorphous silicon layer in the second region, on the side of the heavily phosphorus-doped layer away from the silicon wafer, and in the spacer region.
[0054] That is, an amorphous silicon layer 205 is prepared in the first region, the second region and the spacer region.
[0055] For example, an amorphous silicon layer can be prepared by CVD.
[0056] For example, the thickness of the amorphous silicon layer 205 ranges from 150 nm to 300 nm.
[0057] For example, the amorphous silicon layer 205 can be prepared based on silane.
[0058] Step 105: Boron doping is performed on the amorphous silicon layer using a low-temperature CVD process to form a boron-doped amorphous silicon layer.
[0059] For example, the boron-doped amorphous silicon layer 206 can be prepared based on borane.
[0060] For example, the sheet resistance of the boron-doped amorphous silicon layer 206 is in the range of 80 Ω to 200 Ω.
[0061] For example, the amorphous silicon layer 205 can be boron-doped using a low-temperature CVD process via PECVD to form a boron-doped amorphous silicon layer 206.
[0062] Specifically, such as Figures 25 to 4 As shown, in steps 104 and 105, silane can be first introduced into the PECVD to deposit a portion of the amorphous silicon layer 205 in the second region, the side of the phosphorus-doped layer 204 away from the silicon wafer 200, and the interstitial region. Then, silane and borane are simultaneously introduced into the PECVD to grow a boron-doped amorphous silicon layer 206 (intrinsic amorphous silicon) on the surface of the amorphous silicon layer 205. This low-temperature deposition of the boron-doped amorphous silicon layer 206 significantly reduces the process temperature compared to high-temperature boron diffusion, thus reducing thermal damage to the silicon wafer 200 and the amorphous silicon layer 205. In subsequent processes, the intrinsic amorphous silicon is converted into intrinsic polycrystalline silicon, which can serve as a tunneling layer to achieve the tunneling effect and improve the efficiency of the back contact cell.
[0063] Step 106: Remove the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, as well as the boron-doped amorphous silicon layer in the intervening region.
[0064] In the above embodiments, since the process temperature of the amorphous silicon layer is lower than the process temperature of the traditional LPCVD preparation of the tunneling oxide layer and polycrystalline silicon layer, and the temperature of boron doping of the amorphous silicon layer 205 by low-temperature CVD technology is lower than the temperature of boron diffusion of the polycrystalline silicon layer by diffusion furnace, in this embodiment, by preparing the amorphous silicon layer 205 in the second region of the silicon wafer 200 to replace the tunneling oxide layer and polycrystalline silicon layer in the traditional BC cell, and by performing boron doping on the amorphous silicon layer 205 by low-temperature CVD process to replace the boron diffusion of the polycrystalline silicon layer by diffusion furnace in the traditional BC cell, the thermal damage to the silicon wafer 200 caused by high temperature can be significantly reduced, the cell life can be improved, and the occurrence of velour diffusion phenomenon in the thinner areas of the amorphous silicon layer 205 can be reduced, improving the passivation effect of the second region, thereby improving the efficiency stability of the cell.
[0065] Figure 6 The diagram shown is a schematic diagram of the structure of a cut silicon wafer provided in an exemplary embodiment of this application.
[0066] In some embodiments, such as Figure 6 and Figure 2 As shown, before step 101, a wet plating process can be used to remove the mechanically damaged layer 207 caused by cutting of the silicon wafer 200 after cutting, so as to obtain a smooth and defect-free surface. After polishing, the surface of the silicon wafer 200 is flatter, providing a flatter substrate for subsequent processes, and improving the contact effect between the amorphous silicon layer 205 and the silicon wafer 200, as well as the contact effect between the tunneling oxide layer 201 and the silicon wafer 200.
[0067] In some embodiments, when the first mask layer 209 is prepared on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200 in step 102, the first mask layer 209 can be deposited on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200 using a PECVD device. The first mask layer 209 includes silicon nitride (molecular formula SiNx).
[0068] For example, the thickness of the first mask layer 209 ranges from 30 nm to 60 nm.
[0069] For example, the first mask layer can be prepared using silane and ammonia.
[0070] In the above embodiments, the first mask layer 209 of silicon nitride material can protect the tunneling oxide layer 201 and the heavily phosphorus-doped layer 204 in the first region from being removed.
[0071] In some embodiments, when the amorphous silicon layer 205 is prepared in the second region, the side of the phosphorus-doped layer 204 away from the silicon wafer 200, and the spacer region in step 104, the amorphous silicon layer 205 can be prepared in the second region, the side of the phosphorus-doped layer 204 away from the silicon wafer, and the spacer region at a first process temperature, wherein the range of the first process temperature is 250 ℃ to 400 ℃.
[0072] For example, the first process temperature is 250 ℃, 280 ℃, 300 ℃, 330 ℃, 350 ℃ or 400 ℃.
[0073] In the above embodiments, since the first process temperature is relatively low, by preparing an amorphous silicon layer 205 mainly composed of amorphous silicon at the first process temperature, the thermal damage to the silicon wafer 200 caused by high temperature can be reduced, the life of the cell can be improved, and the perforation phenomenon in the thinner areas of the amorphous silicon layer 205 can be reduced, thereby improving the passivation effect of the second region and improving the stability of the cell efficiency.
[0074] In some embodiments, in step 105, when boron doping is performed on the amorphous silicon layer 205 by a low-temperature CVD process to form a boron-doped amorphous silicon layer 206, boron doping can be performed on the amorphous silicon layer 205 by a low-temperature CVD process at a second process temperature to form a boron-doped amorphous silicon layer 206, wherein the range of the second process temperature is 250 ℃ to 400 ℃.
[0075] For example, the second process temperature is 250 ℃, 280 ℃, 300 ℃, 330 ℃, 350 ℃ or 400 ℃.
[0076] In the above embodiments, since the second process temperature is relatively low, boron doping at the second process temperature can reduce the thermal damage to the silicon wafer 200 caused by high temperature, improve the life of the cell, and reduce the perforation phenomenon in the thinner area of the amorphous silicon layer 205, thereby improving the passivation effect of the second region and improving the stability of cell efficiency.
[0077] In some embodiments, when preparing an amorphous silicon layer 205 in step 104, in the second region, on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer, and in the spacer region, the amorphous silicon layer 205 can be prepared by a low-temperature CVD process using a PECVD device.
[0078] For example, a low-pressure CVD equipment is used in the process. The low-pressure CVD equipment is a PECVD equipment. Specifically, the PECVD can be a plate-type PECVD to facilitate single-sided coating processes.
[0079] The gas pressure inside the PECVD equipment chamber is 100 mTorr~600 mTorr.
[0080] In the above embodiments, by using a PECVD equipment, an amorphous silicon layer 205 can be prepared using a low-temperature CVD process, thereby reducing the process temperature and minimizing thermal damage. Furthermore, by using a plate-type PECVD equipment, the surface of the silicon wafer 200 on the first side 202 can be bonded to the substrate of the plate-type PECVD equipment during the process, effectively reducing the contact between process gases and the surface of the silicon wafer 200 on the first side 202, and reducing the occurrence of plating around (i.e., deposition of the amorphous silicon layer 205 on the surface of the silicon wafer 200 on the first side 202).
[0081] In some embodiments, in step 105, when boron doping is performed on the amorphous silicon layer 205 by a low-temperature CVD process to form a boron-doped amorphous silicon layer 206, boron doping can be performed on the amorphous silicon layer 205 by a low-temperature CVD process using a PECVD device to form a boron-doped amorphous silicon layer 206.
[0082] For example, the gas pressure inside the PECVD equipment chamber during the process is 100 mTorr to 600 mTorr. Specifically, plate PECVD can be used.
[0083] In the above embodiments, by using a PECVD equipment, a low-temperature CVD process can be used to dope the amorphous silicon layer 205 with boron, thereby reducing the process temperature and thermal damage. Furthermore, by using a plate-type PECVD equipment, the surface of the silicon wafer 200 on the first side 202 can be bonded to the substrate of the plate-type PECVD equipment during the process, effectively reducing the contact between process gases and the surface of the silicon wafer 200 on the first side 202, and reducing the occurrence of the diffusion phenomenon (i.e., boron doping into the surface of the silicon wafer 200 on the first side 202).
[0084] Figure 7 The diagram shown is a schematic flowchart of the process for preparing a tunneling oxide layer and a heavily phosphorus-doped layer according to an exemplary embodiment of this application. Figure 8 The diagram shown is a schematic representation of the structure of a silicon wafer after the preparation of a tunneling oxide layer, according to an exemplary embodiment of this application. Figure 9 The diagram shown is a schematic representation of the structure of a silicon wafer after the preparation of a polycrystalline silicon layer, according to an exemplary embodiment of this application. Figure 10 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a heavily phosphorus-doped layer according to an exemplary embodiment of this application.
[0085] In some embodiments, during step 101, when the tunneling oxide layer 201 and the heavily phosphorus-doped layer 204 are sequentially prepared in the first region, the second region, and the spacer region, as follows: Figures 7-10 As shown, the following steps 301 to 304 can be performed.
[0086] Step 301: Prepare a tunneling oxide layer in the first region, the second region, and the interval region.
[0087] For example, an LPCVD equipment can be used to prepare the tunneling oxide layer 201. Specifically, oxygen can be introduced into the cavity of the LPCVD equipment at a process temperature of 550 °C to 650 °C to grow the tunneling oxide layer 201 on the surface of the silicon wafer 200 on the second side 203.
[0088] For example, the thickness of the tunneling oxide layer 201 ranges from 1 nm to 2 nm.
[0089] Step 302: Prepare a polycrystalline silicon layer on the side of the tunneling oxide layer away from the silicon wafer.
[0090] For example, after preparing the tunneling oxide layer 201, the cavity of the LPCVD equipment can be evacuated first, and then silane can be introduced under conditions of a temperature range of 550 ℃~650 ℃ and a pressure range of 150 mTorr~500 mTorr. The gas is used to grow a polycrystalline silicon layer 208 (commonly known as Poly-Si) on the surface of the tunneling oxide layer 201 through thermal decomposition.
[0091] For example, the thickness of the polysilicon layer 208 ranges from 150 nm to 300 nm.
[0092] Step 303: Dope phosphorus into the polycrystalline silicon layer to form a heavily phosphorus-doped layer.
[0093] For example, a phosphorus diffusion process can be performed in a diffusion furnace to form a heavily phosphorus-doped layer 204. Specifically, phosphorus oxychloride, oxygen, and nitrogen can be introduced into the cavity of the diffusion furnace under low-pressure conditions in the temperature range of 800 °C to 900 °C to dope the polycrystalline silicon layer 208 with phosphorus to form a heavily phosphorus-doped layer 204 (commonly known as an N++ layer). In addition, the portion of the heavily phosphorus-doped layer 204 away from the silicon wafer 200 also includes phosphorosilicate glass (PSG).
[0094] For example, the sheet resistance of the phosphorus-doped layer 204 ranges from 20 Ω to 80 Ω.
[0095] For example, the thickness of the phosphosilicate glass ranges from 10 nm to 60 nm.
[0096] In the above embodiments, the tunneling oxide layer 201 and the phosphorus heavily doped layer 204 can be prepared through steps 301 to 303.
[0097] Figure 11 The diagram shown is a flowchart illustrating a method for removing the tunneling oxide layer and the heavily phosphorus-doped layer in the second region and the spacer region according to an exemplary embodiment of this application. Figure 12 The diagram shown is a schematic representation of the structure of a silicon wafer after the fabrication of the first mask layer, provided in an exemplary embodiment of this application. Figure 13 The diagram shown is a schematic representation of the structure for laser processing of the second region provided in an exemplary embodiment of this application. Figure 13 The middle arrow represents the laser, and the area between the dashed lines on either side of each arrow represents the laser processing area. Figure 3 The structure of the silicon wafer after removing the tunneling oxide layer 201 and the phosphorus-doped layer 204 remaining in the second region and the spacer region, as well as the first mask layer 209 in the first region, is shown.
[0098] In some embodiments, during step 102, when removing the first mask layer, tunneling oxide layer, and heavily phosphorus-doped layer from the second region and the spacer region, as... Figures 11-13 and Figure 3 As shown, the following steps 401 to 402 can be performed.
[0099] Step 401: Groove the first mask layer of the second region and the interval region using a laser.
[0100] In this process, the laser concentrates energy locally on the first mask layer 209, causing the first mask layer 209 in the laser-irradiated area to loosen, i.e., create a groove. However, the laser cannot completely remove the tunneling oxide layer 201 and the heavily doped phosphorus layer 204 in the second region and the spacer region. Therefore, step 403 is required to remove the remaining tunneling oxide layer and heavily doped phosphorus layer in the second region and the spacer region.
[0101] Step 402: Remove the first mask layer, phosphorus-doped layer and tunneling oxide layer of the second region and the spacer region by wet etching process.
[0102] Specifically, since the first region has a first mask layer 209, after the wet etching process is performed in step 402, the first mask layer 209 can protect the tunneling oxide layer 201 and the heavily phosphorus-doped layer 204 in the first region from being removed. In step 402, after the first mask layer 209, the heavily phosphorus-doped layer 204, and the tunneling oxide layer 201 of the second region and the spacer region are removed by the wet etching process, the first mask layer 209 of the first region can be removed again by the wet etching process.
[0103] In addition, in step 402, besides removing the first mask layer, heavily doped phosphorus layer, and tunneling oxide layer from the second region and the spacer region, the polysilicon and phosphorus diffusion-deposited portions around the first side 202 of the silicon wafer 200 are also removed, and as... Figure 4 As shown, a textured structure is also formed on the surface of the silicon wafer 200 on the first side 202 and on the surface of the silicon wafer 200 on the second side 203 located in the second region and the spacer region (i.e., step 103).
[0104] In the above embodiments, through steps 401 to 402, the first mask layer 209, the phosphorus heavily doped layer 204, and the tunneling oxide layer 201 of the second region and the interval region can be precisely removed. Furthermore, by removing the polycrystalline silicon and phosphorus diffusion portion that were deposited around the first side 202 of the silicon wafer 200, the battery performance is improved. In addition, by forming a textured structure on the surface of the first side 202 of the silicon wafer 200, the light absorption rate of the silicon wafer 200 can be increased, thereby improving the battery efficiency.
[0105] Figure 14 The diagram shown is a flowchart illustrating a method for removing a boron-doped amorphous silicon layer on the side of the silicon wafer away from the heavily phosphorus-doped layer, and a boron-doped amorphous silicon layer in the intervening region, according to an exemplary embodiment of this application. Figure 15 The diagram shown is a schematic representation of the structure of a silicon wafer after the fabrication of the second mask layer, provided in an exemplary embodiment of this application. Figure 16The diagram shown is a schematic representation of the structure for laser processing of a first region and an interval region provided in an exemplary embodiment of this application. Figure 16 The middle arrow represents the laser, and the area between the dashed lines on either side of each arrow represents the laser processing area. Figure 5 The structure of the silicon wafer after removing the boron-doped amorphous silicon layer 206 remaining in the first region and the spacer region, and the second mask layer 210 in the second region, is shown.
[0106] In some embodiments, during step 104, when removing the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region, as... Figures 14-16 and Figure 5 As shown, the following steps 501 to 503 can be performed.
[0107] Step 501: At the third process temperature, prepare a second mask layer on the side of the boron-doped amorphous silicon layer away from the silicon wafer.
[0108] The third process temperature range is 300 ℃~400 ℃.
[0109] For example, the third process temperature is 300 ℃, 330 ℃, 350 ℃, 370 ℃ or 400 ℃.
[0110] For example, the second mask layer 210 includes silicon nitride (molecular formula SiNx).
[0111] For example, the thickness of the second mask layer 210 ranges from 30 nm to 60 nm, such as 40 nm.
[0112] For example, the second mask layer 210 can be prepared using a PECVD device, silane, and ammonia.
[0113] Step 502: Groove the second mask layer of the first region and the interval region using a laser.
[0114] In this process, the laser concentrates energy locally on the second mask layer 210, causing the second mask layer 210 in the laser-irradiated area to loosen, i.e., create a groove. However, the laser cannot completely remove the second mask layer and part of the boron-doped amorphous silicon layer 206 in the first region and the spacer region. Therefore, step 503 is required to remove the remaining boron-doped amorphous silicon layer 206 in the first region and the spacer region.
[0115] Step 503: Remove the second mask layer and boron-doped amorphous silicon layer in the first region and the spacer region by wet etching process.
[0116] Specifically, the wet etching process may include two etching sub-steps. Since the second region has a second mask layer 210, in the first etching sub-step in step 503, i.e., when the wet etching process is performed to remove the second mask layer 210 and the boron-doped amorphous silicon layer 206 of the first region and the spacer region, the second region is protected from etching of the boron-doped amorphous silicon layer 206 by the second mask layer 210. Then, a second etching sub-step is performed targeting the second mask layer 210 of the second region, so that the second mask layer 210 of the second region is removed.
[0117] In the above embodiments, the second mask layer 210 and the boron-doped amorphous silicon layer 206 in the first region and the interval region can be accurately removed through the above steps 501 to 503.
[0118] Figure 17 The diagram shown is a schematic diagram of the structure of a silicon wafer after the preparation of a conductive film layer according to an exemplary embodiment of this application.
[0119] In some embodiments, such as Figure 17 As shown, after step 106, that is, after removing the boron-doped amorphous silicon layer 206 on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200, and the boron-doped amorphous silicon layer 206 in the spacer region, a conductive film layer 211 can be prepared on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200 (i.e., the first region), the spacer region, and the side of the boron-doped amorphous silicon layer 206 away from the silicon wafer 200 (i.e., the second region). Then, the conductive film layer 211 in the spacer region is grooved and cleaned by laser to insulate the first region and the second region.
[0120] For example, the conductive film layer 211 includes indium tin oxide (ITO).
[0121] For example, a magnetron sputtering device and an indium tin oxide target can be used to physically sputter target particles to the side of the phosphorus heavily doped layer 204 away from the silicon wafer 200, the spacer region, and the side of the boron doped amorphous silicon layer 206 away from the silicon wafer 200 at a temperature of 150 ℃ to 300 ℃, thereby depositing a conductive film layer 211.
[0122] For example, the thickness of the conductive film layer 211 ranges from 60 nm to 90 nm.
[0123] In the above embodiments, by preparing the conductive film layer 211, the lateral carrier flow efficiency of the phosphorus heavily doped layer 204 and the boron doped amorphous silicon layer 206 can be improved, and the contact resistance between the metal gate lines and the phosphorus heavily doped layer 204, and between the metal gate lines and the boron doped amorphous silicon layer 206 on both sides of the conductive film layer 211 can be reduced.
[0124] Figure 18The diagram shown is a schematic representation of the structure of a silicon wafer after the fabrication of the first antireflection passivation layer, according to an exemplary embodiment of this application. Figure 19 The diagram shown is a schematic diagram of the structure of a silicon wafer after the fabrication of the second antireflection passivation layer, provided by an exemplary embodiment of this application.
[0125] In some embodiments, after forming a conductive film layer 211 on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200, in the spacer region, and on the side of the boron-doped amorphous silicon layer 206 away from the silicon wafer 200, as... Figure 18 As shown, a first antireflection passivation layer 212 can also be prepared on the side of the conductive film layer 211 away from the silicon wafer 200, and then the first antireflection passivation layer 212 in the spaced area can be opened by laser (grooving and cleaning to remove it), thereby avoiding the film layer in the adjacent first region from conducting with the film layer in the second region; and / or, as Figure 19 As shown, a second antireflection passivation layer 213 can be prepared on the first side 202 of the silicon wafer 200.
[0126] For example, the thickness of the first antireflection passivation layer 212 is in the range of 70 nm to 80 nm, such as 75 nm. For example, the first antireflection passivation layer 212 includes silicon nitride and / or silicon oxynitride.
[0127] For example, the thickness of the second antireflection passivation layer 213 is in the range of 70 nm to 80 nm, such as 78 nm.
[0128] For example, the second antireflection passivation layer 213 includes silicon nitride and / or silicon oxynitride.
[0129] For example, both the first antireflective passivation layer 212 and the second antireflective passivation layer 213 can be prepared by PECVD equipment and process gases such as silane, ammonia, and nitrous oxide.
[0130] In the above embodiments, by preparing the first antireflection passivation layer 212 and the second antireflection passivation layer 213, the light absorption rate of the solar cell can be improved, thereby improving the photoelectric conversion efficiency of the solar cell.
[0131] Figure 20 The diagram shown is a schematic flowchart of a method for screen printing grid lines provided in an exemplary embodiment of this application. Figure 21 The diagram shown is a schematic representation of a structure for laser processing of a first region, a second region, and an interval region, provided in an exemplary embodiment of this application. Figure 21 The middle arrow represents a laser, and the area between the dashed lines on either side of each arrow represents the laser processing area. Figure 22 The diagram shown is a schematic diagram of the structure of a silicon wafer after opening the first anti-reflection passivation layer and conductive film layer according to an exemplary embodiment of this application.
[0132] In some embodiments, after the first antireflection passivation layer 212 is formed on the side of the conductive film layer 211 away from the silicon wafer 200, as... Figures 20-22 As shown, steps 601 and 602 can also be performed.
[0133] Step 601: Create openings in the first antireflection passivation layer and conductive film layer of the first and second regions using a laser.
[0134] The through-hole formed by the openings in the first anti-reflection passivation layer 212 and the conductive film layer 211 is shown in Figure 214.
[0135] Step 602: Using paste at a preset temperature, screen printing is performed in the first area, the second area, and the interval area to form grid lines. The preset temperature range is 200 ℃ to 400 ℃.
[0136] In the aforementioned embodiments, the steps of removing the conductive film layer 211 of the interval region by laser and opening the first anti-reflection passivation layer 212 of the interval region by laser can be performed simultaneously with step 601.
[0137] For example, the preset temperature is 200 ℃, 250 ℃, 300 ℃, 350 ℃ or 400 ℃.
[0138] In traditional BC battery film preparation methods, high-temperature pastes are typically used for screen printing in the first, second, and spacer regions. However, using high-temperature pastes can cause the boron-doped amorphous silicon layer 206 to convert into polycrystalline silicon, reducing its passivation effect and causing thermal damage to the silicon wafer 200. In the above embodiment, using low-temperature pastes for screen printing can prevent the phosphorus-doped layer 204 and the boron-doped amorphous silicon layer 206 from burning through. Furthermore, since the low-temperature paste cannot completely burn through the conductive film layer 211 and the first antireflection passivation layer 212, a laser is needed to perform dot-shaped film opening (i.e., to create holes in the first antireflection passivation layer 212 and the conductive film layer 211) before performing step 602. This allows the low-temperature paste to pass through the holes in the first antireflection passivation layer 212 and the conductive film layer 211 and contact the phosphorus-doped layer 204 and the boron-doped amorphous silicon layer 206, thereby preventing poor contact between the gate lines formed by the low-temperature paste and the phosphorus-doped layer 204 and the boron-doped amorphous silicon layer 206.
[0139] Figure 23 The diagram shown is a flowchart illustrating a specific method for preparing a film layer of a back contact battery according to an embodiment of this application.
[0140] In summary, this application also provides a specific method for preparing the film layer of a back contact battery, including the following steps 701 to 718.
[0141] Step 701: Obtain the cut silicon wafer.
[0142] Step 702: Polish the cut silicon wafers using a wet polishing method.
[0143] Step 703: Prepare tunneling oxide layers in the first region, the second region, and the interstitial region using LPCVD.
[0144] Step 704: Prepare a polycrystalline silicon layer on the side of the tunnel oxide layer away from the silicon wafer by LPCVD.
[0145] Step 705: Phosphorus is doped into the polycrystalline silicon layer by phosphorus diffusion to form a heavily phosphorus-doped layer.
[0146] Step 706: Prepare a first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer by PECVD.
[0147] Step 707: Groove the first mask layer of the second region and the interval region using a laser.
[0148] Step 708: Remove the first mask layer, tunneling oxide layer, and phosphorus heavily doped layer of the second region and the spacer region, as well as the first mask layer of the first region, by wet etching process.
[0149] Step 709: Prepare an amorphous silicon layer in the second region, on the side of the heavily phosphorus-doped layer away from the silicon wafer, and in the interstitial region using a low-temperature CVD process.
[0150] Step 710: Boron doping is performed on the amorphous silicon layer using a low-temperature CVD process to form a boron-doped amorphous silicon layer.
[0151] Step 711: Prepare a second mask layer on the side of the boron-doped amorphous silicon layer away from the silicon wafer by PECVD.
[0152] Step 712: Groove the second mask layer of the first region and the interval region using a laser.
[0153] Step 713: Remove the second mask layer and boron-doped amorphous silicon layer of the first region and the spacer region, as well as the second mask layer of the second region, by wet etching process.
[0154] Step 714: Conductive film layers are prepared by magnetron sputtering on the side of the heavily phosphorus-doped layer away from the silicon wafer, the spacer region, and the side of the boron-doped amorphous silicon layer away from the silicon wafer.
[0155] Step 715: Prepare the first anti-reflection passivation layer on the side of the conductive film away from the silicon wafer by PECVD.
[0156] Step 716: Prepare a second antireflection passivation layer on the first side of the silicon wafer by PECVD.
[0157] Step 717: Use a laser to create openings in the first antireflection passivation layer and conductive film layer in the first and second regions, and use a laser to create grooves in the first antireflection passivation layer and conductive film layer in the interval region and clean and remove them.
[0158] Step 718: Using paste at a preset temperature, screen printing is performed in the first area, the second area, and the interval area to form grid lines.
[0159] Figure 24 The diagram shown is a schematic diagram of the film preparation system for a back contact battery provided in an exemplary embodiment of this application.
[0160] Based on the same concept, such as Figure 24 As shown, this application embodiment also provides a film preparation system 800 for a back contact battery, used to prepare a film on a silicon wafer 200. The silicon wafer 200 has a first side 202 and a second side 203 in a first direction. The second side 203 of the silicon wafer 200 has a first region and a second region arranged in an interdigitated manner. There is also a gap region between adjacent first regions and second regions. The film preparation system 800 for a back contact battery includes: a first preparation device 801, a second preparation device 802, a first removal device 803, a texturing device 804, a third preparation device 805, and a second removal device 806. The first fabrication apparatus 801 is configured to sequentially fabricate a tunneling oxide layer 201 and a heavily phosphorus-doped layer 204 in a first region, a second region, and a spacer region, wherein the heavily phosphorus-doped layer 204 comprises a phosphorus-doped polycrystalline silicon layer; the second fabrication apparatus 802 is configured to fabricate a first mask layer 209 on the side of the heavily phosphorus-doped layer 204 away from the silicon wafer 200; the first removal apparatus 803 is configured to remove the first mask layer 209, the tunneling oxide layer 201, and the heavily phosphorus-doped layer 204 in the second region and the spacer region; and the texturing apparatus 804... The equipment is configured to texturize the second region and the spacer region; the third preparation equipment 805 is configured to prepare an amorphous silicon layer 205 in the second region, on the side of the phosphorus-doped layer 204 away from the silicon wafer 200 and in the spacer region, and to boron-dopant the amorphous silicon layer 205 by a low-temperature CVD process to form a boron-doped amorphous silicon layer 206; the second removal equipment 806 is configured to remove the boron-doped amorphous silicon layer 206 on the side of the phosphorus-doped layer 204 away from the silicon wafer 200 and the boron-doped amorphous silicon layer 206 in the spacer region.
[0161] For example, the first preparation apparatus 801 includes: an LPCVD apparatus and a diffusion furnace.
[0162] For example, the second preparation apparatus 802 includes a PECVD apparatus.
[0163] For example, the first removal device 803 includes a laser device and a tank-type wet cleaning device.
[0164] For example, the texturing equipment 804 includes: a tank-type wet cleaning equipment.
[0165] For example, the third preparation apparatus 805 includes: a plate-type low-pressure CVD apparatus, which may be a PECVD apparatus.
[0166] For example, the second removal device 806 includes: PECVD equipment, laser equipment, and tank-type wet cleaning equipment, etc.
[0167] Among them, the same equipment in the first preparation equipment 801, the second preparation equipment 802, the first removal equipment 803, the texturing equipment 804, the third preparation equipment 805, and the second removal equipment 806 can be the same equipment or different equipment.
[0168] Since the film preparation system 800 for the back contact battery is used to perform the film preparation method for the back contact battery in the foregoing embodiments, the film preparation system 800 for the back contact battery includes all the technical features and effects of the film preparation method for the back contact battery, and will not be repeated here.
[0169] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.
[0170] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.
[0171] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.
[0172] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0173] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.
Claims
1. A method for preparing a film layer in a back contact battery, characterized in that, For preparing a film layer on a silicon wafer, the silicon wafer having a first side and a second side in a first direction, the second side of the silicon wafer having a first region and a second region arranged in an interlocking manner, and a spacing region between adjacent first regions and second regions, including: A tunneling oxide layer and a phosphorus-doped layer are sequentially prepared in the first region, the second region and the interval region, wherein the phosphorus-doped layer comprises a phosphorus-doped polycrystalline silicon layer. A first mask layer is prepared on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the first mask layer, the tunneling oxide layer, and the heavily phosphorus-doped layer are removed from the second region and the spacer region; The second region and the interval region are texturized; An amorphous silicon layer is prepared in the second region, on the side of the heavily phosphorus-doped layer away from the silicon wafer, and in the spacer region; Boron-doped amorphous silicon layer is formed by boron doping of the amorphous silicon layer using a low-temperature CVD process. Remove the boron-doped amorphous silicon layer on the side of the phosphorus-doped layer away from the silicon wafer, as well as the boron-doped amorphous silicon layer in the spacer region.
2. The method for preparing the film layer of a back contact battery according to claim 1, characterized in that, The fabrication of an amorphous silicon layer in the second region, on the side of the heavily phosphorus-doped layer away from the silicon wafer, and in the spacer region includes: At a first process temperature, an amorphous silicon layer is prepared in the second region, on the side of the phosphorus-doped layer away from the silicon wafer, and in the spacer region, wherein the range of the first process temperature is 250 °C to 400 °C. And / or, The step of boron doping the amorphous silicon layer using a low-temperature CVD process to form a boron-doped amorphous silicon layer includes: At a second process temperature, the amorphous silicon layer is boron-doped using a low-temperature CVD process to form a boron-doped amorphous silicon layer, wherein the range of the second process temperature is 250 ℃ to 400 ℃.
3. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, The fabrication of an amorphous silicon layer in the second region, on the side of the heavily phosphorus-doped layer away from the silicon wafer, and in the spacer region includes: Based on PECVD equipment, an amorphous silicon layer is prepared in the second region, the side of the phosphorus-doped layer away from the silicon wafer, and the spacer region by a low-temperature CVD process. And / or, The step of boron doping the amorphous silicon layer using a low-temperature CVD process to form a boron-doped amorphous silicon layer includes: Based on the PECVD equipment, the amorphous silicon layer is boron-doped using a low-temperature CVD process to form a boron-doped amorphous silicon layer.
4. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, The step of fabricating a first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer includes: The first mask layer, comprising silicon nitride, is deposited on the side of the heavily phosphorus-doped layer away from the silicon wafer using a PECVD device.
5. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, The step of sequentially preparing a tunneling oxide layer and a phosphorus-doped layer in the first region, the second region, and the interval region includes: A tunneling oxide layer is prepared in the first region, the second region, and the interval region; A polycrystalline silicon layer is formed on the side of the tunneling oxide layer away from the silicon wafer; Phosphorus is doped into the polycrystalline silicon layer to form the heavily phosphorus-doped layer.
6. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, The removal of the first mask layer, the tunneling oxide layer, and the heavily phosphorus-doped layer from the second region and the spacer region includes: The first mask layer of the second region and the interval region is slotted using a laser; The first mask layer, the heavily phosphorus-doped layer, and the tunneling oxide layer of the second region and the spacer region are removed by a wet etching process.
7. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, The removal of the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region, includes: At a third process temperature, a second mask layer is prepared on the side of the boron-doped amorphous silicon layer away from the silicon wafer, wherein the third process temperature ranges from 300 °C to 400 °C. The second mask layer of the first region and the interval region is slotted using a laser; The second mask layer and the boron-doped amorphous silicon layer in the first region and the spacer region are removed by a wet etching process.
8. The method for preparing the film layer of a back contact battery according to claim 1 or 2, characterized in that, After removing the boron-doped amorphous silicon layer on the side of the heavily phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region, the method further includes: Conductive films are prepared on the side of the heavily phosphorus-doped layer away from the silicon wafer, in the spacer region, and on the side of the boron-doped amorphous silicon layer away from the silicon wafer. The conductive film layer in the spaced region is removed by laser.
9. The method for preparing the film layer of a back contact battery according to claim 8, characterized in that, After forming conductive films on the side of the heavily phosphorus-doped layer away from the silicon wafer, in the spacer region, and on the side of the boron-doped amorphous silicon layer away from the silicon wafer, the method further includes: A first antireflection passivation layer is prepared on the side of the conductive film layer away from the silicon wafer; The first antireflection passivation layer in the spaced region is opened using a laser. And / or, A second antireflection passivation layer is prepared on the first side of the silicon wafer.
10. The method for preparing the film layer of a back contact battery according to claim 9, characterized in that, After the first antireflection passivation layer is formed on the side of the conductive film layer away from the silicon wafer, the method further includes: A hole is created in the first antireflection passivation layer and the conductive film layer in the first region and the second region by using a laser. Using a paste at a preset temperature, screen printing is performed on the first region, the second region, and the interval region to form grid lines. The preset temperature range is 200 ℃ to 400 ℃.
11. A film preparation system for a back contact battery, characterized in that, For preparing a film layer on a silicon wafer, the silicon wafer having a first side and a second side in a first direction, the second side of the silicon wafer having a first region and a second region arranged in an interlocking manner, and a spacing region between adjacent first regions and second regions, including: A first fabrication apparatus is configured to sequentially fabricate a tunneling oxide layer and a heavily phosphorus-doped layer in the first region, the second region, and the interval region, wherein the heavily phosphorus-doped layer comprises a phosphorus-doped polycrystalline silicon layer. The second fabrication apparatus is configured to fabricate a first mask layer on the side of the heavily phosphorus-doped layer away from the silicon wafer; A first removal device is configured to remove the first mask layer, the tunneling oxide layer, and the phosphorus-doped layer from the second region and the spacer region; A flocking device is configured to flock the second region and the interval region; A third fabrication apparatus is configured to fabricate an amorphous silicon layer in the second region, on the side of the phosphorus-doped layer away from the silicon wafer, and in the spacer region, and to perform boron doping on the amorphous silicon layer by a low-temperature CVD process to form a boron-doped amorphous silicon layer. The second removal device is configured to remove the boron-doped amorphous silicon layer on the side of the phosphorus-doped layer away from the silicon wafer, and the boron-doped amorphous silicon layer in the spacer region.