Back contact cell and preparation method thereof, laminated cell and photovoltaic module

Abstract

The invention relates to the technical field of solar cells, and particularly discloses a back contact cell and a preparation method thereof, a laminated cell and a photovoltaic module. The preparation method comprises the following steps: forming a back contact structure comprising a P-type region and an N-type region on the back surface of a silicon substrate; when at least one region is formed, a first oxide layer is formed on a silicon substrate through an O3 oxidation method, then a second oxide layer is formed on the first oxide layer through a PECVD method, the first oxide layer and the second oxide layer are in direct contact to form a composite tunneling oxide layer, and then a doped polycrystalline silicon layer is formed on the composite tunneling oxide layer. According to the invention, the composite tunneling oxide layer is prepared through O3 oxidation and PECVD superposition, and optimized thickness matching and process parameters are combined, so that the uniformity and compactness of the oxide layer are remarkably improved, the interface passivation quality is improved, and the carrier recombination is effectively reduced, and therefore, the back contact cell with high conversion efficiency is prepared, and the back contact cell is suitable for laminated cells and photovoltaic modules. And the method is good in process compatibility and suitable for industrial production.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a back-contact cell and its preparation method, a tandem cell, and a photovoltaic module. Background Technology

[0002] Tunneling oxide passivated contact structures are key to constructing high-efficiency crystalline silicon solar cells, especially back-contact (IBC) cells. This structure consists of an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer, enabling both excellent surface passivation (significantly reducing carrier recombination) and efficient selective carrier transport.

[0003] Currently, methods for preparing ultrathin tunneling silicon oxide layers include high-temperature oxidation, plasma-assisted oxidation (PECVD), atomic layer deposition (ALD), wet oxidation, nitric acid oxidation (NAOS), and hydrogen peroxide method. Among these, PECVD is favored in industrial production due to its advantages such as fewer process steps, high deposition rate, and relatively low cost, as it can be integrated with subsequent in-situ doped polycrystalline silicon layer deposition in the same equipment. However, the PECVD method alone has inherent drawbacks in preparing ultrathin oxide layers: First, the plasma in the PECVD process physically bombards the silicon substrate surface, introducing high-density interface defects that become recombination centers for charge carriers, thus degrading the passivation effect; second, for ultrathin films with a thickness of less than 2 nm, the film thickness uniformity of the PECVD process is extremely difficult to control, leading to large fluctuations in battery performance and low production yield.

[0004] Furthermore, to address the aforementioned issues, the industry has attempted to introduce thermal oxidation to prepare high-quality tunneling oxide layers. However, the standard thermal oxidation process temperature is typically above 800°C, which conflicts with the temperature limit of graphite boat supports commonly used in industrial tubular PECVD equipment (typically below 650°C), making it difficult to directly integrate the two processes into existing production lines. Replacing all supports with high-temperature resistant materials would incur significant equipment modification costs.

[0005] Therefore, there is an urgent need in this field for a method to prepare an ultrathin tunneling oxide layer that is suitable for industrial production, can ensure high-quality interface passivation and achieve excellent film uniformity. Summary of the Invention

[0006] The purpose of this invention is to provide a back contact cell and its preparation method, a tandem cell, and a photovoltaic module, so as to overcome the technical bottlenecks of existing PECVD methods for preparing ultrathin tunneling oxide layers, such as numerous interface defects, poor uniformity, and incompatibility with thermal oxidation processes.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0009] A back contact structure comprising P-regions and N-regions is formed on the back side of a silicon substrate; wherein, when forming at least one of the P-regions and N-regions, the process includes: forming a first oxide layer on the silicon substrate by O3 oxidation; forming a second oxide layer on the first oxide layer by PECVD, wherein the first oxide layer and the second oxide layer together constitute a composite tunneling oxide layer; and forming a doped polycrystalline silicon layer on the composite tunneling oxide layer.

[0010] Furthermore, the thickness of the first oxide layer is 0.3~0.8 nm, the thickness of the second oxide layer is 0.6~1.5 nm, and the total thickness of the composite tunneling oxide layer is 0.9~1.8 nm.

[0011] Furthermore, the total thickness of the composite tunneling oxide layer is 1.5~1.8 nm.

[0012] Further, the total thickness of the composite tunneling oxide layer is 1.8 nm; specifically, the thicknesses of the first oxide layer and the second oxide layer are 0.3 nm and 1.5 nm, or 0.4 nm and 1.4 nm, or 0.5 nm and 1.3 nm, or 0.6 nm and 1.2 nm, or 0.7 nm and 1.1 nm, or 0.8 nm and 1.0 nm, respectively.

[0013] Furthermore, the process conditions for the O3 oxidation method include: a temperature of 90~100℃, an O3 flow rate of 1400~1600ppb, and a reaction time of 800~2500s.

[0014] Furthermore, the process conditions of the PECVD method include: using nitrous oxide as the reaction gas, a gas flow rate of 14000~16000 sccm, a radio frequency power of 14000~16000 W, and a reaction time of 60~180s.

[0015] Furthermore, the preparation method specifically includes the following steps:

[0016] S1: In the P region on the back side of the silicon substrate, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping, and then a boron-doped polycrystalline silicon layer is formed by annealing.

[0017] S2: The first laser engraving defines the P-area graphic and the Gap area;

[0018] S3: In the N-region on the back side of the silicon substrate, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping, followed by annealing to form a phosphorus-doped polycrystalline silicon layer.

[0019] S4: The second laser engraving defines the N-zone graphic and the Gap zone;

[0020] S5: Perform surface treatment, passivation layer deposition, and back electrode fabrication.

[0021] Secondly, the present invention provides a back contact battery, which is prepared by the above-described preparation method.

[0022] Furthermore, the back contact cell includes: a silicon substrate and alternating P-regions and N-regions located on its back side, wherein at least one of the P-regions and N-regions is provided with a passivation contact structure, the passivation contact structure including a composite tunneling oxide layer and a doped polycrystalline silicon layer thereon; the composite tunneling oxide layer is formed by directly stacking a first oxide layer formed by O3 oxidation and a second oxide layer deposited by PECVD.

[0023] Thirdly, the present invention provides a stacked battery, comprising a bottom battery, which is the aforementioned back contact battery or a back contact battery prepared by the aforementioned back contact battery preparation method; and a top battery, which is located on one side of the bottom battery and is electrically connected to the bottom battery.

[0024] Fourthly, the present invention provides a photovoltaic module, comprising a battery string, which is formed by connecting multiple back-contact batteries as described above, or by connecting multiple back-contact batteries prepared by the above-described method, or by connecting multiple stacked batteries as described above; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] (1) This invention creatively combines low-temperature ozone oxidation with PECVD to prepare a composite tunneling oxide layer. Ozone oxidation can form a dense, uniform, plasma-damaged ultrathin silicon oxide layer without damaging the silicon substrate. This layer can provide excellent interfacial chemical passivation and serve as an ideal nucleation substrate for subsequent PECVD deposition, effectively buffering plasma bombardment and significantly reducing the interfacial state density.

[0027] (2) By introducing low-temperature ozone oxidation as the bottom layer, this invention effectively improves the substrate surface state of subsequent PECVD film formation and significantly enhances the overall uniformity of the composite tunneling oxide layer. At the same time, by optimizing the thickness matching of the oxide layer, the carrier tunneling and surface passivation achieve the best balance, thereby obtaining a higher minority carrier lifetime (up to 2395 μs) and implicit open-circuit voltage (up to 0.744 V).

[0028] (3) The ozone oxidation process used in this invention is a low-temperature process that is fully compatible with the graphite boat carrier used in existing PECVD production lines. It does not require expensive modifications or replacements of the core hardware, and effectively controls production costs while improving performance. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the back contact battery structure prepared by the method of this invention.

[0031] Figure 2 This is a schematic diagram of the sample location during the film uniformity experiment in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram showing the test point locations in the film uniformity experiment of this invention.

[0033] Figure 4 This is a comparison diagram of the film uniformity of different embodiments and comparative examples of the present invention;

[0034] Figure 5 Figure 1 shows a comparison of passivation performance between different embodiments and comparative examples of the present invention; wherein, Figure 2(a) is a comparison of minority carrier lifetime; Figure 3(b) is a comparison of implicit open-circuit voltage (iVoc); and Figure 4(c) is a comparison of recombination current density (J0).

[0035] Figure 6 Figure 1 shows a comparison of the electrical performance of different embodiments and comparative examples of the present invention; wherein, Figure 2(a) is a comparison of conversion efficiency (Eta); Figure 3(b) is a comparison of fill factor (FF); Figure 4(c) is a comparison of open circuit voltage (Voc); and Figure 5(d) is a comparison of short circuit current (Isc).

[0036] Explanation of key figure labels:

[0037] 1. Silicon substrate; 2. First oxide layer; 3. Second oxide layer; 4. Boron-doped polysilicon layer; 5. Phosphorus-doped polysilicon layer; 6. Gap region; 7. P-region electrode; 8. N-region electrode; 9. Back passivation layer; 10. Back antireflection layer; 11. Front passivation layer; 12. Front antireflection layer; Detailed Implementation

[0038] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other embodiments, well-known materials or methods have not been specifically described in order to avoid obscuring the invention.

[0039] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “an embodiment,” “an example,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0040] Terminology Explanation:

[0041] PECVD: Plasma Enhanced Chemical Vapor Deposition

[0042] TOPCon: Tunnel Oxide Passivated Contact;

[0043] ALD: Atomic Layer Deposition;

[0044] PVD: Physical Vapor Deposition;

[0045] PSG: Phosphosilicate Glass.

[0046] BSG: Boron Silicate Glass.

[0047] In a first aspect, the present invention provides a method for preparing a back contact battery, comprising the following steps:

[0048] A back contact structure comprising P-regions and N-regions is formed on the back side of a silicon substrate 1; wherein, when forming at least one of the P-regions and N-regions, the process includes: forming a first oxide layer 2 on the silicon substrate by O3 oxidation; forming a second oxide layer 3 on the first oxide layer 2 by PECVD, wherein the first oxide layer 1 and the second oxide layer 3 together constitute a composite tunneling oxide layer; and forming a doped polycrystalline silicon layer 5 on the composite tunneling oxide layer.

[0049] In one specific embodiment, the thickness of the first oxide layer 2 is 0.3~0.8 nm, the thickness of the second oxide layer 3 is 0.6~1.5 nm, and the total thickness of the composite tunneling oxide layer is 0.9~1.8 nm. For example, the thickness of the first oxide layer 2 can be 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, or between any two of the above values; the thickness of the second oxide layer 3 can be 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1.1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, or between any two of the above values; and the thickness of the composite tunneling oxide layer can be 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, or between any two of the above values.

[0050] In one specific embodiment, the total thickness of the composite tunneling oxide layer is 1.5~1.8 nm.

[0051] More specifically, the total thickness of the composite tunneling oxide layer is 1.8 nm; for example, the thicknesses of the first oxide layer 2 and the second oxide layer 3 are 0.3 nm and 1.5 nm, or 0.4 nm and 1.4 nm, or 0.5 nm and 1.3 nm, or 0.6 nm and 1.2 nm, or 0.7 nm and 1.1 nm, or 0.8 nm and 1.0 nm, respectively.

[0052] In one specific embodiment, the process conditions for the O3 oxidation method include: a temperature of 90~100℃, an O3 flow rate of 1400~1600 ppb, and a reaction time of 800~2500s. Specifically, the temperature for preparing the first oxide layer 2 by the O3 oxidation method is 95℃, the O3 flow rate is 1500 ppb, and the reaction time is 800~2500s; exemplaryly, the reaction time can be 800 s, 1100 s, 1400 s, 1700 s, 2000 s, 2100 s, 2300 s, 2500 s, or between any two of the above values.

[0053] In one specific embodiment, the process conditions of the PECVD method include: using nitrous oxide as the reactant gas, a gas flow rate of 14000~16000 sccm, a radio frequency power of 14000~16000 W, and a reaction time of 60~180 s. Specifically, in the PECVD method, the second oxide layer 3 is prepared by ionization of nitrous oxide (N2O) gas at a temperature of 430℃, a pressure of 2500 mtorr, a power of 15000 W, a pulse ratio of 1:125, a nitrous oxide flow rate of 15000 sccm, and a reaction time of 60~180 s. Exemplarily, the reaction time can be 60 s, 80 s, 100 s, 120 s, 140 s, 160 s, 170 s, 180 s, or between any two of the above values.

[0054] In one specific embodiment, the method for preparing the back contact battery includes the following steps:

[0055] S1: In the P region on the back side of silicon substrate 1, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping. After annealing, a boron-doped polycrystalline silicon layer 4 is formed.

[0056] S2: First laser engraving defines the P-area graphic and Gap area 6;

[0057] S3: In the N region on the back side of silicon substrate 1, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping. After annealing, a phosphorus-doped polycrystalline silicon layer 5 is formed.

[0058] S4: The second laser engraving defines the N-zone graphic and Gap area 6;

[0059] S5: Perform surface treatment, passivation layer deposition, and back electrode fabrication.

[0060] More specifically, the method for preparing a back contact battery includes the following steps:

[0061] S10: Provide an N-type silicon substrate 1, and prepare a first oxide layer 2 in the P-region on the back side of the silicon substrate 1 by oxidation with O3;

[0062] S20: On the first oxide layer 2, a second oxide layer 3 is prepared by PECVD, and then in-situ doping and deposition of a polycrystalline silicon layer are performed by PECVD to form a P-region passivation contact structure.

[0063] S30: Perform high-temperature annealing to crystallize the polysilicon layer in the P-region passivation contact structure, forming boron-doped polysilicon layer 4 and BSG mask.

[0064] S40: Perform the first laser engraving to define the P-region pattern and Gap region 6 on the back side of silicon substrate 1;

[0065] S50: Polish the area after laser engraving, and then prepare the first oxide layer 2 on the back N region of the silicon substrate 1 by O3 oxidation;

[0066] S60: On the first oxide layer 2 in the N region, the second oxide layer 3 is prepared by PECVD, and then in-situ doping and deposition of polysilicon layer are performed by PECVD to form the N region passivation contact structure.

[0067] S70: High-temperature annealing is performed to crystallize the polysilicon layer in the N-region passivation contact structure, forming a phosphorus-doped polysilicon layer 5 and a PSG mask.

[0068] S80: Perform a second laser engraving to define the N-region pattern and Gap region 6 on the back side of the silicon substrate;

[0069] S90: Remove the mask and polysilicon layer from the front and edge of silicon substrate 1, polish the area of ​​the second laser, then texturize the front and Gap areas 6 of silicon substrate 1, and finally remove the mask layer from the back.

[0070] S100: A front passivation layer 11 and a back passivation layer 9 are deposited on the front and back sides of the silicon substrate 1, respectively;

[0071] S110: A front antireflection layer 12 and a back antireflection layer 10 are deposited on the front and back sides of the silicon substrate 1, respectively;

[0072] S120: Gate electrodes corresponding to the N-region and P-region respectively are fabricated on the back side of silicon substrate 1 to form P-region electrode 7 and N-region electrode 8.

[0073] Secondly, the present invention provides a back contact battery, which is prepared by the above-described method.

[0074] In one specific embodiment, the back contact cell includes: a silicon substrate 1 and alternating P-regions and N-regions located on its back side, wherein at least one of the P-regions and N-regions is provided with a passivation contact structure, the passivation contact structure including a composite tunneling oxide layer and a doped polycrystalline silicon layer thereon; the composite tunneling oxide layer is formed by directly stacking a first oxide layer 2 formed by O3 oxidation and a second oxide layer 3 formed by PECVD deposition.

[0075] More specifically, the back contact battery includes:

[0076] Silicon substrate 1: An N-type silicon substrate 1 is used as the substrate, which has a front side (light incident surface) and a back side (electrode surface) arranged opposite to each other.

[0077] Backside doped region structure: On the back side of silicon substrate 1, alternating P-type and N-type regions are provided, forming an interdigitated distribution; wherein:

[0078] P-region passivation contact structure: includes a composite tunneling oxide layer and a boron-doped polysilicon layer 4; the composite tunneling oxide layer is composed of two layers directly stacked - the bottom layer is a first oxide layer 2 (thickness 0.3~0.8 nm) generated by O3 oxidation method, and the top layer is a second oxide layer 3 (thickness 0.6~1.5 nm) deposited by PECVD method. The total thickness of the composite tunneling oxide layer is controlled at 0.9~1.8 nm to optimize the carrier tunneling effect; on top of it is a boron-doped polysilicon layer 4, forming an emitter or back surface field.

[0079] N-region passivation contact structure: also includes a composite tunneling oxide layer (structure consistent with P-region) and a phosphorus-doped polysilicon layer 5, forming a back surface field or emitter.

[0080] Gap area: A gap area 6 is defined between the P area and the N area by laser engraving. This area serves as electrical isolation to prevent short circuits between the P and N areas.

[0081] Passivation and antireflection layer: A front passivation layer 11 and a front antireflection layer 12 are sequentially deposited on the front side of the silicon substrate 1 to reduce surface recombination and optical loss; a back passivation layer 9 and a back antireflection layer 10 are sequentially deposited on the back side of the silicon substrate 1, covering the P-region, N-region and Gap region 6, to provide full passivation.

[0082] Electrode system: All electrodes are located on the back of the battery, including P-area electrode 7 which is electrically connected to the P-area and N-area electrode 8 which is electrically connected to the N-area. The electrodes are arranged in a grid pattern, with no metal grid lines obstructing the front.

[0083] Thirdly, the present invention provides a stacked battery, comprising a bottom battery, which is the aforementioned back contact battery or a back contact battery prepared by the aforementioned back contact battery preparation method; and a top battery, which is located on one side of the bottom battery and is electrically connected to the bottom battery.

[0084] In one specific embodiment, the top cell is a perovskite cell, a cadmium telluride solar cell, a copper indium gallium selenide solar cell, or a gallium arsenide solar cell.

[0085] Fourthly, this application provides a photovoltaic module, including a battery string, which is formed by connecting multiple back-contact batteries as described above, or by connecting multiple back-contact batteries prepared by the above-described method, or by connecting multiple stacked batteries as described above; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0086] Exemplarily, the tandem solar cells are electrically connected in a single sheet or in multiple segments to form multiple cell strings, which are then electrically connected in series and / or parallel. Specifically, in some embodiments, the multiple cell strings can be electrically connected through conductive links. An encapsulation layer covers the surface of the solar cell. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or other light-transmitting cover plate.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The technical solution of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0089] Example 1

[0090] like Figure 1 As shown, this embodiment provides a back contact battery, which includes:

[0091] Silicon substrate 1: An N-type silicon substrate 1 is used, having a front side and a back side;

[0092] Backside region structure: On the backside of the silicon substrate 1, alternating P-regions and N-regions are provided, as well as a gap region 6 for isolation; both the P-regions and N-regions are provided with passivation contact structures, which include:

[0093] Composite tunneling oxide layer: It is formed by directly stacking the first oxide layer 2 and the second oxide layer 3; the first oxide layer 2 is formed by O3 oxidation and has a thickness of 0.5 nm; the second oxide layer 3 is formed by PECVD deposition and has a thickness of 1.3 nm; the total thickness of the composite tunneling oxide layer is 1.8 nm.

[0094] Doped polycrystalline silicon layer: In the P region, a boron-doped polycrystalline silicon layer 4 is provided on the composite tunneling oxide layer; in the N region, a phosphorus-doped polycrystalline silicon layer 5 is provided on the composite tunneling oxide layer.

[0095] Passivation and antireflection layers: A front passivation layer 11 and a front antireflection layer 12 are sequentially deposited on the front side of the silicon substrate 1; a back passivation layer 9 and a back antireflection layer 10 are sequentially deposited on the back side;

[0096] Electrodes: On the back side of the silicon substrate 1, gate electrodes corresponding to the P-region and N-region are respectively fabricated, namely P-region electrode 7 and N-region electrode 8.

[0097] This embodiment also provides a method for preparing the above-mentioned back contact battery, which specifically includes the following steps:

[0098] S10: Using an N-type single-crystal silicon wafer as the silicon substrate 1, the wafer is cleaned, and a first oxide layer (SiO2) in the P-region is prepared on one side of the silicon wafer 1 by passing O3 through a drying tank. x 2. Use this side as the back side of the silicon wafer; O3 is used to prepare SiO2. x The temperature was 95℃, the O3 flow rate was 1500 ppb, and the reaction time was 1200 s, forming a first oxide layer 2 with a thickness of 0.5 nm. O3 was connected to the drying tank in step S10 and the drying tank in the polishing equipment in S50. After polishing, SiO2 was directly prepared in the drying tank using O3. x Layer 2;

[0099] S20: Preparation of the second oxide layer (SiO2) in the P-region using N2O gas ionization in PECVD. x 3; Next, using BCl3 as the boron source, a polycrystalline silicon layer was prepared by in-situ boron doping; SiO2 was prepared by PECVD. x The temperature of the layer was 430℃, the pressure was 2500 mtorr, the power was 15000 W, the pulse ratio was 1:125, the nitrous oxide flow rate was 15000 sccm, and the reaction time was 100 s, forming a second oxide layer 3 with a thickness of 1.3 nm.

[0100] S30: After high-temperature annealing, the back side is crystallized to form a boron-doped polycrystalline silicon layer 4 and a BSG mask, resulting in a back side sheet resistance of Rsq140Ω / □.

[0101] S40: Using laser equipment, the P area graphic and Gap area 6 on the back are laser engraved for the first time;

[0102] S50: In wet etching, an alkaline solution is used to polish the laser area on the back of the silicon wafer, and O3 is passed through a wet drying tank to prepare the first oxide layer (SiO2) in the N-region on the back of the silicon wafer. x 2. The method is the same as step S10;

[0103] S60: A second oxide layer (SiO2) in the N-region is first prepared on the back side using PECVD. x 3. Then, PECVD is used to dope phosphorus in situ and prepare a polycrystalline silicon layer, using the same method as step S20.

[0104] S70: The back side is annealed at high temperature and crystallized to form a phosphorus-doped polycrystalline silicon layer 5 and a PSG mask, resulting in a back side N-region sheet resistance Rsq40Ω / □.

[0105] S80: Using laser equipment, the N-area graphic and Gap area 6 on the back are laser engraved a second time;

[0106] S90: In wet etching, the mask and polysilicon layer on the front and edge are first removed by a chain equipment. Then, the second laser area is polished with alkali, and texturing is performed on the front and back Gap areas 6. Finally, the back mask layer is removed by acid washing.

[0107] S100: A passivation layer (AlO2) is prepared on both the front and back sides using the ALD method. x )11 and back passivation layer (AlO x 9;

[0108] S110: Anti-reflection layers (SiN2) are fabricated on both the front and back sides using PECVD. x )12 and back antireflection layer (SiN) x 10;

[0109] S120: On the back side, gate line electrodes corresponding to the N region and P region are prepared respectively to form P region electrode 7 and N region electrode 8, and then sintered.

[0110] Example 2

[0111] This embodiment provides a back contact battery and its preparation method, which differs from Embodiment 1 in that:

[0112] The different times for preparing the first oxide layer 2 by O3 oxidation in step S10 and the second oxide layer 3 by PECVD in step S20 result in different thicknesses of the oxide layers. Specifically, the O3 oxidation time is adjusted to 800 s, making the thickness of the first oxide layer 2 approximately 0.3 nm. At the same time, the PECVD deposition time is adjusted to 180 s, making the thickness of the second oxide layer 3 approximately 1.5 nm, so as to ensure a total thickness of 1.8 nm.

[0113] The remaining process steps and parameters are consistent with those in Example 1.

[0114] Example 3

[0115] This embodiment provides a back contact battery and its preparation method, which differs from Embodiment 1 in that:

[0116] By adjusting the reaction time of the O3 oxidation method in step S10 to prepare the first oxide layer 2 and the PECVD method in step S20 to prepare the second oxide layer 3, the thickness of the first oxide layer 2 is 0.4 nm and the thickness of the second oxide layer 3 is 1.4 nm.

[0117] The remaining process steps and parameters are consistent with those in Example 1.

[0118] Example 4

[0119] This embodiment provides a back contact battery and its preparation method, which differs from Embodiment 1 in that:

[0120] By adjusting the reaction time of the O3 oxidation method in step S10 to prepare the first oxide layer 2 and the PECVD method in step S20 to prepare the second oxide layer 3, the thickness of the first oxide layer 2 is 0.6 nm and the thickness of the second oxide layer 3 is 1.2 nm.

[0121] The remaining process steps and parameters are consistent with those in Example 1.

[0122] Example 5

[0123] This embodiment provides a back contact battery and its preparation method, which differs from Embodiment 1 in that:

[0124] By adjusting the reaction time of the O3 oxidation method in step S10 to prepare the first oxide layer 2 and the PECVD method in step S20 to prepare the second oxide layer 3, the thickness of the first oxide layer 2 is 0.7 nm and the thickness of the second oxide layer 3 is 1.1 nm.

[0125] The remaining process steps and parameters are consistent with those in Example 1.

[0126] Example 6

[0127] This embodiment provides a back contact battery and its preparation method, which differs from Embodiment 1 in that:

[0128] The different times for preparing the first oxide layer 2 by O3 oxidation in step S10 and the second oxide layer 3 by PECVD in step S20 result in different thicknesses of the oxide layers. Specifically, the O3 oxidation time is adjusted to 2500 s, making the thickness of the first oxide layer 2 approximately 0.8 nm. At the same time, the PECVD deposition time is adjusted to 60 s, making the thickness of the second oxide layer 3 approximately 1.0 nm, so as to ensure a total thickness of 1.8 nm.

[0129] The remaining process steps and parameters are consistent with those in Example 1.

[0130] Comparative Example 1

[0131] This comparative example provides a back contact battery and its fabrication method. The tunneling oxide layer in this comparative example is prepared using pure PECVD. The difference between this example and Example 1 is that in steps S10 and S50, O3 oxidation is not performed; instead, a single tunneling oxide layer (SiO2) with a total thickness of 1.8 nm is deposited directly via PECVD within a reaction time of 180 s. x .

[0132] Comparative Example 2

[0133] This comparative example provides a back-contact battery and its fabrication method. This comparative example uses a traditional high-temperature thermal oxidation method to prepare the tunneling oxide layer, which is compared with the low-temperature composite oxidation process described in this invention. Its preparation method is basically the same as in Example 1, except for the formation method of the tunneling oxide layer in steps S10-S20 and S50-S60. Specifically, O3 oxidation is not performed. After cleaning the silicon substrate, it is placed in a high-temperature oxidation furnace tube and thermally oxidized in a dry oxygen atmosphere at >800℃ (e.g., 850℃). By precisely controlling the temperature and time, a single thermal tunneling oxide layer SiO with a thickness of approximately 1.8 nm is directly grown. x Subsequently, PECVD in-situ doping of polycrystalline silicon layers and all subsequent steps were carried out.

[0134] Comparative Example 3

[0135] This comparative example provides a back contact battery and its fabrication method. This comparative example uses a wet oxidation method and a PECVD method to prepare a composite tunneling oxide layer. The difference between this and Example 1 is that in step S10, after the silicon substrate 1 is cleared, a wet oxidation method is used to prepare the first oxide layer (SiO2). x 2. The temperature for preparing the first oxide layer 2 by wet oxidation is 95°C, the volume concentration of KOH solution is 0.5%, the volume concentration of hydrogen peroxide is 2.7%, and the reaction time is 100s, forming a first oxide layer 2 with a thickness of 0.5nm; the remaining process steps and parameters are consistent with those in Example 1.

[0136] Performance testing

[0137] Performance tests were performed on the back-contact batteries prepared in all the above embodiments and comparative examples. A WCT-120 minority carrier lifetime meter was used to characterize the effective minority carrier lifetime of the samples. An ellipsometer was used to measure the SiO₂... x The thickness was determined using a Halm pulse solar simulator at an ambient temperature of 25°C, AM1.5 atmospheric mass, and 51000 W / m². 2 The electrical performance data of the back-contact battery, including photoelectric conversion efficiency Eta, fill factor FF, open-circuit voltage Voc, and short-circuit current Isc, were measured under solar irradiance. The results are shown in the table below:

[0138] Table 1. Battery test results for the examples and comparative examples.

[0139] condition Group number Film uniformity Minority birth lifetime (μs) iVoc (V) <![CDATA[Jo (fA / cm 2 )]]> Eta (%) FF (%) Voc(V) Isc(A) Example 1 A 8.52% 2300 0.744 6.25 26.98 84.01 0.744 14.461 Example 2 B 13.72% 2055 0.739 7.24 26.56 83.21 0.739 14.463 Example 3 C 11.95% 2090 0.741 6.93 26.65 83.39 0.740 14.46 Example 4 D 7.69% 2150 0.742 6.83 26.72 83.63 0.742 14.463 Example 5 E 8.32% 2250 0.740 6.68 26.78 83.56 0.741 14.461 Example 6 F 8.69% 2180 0.738 6.78 26.73 83.73 0.741 14.458 Comparative Example 1 G 9.35% 2030 0.739 7.71 26.5 83.22 0.742 14.46 Comparative Example 2 H 8.55% 2260 0.743 6.68 26.89 83.66 0.743 14.465 Comparative Example 3 J 8.59% 2190 0.742 6.68 26.68 83.28 0.741 14.464

[0140] Performance test data conclusions analysis:

[0141] The superior performance of embodiments (1-6) of the present invention: All embodiments (1-6) of the present invention exhibit significantly better overall performance than the comparative examples. In particular, Embodiment 1, with a first oxide layer of 0.5 nm and a second oxide layer of 1.3 nm, exhibits excellent overall performance, surpassing that of Embodiments 2-6. This indicates that different oxide layer thickness matching schemes have a significant impact on film uniformity, passivation performance, and electrical performance. Reasonable oxide layer thickness matching can effectively improve film uniformity, enhance passivation effect, reduce carrier recombination, and significantly improve the open-circuit voltage, fill factor, and conversion efficiency of the battery.

[0142] Compared with Comparative Example 1 (pure PECVD method): Example 1 has higher conversion efficiency, fill factor and iVoc, which indicates that the oxide layer thickness matching scheme of the present invention is superior to the pure PECVD method in improving battery performance.

[0143] Compared with Comparative Example 2 (pure high-temperature thermal oxidation method): Example 1 has better iVoc, film uniformity and minority carrier lifetime, and the conversion efficiency and fill factor are close. This shows that the composite tunneling oxide layer scheme of the present invention has better overall performance while maintaining high conversion efficiency.

[0144] Compared with Comparative Example 3 (wet oxidation plus PECVD): The battery performance after passivation in Example 1 is better than that in Comparative Example 3. This shows that the battery benefits brought by the composite tunneling oxide layer prepared by O3 and PECVD are greater than those of the wet oxidation plus PECVD method, and it is more suitable as a solution for producing high-efficiency batteries.

[0145] 1. The effect of different oxide layer thickness matching schemes on film uniformity

[0146] After coating, two silicon wafers were taken from the same location in each of the six regions. The film thickness was measured at five points: the four corners and the center of the sample. The uniformity of the film layer was calculated. The specific wafer locations and test point locations are as follows: Figure 2 , Figure 3 As shown.

[0147] The formula for calculating the film uniformity M is:

[0148]

[0149] The smaller the value of film thickness uniformity M, the better the uniformity; conversely, the larger the value, the worse the uniformity.

[0150] Figure 4The film uniformity of the back contact battery samples prepared in all the above embodiments and comparative examples was calculated using the above formula. The film uniformity of Example 1 (8.52%) was better than that of Example 2 (13.72%) and Example 3 (11.95%), indicating that reasonable oxide layer thickness matching can effectively improve film uniformity, thereby improving battery performance.

[0151] 2. The effect of different oxide layer thickness matching schemes on passivation performance

[0152] The passivation performance of the back contact battery samples prepared in all the above embodiments and comparative examples is as follows: Figure 5 As shown, the minority carrier lifetime (2300 μs) of Example 1 was significantly higher than that of Examples 2-6 and Comparative Examples 1-3, indicating that appropriate oxide layer thickness matching can enhance the passivation effect and reduce carrier recombination.

[0153] 3. The impact of different oxide layer thickness matching schemes on electrical performance

[0154] The electrochemical performance of the back contact battery samples prepared in all the above embodiments and comparative examples is as follows: Figure 6 As shown, the iVoc (0.744V), fill factor (84.1%), and conversion efficiency (26.98%) of Example 1 are all higher than those of other examples, indicating that the composite tunneling oxide layer design of the present invention provides excellent passivation effect and further significantly improves the open circuit voltage, fill factor, and conversion efficiency of the battery.

[0155] In summary, this invention utilizes an O3-superimposed PECVD method to prepare an ultrathin tunneling oxide layer for the production of high-efficiency back-contact batteries in industry, combining the advantages of different O3-prepared SiO2 layers. x Thickness and PECVD SiO x Matching the film thickness can improve the uniformity of the film layer, the appearance of TBC solar cells, passivation performance, and electrical performance test results to a certain extent.

[0156] (1) The uniformity of the tunneling oxide layer prepared by pure PECVD method is poor. The uniformity of the oxide layer can be significantly improved by using O3 oxidation superimposed with PECVD method. x As the thickness increases, the uniformity of the oxide layer gradually improves;

[0157] (2) SiO prepared with O3 x With the gradual increase in thickness, SiO2 prepared by PECVD... x As the thickness gradually decreases, the quality of the solar cell first increases and then decreases, especially with the O3 oxidation method for SiO2. x The highest yield of solar cells is achieved when the thickness is 0.5 nm and the SiOx thickness is 1.3 nm using the PECVD method.

[0158] (3) SiO prepared with O3 x With the gradual increase in thickness, SiO2 prepared by PECVD... x As the thickness gradually decreases, the passivation performance of the solar cell first increases and then decreases. This is especially true when SiO2 is prepared using the O3 oxidation method. x SiO₂ with a thickness of 0.5 nm prepared by PECVD x The passivation performance of the solar cell is optimal at a thickness of 1.3 nm, with minority carrier lifetime (lifetime), implied open-circuit voltage (iVoc), and single-sided saturated recombination current density (J0) of 2300 μs, 0.744 V, and 6.25 fA / cm², respectively. 2 ;

[0159] (4) SiO prepared with O3 x With increasing thickness, the average conversion efficiency first increases and then decreases when SiO2 is prepared from O3. x When the thickness of SiOx prepared by PECVD is 1.3 nm and the thickness is 0.5 nm, the average conversion efficiency Eta is the highest at 26.98%.

[0160] Further verification of O3 preparation of SiO xThe "critical irreplaceability" of parameters (95℃, 1500ppb) and PECVD (15000W, 15000sccm) was investigated. 1000 182mm×182mm single-crystal silicon wafers were continuously produced, with a fixed O3 oxidation temperature of 95℃ and a flow rate of 1500ppb. Core oxide layer indicators were tested every 200 wafers, and the stability differences of the "deviation parameter group (90℃, 1400ppb)" were compared. In the final test results, the standard group showed stability: after continuous production of 1000 wafers, the oxide layer thickness fluctuation was only ±0.05nm, the uniformity fluctuation was ≤±0.5%, and the consistency reached 99.5%, fully meeting the requirements for composite oxide layer substrates. In the deviation group experiment, the deviation was only 5℃ temperature + 100ppb flow rate. As production time increased, the parameter fluctuations continued to expand, ultimately resulting in a defect rate exceeding 25% due to "insufficient oxide layer density," making it unsuitable for subsequent PECVD deposition. Based on a standard O3 oxide layer (0.5nm), 1000 silicon wafers were continuously produced with a fixed PECVD power of 15000W and nitrous oxide concentration of 15000 sccm. Core composite layer indicators were tested every 200 wafers, and the stability differences of the "deviation parameter group (power 14000W, nitrous oxide 14000 sccm)" were compared. Standard group stability: During the continuous production of 1000 wafers, the composite layer thickness fluctuation was ≤±0.1nm, the uniformity fluctuation was ≤±0.4%, and the minority carrier lifetime remained stable at 2300-2500μs, fully meeting the performance requirements of high-efficiency monocrystalline silicon cells (conversion efficiency ≥26.9%). Deviation group risk: Deviating only from 1000W power + 1000sccm nitrous oxide, the "passivation performance" and "uniformity" of the composite layer continuously deteriorated with prolonged production time, ultimately leading to a 0.3%+ decrease in cell conversion efficiency and a yield of only 65%.

[0161] Whether using O3 oxidation or PECVD (95℃ / 1500ppb, 15000W / 15000sccm), the core indicators show minimal fluctuations (consistency ≥99.5%) during continuous production of 1000 wafers, forming a stable foundation for achieving a "high-quality composite oxide layer." Parameter deviations trigger a failure chain: even small deviations (such as temperature ±5℃, power ±1000W) will amplify defects throughout the production process, ultimately leading to a chain reaction of "substandard oxide layer → composite layer passivation failure → battery performance degradation → sharp drop in yield." Deviations in parameter sets will either result in substandard performance (such as insufficient minority carrier lifetime) or a surge in costs (such as a 20% increase in rework rate and a 0.3% efficiency loss). Therefore, the process parameters of O3 oxidation and PECVD in this invention are the key parameter combination for achieving a high-quality, uniform composite oxide layer.

[0162] This invention successfully fabricates high-performance back-contact solar cells suitable for industrial production through an innovative "O3 oxidation + PECVD" composite tunneling oxide layer structure, combined with carefully optimized thickness matching and process parameters, laying the foundation for their application in tandem solar cells and photovoltaic modules.

[0163] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that, Includes the following steps: A back contact structure containing P-regions and N-regions is formed on the back side of the silicon substrate; Wherein, forming at least one of the P region and N region includes: A first oxide layer is formed on the silicon substrate by O3 oxidation. A second oxide layer is formed on the first oxide layer by PECVD, wherein the first oxide layer and the second oxide layer together constitute a composite tunneling oxide layer; A doped polycrystalline silicon layer is formed on the composite tunneling oxide layer.

2. The method for preparing a back contact battery according to claim 1, characterized in that, The thickness of the first oxide layer is 0.3~0.8 nm, the thickness of the second oxide layer is 0.6~1.5 nm, and the total thickness of the composite tunneling oxide layer is 0.9~1.8 nm.

3. The method for preparing a back contact battery according to claim 2, characterized in that, The total thickness of the composite tunneling oxide layer is 1.5~1.8 nm.

4. The method for preparing a back contact battery according to claim 1, characterized in that, The process conditions for the O3 oxidation method include: a temperature of 90~100℃, an O3 flow rate of 1400~1600 ppb, and a reaction time of 800~2500s.

5. The method for preparing a back contact battery according to claim 1, characterized in that, The process conditions for the PECVD method include: using nitrous oxide as the reaction gas, a gas flow rate of 14,000~16,000 sccm, a radio frequency power of 14,000~16,000 W, and a reaction time of 60~180 s.

6. The method for preparing a back contact battery according to claim 1, characterized in that, The preparation method specifically includes the following steps: S1: In the P region on the back side of the silicon substrate, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping, and then a boron-doped polycrystalline silicon layer is formed by annealing. S2: The first laser engraving defines the P-area graphic and the Gap area; S3: In the N-region on the back side of the silicon substrate, a composite tunneling oxide layer is formed sequentially by O3 oxidation and PECVD, and a polycrystalline silicon layer is deposited in situ by doping, followed by annealing to form a phosphorus-doped polycrystalline silicon layer. S4: The second laser engraving defines the N-zone graphic and the Gap zone; S5: Perform surface treatment, passivation layer deposition, and back electrode fabrication.

7. A back-contact battery, characterized in that, The back contact battery is prepared by the preparation method according to any one of claims 1-6.

8. The back contact battery according to claim 7, characterized in that, include: A silicon substrate and alternating P-regions and N-regions on its back side, wherein at least one of the P-regions and N-regions is provided with a passivation contact structure, the passivation contact structure comprising a composite tunneling oxide layer and a doped polycrystalline silicon layer thereon; the composite tunneling oxide layer is formed by directly stacking a first oxide layer formed by O3 oxidation and a second oxide layer formed by PECVD deposition.

9. A stacked battery, characterized in that, include: The bottom battery is a back contact battery as described in claims 7-8, or a back contact battery prepared by the method for preparing a back contact battery as described in any one of claims 1-6; A top battery is located on one side of the bottom battery and is electrically connected to the bottom battery.

10. A photovoltaic module, characterized in that, include: The battery string is formed by connecting multiple back contact batteries as described in claim 7 or 8, or by connecting multiple back contact batteries formed by the preparation method of any one of claims 1-6, or by connecting multiple stacked batteries as described in claim 9. Encapsulation layer, the encapsulation layer being used to cover the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.

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