Back contact battery and back contact battery assembly

Abstract

The invention relates to the technical field of semiconductors, and discloses a back contact battery and a back contact battery assembly. The first doping layer and the second doping layer are located on the backlight surface of the substrate layer; the first auxiliary grid line and the first main grid line are located on the surface of the first doping layer; the second auxiliary grid line and the second main grid line are located on the surface of the second doped layer; the surface of the first doping layer or the second doping layer is also provided with a plurality of bonding pads at intervals; the auxiliary grid lines intersect with the main grid lines, or the auxiliary grid lines are directly connected to the bonding pads; for any bonding pad, the width of the main grid line connected with the bonding pad is gradually reduced in the direction away from the bonding pad; for the first doping layer or the second doping layer where any bonding pad is located, the width of the first doping layer or the second doping layer at the bottom of the main grid line is gradually reduced in the direction away from the bonding pad. According to the invention, the slurry consumption of the main grid line can be reduced, parasitic absorption can be reduced, the length of the auxiliary grid line can be increased, carriers in the silicon substrate can be comprehensively collected, and the collection performance of the cell is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a back contact battery and a back contact battery assembly. Background Technology

[0002] Back-contact batteries, by moving the front grid lines to the back, avoid the light loss caused by the front grid lines in conventional batteries. This results in a more uniform and aesthetically pleasing appearance, and also significantly improves light utilization, leading to higher battery conversion efficiency. However, while back-contact batteries currently offer superior performance, their higher investment and operating costs make their overall cost-effectiveness still inferior to conventional TOPCon batteries.

[0003] As the main component of the overall operating cost of back-contact batteries, paste costs account for almost half of the total non-silicon cost of the battery. Reducing paste consumption while maintaining high battery performance is a pressing issue for back-contact batteries. Simply reducing the grid area to control costs will result in insufficient collection of charge carriers in the polycrystalline silicon regions not covered by paste, thereby reducing carrier performance.

[0004] Therefore, a solution is needed that can reduce slurry consumption and lower costs while ensuring that charge carriers in each region of the back contact battery are effectively collected, so that the back contact battery can maintain high battery performance. Summary of the Invention

[0005] This disclosure provides a back-contact battery and a back-contact battery assembly to solve the problems of high paste cost and ineffective collection of charge carriers in various regions of the silicon substrate in related technologies.

[0006] In a first aspect, this disclosure provides a back contact battery, comprising: The base layer includes a light-receiving surface and a backlighting surface that are positioned opposite to each other; The first doped layer and the second doped layer are alternately disposed on the back side of the substrate layer along the first direction; The first secondary gate line and the first primary gate line are located on the surface of the first doped layer; The second sub-gate line and the second main gate line are located on the surface of the second doped layer; Wherein, the first sub-gate line and the second sub-gate line are arranged alternately along the second direction and both extend along the first direction; the first main gate line and the second main gate line are arranged alternately along the first direction and both extend along the second direction; the first direction and the second direction intersect; The surface of the first or second doped layer is further provided with multiple spaced pads; the sub-gate line intersects with the main gate line, or the sub-gate line is directly connected to the pads; the main gate line is the first main gate line, and the sub-gate line is the first sub-gate line; or the main gate line is the second main gate line, and the sub-gate line is the second sub-gate line; For any pad, the width of the main gate line connected to the pad gradually decreases along the direction away from the pad; the width of the main gate line between two adjacent pads connected by the same main gate line first decreases and then increases in the direction from one pad to the other. For any pad in the first or second doped layer, the width of the first or second doped layer at the bottom of the main gate line gradually decreases along the direction away from the pad; the width of the first or second doped layer between two adjacent pads first decreases and then increases in the direction from one pad to the other.

[0007] Beneficial effects: The back-contact battery provided by this disclosure has the following advantages. First, for any pad, the width of the main grid line connected to the pad gradually decreases along the direction away from the pad, which can reduce the paste consumption of the main grid line and lower the cost. In addition, the wider main grid line at the contact position with the pad can reduce the grid line resistance and reduce the loss of charge carriers at the contact position with the pad. At the same time, it can also extend the length of the sub-grid lines of the same polarity on both sides, which can fully collect the charge carriers in the silicon substrate and improve the battery collection performance. Second, for any first doped layer or second doped layer where the pad is located, the width of the first doped layer or second doped layer at the bottom of the main grid line gradually decreases along the direction away from the pad, which can reduce the parasitic absorption of the first doped layer or second doped layer. It can also increase the length of the sub-grid lines of opposite polarity on both sides, that is, increase the length of the sub-grid lines on the entire battery surface, and comprehensively improve the charge carrier collection performance. Therefore, the back contact battery provided in this disclosure sets both the main grid line and the doped layer at its bottom as a gradient structure, which can reduce the paste consumption of the main grid line, reduce parasitic absorption, and increase the length of the first and second sub-grid lines, thereby comprehensively collecting carriers in the silicon substrate and improving the battery collection performance.

[0008] In one alternative implementation, for any first or second doped layer where a pad is located, the width of the first or second doped layer at the bottom of the main gate line gradually decreases either in a stepwise manner or in a continuous manner in a direction away from the pad. The first or second doped layer corresponding to the bottom of the main gate line is divided into multiple sub-regions; at least one sub-gate line is connected to the side of each sub-region; for any pad in the first or second doped layer, the width of each sub-region gradually decreases along the direction away from the pad; the width of the multiple sub-regions between two adjacent pads first decreases and then increases; Alternatively: For any pad in the first or second doped layer, the width of the first or second doped layer at the bottom of the main gate line decreases smoothly in the direction away from the pad.

[0009] Beneficial effects: The back-contact battery provided in this disclosure has a first or second doped layer corresponding to the bottom of the main grid line divided into multiple sub-regions. These sub-regions are suitable for formation by laser processing, allowing for simultaneous formation of the first and second doped layers, thus simplifying the process. For any pad located in the first or second doped layer, the width of the first or second doped layer at the bottom of the main grid line smoothly decreases along the direction away from the pad. This further reduces the paste consumption of the main grid line, lowers costs, increases the number of sub-grid lines of the same and different polarities on both sides of the main grid line, and further reduces parasitic absorption in the first or second doped layer.

[0010] In one optional embodiment, a plurality of first sub-gate lines and a plurality of adjacent second sub-gate lines are arranged in an interdigitated pattern; the first doped layer corresponding to the bottom of the first sub-gate line and the second doped layer corresponding to the bottom of the second sub-gate line are arranged in an interdigitated pattern. The pads include a first pad connecting a first main gate line and a second pad connecting a second main gate line; the first sub-gate line intersects with the first main gate line, or the first sub-gate line intersects with the first pad; the second sub-gate line intersects with the second main gate line, or the second sub-gate line intersects with the second pad; For any first pad, along the direction away from the first pad, the length of the first sub-gate line gradually increases, and the length of the second doped layer corresponding to the bottom of the adjacent second sub-gate line gradually decreases; For any second pad, the length of the second sub-gate line gradually increases along the direction away from each second pad, while the length of the first doped layer corresponding to the bottom of the adjacent first sub-gate line gradually decreases.

[0011] Beneficial effects: The back contact battery provided by this disclosure can increase the length of the sub-grid lines on the back side of the entire back contact battery while reducing the slurry consumption of the main grid lines, so that the charge carriers in each region can be effectively collected, comprehensively improving the charge carrier collection performance and further enhancing the performance of the back contact battery.

[0012] In one alternative embodiment, the materials of the first doped layer and the second doped layer include polycrystalline silicon; The top view of each main grid line is axially symmetric, with its axis of symmetry parallel to the second direction; The top view of the first or second doped layer corresponding to the bottom of each main gate line is axially symmetric, with its axis of symmetry parallel to the second direction.

[0013] Beneficial effects: The back-contact battery provided in this disclosure has the following advantages. First, the top view of each main grid line is axially symmetrical. For any pad, the two sides of the main grid line connected to the pad can be synchronously recessed along the axis of symmetry in the direction away from the pad. This can simultaneously increase the length of the sub-grid lines of the same polarity connected to both sides of the main grid line, which can fully collect carriers in the silicon substrate and improve the battery's collection performance. Second, the top view of the first or second doped layer corresponding to the bottom of each main grid line is axially symmetrical. For any first or second doped layer where the pad is located, the two sides of the first or second doped layer can be synchronously recessed along the axis of symmetry in the direction away from the pad. This can further reduce the parasitic absorption of the first or second doped layer and simultaneously increase the length of the opposite polarity sub-grid lines spaced on both sides of the first or second doped layer, so that the sub-grid lines can fully collect carriers in the silicon substrate and comprehensively improve the carrier collection performance.

[0014] In one alternative implementation, the width of the main gate line at the connection point with the pad is less than or equal to the width of the pad.

[0015] In one alternative implementation, for any pad, the rate at which the width of the main gate line decreases gradually increases in the direction away from the pad; the side of the main gate line is an inwardly concave curve.

[0016] Beneficial effects: The back contact battery provided by this disclosure has a main grid line width at the connection point with the pad equal to the width of the pad. This minimizes the grid line resistance at the contact point between the main grid line and the pad, and also minimizes the carrier loss at that contact point, further improving the electrical performance of the back contact battery. For any pad, the rate of decrease in the width of the main grid line gradually increases along the direction away from the pad. The side of the main grid line is a concave curve, which can reduce the main grid paste consumption and increase the length and area of ​​the sub-grid line on the side of the main grid line while ensuring the minimum grid line resistance and carrier loss at the contact point between the main grid line and the pad. This allows for the full collection of carriers in the silicon substrate and improves the battery's collection performance.

[0017] In one alternative embodiment, the material forming the sub-gate line is a first paste; the sub-gate line penetrates a portion of the first doped layer or the second doped layer; The main gate line includes multiple first conductive layers and a second conductive layer covering the first conductive layers; the material forming the first conductive layer is a first paste; the material forming the second conductive layer is a second paste; the first conductive layer penetrates a portion of the first doped layer or the second doped layer; the contact resistivity of the first paste is less than 10 mΩ / cm. 2 The contact resistivity of the second slurry is greater than or equal to 10 mΩ·cm. 2 ; The second conductive layer at least covers the sides of the first conductive layer.

[0018] Beneficial Effects: The back-contact battery provided by this disclosure, on the one hand, includes a main grid line comprising multiple first conductive layers and a second conductive layer covering the first conductive layers; the material forming the first conductive layer is a first paste with low contact resistivity; the material forming the second conductive layer is a second paste with high contact resistivity; the first conductive layer penetrates a portion of the first doped layer or the second doped layer; the multiple first conductive layers can fully collect charge carriers in the first doped layer and / or the second doped layer at the bottom of the main grid line, and the second conductive layer can facilitate the convergence of the sub-grid line and the first conductive layer, thereby improving the utilization rate and collection efficiency of charge carriers; on the other hand, the second conductive layer at least covers the side surface of the first conductive layer, which can reduce the gold / semi-composite area of ​​the main grid line in a predetermined region, and simultaneously reduce the line resistance of the grid line, reducing the resistive loss of charge carriers in the grid line, further improving the charge carrier collection performance, thereby improving the electrical performance of the battery. The back-contact battery provided by this disclosure can fully collect charge carriers in each region of the silicon substrate while reducing the gold / semi-composite area, improving the utilization rate and collection efficiency of charge carriers, thereby improving the electrical performance of the battery.

[0019] In one optional embodiment, the first conductive layer includes a plurality of conductive blocks; the cross-sectional shape of the conductive blocks includes rectangular, rhomboid, circular or elliptical shapes; The first conductive layer is discontinuous; there is a certain gap between adjacent conductive blocks.

[0020] Beneficial effects: The back contact battery provided in this disclosure includes multiple conductive blocks in each first conductive layer, with a certain spacing between adjacent conductive blocks. Multiple conductive blocks can be dispersed according to requirements to fully absorb the charge carriers in each region below the main grid line. The first conductive layer is discontinuous, and all currents are collected through the second conductive layer and connected to the pads, which can improve the design flexibility of the first conductive layer and reduce the fabrication difficulty of the main grid line.

[0021] In one alternative embodiment, the top view of the back-contact battery includes multiple sides; Define the main gate line closest to the side as the target main gate line; the side of the target main gate line closest to the side is parallel to the side. The target main gate line is connected to multiple sub-gate lines and multiple target pads on its side facing away from the side; the target pads are connected to the area to be led out of the target main gate line through at least one sub-gate line. For any target pad, the width of the target main gate line connected to the target pad gradually decreases along the direction away from each area to be led out; the width of the target main gate line between two adjacent target pads first decreases and then increases. For any target pad located in the first or second doped layer, the width of the first or second doped layer at the bottom of the target main gate line gradually decreases along the direction away from the area to be led out; the width of the first or second doped layer between two adjacent target pads first decreases and then increases.

[0022] Beneficial effects: The back-contact battery provided in this disclosure has a target main grid line that is parallel to the side edge on the side closest to it; a first doped layer or a second doped layer at the bottom of the target main grid line that is parallel to the side edge; for any target pad, the width of the target main grid line connected to the pad gradually decreases along the direction away from the area to be led out; the width of the first doped layer or the second doped layer at the bottom of the target main grid line gradually decreases; the length of the sub-grid lines of the same polarity and the sub-grid lines of opposite polarity on the side of the target main grid line away from the side edge can be increased, further increasing the length of the sub-grid lines on the entire battery surface, thereby further improving the carrier collection performance.

[0023] In a second aspect, this disclosure provides a back contact battery assembly, including the back contact battery described in the first aspect above. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a back contact battery according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of the first main grid line and the first doped layer in a back contact battery according to Example 1 of the present disclosure; Figure 3 This is a schematic diagram of the structure of the first main grid line and the first doped layer in a back contact battery according to Example 2 of the present disclosure; Figure 4 This is a schematic diagram of the structure of the first main grid line and the first doped layer in a back contact battery according to Example 3 of the present disclosure; Figure 5 This is a schematic diagram of the structure of the first main grid line and the first doped layer in a back contact battery according to Example 4 of the present disclosure. Figure 6 This is a schematic diagram of the structure of the first main grid line in a back contact battery according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of a target main grid line in a back contact battery according to an embodiment of the present disclosure; Figure 8 This is a schematic flowchart of a method for preparing a back contact battery according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the structure in which a first doped layer and a second doped layer are formed in a method for preparing a back contact battery according to an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the structure of forming main grid lines and sub-grid lines in a method for preparing a back contact battery according to an embodiment of the present disclosure.

[0026] Figure label: 10. Substrate layer; 20. First doped layer; 21. First main gate line; 22. First sub-gate line; 23. First pad; 30. Second doped layer; 31. Second main gate line; 32. Second sub-gate line; 33. Second pad; 40. Isolation groove; 51. First conductive layer; 52. Second conductive layer; 60. Target pad; 70. Target main gate line; 80. First paste; 90. Second paste. Detailed Implementation

[0027] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the drawings, not the entire structure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without inventive effort are within the scope of protection of the present disclosure.

[0028] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of this disclosure. Various structural schematic diagrams according to embodiments of this disclosure are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0029] Back-contact batteries, by moving the front grid lines to the back, avoid the light loss caused by the front grid lines in conventional batteries. This results in a more uniform and aesthetically pleasing appearance, and also significantly improves light utilization, leading to higher battery conversion efficiency. However, while back-contact batteries currently offer superior performance, their higher investment and operating costs make their overall cost-effectiveness still inferior to conventional TOPCon batteries.

[0030] As the main component of the overall operating cost of back-contact batteries, paste costs account for almost half of the total non-silicon cost of the battery. Reducing paste consumption while maintaining high battery performance is a pressing issue for back-contact batteries. Simply reducing the grid area to control costs will result in insufficient collection of charge carriers in the polycrystalline silicon regions not covered by paste, thus reducing charge carrier performance. At the same time, the polycrystalline silicon doped layer will also generate high parasitic absorption, further reducing battery performance.

[0031] Conventional back-contact solar cell patterning typically employs a "dendritic" structure with a main gate and a sub-gate. The sub-gate usually uses a highly corrosive paste to sinter with the underlying silicon substrate to form an ohmic contact; the main gate uses a non-corrosive or low-corrosive paste. This structure also has significant problems. First, the main gate is often quite wide and generally uses a non-corrosive or low-corrosive paste, thus failing to burn through the underlying passivation and antireflection film, serving only as a current collector. This results in insufficient carrier collection within the silicon substrate at the bottom of the main gate. Second, if a highly corrosive paste is used for the main gate, the gold / semi-composite area in that region becomes excessively large, further limiting carrier collection performance.

[0032] Therefore, a solution is needed that can reduce slurry consumption and lower costs while ensuring that charge carriers in each region of the back contact battery are effectively collected, so that the back contact battery can maintain high battery performance.

[0033] refer to Figure 1 This embodiment provides a back contact battery, including: The substrate 10 includes a light-receiving surface and a back-lighting surface that are disposed opposite to each other. The first doped layer 20 and the second doped layer 30 are alternately disposed on the back side of the substrate layer 10 along the first direction; The isolation groove 40 occupies the space between the adjacent first doped layer 20 and second doped layer 30 and extends into part of the substrate layer 10; The first sub-gate line 22 and the first main gate line 21 are located on the surface of the first doped layer 20; The second sub-gate line 32 and the second main gate line 31 are located on the surface of the second doped layer 30; Wherein, the first sub-gate line 22 and the second sub-gate line 32 are arranged alternately along the second direction and both extend along the first direction; the first main gate line 21 and the second main gate line 31 are arranged alternately along the first direction and both extend along the second direction; the first direction and the second direction intersect; The surface of the first doped layer 20 or the second doped layer 30 is further provided with a plurality of spaced pads; the sub-gate line intersects with the main gate line, or the sub-gate line is directly connected to the pads; the main gate line is a first main gate line 21 or a second main gate line 31, and the sub-gate line is a first sub-gate line 22 or a second sub-gate line 32; wherein, when the main gate line is the first main gate line 21, the sub-gate line is the first sub-gate line 22; when the main gate line is the second main gate line 31, the sub-gate line is the second sub-gate line 32; For any pad, the width of the main gate line connected to the pad gradually decreases along the direction away from the pad; the width of the main gate line between two adjacent pads connected by the same main gate line first decreases and then increases in the direction from one pad to the other. For any pad in the first doped layer 20 or the second doped layer 30, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the main gate line gradually decreases in the direction away from the pad; the width of the first doped layer 20 or the second doped layer 30 between two adjacent pads first decreases and then increases in the direction from one pad to the other.

[0034] It should be noted that the sub-gate line intersects with the main gate line, or the sub-gate line is directly connected to the pad. When the main gate line is the first main gate line 21, the sub-gate line is the first sub-gate line 22. When the main gate line is the second main gate line 31, the sub-gate line is the second sub-gate line 32. That is, the first sub-gate line 22 intersects with the first main gate line 21, or the first sub-gate line 22 is directly connected to the pad; the second sub-gate line 32 intersects with the second main gate line 31, or the second sub-gate line 32 is directly connected to the pad.

[0035] In practice, the main gate line is configured with a gradient structure, becoming wider closer to the pad (PAD point) and narrower further away. Simultaneously, the first doped layer 20 or the second doped layer 30 below the main gate line is also configured with a gradient structure, becoming wider closer to the pad (PAD point) and narrower further away. At any given location, the main gate line, sub-gate line, and pad are all located on the first doped layer 20 or the second doped layer 30.

[0036] In some embodiments, the pads are either first pads 23 or second pads 33. Specifically, the pads on the surface of the first doped layer 20 are first pads 23, which are spaced apart on the first main gate line 21; the pads on the surface of the second doped layer 30 are second pads 33, which are spaced apart on the second main gate line 31.

[0037] Since the carrier transport path is from silicon substrate → sub-gate line → main gate line → pad, the main gate line closer to the pad collects more carriers. Therefore, the main gate line portion connected to the pad must maintain a certain width to reduce carrier losses near the pad edge during transport. Conversely, the width of the main gate line gradually decreases away from the pad, reducing paste consumption and cost, while simultaneously extending the width of the sub-gate lines connected to both sides, thus fully collecting carriers from the silicon substrate. Setting the first doped layer 20 or the second doped layer 30 below the main gate line as a gradient structure reduces parasitic absorption and increases the length of the oppositely polarized sub-gate lines on both sides. For example, in... Figure 1 In this process, for a first pad 23, the width of the first main gate line 21 above it gradually decreases from bottom to top, so the first sub-gate lines 22 (i.e., of the same polarity) connected on both sides of the first main gate line 21 can gradually extend from bottom to top; at the same time, the width of the first doped layer 20 at the bottom of the first main gate line 21 gradually decreases from bottom to top, so the second sub-gate lines 32 (i.e., of opposite polarity) spaced on both sides of the first main gate line 21 can gradually extend from bottom to top.

[0038] Beneficial effects: The back-contact battery provided by this disclosure has the following advantages. First, for any pad, the width of the main grid line connected to the pad gradually decreases along the direction away from the pad, which can reduce the paste consumption of the main grid line and reduce costs. In addition, the wider main grid line at the contact position with the pad can reduce the grid line resistance and reduce the loss of charge carriers at the contact position with the pad. At the same time, it can also extend the length of the sub-grid lines of the same polarity on both sides, which can fully collect the charge carriers in the silicon substrate and improve the battery collection performance. Second, for any pad in the first doped layer 20 or the second doped layer 30, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the main grid line gradually decreases along the direction away from the pad, which can reduce the parasitic absorption of the first doped layer 20 or the second doped layer 30. It can also increase the length of the sub-grid lines of opposite polarity on both sides, that is, increase the length of the sub-grid lines on the entire battery surface, and comprehensively improve the charge carrier collection performance. Therefore, the back contact battery provided in this disclosure sets both the main grid line and the doped layer at its bottom as a gradient structure, which can reduce the paste consumption of the main grid line, reduce parasitic absorption, and increase the length of the first sub-grid line 22 and the second sub-grid line 32, thereby comprehensively collecting carriers in the silicon substrate and improving the battery collection performance.

[0039] In some alternative embodiments, the substrate 10 is a silicon substrate; the first doped layer 20 and the second doped layer 30 have opposite doping types. In some examples, the first doped layer 20 is a P-type doped layer and the second doped layer 30 is an N-type doped layer.

[0040] In some alternative implementations, for any first or second doped layer where a pad is located, the width of the first or second doped layer at the bottom of the main gate line gradually decreases in a stepwise or continuous manner along the direction away from the pad. Specifically, "continuous gradual decrease" means that the width of the first doped layer 20 or the second doped layer 30 continuously decreases along the direction away from the pad; "gradual gradual decrease" means that the width of the first doped layer 20 or the second doped layer 30 decreases in segments along the direction away from the pad, and the overall width shows multiple stages of change from "decreasing-unchanged-decreasing...", with an overall decreasing trend.

[0041] For ease of explanation, Figures 2-6 In this paper, the first main gate line 21, the first sub-gate line 22 and the first pad 23 on the surface of the first doped layer 20 are used as examples for specific explanation.

[0042] In some alternative implementations, such as in Example 1, as Figure 2 As shown, the first doped layer 20 or the second doped layer 30 corresponding to the bottom of the main gate line is divided into multiple sub-regions; at least one sub-gate line is connected to the side of each sub-region; for any pad in the first doped layer 20 or the second doped layer 30, the width of each sub-region gradually decreases along the direction away from the pad, that is, the width of the first doped layer or the second doped layer gradually decreases in a stepwise manner; the width of the multiple sub-regions between two adjacent pads first decreases and then increases.

[0043] In practice, multiple sub-regions can be formed by laser processing, which can be done simultaneously with the preparation of the first doped layer 20 and the second doped layer 30 without additional process steps, thus simplifying the process.

[0044] Beneficial effects: The back contact battery provided in this disclosure has a first doped layer 20 or a second doped layer 30 corresponding to the bottom of the main grid line divided into multiple sub-regions. These multiple sub-regions are suitable for formation by laser processing. Multiple sub-regions can be formed simultaneously with the preparation process of the first doped layer 20 and the second doped layer 30, which can simplify the process.

[0045] In some alternative implementations, such as in Example 2, as Figure 3 As shown, for any pad located in the first doped layer 20 or the second doped layer 30, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the main gate line decreases smoothly along the direction away from the pad, that is, the width continuity of the first doped layer or the second doped layer gradually decreases.

[0046] In practical implementation, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the main gate line decreases smoothly along the direction away from the pads. Compared to Example 1, this further reduces the paste consumption of the main gate line, lowers costs, increases the number of sub-gate lines of the same and different polarities on both sides of the main gate line, and further reduces parasitic absorption of the first doped layer 20 or the second doped layer 30. From a process perspective, the first doped layer 20 or the second doped layer 30 with a smoothly decreasing width is suitable for formation by photolithography.

[0047] In some alternative implementations, such as Figure 2 or Figure 3 As shown, a plurality of first sub-gate lines 22 on the surface of the first doped layer 20 and a plurality of second sub-gate lines 32 on the surface of the adjacent second doped layer 30 are arranged in an interdigital pattern; the first doped layer 20 corresponding to the bottom of the first sub-gate line 22 and the second doped layer 30 corresponding to the bottom of the second sub-gate line 32 are arranged in an interdigital pattern. The pads include a first pad 23 connecting the first main gate line 21 and a second pad 33 connecting the second main gate line 31; the first sub-gate line 22 intersects the first main gate line 21, or the first sub-gate line 22 intersects the first pad 23; the second sub-gate line 32 intersects the second main gate line 31, or the second sub-gate line 32 intersects the second pad 33; For any first pad 23, along the direction away from the first pad 23, the length of the first sub-gate line 22 connected to the first main gate line 21 gradually increases, the length of the second sub-gate line 32 spaced on the side of the first main gate line 21 gradually increases, and the length of the second doped layer 30 corresponding to the bottom of the adjacent second sub-gate line 32 gradually increases. For any second pad 33, along the direction away from each second pad 33, the length of the second sub-gate line 32 connected to the second main gate line 31 gradually increases, the length of the first sub-gate line 22 spaced on the side of the second main gate line 31 gradually increases, and the length of the first doped layer 20 corresponding to the bottom of the adjacent first sub-gate line 22 gradually increases.

[0048] Beneficial effects: The back contact battery provided by this disclosure can increase the length of the sub-grid lines on the back side of the entire back contact battery while reducing the slurry consumption of the main grid lines, so that the charge carriers in each region can be effectively collected, comprehensively improving the charge carrier collection performance and further enhancing the performance of the back contact battery.

[0049] In some alternative embodiments, the materials of the first doped layer 20 and the second doped layer 30 include polycrystalline silicon; the first doped layer 20 includes a first doped polycrystalline silicon layer; and the second doped layer 30 includes a second doped polycrystalline silicon layer. The top view of each main grid line is axially symmetric, with its axis of symmetry parallel to the second direction; The top view of the first doped layer 20 or the second doped layer 30 corresponding to the bottom of each main gate line is axially symmetric, and its axis of symmetry is parallel to the second direction.

[0050] Beneficial effects: The back-contact battery provided by this disclosure has the following advantages. Firstly, the top view of each main grid line is axially symmetrical. For any pad, the two sides of the main grid line connected to the pad can be synchronously recessed along the axis of symmetry in the direction away from the pad. This can simultaneously increase the length of the sub-grid lines of the same polarity connected to both sides of the main grid line, which can fully collect carriers in the silicon substrate and improve the battery's collection performance. Secondly, the top view of the first doped layer 20 or the second doped layer 30 corresponding to the bottom of each main grid line is axially symmetrical. For any pad, the two sides of the first doped layer 20 or the second doped layer 30 can be synchronously recessed along the axis of symmetry in the direction away from the pad. This can further reduce the parasitic absorption of the first doped layer 20 or the second doped layer 30, and can also simultaneously increase the length of the opposite polarity sub-grid lines spaced on both sides of the first doped layer 20 or the second doped layer 30, so that the sub-grid lines can fully collect carriers in the silicon substrate and comprehensively improve the carrier collection performance.

[0051] In some alternative implementations, the width of the main gate line at the connection point with the pad is less than or equal to the width of the pad.

[0052] In practice, the width of the main gate line at the connection point with the pad refers to the width of the main gate line at the connection point between the main gate line and the pad.

[0053] In some alternative implementations, such as Figure 4 and Figure 5 As shown, the width of the main gate line at the connection point with the pad is equal to the width of the pad; Since the carrier transport path is from silicon substrate → sub-gate line → main gate line → pad, the closer the main gate line is to the pad, the more carriers it collects. Thickening the gate line at this location reduces gate line resistance and lowers carrier losses in this area. The main gate line at the pad connection point refers to the widest portion of the main gate line where it connects to the pad.

[0054] Beneficial effects: The back contact battery provided in this disclosure has a main grid line width at the connection point with the pad equal to the width of the pad, which can minimize the grid line resistance at the contact point between the main grid line and the pad, and also minimize the carrier loss at the contact point, thereby further improving the electrical performance of the back contact battery.

[0055] In some alternative implementations, such as in Example 3, as Figure 4 As shown, the width of the main gate line at the connection with the pad is equal to the width of the pad; for any pad, the rate at which the width of the main gate line decreases remains constant in the direction away from the pad; the side of the main gate line is a straight line.

[0056] In some alternative implementations, such as in Example 4, as Figure 5 As shown, the width of the main gate line at the connection point with the pad is equal to the width of the pad; For any pad, the rate at which the width of the main gate line decreases gradually increases in the direction away from the pad; the side of the main gate line is a concave curve.

[0057] Beneficial effects: The back contact battery provided by this disclosure has a main grid line width equal to the pad width at the connection point with the pad, which minimizes the grid line resistance and carrier loss at the contact point, further improving the electrical performance of the back contact battery. For any pad, the rate of decrease in the width of the main grid line gradually increases along the direction away from the pad, and the side of the main grid line is an inwardly concave curve. This can reduce the main grid paste consumption and increase the length and area of ​​the sub-grid line on the side of the main grid line while ensuring the minimum grid line resistance and carrier loss at the contact point between the main grid line and the pad, thereby fully collecting carriers in the silicon substrate and improving the battery collection performance.

[0058] In related technologies, the secondary gate typically uses a highly corrosive paste to sinter with the doped layer at the bottom to form an ohmic contact. The main gate is often wider and generally uses a non-corrosive or low-corrosive paste to avoid burning through the passivation and antireflection film at the bottom, serving only as a current collector. This results in insufficient collection of carriers within the silicon substrate at the bottom of the main gate. If the main gate uses a highly corrosive paste, the gold / semi-reinforced composite area in that region will be too large, further limiting carrier collection performance.

[0059] In some alternative implementations, such as Figure 6 As shown, the material forming the sub-gate line is the first paste 80; the sub-gate line penetrates into the first doped layer 20 or the second doped layer 30. The main gate line includes multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80; the material forming the second conductive layer 52 is a second paste 90; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30; the contact resistivity of the first paste is less than 10 mΩ / cm. 2 The contact resistivity of the second slurry is greater than or equal to 10 mΩ·cm. 2 ; The second conductive layer 52 at least covers the sides of the first conductive layer 51.

[0060] The contact resistivity of the first slurry 80 is less than that of the second slurry 90.

[0061] In specific implementation, the first slurry 80 is a highly corrosive slurry, and the contact resistivity of the first slurry 80 is less than 10 mΩ / cm.2 The second slurry 90 is a low-corrosive or non-corrosive slurry, and its contact resistivity is greater than or equal to 10 mΩ·cm. 2 .

[0062] Beneficial effects: The back contact battery provided in this disclosure, on the one hand, includes a main grid line comprising multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80 with low contact resistivity; the material forming the second conductive layer 52 is a second paste 90 with high contact resistivity; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30; the multiple first conductive layers 51 can fully collect the charge carriers in the first doped layer 20 and / or the second doped layer 30 at the bottom of the main grid line, and the second conductive layer 52 can facilitate the convergence of the sub-grid line and the first conductive layer 51, thereby improving the utilization rate and collection efficiency of the charge carriers; on the other hand, the second conductive layer 52 at least covers the side surface of the first conductive layer 51, which can reduce the gold / semi-composite area of ​​the preset region of the main grid line, and simultaneously reduce the line resistance of the grid line, reducing the resistance loss of the charge carriers in the grid line, further improving the charge carrier collection performance, thereby improving the electrical performance of the battery. The back-contact battery disclosed herein can fully collect charge carriers in various regions of the silicon substrate while reducing the gold / semi-composite area, thereby improving the utilization rate and collection efficiency of charge carriers and thus enhancing the electrical performance of the battery.

[0063] In some alternative embodiments, the sub-gate lines and the main gate lines are suitable for fabrication by the following process: First paste 80 is printed simultaneously in the preset regions of the sub-gate lines and the preset regions of the main gate lines on the surface of the doped layer; wherein, multiple lines of first paste 80 are printed in the preset region of the main gate lines; the doped layer is a first doped layer 20 or a second doped layer 30. A second paste 90 is superimposed on the surface of a preset area of ​​the main grid line, and the second paste 90 covers the surface and sides of the first paste 80; After annealing and sintering, the first paste 80 in the preset area of ​​the sub-gate line forms the sub-gate line; the first paste 80 in the preset area of ​​the main gate line forms the first conductive layer 51; the second paste 90 in the preset area of ​​the main gate line forms the second conductive layer 52; and the second conductive layer 52 covers the surface and side of the first conductive layer 51.

[0064] In some alternative embodiments, the sub-gate lines and the main gate lines are suitable for fabrication by the following process: A second paste 90 is printed in a predetermined area of ​​the main grid line on the surface of the doped layer; Multiple grooves are formed on the surface of the second slurry 90; the grooves penetrate the second slurry 90 and expose the bottom doped layer; The first paste 80 is printed simultaneously in the groove and the preset area of ​​the sub-grid line; After annealing and sintering, the first paste 80 of the preset area of ​​the sub-gate line forms the sub-gate line; the first paste 80 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the first conductive layer 51; the second paste 90 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the second conductive layer 52; the second conductive layer 52 covers the surface and side of the first conductive layer 51.

[0065] In some alternative embodiments, the pad also includes multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80; the material forming the second conductive layer 52 is a second paste 90; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30. Beneficial effects: The back contact battery provided in this disclosure has a pad comprising multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80; the material forming the second conductive layer 52 is a second paste 90; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30; the multiple first conductive layers 51 can fully collect the charge carriers in the first doped layer 20 and / or the second doped layer 30 at the bottom of the pad, and the main grid line and the second conductive layer 52 are led out through the second conductive layer 52, which can improve the utilization rate and collection efficiency of the charge carriers.

[0066] In some optional embodiments, each first conductive layer 51 includes a plurality of conductive blocks; the cross-sectional shape of the conductive blocks includes rectangular, rhomboid, circular or elliptical shapes; The first conductive layer 51 is discontinuous; there is a certain gap between adjacent conductive blocks.

[0067] In practice, the cross-sectional shape of the conductive block refers to the shape of the conductive block in the top view.

[0068] Beneficial effects: The back contact battery provided in this disclosure includes multiple conductive blocks in each first conductive layer 51, with a certain spacing between adjacent conductive blocks. Multiple conductive blocks can be dispersed according to requirements to fully absorb the charge carriers in each region below the main grid line. The first conductive layer 51 is discontinuous, and all of them are connected to the pads through the second conductive layer 52. This can improve the design flexibility of the first conductive layer 51 and reduce the fabrication difficulty of the main grid line.

[0069] In some alternative implementations, such as Figure 1 and Figure 7 As shown, the top view of the back-contact battery includes multiple sides; Define the main gate line near the side as the target main gate line 70; the side of the target main gate line 70 near the side is parallel to the side; the first doped layer 20 or the second doped layer 30 at the bottom of the target main gate line 70 is parallel to the side; The target main gate line 70 is connected to multiple sub-gate lines and multiple target pads 60 on its side facing away from the side; the target pads 60 are connected to the area to be led out of the target main gate line 70 through at least one sub-gate line; For any target pad 60, the width of the target main gate line 70 connected to the pad gradually decreases along the direction away from the area to be led out; the width of the target main gate line 70 between two adjacent target pads 60 first decreases and then increases. For any target pad 60 located in the first doped layer 20 or the second doped layer 30, along the direction away from the area to be led out, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the target main gate line 70 gradually decreases; the width of the first doped layer 20 or the second doped layer 30 between two adjacent pads first decreases and then increases.

[0070] In specific implementation, the top view of the back contact battery is rectangular, including two opposing sides; the two sides are arranged along a first direction and extend in a second direction. Since the connection morphology between the target main gate near the side and the target pad 60 differs from that in the middle position, in order to maximize the length of the sub-gate line with the same polarity as the target main gate line 70 and ensure overall area utilization, the side of the target main gate line 70 closest to the side is made parallel to the side (i.e.,...). Figure 8 The left side of the target main grid line 70 is parallel to the side edge, and the other side gradually recedes towards the side edge along the direction away from the area to be drawn out (i.e., Figure 8 (The right side of the target main grid line 70 is recessed to the left), and the width of the overall target main grid line 70 gradually decreases.

[0071] At the same time, the first doped layer 20 or the second doped layer 30 at the bottom of the target main gate line 70 is made parallel to the side; and along the direction away from the area to be extracted; the width of the first doped layer 20 or the second doped layer 30 at the bottom of the target main gate line 70 is gradually reduced, which can maximize the length of the opposite polarity sub-gate lines spaced inside the target main gate line 70, which can fully collect carriers in the silicon substrate and improve the battery collection performance.

[0072] Beneficial effects: In the back-contact battery provided by this disclosure, the side of the target main grid line 70 closest to the side is parallel to the side; the first doped layer 20 or the second doped layer 30 at the bottom of the target main grid line 70 is parallel to the side; for any target pad 60, the width of the target main grid line 70 connected to the pad gradually decreases along the direction away from the area to be led out; the width of the first doped layer 20 or the second doped layer 30 at the bottom of the target main grid line 70 gradually decreases; the length of the sub-grid lines of the same polarity and the sub-grid lines of opposite polarity on the side of the target main grid line 70 away from the side can be increased, further increasing the length of the sub-grid lines on the entire battery surface, thereby further improving the carrier collection performance.

[0073] This disclosure also provides a back contact battery assembly, including the aforementioned back contact battery.

[0074] refer to Figure 8 This disclosure also provides a method for preparing a back contact battery, which includes, but is not limited to, steps S101 to S103.

[0075] Step S101: Provide a substrate layer 10, which includes a light-receiving surface and a backlight surface disposed opposite to each other.

[0076] Step S102: A first doped layer 20 and a second doped layer 30 are formed on the back surface of the substrate layer 10, and an isolation groove 40 is formed between adjacent first doped layers 20 and second doped layers 30; for the first doped layer 20 or the second doped layer 30 corresponding to a preset area of ​​any pad, the width of the first doped layer 20 or the second doped layer 30 at the bottom of the preset area of ​​the main gate line gradually decreases along the direction away from the preset area of ​​the pad; the width of the first doped layer 20 or the second doped layer 30 between the preset areas of two adjacent pads first decreases and then increases in the direction from the preset area of ​​one pad to the preset area of ​​the other pad, such as... Figure 9 As shown.

[0077] Step S103: A first sub-gate line 22, a first main gate line 21, and multiple spaced pads are formed on the surface of the second doped layer 30; a second sub-gate line 32, a second main gate line 31, and multiple spaced pads are formed on the surface of the second doped layer 30; wherein, the first sub-gate line 22 and the second sub-gate line 32 are alternately spaced along a second direction and both extend along a first direction; the first main gate line 21 and the second main gate line 31 are alternately spaced along the first direction and both extend along the second direction; the first direction intersects the second direction; the sub-gate line intersects the main gate line, or the sub-gate line is directly connected to the pad; the main gate line is the first main gate line 21, and the sub-gate line is the first sub-gate line 22; or the main gate line is the second main gate line 31, and the sub-gate line is the second sub-gate line 32; for any pad, the width of the main gate line connected to the pad gradually decreases along the direction away from the pad; the width of the main gate line between two adjacent pads connected by the same main gate line first decreases and then increases in the direction from one pad to the other, such as... Figure 10 As shown.

[0078] In some alternative implementations, such as Figure 6 As shown, the material forming the sub-gate line is the first paste 80; the sub-gate line penetrates into the first doped layer 20 or the second doped layer 30. The main gate line includes multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80; the material forming the second conductive layer 52 is a second paste 90; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30; the second conductive layer 52 at least covers the side surface of the first conductive layer 51.

[0079] In some alternative embodiments, the pad also includes multiple first conductive layers 51 and a second conductive layer 52 covering the first conductive layers 51; the material forming the first conductive layer 51 is a first paste 80; the material forming the second conductive layer 52 is a second paste 90; the first conductive layer 51 extends into a portion of the first doped layer 20 or the second doped layer 30.

[0080] In some optional embodiments, in step S103, the sub-gate line, main gate line, and pad are fabricated by the following process: The first paste 80 is simultaneously printed in the preset areas of the sub-gate lines, the preset areas of the main gate lines, and the preset areas of the pads on the surface of the doped layer; wherein, multiple lines of the first paste 80 are printed in the preset areas of the main gate lines and multiple lines of the first paste 80 are printed in the preset areas of the pads; the doped layer is a first doped layer 20 and / or a second doped layer 30. A second paste 90 is overprinted on the surface of the preset area of ​​the pad and the preset area of ​​the main grid line, and the second paste 90 covers the surface and side of the first paste 80. After annealing and sintering, the first paste 80 of the preset area of ​​the sub-gate line forms the sub-gate line; the first paste 80 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the first conductive layer 51; the second paste 90 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the second conductive layer 52; the second conductive layer 52 covers the surface and side of the first conductive layer 51.

[0081] In some alternative embodiments, the sub-gate lines and the main gate lines are suitable for fabrication by the following process: A second paste 90 is printed in the preset area of ​​the main gate line and the preset area of ​​the pad on the surface of the doped layer; Multiple grooves are formed on the surface of the second slurry 90; the grooves penetrate the second slurry 90 and expose the bottom doped layer; The first paste 80 is printed simultaneously in the groove and the preset area of ​​the sub-grid line; After annealing and sintering, the first paste 80 of the preset area of ​​the sub-gate line forms the sub-gate line; the first paste 80 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the first conductive layer 51; the second paste 90 of the preset area of ​​the pad and the preset area of ​​the main gate line forms the second conductive layer 52; the second conductive layer 52 covers the surface and side of the first conductive layer 51.

[0082] In some alternative embodiments, a passivation film is disposed on the back side of the first doped layer 20 or the second doped layer 30; in some examples, the passivation film comprises stacked AlO₂. x Dielectric films and SiN x Dielectric film. During the subsequent printing of the first paste 80 and annealing / sintering process, the first paste 80 will melt and burn through the surface AlO₂. x and SiN x The dielectric film, along with the high-temperature melting of silver particles in the first paste 80, undergoes recrystallization during cooling to form a silver-silicon alloy ohmic contact with the silicon in the doped layer. This allows for the collection of charge carriers within the doped layer at the bottom of the main gate line, the bottom of the sub-gate line, and the bottom of the pads. Furthermore, since the main gate width is greater than the sub-gate width, the second paste 90 printed on the surface of the main gate region is located at least on the side of the first paste 80, preventing an excessively large gold / semi-composite area. The second paste 90 may be located only on the side of the first paste 80, or it may be located on both the surface and the side of the first paste 80.

[0083] In some alternative embodiments, the contact resistivity of the first slurry 80 is less than 10 mΩ·cm. 2 ; The contact resistivity of the second slurry (90%) is greater than or equal to 10 mΩ / cm. 2 .

[0084] Beneficial effects: The back contact battery preparation method provided in this disclosure has a contact resistivity of less than 10 mΩ·cm for the first slurry 80. 2 This ensures that the main and sub-gate lines formed by the first paste 80 after annealing and sintering can fully collect carriers from various regions of the silicon substrate, improving carrier utilization and collection efficiency. The contact resistivity of the second paste 90 is greater than or equal to 10 mΩ·cm. 2 This can reduce the gold / semi-composite area of ​​the preset region of the main grid line, and simultaneously reduce the line resistance of the grid line, reduce the resistive loss of charge carriers in the grid line, further improve the charge carrier collection performance, and thus improve the electrical performance of the battery.

[0085] In some optional embodiments, the maximum width of the main grid line is 100~300μm; the second slurry 90 includes aluminum-free or low-aluminum silver powder, resin binder and solvent; wherein, the aluminum content of the low-aluminum silver powder is ≤0.5 wt%; the resin binder is dispersible latex powder or modified resin; the solvent is disodium ethylenediaminetetraacetate or stearic acid.

[0086] Beneficial effects: The back contact battery preparation method provided in this disclosure includes a second paste 90 printed in the preset area of ​​the main grid line, comprising aluminum-free or low-aluminum-doped silver powder, a resin binder, and a solvent; wherein the aluminum content of the low-aluminum-doped silver powder is ≤0.5 wt%; the resin binder is a dispersible latex powder or a modified resin; and the solvent is disodium ethylenediaminetetraacetate or stearic acid; this can ensure reliable connection between the main grid line and the sub-grid line, as well as between the pads and external conductors; at the same time, the use of the second paste 90 can reduce the risk of material degradation of the main grid line and pads during long-term use, improve durability, and thus improve the reliability and lifespan of the back contact battery electrode structure.

[0087] In some alternative embodiments, the first slurry 80 is a first corrosive slurry or a second corrosive slurry.

[0088] In some optional embodiments, the material of the sub-gate lines on the surface of the first doped layer 20 and the first conductive layer 51 is a first etchable paste; the material of the sub-gate lines on the surface of the second doped layer 30 and the first conductive layer 51 is a second etchable paste.

[0089] In some optional embodiments, the first doped layer 20 is a P-type doped layer; the width of the first sub-gate line 22 is 5~50 μm; The first corrosive slurry includes nano silver powder, glass powder, and solvent; the glass powder contains B2O3, Na2O, and SiO2, wherein the content of B2O3 is <30%; the particle size of the glass powder is >2 μm; the solvent includes diethylene glycol butyl ether or polyacrylate; the annealing and sintering temperature of the first corrosive slurry is 700~800℃. The second doped layer 30 is an N-type doped layer, and the width of the second sub-gate line 32 is 5~50 μm; The second corrosive slurry includes nano silver powder, glass powder, and solvent; the glass powder contains PbO, Bi2O3, and TeO2, wherein the content of PbO is <60 wt% and the particle size of the glass powder is >2 μm; the solvent is terpineol or methyl formate; the annealing and sintering temperature of the second corrosive slurry 82 is 700~800℃.

[0090] Specifically, the linewidth of the second sub-gate line 32 located in the N-type doped layer is 5~30 μm. Compared with the second paste 90 of the main gate and pads, the paste at this location needs to form ohmic contact with the bottom silicon during sintering, and therefore needs to have a certain degree of corrosivity. The specific process is as follows: during the high-temperature sintering process, the glass powder melts and burns through the surface AlO. x and SiN xThe dielectric film, along with the high-temperature melting of silver particles in the paste, undergoes recrystallization during cooling to form a silver-silicon alloy ohmic contact with silicon. The linewidth of the first sub-gate line 22 located in the P-type doped layer is 5~30μm; it also needs to form an ohmic contact with the underlying silicon through sintering, therefore a high-density first paste 80 is selected. Since the surface paste contact characteristics of the n-region are different from those of the p-region, the properties and composition of the corresponding p-region surface sub-gate first paste 80 are also different.

[0091] Beneficial Effects: The back contact battery fabrication method provided in this disclosure uses a first etchant slurry corresponding to the first sub-gate line 22 on the surface of the P-type doped layer, comprising nano-silver powder, glass powder, and a solvent. The glass powder contains B2O3, Na2O, and SiO2, wherein the content of B2O3 is <30%, and the particle size of the glass powder is >2 μm. The solvent includes diethylene glycol butyl ether or polyacrylate. This slurry can effectively penetrate the passivation film to form an ohmic contact with the P-type doped layer, reducing the contact resistance of the first sub-gate line 22. The second etchant slurry corresponding to the second sub-gate line 32 on the N-type doped layer comprises nano-silver powder, glass powder, and a solvent. The glass powder contains PbO, Bi2O3, and TeO2, wherein the content of PbO is <60 wt%, and the particle size of the glass powder is >2 μm. The solvent is terpineol or methyl formate. This slurry can effectively etch the bottom passivation film and form an ohmic contact with the N-type doped layer, reducing the contact resistance of the second sub-gate line 32.

[0092] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0093] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0094] The above description is merely a preferred embodiment and the technical principles employed in this disclosure. Those skilled in the art will understand that this disclosure is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of this disclosure. Therefore, although this disclosure has been described in detail through the above embodiments, it is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this disclosure, and the scope of protection of this disclosure is determined by the scope of the appended claims.

Claims

1. A back-contact battery, characterized in that, include: The base layer includes a light-receiving surface and a backlighting surface that are positioned opposite to each other; The first doped layer and the second doped layer are alternately and spaced along the first direction on the back side of the substrate layer; The first secondary gate line and the first primary gate line are located on the surface of the first doped layer; The second sub-gate line and the second main gate line are located on the surface of the second doped layer; Wherein, the first sub-gate line and the second sub-gate line are arranged alternately along the second direction and both extend along the first direction; the first main gate line and the second main gate line are arranged alternately along the first direction and both extend along the second direction; the first direction and the second direction intersect; The surface of the first doped layer or the second doped layer is further provided with a plurality of spaced pads; the sub-gate line intersects with the main gate line, or the sub-gate line is directly connected to the pads; the main gate line is the first main gate line, and the sub-gate line is the first sub-gate line; or the main gate line is the second main gate line, and the sub-gate line is the second sub-gate line; For any of the pads, the width of the main gate line connected to the pad gradually decreases along the direction away from the pad; the width of the main gate line between two adjacent pads connected by the same main gate line first decreases and then increases in the direction from one pad to the other. For any of the pads located in the first or second doped layer, the width of the first or second doped layer at the bottom of the main gate line gradually decreases along the direction away from the pad; the width of the first or second doped layer between two adjacent pads first decreases and then increases in the direction from one pad to the other.

2. The back contact battery according to claim 1, characterized in that, For any of the pads in the first or second doped layer, the width of the first or second doped layer at the bottom of the main gate line gradually decreases either in a stepwise or continuous manner along the direction away from the pad. The first or second doped layer corresponding to the bottom of the main gate line is divided into multiple sub-regions; at least one sub-gate line is connected to the side of each sub-region; for any first or second doped layer where the pad is located, the width of each sub-region gradually decreases along the direction away from the pad; the width of the multiple sub-regions between two adjacent pads first decreases and then increases; Alternatively: For any of the first or second doped layers where the pad is located, the width of the first or second doped layer at the bottom of the main gate line decreases smoothly in a direction away from the pad.

3. The back contact battery according to claim 1, characterized in that, Multiple first sub-gate lines are arranged in an interdigitated pattern with multiple adjacent second sub-gate lines; the first doped layer corresponding to the bottom of the first sub-gate line and the second doped layer corresponding to the bottom of the second sub-gate line are arranged in an interdigitated pattern. The pads include a first pad connecting a first main gate line and a second pad connecting a second main gate line; the first sub-gate line intersects with the first main gate line, or the first sub-gate line intersects with the first pad; the second sub-gate line intersects with the second main gate line, or the second sub-gate line intersects with the second pad; For any first pad, along the direction away from the first pad, the length of the first sub-gate line gradually increases, and the length of the second doped layer corresponding to the bottom of the adjacent second sub-gate line gradually decreases; For any second pad, the length of the second sub-gate line gradually increases in the direction away from each second pad, and the length of the first doped layer corresponding to the bottom of the adjacent first sub-gate line gradually decreases.

4. The back contact battery according to claim 1, characterized in that, The materials of the first doped layer and the second doped layer include polycrystalline silicon; The top view of each of the main grid lines is axially symmetric, with its axis of symmetry parallel to the second direction; The top view of the first or second doped layer corresponding to the bottom of each main gate line is axially symmetric, with its axis of symmetry parallel to the second direction.

5. The back contact battery according to claim 1, characterized in that, The width of the main gate line at the connection point with the pad is less than or equal to the width of the pad.

6. The back contact battery according to claim 5, characterized in that, For any of the pads, the rate at which the width of the main gate line decreases gradually increases in the direction away from the pad; the side of the main gate line is an inwardly concave curve.

7. The back contact battery according to claim 1, characterized in that, The material forming the sub-gate line is a first paste; the sub-gate line penetrates a portion of the first doped layer or the second doped layer; The main grid line includes multiple first conductive layers and a second conductive layer covering the first conductive layers; The material forming the first conductive layer is a first paste; the material forming the second conductive layer is a second paste; the first conductive layer penetrates a portion of the first doped layer or the second doped layer; the contact resistivity of the first paste is less than 10 mΩ / cm. 2 The contact resistivity of the second slurry is greater than or equal to 10 mΩ·cm. 2 ; The second conductive layer at least covers the sides of the first conductive layer.

8. The back contact battery according to claim 7, characterized in that, The first conductive layer includes multiple conductive blocks; the cross-sectional shape of the conductive blocks includes rectangular, rhomboid, circular, or elliptical shapes. The first conductive layer is discontinuous; there is a certain gap between adjacent conductive blocks.

9. The back contact battery according to claim 1, characterized in that, The top view of the back contact battery includes multiple sides; The main gate line closest to the side is defined as the target main gate line; the side of the target main gate line closest to the side is parallel to the side. The target main gate line is connected to a plurality of sub-gate lines and a plurality of target pads on its side facing away from the side; the target pads are connected to the area to be led out of the target main gate line through at least one of the sub-gate lines. For any target pad, the width of the target main gate line connected to the target pad gradually decreases along the direction away from the area to be led out; the width of the target main gate line between two adjacent target pads first decreases and then increases. For any target pad located in the first or second doped layer, the width of the first or second doped layer at the bottom of the target main gate line gradually decreases along the direction away from the area to be led out; the width of the first or second doped layer between two adjacent target pads first decreases and then increases.

10. A back-contact battery assembly, characterized in that, Including the back contact battery as described in any one of claims 1 to 9.

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