Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to the technical field of photovoltaics, in particular to a solar cell and a preparation method thereof and a photovoltaic module, the preparation method comprises the following steps: printing a 3-aminopropyltrimethoxysilane solution to a grid line area of a transparent conductive layer of a cell substrate, and performing first thermocuring to form an aminosilane activated self-assembly layer in the grid line area; performing electrophoretic deposition on the amino silane activated self-assembled layer by using an electrophoretic liquid, and performing second thermal curing to form a transition layer which is a poly (3, 4-ethylenedioxythiophene)-poly (styrenesulfonic acid) transition layer; and electroplating on the transition layer to form a copper grid line. The solar cell prepared by the preparation method can be used for a photovoltaic module, and the solar cell can improve the adhesive force of the copper grid line, reduce the interface contact resistance and further reduce the production cost.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically, to solar cells, their fabrication methods, and photovoltaic modules. Background Technology

[0002] The fabrication process of the grid lines in heterojunction solar cells includes screen printing and copper interconnection. The screen printing method involves using a screen to print silver paste onto a transparent conductive layer of the cell substrate, followed by drying and curing.

[0003] Since screen printing uses silver paste, which is expensive, copper interconnect is used to fabricate copper grid lines to reduce production costs. Related technologies provide methods for copper interconnect that include: PVD deposition of a copper seed layer on a transparent conductive layer of the battery substrate; patterning to form pre-plated grooves; electroplating copper grid lines within the pre-plated grooves; and removing the patterning mask.

[0004] However, the copper interconnect technology provided by the related technologies still has problems such as poor adhesion of copper grid lines and high interface contact resistance; moreover, the cost still needs to be reduced. Summary of the Invention

[0005] The purpose of this invention is to provide a solar cell, a method for its fabrication, and a photovoltaic module. The solar cell prepared by this method can be used in photovoltaic modules, and the solar cell can improve the adhesion of copper grid lines, reduce interfacial contact resistance, and further reduce production costs.

[0006] This invention is implemented as follows: In a first aspect, the present invention provides a solar cell, comprising: The battery substrate includes a transparent conductive layer; An aminosilane-activated self-assembled layer is formed in the gate line region of a transparent conductive layer. The transition layer is formed in the aminosilane activated self-assembled layer and is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer. Copper grid lines are formed in the transition layer.

[0007] In an optional embodiment, the thickness of the aminosilane-activated self-assembled layer is 1.2 ± 0.3 nm; The thickness of the transition layer is 100±20 nm; The aspect ratio of the copper grid lines is greater than 0.6.

[0008] In an optional embodiment, the surface amino group density of the aminosilane-activated self-assembled layer is ≥7.7 nucleotides / nm. 2 ; The sheet resistance of the transition layer is <100Ω / □; The resistivity of the copper grid wire is <1.8 μΩ·cm.

[0009] Secondly, the present invention provides a method for preparing a solar cell as described in any of the foregoing embodiments, comprising: A 3-aminopropyltrimethoxysilane solution is printed onto the grid line region of the transparent conductive layer of the battery substrate, followed by a first thermal curing to form an aminosilane activated self-assembled layer in the grid line region. An electrophoretic deposition of an aminosilane-activated self-assembled layer is performed using an electrophoretic solvent, followed by a second thermal curing to form a transition layer. Copper grid lines are formed by electroplating on the transition layer.

[0010] In an optional embodiment, the 3-aminopropyltrimethoxysilane solution is an alcohol solution with a volume concentration of 0.5 ± 0.2 vol%; and / or, The first thermosetting temperature is 100-130℃, and the humidity is <40%RH; and / or, The first thermosetting process is carried out under a protective atmosphere.

[0011] In an optional embodiment, the method further includes: plasma treating the transparent conductive layer before printing the aminopropyltrimethoxysilane solution onto the gate line region of the transparent conductive layer of the battery substrate.

[0012] In an optional embodiment, the ratio of argon to hydrogen in the plasma treatment is (92~98):(2~8), the plasma treatment power is 300±50W, and the time is 2±1min.

[0013] In an optional embodiment, the electrophoresis buffer is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) electrophoresis buffer, wherein the mass concentration of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) is 1.2 ± 0.2 wt%, and the mass concentration of the alcohol is 5 ± 1 wt%; and / or, The applied cathode voltage for electrophoretic deposition is 5 ± 1 V; and / or, The electrophoretic deposition time is 30 ± 5 s; and / or, The temperature for the second thermosetting is 120±10℃; and / or, The second heat curing process is carried out under a protective atmosphere.

[0014] In an optional embodiment, the electroplating solution for forming the copper grid lines comprises: 70±5 g / L CuSO4, 90±5 g / L H2SO4, 300±100 ppm polyaspartic acid derivative, 50±5 ppm nucleating agent, 0.1±0.05 g / L sodium citrate, and 15±5 ppm EMIM-BF4; and / or, The electroplating temperature is 32-38℃; the forward current density for electroplating is 15 ±2 mA / cm².2 The pulse width is 10 ± 1 ms; the negative current density for electroplating is -5 ± 1 mA / cm². 2 The pulse width is 2±1ms, the duty cycle is 80~85%, and the electroplating deposition rate is 0.8±0.05μm / min.

[0015] In an optional embodiment, the electroplating solution comprises: 300±20 ppm of a polyaspartic acid derivative; and / or, Nucleating agents include at least one of nicotinic acid nucleoside and tyrosine derivatives.

[0016] Thirdly, the present invention provides a photovoltaic module comprising a solar cell as described in any of the foregoing embodiments, or a solar cell prepared by a method for preparing a solar cell as described in any of the foregoing embodiments.

[0017] The present invention has the following beneficial effects: The solar cell provided in this embodiment of the invention sequentially forms an aminosilane activated self-assembled layer and a transition layer in the grid line region of the transparent conductive layer of the cell substrate. The transition layer is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer, and copper grid lines are formed on the transition layer. This allows the -NH2 groups of the self-assembled layers (SAMs) to form covalent bonds with the oxygen vacancies in the transparent conductive layer, improving the adhesion of the copper grid lines. Simultaneously, the conductive polymer transition layer prevents copper diffusion to the amorphous silicon layer, forming ohmic contacts and improving carrier extraction efficiency, thus mitigating the problem of high interface resistance.

[0018] In the method for preparing a solar cell provided in this embodiment of the invention, an aminosilane activated self-assembly layer is first formed on the transparent conductive layer to utilize -NH2 to form covalent bonds with the oxygen vacancies of the transparent conductive layer, thereby improving the adhesion of copper grid lines.

[0019] By utilizing a conductive polymer transition layer (i.e., poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer) formed on SAMs to block copper diffusion to the amorphous silicon layer and form ohmic contacts to improve carrier extraction efficiency, the problem of high interface resistance is improved.

[0020] Since this preparation method does not require the deposition of a copper seed layer on the transparent conductive layer via PVD, it can save metal target material and eliminate the need for PVD equipment, thereby reducing production costs.

[0021] The photovoltaic modules provided in this invention have better adhesion of copper grid lines in the solar cells and can improve the problem of high interface resistance. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of the solar cell disclosed herein.

[0024] Icons: 010 - Solar cell; 100 - Silicon substrate; 110 - Intrinsic amorphous silicon layer; 121 - N-type doped layer; 122 - P-type doped layer; 130 - Transparent conductive layer; 141 - Aminosilane activated self-assembled layer; 142 - Transition layer; 143 - Copper grid line. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0026] The method for preparing copper grid lines in heterojunction solar cells via copper interconnects provided by related technologies includes: PVD deposition of a copper seed layer on a transparent conductive layer of the cell substrate, patterning to form a pre-plated groove, electroplating to form copper grid lines in the pre-plated groove, and removing the patterning mask.

[0027] Among these, the cost of preparing copper gate lines using copper interconnect is still relatively high because PVD equipment and metal targets are required when preparing copper seed layers. The laser patterning process for preparing copper gate lines using copper interconnect will damage the TCO, leading to an increase in series resistance. Moreover, the additive PEG (polyethylene glycol) in the plating solution will cause grain boundary voids, resulting in high gate line resistivity (>2.0 μΩ·cm).

[0028] The inventors discovered that while direct electroplating with thiol (-SH)-modified TCO eliminates the need for PVD deposition of a copper seed layer, thus reducing costs, it also reduces the adhesion of the copper gate lines. Furthermore, thiol modification leading to corrosion of the amorphous silicon layer results in a Voc loss exceeding 10mV.

[0029] To address the aforementioned issues, this disclosure provides a method for fabricating a solar cell. The solar cell prepared by this method can be used in photovoltaic modules, and can improve the adhesion of copper grid lines, reduce interfacial contact resistance, and further reduce production costs.

[0030] Please refer toFigure 1 The solar cell 010 disclosed herein includes: The battery substrate includes a transparent conductive layer 130; An aminosilane activated self-assembled layer 141 is formed in the gate line region of the transparent conductive layer 130. Transition layer 142 is formed on aminosilane activated self-assembled layer 141. Transition layer 142 is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer. Copper grid line 143 is formed in transition layer 142.

[0031] The solar cell 010 sequentially forms an aminosilane activated self-assembled layer 141 and a transition layer 142 in the grid line region of the transparent conductive layer 130 of the cell substrate. The transition layer 142 is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer. Copper grid lines 143 are formed on the transition layer 142. This allows the -NH2 groups of the self-assembled layers (SAMs) to form covalent bonds with the oxygen vacancies in the transparent conductive layer 130, improving the adhesion of the copper grid lines 143. Simultaneously, the conductive polymer transition layer 142 prevents copper diffusion to the amorphous silicon layer, forming ohmic contacts and improving carrier extraction efficiency, thus mitigating the problem of high interfacial resistance.

[0032] Optionally, the solar cell 010 may refer to a heterojunction cell, and the cell substrate includes a silicon substrate 100, an intrinsic amorphous silicon layer 110 formed on the front and back sides of the silicon substrate 100, an N-type doped layer 121 formed on the intrinsic amorphous silicon layer 110 on the front side, a P-type doped layer 122 formed on the intrinsic amorphous silicon layer 110 on the back side, and a transparent conductive layer 130 (e.g., ITO) formed on the N-type doped layer 121 and the P-type doped layer 122, respectively.

[0033] Optionally, the thickness ratio of the copper gate line 143 (i.e., the copper layer), the transition layer 142, the aminosilane activated self-assembled layer 141, and the transparent conductive layer 130 can be selected as needed. For example, in some embodiments, the thickness ratio of the copper gate line 143 (i.e., the copper layer), the transition layer 142, the aminosilane activated self-assembled layer 141, and the transparent conductive layer 130 is 13000nm:100nm:1.2nm:80nm.

[0034] Optionally, the thickness of the aminosilane activated self-assembled layer 141 (SAMs, which form a highly ordered and closely packed thin film by spontaneously and orderly arranging molecules on a solid surface) is a monolayer with a thickness of 1.2 ± 0.3 nm (e.g., 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc., which are not specifically limited here); the thickness of the transition layer 142 is 100 ± 20 nm (e.g., 80 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 120 nm, etc., which are not specifically limited here). If the transition layer 142 is too thin, it is easy to cause perforation; if it is too thick, it will increase the series resistance.

[0035] Optionally, the aspect ratio of the copper grid line 143 is greater than 0.6 (e.g., 0.62, 0.65, etc., which are not specifically limited here). For example, the aspect ratio of the copper grid line 143 is 0.65, the line width is 20μm, and the line height is 13μm.

[0036] Optionally, the surface amino group density of the aminosilane-activated self-assembled layer 141 is ≥7.7 amino groups / nm. 2 (For example: 7.7 per nm) 2 8 per nm 2 9 / nm 2 10 per nm 2 (Etc., not specifically limited here); the sheet resistance of the transition layer 142 is <100Ω / □ (e.g., 99Ω / □, 98Ω / □, 95Ω / □, etc., not specifically limited here). The resistivity of the copper grid line 143 is <1.8 μΩ·cm (e.g., 1.7μΩ·cm, 1.6μΩ·cm, 1.5μΩ·cm, etc., not specifically limited here).

[0037] This disclosure also provides a method for preparing a solar cell 010, which includes: A 3-aminopropyltrimethoxysilane solution is printed onto the grid line region of the transparent conductive layer 130 of the battery substrate, followed by a first thermal curing to form an aminosilane activated self-assembly layer 141 in the grid line region. Electrophoretic deposition is performed on the aminosilane activated self-assembled layer 141 using an electrophoretic solution, followed by a second thermal curing to form a transition layer 142; Copper grid lines 143 are formed by electroplating on the transition layer 142.

[0038] The solar cell 010 first forms an aminosilane activated self-assembly layer 141 on the transparent conductive layer 130, so as to utilize -NH2 to form covalent bonds with the oxygen vacancies of the transparent conductive layer 130, thereby improving the adhesion of the copper grid lines 143.

[0039] By utilizing the conductive polymer transition layer 142 (i.e., poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer) formed on SAMs to block copper diffusion to the amorphous silicon layer and form ohmic contacts to improve carrier extraction efficiency, that is, to improve the problem of high interface resistance.

[0040] Since this preparation method does not require the deposition of a copper seed layer on the transparent conductive layer 130 by PVD, it can save metal target material and eliminate the need for PVD equipment, thereby reducing production costs.

[0041] It should be noted that this preparation method does not require the use of thiol to modify the transparent conductive layer 130, thereby improving the problem of Voc loss >10mV caused by thiol modification etching the amorphous silicon layer. Simultaneously, this preparation method does not require laser patterning, avoiding laser damage to the transparent conductive layer 130 and improving the problem of increased series resistance.

[0042] Optionally, the 3-aminopropyltrimethoxysilane solution is an alcohol solution (e.g., an ethanol solution) with a volume concentration of 0.5 ± 0.2 vol% (e.g., 0.3 vol%, 0.4 vol%, 0.5 vol%, 0.6 vol%, 0.7 vol%, etc., which are not specifically limited here).

[0043] 3-Aminopropyltrimethoxysilane (APTMS), structural formula: H2N-(CH2)3-Si(OCH3)3. The amino group (-NH2) forms an N-Ti / N-In covalent bond with an oxygen vacancy on the ITO surface (bond energy > 200 kJ / mol); the methoxy group (-OCH3) hydrolyzes to form Si-OH, which condenses with hydroxyl groups on the TCO surface (Si-O-Ti / Si-O-In).

[0044] The mechanism by which an aminosilane-activated self-assembled layer 141 is formed on the transparent conductive layer 130 to improve the adhesion of the copper gate line 143 is as follows: 1. Molecular-level bonding model TCO surface: Ti 4+ -O 2- +H₂O→Ti 4+ -OH - +H + ; APTMS: H2N-(CH2)3-Si(OCH3)3+3H2O→H2N-(CH2)3-Si(OH)3+3CH3OH; Condensation reaction: Ti 4+ -OH - +H2N-(CH2)3-Si(OH)3→Ti 4+ -O --Si-(CH2)3-NH2+2H2O; Double bond point: Si-O-Ti: provides mechanical anchoring (shear strength > 50 MPa) for Ti-N, forming coordination bonds to enhance electron transport.

[0045] 2. Corrosion resistance mechanism Passivation effect: The aminosilane layer covers the TCO surface, blocking H in the acidic plating solution (pH=1.5). + The erosion path.

[0046] Verification experiment: After immersing the activated TCO in the plating solution for 1 hour, XPS analysis showed that the surface [In] concentration decreased by only 1.2% (compared to 18.7% for the unactivated layer).

[0047] In other words, the preparation method provided in this disclosure can form a mechanical anchor by using an APTMS solution to form a self-assembled layer on the TCO, thereby improving the adhesion of the copper grid line 143. At the same time, the aminosilane layer covering the TCO surface also blocks the corrosion caused by H ions in the electroplating solution of the subsequent process, thereby further improving the adhesion of the copper grid line 143.

[0048] It should be noted that selective micro-region modification of the TCO surface using aminosilane self-assembled monolayers (-NH2SAMs) can achieve directional copper deposition by exposing only the gate line region.

[0049] Alternatively, the method of printing the 3-aminopropyltrimethoxysilane (APTMS) solution onto the grid area of ​​the transparent conductive layer 130 of the battery substrate can be microcontact printing, which can improve the transfer accuracy (accuracy is improved by approximately ±2 μm), that is, improve the patterning accuracy.

[0050] Optionally, the specific method of microcontact printing includes: coating (e.g., spin-coating) a 3-aminopropyltrimethoxysilane solution onto the surface of a PDMS (polydimethylsiloxane) stamp (the microchannels of the stamp adsorb the APTMS solution through capillary action), purging excess solution from the raised portion of the stamp with nitrogen gas, imprinting the 3-aminopropyltrimethoxysilane solution onto the transparent conductive layer 130 with the stamp, washing away the non-contact area (i.e., washing away the non-gate area) with isopropanol, and retaining the APTMS solution imprinted on the gate area.

[0051] Optionally, the width of the microchannels in the PDMS (polydimethylsiloxane) stamp roughly determines the linewidth of the grid region. For example, if the width of the microchannels in the PDMS (polydimethylsiloxane) stamp is 20 μm, the width of the self-assembled layer formed in the grid region is approximately 20 μm.

[0052] Of course, the microchannel width of PDMS (polydimethylsiloxane) stamps is not limited to this; it can also be 18μm, 22μm, 25μm, etc., without specific limitations here. Similarly, the depth of the microchannels in PDMS (polydimethylsiloxane) stamps can be selected as needed, such as 8μm, 10μm, 12μm, etc., without specific limitations here.

[0053] Optionally, the first thermosetting is carried out under a protective atmosphere (e.g., N2) at a temperature of 100-130°C, such as 100°C, 110°C, 115°C, 120°C, 125°C, 130°C, etc., without specific limitations. Curing the APTMS printed onto the TCO (transparent conductive layer 130) at the above temperature forms a SAMs layer (self-assembled monolayer) to complete selective activation, i.e., to complete the condensation reaction: Si-OH + HO-TiO2 → Si-O-Ti + H2O.

[0054] Optionally, during the first thermosetting, a humidity level of <40%RH (e.g., 20%, 30%, 35%, etc., without specific limitations) helps prevent the self-polymerization of the APTMS solution.

[0055] Optionally, the first heat curing time is 4 min, 5 min, 6 min, etc., and no specific limitation is made here.

[0056] Optionally, the preparation method further includes: cleaning and plasma treatment of the transparent conductive layer 130 before printing the aminopropyltrimethoxysilane solution onto the grid line region of the transparent conductive layer 130 of the battery substrate, in order to clean the surface of the transparent conductive layer 130 of the battery substrate and increase the hydroxyl density (e.g., increasing the number of -OH groups from 5 to 15 per nm). 2 .

[0057] Optionally, the ratio of argon to hydrogen in the plasma treatment is (92~98):(2~8) (e.g., 92:8, 95:5, 98:2, etc., which are not specifically limited here), the power of the plasma treatment is 300±50W (e.g., 250W, 270W, 300W, 330W, 350W, etc.), and the time is 2±1min (e.g., 1min, 2min, 3min, etc., which are not specifically limited here).

[0058] It should be noted that, according to the inventors' measurements using a water droplet contact angle meter, after selective activation to form the SAMs layer, the contact angle of the gate line region changed from 85° before activation to 32° after activation; the surface energy of the activated region was measured to be 65.3 mN / m using the Owens-Wendt equation; and the amino density of the activated region was measured to be 8.2 ± 0.5 amino groups / nm using XPS nitrogen peak area integration. 2X-ray photoelectron spectroscopy (XPS) analysis showed that the bonding structure of the active region was Ti-N bond (binding energy 399.2 eV); laser confocal microscopy revealed that the linewidth of the active region was 20 μm ± 1.5 μm.

[0059] It should also be noted that the inventors confirmed the enrichment of nitrogen in the selected region using EDS surface scanning and compared the energy spectra of the activated and non-activated regions of the TCO, as shown in the table below:

[0060] The inventors also discovered that the cost of forming a self-assembled layer on the TCO surface using APTMS solution is far lower than that of treating TCO with thiols; the cost of treating TCO with APTMS solution is approximately ¥0.08 per cell, while the cost of treating TCO with thiols is approximately ¥0.15 per cell. Furthermore, existing equipment can be used for plasma treatment of the battery substrate, without incurring additional equipment costs.

[0061] Optionally, the electrophoresis buffer is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) electrophoresis buffer (PEDOT:PSS) to prepare a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer. The mass concentration of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) is 1.2 ± 0.2 wt% (e.g., 1.0 wt%, 1.1 wt%, 1.2 wt%, 1.3 wt%, 1.4 wt%, etc., without specific limitation), the mass concentration of alcohol is 5 ± 1 wt% (e.g., 4 wt%, 5 wt%, 6 wt%, etc., without specific limitation), and the balance is water (e.g., DI pure water). Isopropanol can inhibit PSS phase separation.

[0062] Optionally, the cathode voltage applied during electrophoretic deposition is 5±1V (e.g., 4V, 5V, 6V, etc., which are not specifically limited here) to allow positively charged PEDOT to migrate and deposit towards the anode; the electrophoretic deposition time is 30±5s (e.g., 25s, 30s, 35s, etc., which are not specifically limited here) to control the deposition accuracy to ±5nm through electrophoretic deposition.

[0063] Optionally, the second thermosetting is carried out under a protective atmosphere, such as nitrogen; the temperature of the second thermosetting is 120±10℃, such as 110℃, 120℃, 130℃, etc., without specific limitation, in order to fully remove moisture and improve conductivity.

[0064] Optionally, the second heat curing time can be 1 min, 2 min, 3 min, etc., and no specific limitation is made here.

[0065] The inventors tested the conductivity of the poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer using the four-probe method and found it to be 1200 S / cm. AFM showed an RMS roughness of 1.8 nm, which is beneficial to ensure the smoothness of the subsequent electroplated copper layer. At the same time, TEM confirmed the formation of a Cu / PEDOT:PSS / ITO gradient layer, and the overall diffusion width of the gradient layer reached 2-3 nm.

[0066] Optionally, the electroplating solution for forming the copper grid lines 143 comprises: 70±5 g / L (e.g., 65 g / L, 68 g / L, 70 g / L, 73 g / L, 75 g / L, etc., not specifically limited herein) of CuSO4, 90±5 g / L (e.g., 85 g / L, 88 g / L, 90 g / L, 92 g / L, 95 g / L, etc., not specifically limited herein) of H2SO4, 300±100 ppm (e.g., 200 ppm, 250 ppm, 300 ppm, 350 ppm, 400 ppm, etc., not specifically limited herein) of polyaspartic acid derivatives, 50±5 ppm (e.g., 45 ppm, 48 ppm, 50 ppm, 52 ppm, 55 ppm, etc., not specifically limited herein) of nucleating agent, and 0.1±0.05 g / L (e.g., 0.05 g / L, 0.08 g / L, etc., not specifically limited herein) of nucleating agent. Sodium citrate at concentrations of 0.1 g / L, 0.12 g / L, 0.15 g / L, etc. (not specifically limited here), and EMIM-BF4 (i.e., 1-ethyl-3-methylimidazolium tetrafluoroborate) at concentrations of 15±5 ppm (e.g., 10 ppm, 12 ppm, 15 ppm, 18 ppm, 20 ppm, etc., not specifically limited here).

[0067] CuSO4 serves as the copper ion source; H2SO4 enhances conductivity; polyaspartic acid derivatives act as grain boundary inhibitors (replacing PEG), with carboxyl adsorption at grain boundaries inhibiting lateral growth and regulating the grain size of copper gate line 143 to 130-220 nm (e.g., 130 nm, 150 nm, 180 nm, 200 nm, 220 nm, etc., without specific limitations here). In other words, the addition of polyaspartic acid derivatives can effectively reduce dendrite formation rate; moreover, since PEG is not added to the electroplating solution, it can also effectively improve the problem of high resistivity of gate lines caused by interface voids due to PEG; nucleating agent (replacing MBI-CA) adsorbs Cu(111) facets to reduce nucleation barrier; sodium citrate can act as a pH buffer to maintain the pH of the electroplating solution at 1.5; EMIM-BF4 can act as a preservative (replacing molybdate).

[0068] It should be noted that the addition of PASP-D (polyaspartic acid derivative) to the electroplating solution to inhibit dendrites works by utilizing the -COOH groups adsorbed at the copper grain boundaries to reduce the lateral growth rate.

[0069] Optionally, the polyaspartic acid derivatives include, but are not limited to, at least one of polyaspartic acid-dodecyl glycidyl ether grafts and polyaspartic acid-polyethyleneimine block copolymers.

[0070] Optionally, the electroplating solution may include 300±20ppm (e.g., 280ppm, 300ppm, 320ppm, etc., which are not specifically limited here) of polyaspartic acid derivatives; within this concentration range, the resistivity and dendrite formation rate of the obtained grid lines are reduced.

[0071] Optionally, the nucleating agent includes at least one of nicotinic acid nucleoside and tyrosine derivatives.

[0072] The mechanism by which nicotinic acid nucleosides promote dense nucleation includes: the adsorption of the nicotinamide ring on the Cu(111) surface (DFT calculated binding energy -2.3 eV), which increases the nucleation density to 1.2 × 10⁻⁶. 6 / μm 2 (The nucleation density without the addition of nicotinic acid nucleoside is 2 × 10⁻⁶) 5 / μm 2 ).

[0073] Optionally, the tyrosine derivatives include, but are not limited to, at least one of N-acetyl-L-tyrosine ethyl ester and O-phospho-L-tyrosine.

[0074] Optionally, when electroplating grid lines, when the copper ion concentration in the electroplating solution reaches approximately 45 g / L, the electroplating solution can be replenished to achieve more than 200 cycles of reuse, further reducing production costs.

[0075] It should be noted that the electroplating solution contains no cyanide, and the COD of the waste liquid is <50 mg / L, which is far lower than the COD of electroplating solutions of existing technologies, which is >2000 mg / L, thus meeting environmental protection requirements.

[0076] Optionally, the electroplating temperature is 32-38℃ (e.g., 32℃, 34℃, 35℃, 36℃, 38℃, etc., without specific limitation). Electroplating at low temperatures can reduce the corrosion of the transparent conductive layer 130; the forward current density for electroplating is 15 ±2 mA / cm². 2 (For example: 13mA / cm) 2 15 mA / cm 2 17 mA / cm 2Copper ion deposition can be achieved with a pulse width of 10 ± 1 ms (e.g., 9 ms, 10 ms, 11 ms, etc., without specific limitations); the negative current density for electroplating is -5 ± 1 mA / cm². 2 (For example: -6mA / cm) 2 -5 mA / cm 2 -4mA / cm 2 The following parameters are used to dissolve protruding grains and suppress dendrites: pulse width of 2±1ms (e.g., 1ms, 2ms, 3ms, etc., without specific limitation); duty cycle of 80~85% (e.g., 80%, 83%, 85%, etc., without specific limitation) to optimize grain size distribution; and electroplating deposition rate of 0.8±0.05μm / min (e.g., 0.75μm / min, 0.80μm / min, 0.85μm / min, etc., without specific limitation).

[0077] The inventors discovered that the deposition rate of electroplating is 0.8±0.05μm / min, and the time for electroplating grid lines on one side of the battery substrate can be controlled within 75±5s to meet the production cycle of 60 pieces / hour on the production line.

[0078] The preparation method disclosed herein achieves high conductivity, high adhesion, and low corrosion copper grid lines 143 through the synergistic effect of PEDOT:PSS transition layer and pulse electroplating process, breaking through the bottleneck of seedless metallization in HJT cells.

[0079] The present invention will be further described in detail below with reference to the embodiments.

[0080] Example 1 Based on an HJT cell substrate with silicon wafer type G12, TCO layer of ITO and a thickness of 80nm, the following process is performed: 1. TCO Selective Area Activation TCO glass cleaning → Argon-hydrogen plasma treatment → APTMS solution spin coating → PDMS micro-contact printing → Thermosetting to form SAMs layer (self-assembled monolayer) → Selective activation completed.

[0081] 2. Transition layer deposition Amine-activated TCO → Immersion in electrophoresis solution → Application of 5V DC cathode voltage → Deposition of transition layer 142 → Thermal curing.

[0082] 3. Pulse electroplating copper The specific process parameters for steps 1 and 2 above are shown in Tables 1 and 2, respectively; the specific process parameters for step 3 are shown in Tables 3 and 4, respectively. The process parameters for Examples 2 and 3 are also shown in Tables 1, 2, 3, and 4, respectively.

[0083] Table 1

[0084] Table 2

[0085] Table 3

[0086] Table 4

[0087] Comparative Example 1 The difference between Comparative Example 1 and Example 1 is that PASP-D polyaspartic acid derivative was not added to the electroplating solution, while other processes were the same as in Example 1.

[0088] The grain size, resistivity, and dendrite formation rate of the copper grid lines in Examples 1-3 and Comparative Example 1 were tested using the following methods: Grain size detection: Field emission scanning electron microscope (FE-SEM, such as Hitachi SU5000) was used for detection; Detection process: copper grid surface polishing (0.05μm alumina suspension) → electrolytic etching (10% H3PO4 + 5% C2H5OH, 5V / 10s) to expose grain boundaries → SEM imaging of surface morphology (accelerating voltage 5kV, working distance 8mm) → ImageJ software to count the number of grains (≥200 grains) and calculate the average size.

[0089] Resistivity measurement: A four-probe tester (such as Keithley 2450) is used for measurement; Procedure: Prepare independent grid lines (laser cutting, length × width = 10mm × 20μm) → Four probes are perpendicularly contacted with the grid line surface (probe spacing 500μm) → Apply a 10mA current in constant current mode and measure the voltage drop → Calculate resistivity = (πtV) / (In2×I), where: t = grid line thickness (μm), V = voltage (V), I = current (A).

[0090] Dendrite formation rate detection: Detected using a metallographic microscope (e.g., Olympus MX63); Procedure: Surface defect scanning of the gate lines after electroplating (5×5 mm). 2 (Region) → Identify dendrite features (branched protrusions, aspect ratio > 3) → Calculate dendrite occurrence rate = (number of dendrite-containing grid lines / total number of detection grid lines) × 100%.

[0091] The results are shown in Table 5.

[0092] Table 5

[0093] As shown in Table 5, adding polyaspartic acid derivatives to the electroplating solution can effectively reduce the grain size of copper grid wires, lower resistivity, and reduce dendrite formation rate.

[0094] Example 4 The difference between Example 4 and Example 1 is that: the APTMS concentration is 0.6 vol%, the concentration of polyaspartic acid derivative (polyaspartic acid-polyethyleneimine block copolymer) in the electroplating solution is 350 ppm, the PEDOT:PSS thickness is 80 nm, and the temperature of electroplating copper grid lines is 38 °C; other process parameters are the same as in Example 1.

[0095] Example 5 The difference between Example 5 and Example 1 is that: the APTMS concentration is 0.4 vol%, the concentration of polyaspartic acid derivative (polyaspartic acid-polyethyleneimine block copolymer) in the electroplating solution is 400 ppm, the PEDOT:PSS thickness is 120 nm, and the temperature of electroplating copper grid lines is 32 °C; other process parameters are the same as in Example 1.

[0096] Comparative Example 2 Comparative Example 2 shows the fabrication of gate lines using copper interconnects. The process flow is as follows: TCO cleaning → magnetron sputtering of Cu / Ni seed layer → photoresist patterning → copper electroplating for thickening → resist removal + seed layer etching → annealing.

[0097] Magnetron sputtering: Target material (copper / nickel), Cu 50nm + Ni 20nm, sputtering power 5 kW; Electroplating solution: CuSO4·5H2O concentration 60 g / L, H2SO4 concentration 100 g / L, Cl - Concentration: 50 ppm; PEG (MW=6000) concentration: 200 ppm; SPS concentration: 100 ppm; Current density: 5 mA / cm² 2 (DC), time 15 min; plating solution temperature 40℃; Annealing conditions: Temperature / Atmosphere / Time: 180℃ / N2 / 30 min.

[0098] Comparative Example 3 Comparative Example 3 utilizes thiol to activate the transparent conductive layer 130. The process flow is as follows: Ar plasma cleaning of TCO → immersion in ethylenedithiol solution → ultraviolet laser patterning → acid copper plating → annealing.

[0099] Thiol solution: ethylene dithiol (HS-CH2-CH2-SH), 0.3 vol% ethanol solution; Laser patterning: Wavelength / Power / Pulse Width: 355 nm / 0.8 J / cm 2 / 20ns; Plating solution formulation: Additives: MPS (containing -SH), concentration 150 ppm; Current density: DC 15 mA / cm² 2 (DC), time 180 s; plating solution temperature: 45℃; Inhibitor: PEG 8000, concentration 500 ppm; Annealing conditions: Temperature / Time: 160℃ / 20 min.

[0100] Comparative Example 4 Comparative Example 4 utilizes laser activation and synergistic electroplating solution to electroplat the grid lines. The process flow is as follows: TCO wet cleaning → CO2 laser selective activation → mask electroplating → annealing.

[0101] Laser activation: Wavelength / Energy density / Scanning speed: 10.6 μm / 3.5 J / cm 2 / 2 m / s; Plating solution formulation: CuSO4·5H2O concentration 70 g / L, H2SO4 concentration 90 g / L, Cl - Concentration: 60 ppm; Additive: JGB (dye) concentration: 50 ppm; Inhibitor: PEG 3000 concentration: 400 ppm; Current density: 10 mA / cm² 2 (DC), time 16 min; plating solution temperature: 45℃; Annealing conditions: Temperature / Time: 200℃ / 15 min.

[0102] Tests were conducted on Examples 1, 4, 5, and Comparative Examples 2-4, and the test methods are shown in the table below:

[0103] The results are shown in Table 6.

[0104] Table 6

[0105] As shown in Table 6, the preparation method of the present invention can significantly reduce contact resistance and improve the adhesion of the gate line; moreover, the thiol etching of the amorphous silicon layer will also lead to a 12mV reduction in Voc; the thiol-Cu bond is unstable and there are micropores at the interface; laser thermal damage accelerates TCO aging.

[0106] Comparative Example 5 The difference between Comparative Example 5 and Example 1 is that no transition layer is set, and copper grid lines are directly electroplated on the self-assembly layer. Other process parameters are the same as in Example 1.

[0107] The contact resistance of Comparative Example 1 and Comparative Example 5 and the increase in resistance after aging at 85°C for 1000 hours are compared. The detection methods are shown in the table below:

[0108] The results are shown in Table 7.

[0109] Table 7

[0110] Compared to not setting a transition layer, the preparation method of the present invention with a transition layer effectively reduces the contact resistance and can effectively control the increase in aging resistance.

[0111] Comparative Example 6 The difference between Comparative Example 6 and Example 1 is that the electroplated copper grid lines are electroplated using conventional DC electroplating.

[0112] The traditional DC electroplating process is as follows: silicon wafer cleaning → PVD sputtering seed layer → photoresist coating → exposure and development → DC copper electroplating → photoresist removal / etching of seed layer → high-temperature annealing.

[0113] Silicon wafer cleaning: Sonicate at 60℃ for 5 min with solution SC1 (NH4OH:H2O2:H2O = 1:2:5); rinse with dilute HF (0.5wt%) for 30 s; PVD sputtering seed layer: Equipment: Magnetron sputtering system Target material: Copper target (99.999% purity) + Nickel target (transition layer)

[0114] Photoresist coating and patterning: Photoresist: Negative photoresist (such as JSR THB-151N)

[0115] DC copper plating: Plating solution formulation

[0116] Electroplating parameters

[0117] Degumming and seed layer etching: Degumming: Solution: Acetone, sonicated for 10 min → O2 plasma ashing (200 W, 5 min) Seed layer etching:

[0118] High-temperature annealing: Equipment: Tubular furnace (N2 atmosphere) Parameters: Temperature 200℃, time 30 min, the purpose is to eliminate internal stress and enhance adhesion.

[0119] The resistivity, gate grain size, gate aspect ratio, gate adhesion, and TCO corrosion rate were compared between Example 1 and Comparative Example 6. The aspect ratio was detected using a laser confocal microscope, specifically a Keyence VK-X3000 non-contact 3D contour scanning instrument with an accuracy of ±0.01 μm.

[0120] For other testing methods, please refer to the above text.

[0121] Results Table 8.

[0122] Table 8

[0123] The electroplating method of the present invention effectively reduces the resistivity, grain size and adhesion of the gate lines, and can also increase the aspect ratio of the gate lines and reduce the corrosion of TCO.

[0124] In summary, the solar cell 010 prepared by the method of the present invention can be used in photovoltaic modules, and the solar cell 010 can improve the adhesion of the copper grid lines 143, reduce the interfacial contact resistance, and further reduce the production cost.

[0125] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, include: A battery substrate, wherein the battery substrate includes a transparent conductive layer; An aminosilane activated self-assembly layer (141) is formed in the gate line region of the transparent conductive layer. A transition layer (142) is formed on the aminosilane activated self-assembled layer (141), and the transition layer (142) is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) transition layer. Copper grid lines (143) are formed in the transition layer (142).

2. The solar cell according to claim 1, characterized in that, The thickness of the aminosilane activated self-assembled layer (141) is 1.2 ± 0.3 nm; the thickness of the transition layer (142) is 100 ± 20 nm; the aspect ratio of the copper gate line (143) is > 0.6; and / or, The surface amino group density of the aminosilane activated self-assembled layer (141) is ≥7.7 amino groups / nm. 2 The sheet resistance of the transition layer (142) is <100Ω / □; the resistivity of the copper grid line (143) is <1.8 μΩ·cm.

3. The method for preparing a solar cell according to any one of claims 1-2, characterized in that, include: A 3-aminopropyltrimethoxysilane solution is printed onto the grid line region of the transparent conductive layer of the battery substrate, followed by a first thermal curing to form an aminosilane activated self-assembly layer (141) in the grid line region. Electrophoretic deposition is performed on the aminosilane activated self-assembled layer (141) using an electrophoretic solution, followed by a second thermal curing to form a transition layer (142). Copper grid lines (143) are formed by electroplating on the transition layer (142).

4. The method for preparing a solar cell according to claim 3, characterized in that, The 3-aminopropyltrimethoxysilane solution is an alcoholic solution with a volume concentration of 0.5 ± 0.2 vol%; and / or, The first thermosetting temperature is 100-130℃, and the humidity is <40%RH; and / or, The first thermosetting process is carried out under a protective atmosphere.

5. The method for preparing a solar cell according to claim 4, characterized in that, Also includes: Before the aminopropyltrimethoxysilane solution is printed onto the gate area of ​​the transparent conductive layer of the battery substrate, the transparent conductive layer is subjected to plasma treatment.

6. The method for preparing a solar cell according to claim 5, characterized in that, The ratio of argon to hydrogen in the plasma treatment is (92~98):(2~8), the power of the plasma treatment is 300±50W, and the time is 2±1min.

7. The method for preparing a solar cell according to claim 3, characterized in that, The electrophoresis buffer is a poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) electrophoresis buffer, wherein the mass concentration of poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) is 1.2±0.2wt%, and the mass concentration of alcohol is 5±1wt%; and / or, The applied cathode voltage for the electrophoretic deposition is 5 ± 1 V; and / or, The electrophoretic deposition time is 30 ± 5 s; and / or, The second thermosetting temperature is 120±10℃; and / or, The second thermosetting process is carried out under a protective atmosphere.

8. The method for preparing a solar cell according to claim 3, characterized in that, The electroplating solution used to electroplat the copper grid lines (143) comprises: 70±5 g / L CuSO4, 90±5 g / L H2SO4, 300±100 ppm polyaspartic acid derivative, 50±5 ppm nucleating agent, 0.1±0.05 g / L sodium citrate, and 15±5 ppm EMIM-BF4; and / or, The electroplating temperature is 32-38℃; the forward current density of the electroplating is 15 ±2 mA / cm². 2 The pulse width is 10 ± 1 ms; the negative current density of the electroplating is -5 ± 1 mA / cm². 2 The pulse width is 2±1ms, the duty cycle is 80~85%, and the deposition rate of the electroplating is 0.8±0.05μm / min.

9. The method for preparing a solar cell according to claim 8, characterized in that, The electroplating solution comprises: 300±20 ppm of the polyaspartic acid derivative; and / or, The nucleating agent includes at least one of nicotinic acid nucleoside and tyrosine derivatives.

10. A photovoltaic module, characterized in that, The solar cell includes the solar cell according to any one of claims 1-2, or the solar cell prepared by the method according to any one of claims 3-9.

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