Back contact solar cell and preparation method and application thereof

Abstract

The invention provides a back contact solar cell and a preparation method and application thereof. The back contact solar cell comprises a silicon substrate which comprises a front surface and a back surface which are opposite to each other; the back surface comprises first doped regions and second doped regions which are alternately arranged along the first direction, and the adjacent first doped regions and second doped regions are spaced by spacer regions; the first direction is a direction perpendicular to the thickness of the silicon substrate; the first doped region comprises a first tunneling oxide layer, a first type doped polycrystalline silicon layer and a first passivation layer along the direction far away from the thickness of the silicon substrate; and the second doped region comprises a second tunneling oxide layer, a second type doped polycrystalline silicon layer, an oxidation modified phosphorosilicate glass layer and a second passivation layer along the direction far away from the thickness of the silicon substrate. According to the invention, the problem of secondary phosphorus introduction is avoided from the source, and the damage of secondary phosphorus introduction to the passivation layer structure in the back surface of the cell is obviously prevented; the oxidation modified phosphorosilicate glass layer cooperates with the second passivation layer, and the effect of superposition passivation can be achieved.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic technology, specifically relating to a back-contact solar cell, its preparation method, and its application. Background Technology

[0002] Interdigitated Back Contact (IBC) was first proposed by Schwartz and Lammert in 1975. IBC involves fabricating p-regions and n-regions arranged in an interdigitated pattern on the back of the battery, and forming metallized contacts and grid lines on them respectively. The positive and negative electrodes of the IBC battery are both on the back of the battery, and there are no metal grid lines on the front to block light, which avoids light loss due to metal electrodes, greatly improves the optical absorption of the battery, and achieves good short-circuit current. Since the front surface emitter is eliminated, the recombination loss on the front surface is reduced in the IBC battery.

[0003] The Tunnel Oxide Passivated Contact Solar Cell (TOPCon) is a novel passivated contact solar cell first proposed by the Fraunhofer Institute for Solar Energy Research in Germany at the 28th PVSEC Photovoltaic Congress in Europe in 2013. It involves first fabricating a 1-2 nm tunneling oxide layer on the back of the cell, followed by the deposition of a layer of doped polycrystalline silicon. Together, these two layers form the passivated contact structure, providing excellent interface passivation for the back of the silicon wafer. The ultrathin oxide layer allows electrons to tunnel into the polycrystalline silicon layer while blocking hole transport, reducing recombination current. The lateral transport properties of the doped polycrystalline silicon layer reduce series resistance. These two characteristics combined improve the cell's open-circuit voltage, fill factor, and conversion efficiency.

[0004] IBC cells possess excellent process stacking capabilities, allowing them to be organically combined with technologies such as TOPCon, heterojunction with Intrinsic Thin Layer (HJT), and perovskite to further improve cell conversion efficiency. A novel cell based on the IBC cell structure is called an "XBC cell," and XBC cells are expected to become the next generation of mainstream technology.

[0005] In XBC cells, both the P-region and N-region are on the back side. A phosphorus-containing oxide layer is formed on the n-poly layer of the N-region. Typically, a silicon dioxide thin film is formed by thermal oxidation or deposition, and a phosphorus source is introduced for diffusion. In subsequent processing, the phosphorus diffuses into the silicon substrate, forming heavy doping, which makes it difficult to control the surface concentration. Furthermore, the phosphorus introduced in this secondary process can penetrate the aluminum oxide layer during thermal treatment and react with the aluminum, thereby destroying the lattice structure of the aluminum oxide, significantly reducing its negative charge density, and weakening its field passivation capability.

[0006] Therefore, how to prevent the excessive diffusion of secondary phosphorus introduction and its damage to the passivation layer structure on the back of the battery is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a back-contact solar cell, its fabrication method, and its applications. This invention directly oxidizes and modifies the phosphosilicate glass layer generated during the diffusion of phosphorus to form a type-two doped polycrystalline silicon layer, obtaining an oxidized phosphosilicate glass layer. This avoids the problem of secondary phosphorus introduction at the source, significantly preventing the damage to the passivation layer structure on the back of the cell caused by secondary phosphorus introduction. Moreover, this oxidized phosphosilicate glass layer works synergistically with the second passivation layer to achieve a superimposed passivation effect. While ensuring low series resistance and excellent carrier collection capability, this oxidized phosphosilicate glass layer significantly improves the open-circuit voltage and fill factor of the cell, providing a key guarantee for achieving higher cell conversion efficiency and enhancing the stability of cell performance.

[0008] To achieve this objective, the present invention employs the following technical solution: In a first aspect, the present invention provides a back-contact solar cell, the back-contact solar cell comprising: a silicon substrate, the silicon substrate comprising a front side and a back side opposite to each other; the back side comprising alternating first doped regions and second doped regions along a first direction, and adjacent first doped regions and second doped regions being separated by a spacer region; the first direction is a direction perpendicular to the thickness of the silicon substrate.

[0009] The first doped region includes a first tunneling oxide layer, a first type doped polysilicon layer, and a first passivation layer along the direction away from the thickness of the silicon substrate; the second doped region includes a second tunneling oxide layer, a second type doped polysilicon layer, an oxide-modified phosphosilicate glass layer, and a second passivation layer along the direction away from the thickness of the silicon substrate.

[0010] This invention directly oxidizes and modifies the phosphorus-silicon glass layer generated during the diffusion of phosphorus to form a second-type doped polycrystalline silicon layer, resulting in an oxidized phosphorus-silicon glass layer. This avoids the problem of secondary phosphorus introduction at the source and significantly prevents secondary phosphorus introduction from damaging the passivation layer structure on the back of the battery. Moreover, the oxidized phosphorus-silicon glass layer works synergistically with the second passivation layer to achieve a superimposed passivation effect. While ensuring low series resistance and excellent carrier collection capability, the oxidized phosphorus-silicon glass layer significantly improves the open-circuit voltage and fill factor of the battery, providing a key guarantee for obtaining higher battery conversion efficiency and enhancing the stability of battery performance.

[0011] Preferably, the thickness of the oxide-modified phosphosilicate glass layer is 2nm-10nm, for example, it can be 2nm, 3nm, 5nm, 6.5nm, 7nm, 8.5nm or 10nm.

[0012] Preferably, the phosphorus content in the oxide-modified phosphosilicate glass layer is 1×10⁻⁶. 18 cm -3 -5×10 18 cm -3 For example, it could be 1×10 18 cm -3 2×10 18 cm -3 2.5×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 Or 5×10 18 cm -3 wait.

[0013] Preferably, the surface roughness Ra of the oxide-modified phosphosilicate glass layer in contact with the second passivation layer is 0.1μm-2μm, for example, it can be 0.1μm, 0.2μm, 0.5μm, 0.88μm, 1.2μm, 1.4μm, 1.75μm, 1.9μm or 2μm, etc.

[0014] Preferably, the oxide-modified phosphosilicate glass layer has a porous structure.

[0015] Preferably, the first passivation layer and the second passivation layer each independently comprise any one or a combination of at least two of the following: an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0016] Preferably, the thickness ratio of the oxide-modified phosphosilicate glass layer to the second passivation layer is 1:(10-30), for example, it can be 1:10, 1:14, 1:17:1:22, 1:27 or 1:30, etc.

[0017] Preferably, the interval area has a velvety structure.

[0018] Preferably, the first tunneling oxide layer comprises a silicon oxide layer.

[0019] Preferably, the second tunneling oxide layer comprises a silicon oxide layer.

[0020] Preferably, the back side of the silicon substrate further includes a metal electrode.

[0021] Preferably, the front side of the silicon substrate has a textured surface.

[0022] Preferably, the front side of the silicon substrate includes a front passivation layer along a direction away from the thickness of the silicon substrate.

[0023] In a second aspect, the present invention provides a method for fabricating a back-contact solar cell as described in the first aspect, the method comprising the following steps: A silicon substrate is provided, the silicon substrate comprising opposing front and back sides.

[0024] A first tunneling layer and a first type-doped polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then the first tunneling layer and the first type-doped polysilicon layer are removed in a predetermined area of ​​the second doping region and the spacer region.

[0025] A second tunneling layer, a second type-doped polysilicon layer, and a mask layer are deposited on the back side of the silicon substrate. Then, the mask layer, the second type-doped polysilicon layer, and the second tunneling layer in the predetermined areas of the first doped region and the spacer region are removed in sequence. A phosphosilicate glass layer is formed between the second type-doped polysilicon layer and the mask layer.

[0026] A composite etchant is used to remove the mask layer of the predetermined area of ​​the second doped region, and the phosphosilicate glass layer is modified to obtain an oxide-modified phosphosilicate glass layer; wherein the composite etchant includes an oxidant and an acid, and the concentration of the oxidant is >5wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, or 15wt%, etc.

[0027] Passivation layers are deposited in predetermined regions of the first and second doped regions to obtain the first passivation layer and the second passivation layer, respectively.

[0028] In the preparation process provided by this invention, a high-concentration hydrogen peroxide is used to directly oxidize and modify the phosphosilicate glass layer. The oxidation effect of hydrogen peroxide alters the chemical properties of the phosphosilicate glass, making it less susceptible to removal by acid in subsequent processing, thereby forming a stable oxidized phosphosilicate glass layer in situ. This layer not only possesses excellent chemical passivation properties but also effectively combines with the second passivation layer on the back side to synergistically exert a passivation effect, achieving a superimposed passivation effect. This process avoids the introduction of secondary phosphorus from the source, has high process integration, and significantly improves the stability of the passivation effect and the battery conversion efficiency.

[0029] Preferably, the concentration of the oxidant is 5wt%-20wt% and does not include 5wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, 15wt% or 20wt%, etc.

[0030] Preferably, the oxidant includes hydrogen peroxide.

[0031] Preferably, the acid solution includes HF.

[0032] Preferably, the concentration of the acid solution is 5wt%-30wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, 15wt%, 25wt% or 30wt%, etc.

[0033] Preferably, the preparation method includes the following steps: (1) A pretreated silicon substrate is provided, wherein the silicon substrate is an N-type silicon wafer or a P-type silicon wafer; wherein the pretreatment includes polishing.

[0034] (2) A first tunneling layer and an intrinsic polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then boron diffusion is performed to obtain a first tunneling layer and a first type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the first type doped polysilicon layer. (3) The BSG layer located in the predetermined area of ​​the second doped region and the spacer region is removed by laser, and then polishing is performed to remove the exposed first type doped polysilicon layer and the first tunneling layer in sequence, while retaining the BSG layer located in the predetermined area of ​​the first doped region; (4) Based on step (3), a second tunneling layer and an intrinsic polysilicon layer are deposited on the back side of the silicon substrate, and then phosphorus diffusion is performed to obtain a second tunneling layer and a second type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the second type doped polysilicon layer. (5) A mask layer is deposited on the PSG layer, and then the mask layer of the first doped region and the predetermined area of ​​the spacer region is removed by laser; wherein the mask layer includes a silicon nitride layer; During texturing, etching is used to remove the second tunneling layer and the second type-doped polycrystalline silicon layer in the predetermined area of ​​the first doped region and the spacer region.

[0035] (6) The front side of the silicon substrate is acid-etched to remove the parasitic layer on the front side.

[0036] (7) Fabrication, the specific steps of which include: The silicon substrate after step (6) is etched using a composite etchant to form a textured structure on the front side of the silicon substrate. At the same time, the mask layer of the predetermined area of ​​the second doped region on the back side of the silicon substrate is removed, and the PSG layer of the predetermined area of ​​the second doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant includes hydrogen peroxide and acid, the concentration of hydrogen peroxide is 5wt%-20wt%, and the acid includes HF, the concentration of acid is 5wt%-30wt%.

[0037] (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front and back sides of the silicon substrate, such that a front passivation layer is formed on the front side of the silicon substrate, a first passivation layer is formed in a predetermined area of ​​the first doped region on the back side of the silicon substrate, and a second passivation layer is formed in a predetermined area of ​​the second doped region.

[0038] (9) Metallize the back side of the silicon substrate to obtain a metal electrode.

[0039] Thirdly, the present invention provides an application of a back-contact solar cell as described in the first aspect in the photovoltaic field.

[0040] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0041] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention directly oxidizes and modifies the phosphorus-silicon glass layer generated during the diffusion of phosphorus to form a second type of doped polycrystalline silicon layer, thereby obtaining an oxidized phosphorus-silicon glass layer. This avoids the problem of secondary phosphorus introduction from the source and significantly prevents the secondary phosphorus introduction from damaging the passivation layer structure on the back of the battery. Moreover, the oxidized phosphorus-silicon glass layer and the second passivation layer work together to achieve the effect of superimposed passivation. While ensuring low series resistance and excellent carrier collection capability, the oxidized phosphorus-silicon glass layer significantly improves the open-circuit voltage and fill factor of the battery, providing a key guarantee for obtaining higher battery conversion efficiency and enhancing the stability of battery performance.

[0042] (2) In the preparation process provided by this invention, a high concentration of hydrogen peroxide is used to directly oxidize and modify the phosphosilicate glass layer. The oxidation effect of hydrogen peroxide changes the chemical properties of the phosphosilicate glass, making it difficult to be removed by acid in subsequent processing, thereby forming a stable oxidized phosphosilicate glass layer in situ. This layer not only has good chemical passivation performance, but can also effectively combine with the second passivation layer on the back side to synergistically exert a passivation effect and achieve a superimposed passivation effect. This process avoids the introduction of secondary phosphorus from the source, has a high degree of process integration, and significantly improves the stability of the passivation effect and the battery conversion efficiency. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the back contact battery provided in Embodiment 1 of the present invention.

[0044] Among them, 1-N-type silicon wafer; 2-first tunneling oxide layer; 3-p-type doped polycrystalline silicon layer; 4-second tunneling oxide layer; 5-n-type doped polycrystalline silicon layer; 6-oxidation modified phosphosilicate glass layer; 7-alumina layer; 8-silicon nitride layer. Detailed Implementation

[0045] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0046] It should be understood that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0047] It should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0048] In one specific embodiment, the present invention provides a back-contact solar cell, the back-contact solar cell comprising: a silicon substrate, the silicon substrate comprising opposing front and back sides; the back side comprising alternating first doped regions and second doped regions along a first direction, and adjacent first doped regions and second doped regions being spaced apart by a spacer region; the first direction being perpendicular to the thickness of the silicon substrate.

[0049] The first doped region includes a first tunneling oxide layer, a first type doped polysilicon layer, and a first passivation layer along the direction away from the thickness of the silicon substrate; the second doped region includes a second tunneling oxide layer, a second type doped polysilicon layer, an oxide-modified phosphosilicate glass layer, and a second passivation layer along the direction away from the thickness of the silicon substrate.

[0050] This invention directly oxidizes and modifies the phosphorus-silicon glass layer generated during the diffusion of phosphorus to form a second-type doped polycrystalline silicon layer, resulting in an oxidized phosphorus-silicon glass layer. This avoids the problem of secondary phosphorus introduction at the source and significantly prevents secondary phosphorus introduction from damaging the passivation layer structure on the back of the battery. Moreover, the oxidized phosphorus-silicon glass layer works synergistically with the second passivation layer to achieve a superimposed passivation effect. While ensuring low series resistance and excellent carrier collection capability, the oxidized phosphorus-silicon glass layer significantly improves the open-circuit voltage and fill factor of the battery, providing a key guarantee for obtaining higher battery conversion efficiency and enhancing the stability of battery performance.

[0051] Furthermore, the first doped region is a P+ doped region, and the second doped region is an N+ doped region.

[0052] Furthermore, the first type of doped polysilicon layer is a p-type doped polysilicon layer, and the second type of doped polysilicon layer is an n-type doped polysilicon layer. Furthermore, the silicon substrate is an N-type silicon wafer or a P-type silicon wafer.

[0053] Furthermore, the thickness of the oxide-modified phosphosilicate glass layer is 2nm-10nm, for example, it can be 2nm, 3nm, 5nm, 6.5nm, 7nm, 8.5nm or 10nm, etc.

[0054] In this invention, an oxide-modified phosphosilicate glass layer of suitable thickness contributes to the field passivation effect. Field-effect passivation refers to the process where phosphorus in the oxide layer diffuses and forms a heavily doped region near the silicon surface, inducing band bending and generating a built-in electric field. This electric field repels minority carriers (holes) in the N-region, preventing them from approaching the surface and recombinating, thereby enhancing the passivation effect. In conjunction with the second passivation layer: the upper second passivation layer carries a strong negative charge and can also produce field-effect passivation for N-type silicon (although its effect is more significant for P-type silicon). Therefore, the combination of the oxide-modified phosphosilicate glass layer and the upper surface second passivation layer (such as an alumina layer) can theoretically achieve "ultra-strong passivation".

[0055] Furthermore, the phosphorus content in the oxide-modified phosphosilicate glass layer is 1×10⁻⁶. 18 cm -3 -5×10 18 cm -3 For example, it could be 1×10 18 cm -3 2×10 18 cm -3 2.5×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 Or 5×1018 cm -3 wait.

[0056] Furthermore, the surface roughness Ra of the oxide-modified phosphosilicate glass layer in contact with the second passivation layer is 0.1μm-2μm, for example, it can be 0.1μm, 0.2μm, 0.5μm, 0.88μm, 1.2μm, 1.4μm, 1.75μm, 1.9μm or 2μm, etc.

[0057] Furthermore, the oxide-modified phosphosilicate glass layer has a porous structure.

[0058] In this invention, the porous structure of the oxide-modified phosphosilicate glass layer is beneficial for field-effect passivation. Field-effect passivation refers to the process where phosphorus in the oxide layer diffuses and forms a heavily doped region near the silicon surface, inducing band bending and generating a built-in electric field. This electric field repels minority carriers (holes) in the N-region, preventing them from approaching the surface and recombinating, thereby enhancing the passivation effect. In conjunction with a second passivation layer (such as an alumina layer): the upper second passivation layer carries a strong negative charge and can also produce field-effect passivation for N-type silicon (although its effect is more significant on P-type silicon). Therefore, the combination of the oxide-modified phosphosilicate glass layer and the upper surface second passivation layer (such as an alumina layer) can theoretically achieve ultra-strong passivation.

[0059] Furthermore, the first passivation layer and the second passivation layer each independently comprise any one or a combination of at least two of the following: an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0060] Furthermore, the thickness ratio of the oxide-modified phosphosilicate glass layer to the second passivation layer is 1:(10-30), for example, it can be 1:10, 1:14, 1:17:1:22, 1:27 or 1:30, etc.

[0061] Furthermore, the thickness of the first passivation layer is 60-110nm, for example, it can be 60nm, 70nm, 80nm, 90nm, 100nm or 110nm, etc.

[0062] Furthermore, the first passivation layer includes an aluminum oxide layer and a silicon nitride layer, and the thickness of the aluminum oxide layer is 3nm-6nm, for example, it can be 3nm, 4nm, 5nm or 6nm, etc.

[0063] Furthermore, the interval region has a velvety structure.

[0064] Furthermore, the first tunneling oxide layer includes a silicon oxide layer.

[0065] Furthermore, the thickness of the first tunneling oxide layer is 1nm-2nm, for example, it can be 1nm, 1.2nm, 1.3nm, 1.4nm, 1.6nm, 1.8nm or 2nm, etc.

[0066] Furthermore, the second tunneling oxide layer includes a silicon oxide layer.

[0067] Furthermore, the thickness of the second tunneling oxide layer is 1nm-2nm, for example, it can be 1nm, 1.2nm, 1.3nm, 1.4nm, 1.6nm, 1.8nm or 2nm, etc.

[0068] Furthermore, the thickness of the first type of doped polycrystalline silicon layer is 90nm-400nm, for example, it can be 90nm, 120nm, 160nm, 200nm, 240nm, 300nm, 350nm or 400nm, etc.

[0069] Furthermore, the first type of doped polysilicon layer is a p-type doped polysilicon layer, wherein the boron doping concentration is 2 × 10⁻⁶. 19 cm -3 -3.8×10 19 cm -3 For example, it could be 2×10 19 cm -3 2.2×10 19 cm -3 2.4×10 19 cm -3 2.8×10 19 cm -3 3.2×10 19 cm -3 3.5×10 19 cm -3 Or 3.8×10 19 cm -3 wait.

[0070] Furthermore, the thickness of the second type of doped polycrystalline silicon layer is 90nm-400nm, for example, it can be 90nm, 120nm, 160nm, 200nm, 240nm, 300nm, 350nm or 400nm, etc.

[0071] Furthermore, the second type of doped polysilicon layer is an n-type doped polysilicon layer, wherein the phosphorus doping concentration is 2.5 × 10⁻⁶. 20 cm -3 -5×10 20 cm -3 For example, it could be 2.5 × 10 20 cm -3 2.8×10 20 cm-3 3.2×10 20 cm -3 3.5×10 20 cm -3 4.5×10 20 cm -3 Or 5×10 20 cm -3 wait.

[0072] Furthermore, the back side of the silicon substrate also includes a metal electrode. For example, it could be a silver electrode, etc.

[0073] Furthermore, the metal electrode includes a first electrode and a second electrode, the first electrode being in contact with the first passivation layer and the first type of doped polycrystalline silicon layer, and the second electrode being in contact with the second type of doped polycrystalline silicon layer through the oxide-modified phosphosilicate glass layer and the second passivation layer.

[0074] Furthermore, the front side of the silicon substrate has a textured structure. For example, it could be a pyramidal textured surface, etc.

[0075] Furthermore, the front side of the silicon substrate includes a front passivation layer along a direction away from the thickness of the silicon substrate.

[0076] Furthermore, the front passivation layer includes an aluminum oxide layer and / or a silicon nitride layer.

[0077] Furthermore, the thickness of the front passivation layer is 60nm-100nm, for example, it can be 60nm, 75nm, 80nm, 85nm, 90nm or 100nm.

[0078] Furthermore, there is a height difference between the back side of the silicon substrate deposited by the first doped region and the second doped region, and the first doped region is farther away from the front side of the silicon substrate than the second doped region.

[0079] In another specific embodiment, the present invention provides a method for fabricating a back-contact solar cell as described above, the method comprising the following steps: A silicon substrate is provided, the silicon substrate comprising opposing front and back sides.

[0080] A first tunneling layer and a first type-doped polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then the first tunneling layer and the first type-doped polysilicon layer are removed in a predetermined area of ​​the second doping region and the spacer region.

[0081] A second tunneling layer, a second type-doped polysilicon layer, and a mask layer are deposited on the back side of the silicon substrate. Then, the mask layer, the second type-doped polysilicon layer, and the second tunneling layer in the predetermined areas of the first doped region and the spacer region are removed in sequence. A phosphosilicate glass layer is formed between the second type-doped polysilicon layer and the mask layer.

[0082] A composite etchant is used to remove the mask layer of the predetermined area of ​​the second doped region, and the phosphosilicate glass layer is modified to obtain an oxide-modified phosphosilicate glass layer; wherein the composite etchant includes an oxidant and an acid, and the concentration of the oxidant is >5wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, or 15wt%, etc.

[0083] Passivation layers are deposited in predetermined regions of the first and second doped regions to obtain the first passivation layer and the second passivation layer, respectively.

[0084] In the preparation process provided by this invention, a high-concentration hydrogen peroxide is used to directly oxidize and modify the phosphosilicate glass layer. The oxidation effect of hydrogen peroxide alters the chemical properties of the phosphosilicate glass, making it less susceptible to removal by acid in subsequent processing, thereby forming a stable oxidized phosphosilicate glass layer in situ. This layer not only possesses excellent chemical passivation properties but also effectively combines with the second passivation layer on the back side to synergistically exert a passivation effect, achieving a superimposed passivation effect. This process avoids the introduction of secondary phosphorus from the source, has high process integration, and significantly improves the stability of the passivation effect and the battery conversion efficiency.

[0085] Furthermore, the concentration of the oxidant is 5wt%-20wt% and does not include 5wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, 15wt% or 20wt%, etc.

[0086] In this invention, a specific concentration of hydrogen peroxide is beneficial for the formation of an oxide layer thickness and is more conducive to the field passivation effect.

[0087] Furthermore, the oxidant includes hydrogen peroxide.

[0088] Furthermore, the acid solution includes HF.

[0089] Furthermore, the concentration of the acid solution is 5wt%-30wt%, for example, it can be 5.5wt%, 7.5wt%, 8.5wt%, 10wt%, 15wt%, 25wt%, 30wt%, etc.

[0090] Furthermore, the preparation method includes the following steps: (1) A pretreated silicon substrate is provided, wherein the silicon substrate is an N-type silicon wafer or a P-type silicon wafer; wherein the pretreatment includes polishing.

[0091] (2) A first tunneling layer and an intrinsic polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then boron diffusion is performed to obtain a first tunneling layer and a first type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the first type doped polysilicon layer. (3) The BSG layer located in the predetermined area of ​​the second doped region and the spacer region is removed by laser, and then polishing is performed to remove the exposed first type doped polysilicon layer and the first tunneling layer in sequence, while retaining the BSG layer located in the predetermined area of ​​the first doped region; (4) Based on step (3), a second tunneling layer and an intrinsic polysilicon layer are deposited on the back side of the silicon substrate, and then phosphorus diffusion is performed to obtain a second tunneling layer and a second type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the second type doped polysilicon layer. (5) A mask layer is deposited on the PSG layer, and then the mask layer of the first doped region and the predetermined area of ​​the spacer region is removed by laser; wherein the mask layer includes a silicon nitride layer; During texturing, etching is used to remove the second tunneling layer and the second type-doped polycrystalline silicon layer in the predetermined area of ​​the first doped region and the spacer region.

[0092] (6) The front side of the silicon substrate is acid-etched to remove the parasitic layer on the front side (it should be noted that the parasitic layer on the front side refers to the unnecessary multilayer thin films, such as P+ layer and N+ layer, that are deposited on the front side of the silicon wafer while the target microstructure design is completed on the back side of the silicon wafer).

[0093] (7) Fabrication, the specific steps of which include: The silicon substrate after step (6) is etched using a composite etchant to form a textured structure on the front side of the silicon substrate. At the same time, the mask layer of the predetermined area of ​​the second doped region on the back side of the silicon substrate is removed, and the PSG layer of the predetermined area of ​​the second doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant includes hydrogen peroxide and acid, the concentration of hydrogen peroxide is 5wt%-20wt%, and the acid includes any one or at least two of HF, hydrogen peroxide or oxidizing additives, and the concentration of acid is 5wt%-30wt%.

[0094] (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front and back sides of the silicon substrate, such that a front passivation layer is formed on the front side of the silicon substrate, a first passivation layer is formed in a predetermined area of ​​the first doped region on the back side of the silicon substrate, and a second passivation layer is formed in a predetermined area of ​​the second doped region.

[0095] (9) Metallize the back side of the silicon substrate to obtain a metal electrode.

[0096] Example 1 This embodiment provides a back-contact solar cell, the structural schematic of which is shown below. Figure 1 As shown, the back-contact solar cell includes: an N-type silicon wafer 1, which includes a front side and a back side; the back side includes alternating P+ doped regions and N+ doped regions along a first direction, and adjacent P+ doped regions and N+ doped regions are separated by a spacer region; the first direction is perpendicular to the thickness of the N-type silicon wafer 1.

[0097] The P+ doped region includes a first tunneling oxide layer 2, a p-type doped polysilicon layer 3, and a first passivation layer along the direction away from the thickness of the N-type silicon wafer 1; the N+ doped region includes a second tunneling oxide layer 4, an n-type doped polysilicon layer 5, an oxide-modified phosphosilicate glass layer 6, and a second passivation layer along the direction away from the thickness of the N-type silicon wafer 1; the spacer region has a pyramid-shaped textured structure.

[0098] The thickness of the oxide-modified phosphosilicate glass layer 6 is 4.5 nm; the phosphorus content in the oxide-modified phosphosilicate glass layer 6 is 2.2 × 10⁻⁶. 18 cm -3 The surface roughness Ra of the oxide-modified phosphosilicate glass layer 6 in contact with the second passivation layer is 1 μm; the oxide-modified phosphosilicate glass layer 6 has a porous structure.

[0099] The first passivation layer and the second passivation layer each independently comprise an aluminum oxide layer 7 and a silicon nitride layer 8, wherein the aluminum oxide layer 7 has a thickness of 4 nm and the silicon nitride layer 8 has a thickness of 80 nm; the thickness ratio of the oxide-modified phosphosilicate glass layer 6 to the second passivation layer is 1:18.67; the first tunneling oxide layer 2 is a silicon oxide layer with a thickness of 1.45 nm; the second tunneling oxide layer 4 is a silicon oxide layer with a thickness of 1.65 nm; and the p-type doped polycrystalline silicon layer 3 has a thickness of 145 nm and a doping concentration of 2.5 × 10⁻⁶. 19 cm -3 The thickness of the n-type doped polysilicon layer 5 is 165 nm, and the doping concentration is 3.5 × 10⁻⁶. 20 cm -3 .

[0100] The back side of the N-type silicon wafer 1 also includes a first silver electrode and a second silver electrode. The first silver electrode passes through the first passivation layer and contacts the p-type doped polycrystalline silicon layer 3, and the second silver electrode passes through the oxide-modified phosphosilicate glass layer 6 and the second passivation layer and contacts the n-type doped polycrystalline silicon layer 5.

[0101] Among them, the front side of the N-type silicon wafer 1 has a pyramid-shaped textured surface; the front side of the N-type silicon wafer 1 includes a front passivation layer along the direction away from the thickness of the N-type silicon wafer 1, and the front passivation layer includes an aluminum oxide layer with a thickness of 4nm and a silicon nitride layer with a thickness of 80nm.

[0102] There is a height difference between the back side of the N-type silicon wafer 1 deposited with P+ doped region and N+ doped region, and the P+ doped region is farther away from the front side of the N-type silicon wafer 1 than the N+ doped region.

[0103] This embodiment also provides a method for preparing the above-mentioned back-contact solar cell, including the following steps: (1) Provide a polished N-type silicon wafer.

[0104] (2) A silicon dioxide layer and an intrinsic polysilicon layer are deposited sequentially on the back side of an N-type silicon wafer, and then boron diffusion is performed to obtain a silicon oxide layer and a p-type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the p-type polysilicon layer.

[0105] (3) Use a laser device to remove the BSG layer located in the predetermined region of the N+ doped region and the spacer region, and then polish to remove the exposed p-type polysilicon layer and silicon oxide layer in sequence, while retaining the BSG layer located in the predetermined region of the P+ doped region.

[0106] (4) Based on step (3), a silicon oxide layer and an intrinsic polysilicon layer are deposited on the back side of the N-type silicon wafer, and then phosphorus diffusion is performed to obtain a silicon oxide layer and an n-type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the n-type polysilicon layer.

[0107] (5) A silicon nitride mask layer is deposited on the PSG layer, and then the silicon nitride mask layer in the predetermined areas of the P+ doped region and the spacer region is removed by laser.

[0108] Etching removes the silicon oxide layer and n-type doped polysilicon layer in the predetermined area of ​​the spacer region.

[0109] (6) The front side of the N-type silicon wafer is acid-etched by water-floating etching to remove the parasitic layer on the front side.

[0110] (7) Fabrication, the specific steps of which include: The N-type silicon wafer after step (6) is etched using a composite etchant to form a textured structure on the front side of the N-type silicon wafer. At the same time, the silicon nitride mask layer of the predetermined N+ doped region on the back side of the N-type silicon wafer is removed, and the PSG layer of the predetermined N+ doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant includes hydrogen peroxide and HF, with a hydrogen peroxide concentration of 10 wt% and an HF concentration of 15 wt%.

[0111] (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front and back sides of the N-type silicon wafer, so that a front passivation layer is formed on the front side of the N-type silicon wafer, a first passivation layer is formed in a predetermined area of ​​the P+ doped region on the back side of the N-type silicon wafer, and a second passivation layer is formed in a predetermined area of ​​the N+ doped region.

[0112] (9) Metallization process: Silver paste is used to screen print on the back of the N-type silicon wafer, and after sintering, the first silver electrode and the second silver electrode are obtained respectively.

[0113] Example 2 This embodiment provides a back-contact solar cell, which includes an N-type silicon wafer, the N-type silicon wafer including a front side and a back side; the back side includes alternating P+ doped regions and N+ doped regions along a first direction, and adjacent P+ doped regions and N+ doped regions are separated by a spacer region; the first direction is a direction perpendicular to the thickness of the N-type silicon wafer.

[0114] The P+ doped region includes a first tunneling oxide layer, a p-type doped polysilicon layer, and a first passivation layer along the direction away from the thickness of the N-type silicon wafer; the N+ doped region includes a second tunneling oxide layer, an n-type doped polysilicon layer, an oxide-modified phosphosilicate glass layer, and a second passivation layer along the direction away from the thickness of the N-type silicon wafer; the spacer region has a pyramid-shaped textured structure.

[0115] The thickness of the oxide-modified phosphosilicate glass layer is 3 nm; the phosphorus content in the oxide-modified phosphosilicate glass layer is 1 × 10⁻⁶. 18 cm -3 The surface roughness Ra of the oxide-modified phosphosilicate glass layer in contact with the second passivation layer is 0.2 μm; the oxide-modified phosphosilicate glass layer has a porous structure.

[0116] The first and second passivation layers each independently comprise an aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer has a thickness of 3 nm and the silicon nitride layer has a thickness of 60 nm; the thickness ratio of the oxide-modified phosphosilicate glass layer to the second passivation layer is 1:21; the first tunneling oxide layer is a silicon oxide layer with a thickness of 1 nm; the second tunneling oxide layer is a silicon oxide layer with a thickness of 1 nm; and the p-type doped polycrystalline silicon layer has a thickness of 90 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 The thickness of the n-type doped polycrystalline silicon layer is 90 nm, and the doping concentration is 2.5 × 10⁻⁶. 20 cm -3 .

[0117] The back side of the N-type silicon wafer also includes a first silver electrode and a second silver electrode. The first silver electrode passes through the first passivation layer and contacts the p-type doped polysilicon layer, and the second silver electrode passes through the oxide-modified phosphosilicate glass layer and the second passivation layer and contacts the n-type doped polysilicon layer.

[0118] The front side of the N-type silicon wafer has a pyramid-shaped textured surface. Along the direction away from the thickness of the N-type silicon wafer, the front side of the N-type silicon wafer includes a front passivation layer, which includes an aluminum oxide layer with a thickness of 3 nm and a silicon nitride layer with a thickness of 60 nm.

[0119] There is a height difference between the P+ doped region and the N+ doped region on the back side of the N-type silicon wafer, and the P+ doped region is farther away from the front side of the N-type silicon wafer than the N+ doped region.

[0120] This embodiment also provides a method for preparing the above-mentioned back-contact solar cell, including the following steps: (1) Provide a polished N-type silicon wafer.

[0121] (2) A silicon dioxide layer and an intrinsic polysilicon layer are deposited sequentially on the back side of an N-type silicon wafer, and then boron diffusion is performed to obtain a silicon oxide layer and a p-type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the p-type polysilicon layer.

[0122] (3) Use a laser device to remove the BSG layer located in the predetermined region of the N+ doped region and the spacer region, and then polish to remove the exposed p-type polysilicon layer and silicon oxide layer in sequence, while retaining the BSG layer located in the predetermined region of the P+ doped region.

[0123] (4) Based on step (3), a silicon oxide layer and an intrinsic polysilicon layer are deposited on the back side of the N-type silicon wafer, and then phosphorus diffusion is performed to obtain a silicon oxide layer and an n-type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the n-type polysilicon layer.

[0124] (5) A silicon nitride mask layer is deposited on the PSG layer, and then the silicon nitride mask layer in the predetermined areas of the P+ doped region and the spacer region is removed by laser.

[0125] Etching removes the silicon oxide layer and n-type doped polysilicon layer in the predetermined area of ​​the spacer region.

[0126] (6) The front side of the N-type silicon wafer is acid-etched by water-floating etching to remove the parasitic layer on the front side.

[0127] (7) Fabrication, the specific steps of which include: The N-type silicon wafer after step (6) is etched using a composite etchant to form a textured structure on the front side of the N-type silicon wafer. At the same time, the silicon nitride mask layer of the predetermined N+ doped region on the back side of the N-type silicon wafer is removed, and the PSG layer of the predetermined N+ doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant includes hydrogen peroxide and HF, with a hydrogen peroxide concentration of 6 wt% and an HF concentration of 5 wt%.

[0128] (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front and back sides of the N-type silicon wafer, so that a front passivation layer is formed on the front side of the N-type silicon wafer, a first passivation layer is formed in a predetermined area of ​​the P+ doped region on the back side of the N-type silicon wafer, and a second passivation layer is formed in a predetermined area of ​​the N+ doped region.

[0129] (9) Metallization process: Silver paste is used to screen print on the back of the N-type silicon wafer, and after sintering, the first silver electrode and the second silver electrode are obtained respectively.

[0130] Example 3 This embodiment provides a back-contact solar cell, which includes an N-type silicon wafer, the N-type silicon wafer including a front side and a back side; the back side includes alternating P+ doped regions and N+ doped regions along a first direction, and adjacent P+ doped regions and N+ doped regions are separated by a spacer region; the first direction is a direction perpendicular to the thickness of the N-type silicon wafer.

[0131] The P+ doped region includes a first tunneling oxide layer, a p-type doped polysilicon layer, and a first passivation layer along the direction away from the thickness of the N-type silicon wafer; the N+ doped region includes a second tunneling oxide layer, an n-type doped polysilicon layer, an oxide-modified phosphosilicate glass layer, and a second passivation layer along the direction away from the thickness of the N-type silicon wafer; the spacer region has a pyramid-shaped textured structure.

[0132] The thickness of the oxide-modified phosphosilicate glass layer is 10 nm; the phosphorus content in the oxide-modified phosphosilicate glass layer is 5 × 10⁻⁶. 18 cm -3 The surface roughness Ra of the oxide-modified phosphosilicate glass layer in contact with the second passivation layer is 2 μm; the oxide-modified phosphosilicate glass layer has a porous structure.

[0133] The first and second passivation layers each independently comprise an aluminum oxide layer and a silicon nitride layer, wherein the aluminum oxide layer has a thickness of 6 nm and the silicon nitride layer has a thickness of 100 nm; the thickness ratio of the oxide-modified phosphosilicate glass layer to the second passivation layer is 1:10.6; the first tunneling oxide layer is a silicon oxide layer with a thickness of 2 nm; the second tunneling oxide layer is a silicon oxide layer with a thickness of 2 nm; the p-type doped polycrystalline silicon layer has a thickness of 400 nm and a doping concentration of 3.8 × 10⁻⁶. 19 cm -3 The thickness of the n-type doped polysilicon layer is 400 mm, and the doping concentration is 2.5 × 10⁻⁶. 20 cm -3 .

[0134] The back side of the N-type silicon wafer also includes a first silver electrode and a second silver electrode. The first silver electrode passes through the first passivation layer and contacts the p-type doped polysilicon layer, and the second silver electrode passes through the oxide-modified phosphosilicate glass layer and the second passivation layer and contacts the n-type doped polysilicon layer.

[0135] The front side of the N-type silicon wafer has a pyramid-shaped textured surface. Along the direction away from the thickness of the N-type silicon wafer, the front side of the N-type silicon wafer includes a front passivation layer, which includes an aluminum oxide layer with a thickness of 6 nm and a silicon nitride layer with a thickness of 100 nm.

[0136] There is a height difference between the P+ doped region and the N+ doped region on the back side of the N-type silicon wafer, and the P+ doped region is farther away from the front side of the N-type silicon wafer than the N+ doped region.

[0137] This embodiment also provides a method for preparing the above-mentioned back-contact solar cell, including the following steps: (1) Provide a polished N-type silicon wafer.

[0138] (2) A silicon dioxide layer and an intrinsic polysilicon layer are deposited sequentially on the back side of an N-type silicon wafer, and then boron diffusion is performed to obtain a silicon oxide layer and a p-type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the p-type polysilicon layer.

[0139] (3) Use a laser device to remove the BSG layer located in the predetermined region of the N+ doped region and the spacer region, and then polish to remove the exposed p-type polysilicon layer and silicon oxide layer in sequence, while retaining the BSG layer located in the predetermined region of the P+ doped region.

[0140] (4) Based on step (3), a silicon oxide layer and an intrinsic polysilicon layer are deposited on the back side of the N-type silicon wafer, and then phosphorus diffusion is performed to obtain a silicon oxide layer and an n-type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the n-type polysilicon layer.

[0141] (5) A silicon nitride mask layer is deposited on the PSG layer, and then the silicon nitride mask layer in the predetermined areas of the P+ doped region and the spacer region is removed by laser.

[0142] Etching removes the silicon oxide layer and n-type doped polysilicon layer in the predetermined area of ​​the spacer region.

[0143] (6) The front side of the N-type silicon wafer is acid-etched by water-floating etching to remove the parasitic layer on the front side.

[0144] (7) Fabrication, the specific steps of which include: The N-type silicon wafer after step (6) is etched using a composite etchant to form a textured structure on the front side of the N-type silicon wafer. At the same time, the silicon nitride mask layer of the predetermined N+ doped region on the back side of the N-type silicon wafer is removed, and the PSG layer of the predetermined N+ doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant includes hydrogen peroxide and HF, with a hydrogen peroxide concentration of 20wt% and an HF concentration of 30wt%.

[0145] (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on the front and back sides of the N-type silicon wafer, so that a front passivation layer is formed on the front side of the N-type silicon wafer, a first passivation layer is formed in a predetermined area of ​​the P+ doped region on the back side of the N-type silicon wafer, and a second passivation layer is formed in a predetermined area of ​​the N+ doped region.

[0146] (9) Metallization process: Silver paste is used to screen print on the back of the N-type silicon wafer, and after sintering, the first silver electrode and the second silver electrode are obtained respectively.

[0147] Example 4 The difference between this embodiment and Embodiment 1 is that the N-type silicon wafer is replaced with a P-type silicon wafer.

[0148] The remaining preparation methods and parameters are consistent with those in Example 1.

[0149] Example 5 The difference between this embodiment and Embodiment 1 is that the hydrogen peroxide concentration is reduced so that the thickness of the oxidized modified phosphosilicate glass layer is 1 nm.

[0150] The remaining preparation methods and parameters are consistent with those in Example 1.

[0151] Example 6 The difference between this embodiment and Embodiment 1 is that the hydrogen peroxide concentration is increased to make the thickness of the oxidized modified phosphosilicate glass layer 15nm.

[0152] The remaining preparation methods and parameters are consistent with those in Example 1.

[0153] Example 7 The difference between this embodiment and Embodiment 1 is that the phosphorus doping concentration is reduced, resulting in a phosphorus content of 0.5 × 10⁻⁶ in the oxide-modified phosphosilicate glass layer. 18 cm -3 .

[0154] The remaining preparation methods and parameters are consistent with those in Example 1.

[0155] Example 8 The difference between this embodiment and Embodiment 1 is that the phosphorus doping concentration is increased, resulting in a phosphorus content of 1×10⁻⁶ in the oxide-modified phosphorus silicate glass layer. 19 cm -3 .

[0156] The remaining preparation methods and parameters are consistent with those in Example 1.

[0157] Example 9 The difference between this embodiment and Embodiment 1 is that the thickness ratio of the oxide-modified phosphosilicate glass layer and the second passivation layer is 1:5.

[0158] The remaining preparation methods and parameters are consistent with those in Example 1.

[0159] Example 10 The difference between this embodiment and Embodiment 1 is that the thickness ratio of the oxide-modified phosphosilicate glass layer and the second passivation layer is 1:40.

[0160] The remaining preparation methods and parameters are consistent with those in Example 1.

[0161] Comparative Example 1 The difference between this comparative example and Example 1 is that in step (7), the concentration of hydrogen peroxide is adjusted so that the PSG layer in the predetermined region of the N+ doped region is not modified.

[0162] The remaining preparation methods and parameters are consistent with those in Example 1.

[0163] Comparative Example 2 The difference between this comparative example and Example 1 is that in step (7), while removing the silicon nitride mask layer of the predetermined N+ doped region on the back side of the N-type silicon wafer, the PSG layer of the predetermined N+ doped region is also removed, and a silicon dioxide layer is deposited on the n-type polysilicon layer by thermal oxidation, and phosphorus diffusion is performed to form a phosphorus-containing silicon dioxide layer.

[0164] The remaining preparation methods and parameters are consistent with those in Example 1.

[0165] Performance testing The photoelectric performance of the back-contact solar cells provided in the above embodiments and comparative examples was tested. The test method was as follows: a standard solar simulator was used, and a dedicated photovoltaic IV tester was used to apply a continuously adjustable bias voltage to the BC solar cell, and the corresponding current value was collected simultaneously to generate a current-voltage (IV) curve. The open-circuit voltage, short-circuit current density, fill factor and photoelectric conversion efficiency were extracted from the curve.

[0166] Test conditions were: AM1.5G, 1000±50W / m 2 25℃, one standard atmosphere.

[0167] The test results are shown in Table 1.

[0168] Table 1 analyze: As shown in Table 1, this invention directly oxidizes and modifies the phosphosilicate glass layer generated during the formation of an n-type doped polycrystalline silicon layer by phosphorus diffusion, resulting in an oxidized phosphosilicate glass layer. This avoids the problem of secondary phosphorus introduction at the source and significantly prevents the damage to the passivation layer structure on the back of the battery caused by secondary phosphorus introduction. Moreover, this oxidized phosphosilicate glass layer works synergistically with the second passivation layer to achieve a superimposed passivation effect. While ensuring low series resistance and excellent carrier collection capability, this oxidized phosphosilicate glass layer significantly improves the open-circuit voltage and fill factor of the battery, providing a key guarantee for obtaining higher battery conversion efficiency and enhancing the stability of battery performance. In the preparation process provided by this invention, a high concentration of hydrogen peroxide is used to directly oxidize and modify the phosphosilicate glass layer. The oxidation effect of hydrogen peroxide changes the chemical properties of the phosphosilicate glass, making it difficult to be removed by acid in subsequent processing, thereby forming a stable oxidized phosphosilicate glass layer in situ. This layer not only has good chemical passivation performance itself, but can also effectively combine with the second passivation layer on the back to synergistically exert a passivation effect and achieve a superimposed passivation effect. This process avoids the introduction of secondary phosphorus from the source, has a high degree of process integration, and significantly improves the stability of passivation effect and battery conversion efficiency.

[0169] A comparison of Examples 1 and 5-6 shows that if the thickness of the oxide-modified phosphosilicate glass layer is too small, it is difficult to achieve a passivation effect. The extremely thin film layer is more prone to microscopic inhomogeneity, causing local differences and affecting the uniformity of the film layer. Furthermore, the reduction in thickness will significantly weaken the field passivation effect, affecting Voc. If the thickness of the oxide-modified phosphosilicate glass layer is too large, it will block the collection of charge carriers. Electrons in an excessively thick oxide-modified phosphosilicate glass layer cannot pass through, blocking quantum tunneling. Electrons can only transport through inefficient paths such as tunneling assisted by defects in the oxide-modified phosphosilicate glass layer or completely bypassing the oxide-modified phosphosilicate glass layer, resulting in a sharp increase in contact resistance, which is directly reflected in a significant decrease in the battery fill factor. At the same time, the blocked electrons will accumulate and recombine at the interface, which will also reduce the open circuit voltage.

[0170] A comparison of Examples 1 and 7-8 shows that if the phosphorus content in the oxide-modified phosphosilicate glass layer is too low, the resulting back field sheet resistance is high. Although this is beneficial for short-circuit current, it leads to increased contact resistance and a reduced fill factor. The extremely thin phosphorus content also makes the film layer more prone to microscopic inhomogeneity, causing local doping differences and poor field passivation effect. If the phosphorus content in the oxide-modified phosphosilicate glass layer is too high, although there is a lower contact resistance and a higher fill factor, heavy doping may exacerbate Auger recombination, reduce short-circuit current, and during subsequent high-temperature processes, phosphorus atoms in the modified oxide layer may diffuse upwards, destroying the chemical structure of the alumina film deposited in the upper atomic layer, severely degrading its excellent surface passivation ability, and causing a significant decrease in the battery open-circuit voltage.

[0171] As can be seen from the comparison between Example 1 and Examples 9-10, if the thickness ratio of the oxide-modified phosphosilicate glass layer and the second passivation layer is too small or too large, it will not be conducive to the full play of the synergistic effect between the oxide-modified phosphosilicate glass layer and the alumina layer.

[0172] As can be seen from the comparison between Example 1 and Comparative Example 1, if the PSG layer in the predetermined region of the N+ doped region is not modified, the passivation effect is weakened and the open circuit voltage is reduced; it cannot exert its field-effect passivation.

[0173] As can be seen from the comparison between Example 1 and Comparative Example 2, if the PSG layer in the predetermined region of the N+ doped region is removed, and a silicon oxide layer is deposited on the n-type polycrystalline silicon layer by thermal oxidation, and phosphorus diffusion is performed to form a phosphorus-containing silicon oxide layer, then phosphorus will diffuse into the silicon wafer, forming heavy doping, which makes it difficult to control the surface concentration; and the phosphorus introduced in the second step will penetrate the alumina layer during heat treatment and react with aluminum, which will destroy the crystal structure of alumina, significantly reduce its negative charge density, and weaken its field passivation ability.

[0174] It should be noted that the present invention is illustrated through the above embodiments, but the present invention is not limited to the above process steps, that is, it does not mean that the present invention must rely on the above process steps to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions of the raw materials used in the present invention, additions of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A back-contact solar cell, characterized in that, The back-contact solar cell includes a silicon substrate, the silicon substrate having opposing front and back sides; in a first direction, the back side includes alternating first and second doped regions, and adjacent first and second doped regions are separated by a spacer region; the first direction is perpendicular to the thickness of the silicon substrate. The first doped region includes a first tunneling oxide layer, a first type doped polysilicon layer, and a first passivation layer along the direction away from the thickness of the silicon substrate; the second doped region includes a second tunneling oxide layer, a second type doped polysilicon layer, an oxide-modified phosphosilicate glass layer, and a second passivation layer along the direction away from the thickness of the silicon substrate.

2. The back-contact solar cell according to claim 1, characterized in that, The thickness of the oxidized modified phosphosilicate glass layer is 2nm-10nm; And / or, the phosphorus content in the oxide-modified phosphosilicate glass layer is 1×10⁻⁶. 18 cm -3 -5×10 18 cm -3 .

3. The back-contact solar cell according to claim 1, characterized in that, The surface roughness Ra of the oxide-modified phosphosilicate glass layer in contact with the second passivation layer is 0.1 μm-2 μm.

4. The back-contact solar cell according to claim 1, characterized in that, The oxidized modified phosphosilicate glass layer has a porous structure.

5. The back-contact solar cell according to claim 1, characterized in that, The first passivation layer and the second passivation layer each independently comprise any one or a combination of at least two of the following: an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer; And / or, the thickness ratio of the oxide-modified phosphosilicate glass layer and the second passivation layer is 1:(10-30).

6. The back-contact solar cell according to claim 1, characterized in that, The interval area has a velvety structure; And / or, the first tunneling oxide layer includes a silicon oxide layer; And / or, the second tunneling oxide layer includes a silicon oxide layer; And / or, the back side of the silicon substrate also includes a metal electrode; And / or, the front side of the silicon substrate has a textured surface; And / or, the front side of the silicon substrate includes a front passivation layer along a direction away from the thickness of the silicon substrate.

7. A method for preparing a back-contact solar cell as described in any one of claims 1-6, characterized in that, The preparation method includes the following steps: A silicon substrate is provided, the silicon substrate comprising opposing front and back sides; A first tunneling layer and a first type-doped polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then the first tunneling layer and the first type-doped polysilicon layer are removed in a predetermined area of ​​the second doped region and the spacer region. A second tunneling layer, a second type-doped polysilicon layer, and a mask layer are deposited on the back side of the silicon substrate. Then, the mask layer, the second type-doped polysilicon layer, and the second tunneling layer in the predetermined areas of the first doped region and the spacer region are removed in sequence. A phosphosilicate glass layer is formed between the second type-doped polysilicon layer and the mask layer. A composite etchant is used to remove the mask layer in a predetermined area of ​​the second doped region, and the phosphosilicate glass layer is modified to obtain an oxide-modified phosphosilicate glass layer; wherein the composite etchant comprises an oxidant and an acid, and the concentration of the oxidant is >5 wt%; Passivation layers are deposited in predetermined regions of the first and second doped regions to obtain the first passivation layer and the second passivation layer, respectively.

8. The preparation method according to claim 7, characterized in that, The concentration of the oxidant is 5wt%-20wt%, excluding 5wt%; And / or, the oxidizing agent includes hydrogen peroxide; And / or, the acid solution includes HF; And / or, the concentration of the acid solution is 5wt%-30wt%.

9. The preparation method according to claim 7, characterized in that, The preparation method includes the following steps: (1) A pretreated silicon substrate is provided, wherein the silicon substrate is an N-type silicon wafer or a P-type silicon wafer; wherein the pretreatment includes polishing; (2) A first tunneling layer and an intrinsic polysilicon layer are sequentially deposited on the back side of the silicon substrate, and then boron diffusion is performed to obtain a first tunneling layer and a first type doped polysilicon layer; wherein, a BSG layer is formed on the outer surface of the first type doped polysilicon layer. (3) The BSG layer located in the predetermined area of ​​the second doped region and the spacer region is removed by laser, and then polishing is performed to remove the exposed first type doped polysilicon layer and the first tunneling layer in sequence, while retaining the BSG layer located in the predetermined area of ​​the first doped region; (4) Based on step (3), a second tunneling layer and an intrinsic polysilicon layer are deposited on the back side of the silicon substrate, and then phosphorus diffusion is performed to obtain a second tunneling layer and a second type doped polysilicon layer; wherein, a PSG layer is formed on the outer surface of the second type doped polysilicon layer. (5) A mask layer is deposited on the PSG layer, and then the mask layer of the first doped region and the predetermined area of ​​the spacer region is removed by laser; wherein the mask layer includes a silicon nitride layer; During texturing, etching is used to remove the second type-doped tunneling layer and the second type-doped polysilicon layer in the predetermined area of ​​the first doped region and the spacer region; (6) The front side of the silicon substrate is acid-etched to remove the parasitic layer on the front side; (7) Fabrication, the specific steps of which include: The silicon substrate treated in step (6) is etched using a composite etchant to form a textured surface on the front side of the silicon substrate. Simultaneously, the mask layer of the predetermined area of ​​the second doped region on the back side of the silicon substrate is removed, and the PSG layer of the predetermined area of ​​the second doped region is modified to obtain an oxide-modified phosphosilicate glass layer. The composite etchant comprises hydrogen peroxide and an acid solution, with the hydrogen peroxide concentration being 5wt%-20wt% and the acid solution comprising HF, with an acid concentration of 5wt%-30wt%. (8) An aluminum oxide layer and a silicon nitride layer are deposited sequentially on both the front and back sides of the silicon substrate, such that a front passivation layer is formed on the front side of the silicon substrate, a first passivation layer is formed in a predetermined area of ​​the first doped region on the back side of the silicon substrate, and a second passivation layer is formed in a predetermined area of ​​the second doped region. (9) Metallize the back side of the silicon substrate to obtain a metal electrode.

10. An application of a back-contact solar cell as described in any one of claims 1-6 in the photovoltaic field.

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