Preparation method of detection point of interposer and interposer

Abstract

The invention belongs to the technical field of semiconductors, and discloses a preparation method of a detection point of an interposer and the interposer, and the preparation method of the detection point of the interposer comprises the steps: forming a detection bonding pad in the interposer; and processing the side part of the interposer to expose the lateral surface of the detection bonding pad, and forming a metallization structure on the exposed lateral surface to form a detection point located in the lateral direction of the interposer. According to the invention, the technical problems of lengthy signal path, discontinuous impedance, serious reflection noise and occupation of surface wiring space caused by traditional surface test points can be solved, and the technical effects of improving signal integrity, optimizing packaging size, supporting higher-density integration and enhancing anti-interference capability are achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for preparing probe points in an interposer and the interposer itself. Background Technology

[0002] In the packaging structure of high-speed integrated circuits (such as LPDDR4 / 5 memory), the interposer plays a crucial role in connecting the chip to the motherboard and redistributing I / O signals. To ensure packaging yield and signal quality, probe points must be placed on the interposer for production testing and signal integrity verification.

[0003] Traditionally, probe points are placed on the surface of the interposer layer. This design paradigm of routing first and then adding test points forces high-speed signal paths to become exceptionally tortuous and lengthy in order to connect to the surface probe points. The signal needs to originate from the chip solder ball, pass through the surface pad, surface trace, and vertical via to reach the inner layer, then return to the surface probe point through additional blind vias, and finally reach the target solder ball. This path not only significantly increases the signal transmission length and delay, but also introduces multiple impedance discontinuities (such as vias and pad corners), resulting in severe signal reflection and insertion loss. Furthermore, the surface probe pads themselves and their leads occupy the already valuable surface routing resources, limiting the interposer layer routing density and the possibility of integrating passive devices or other functional chips on the surface, becoming a bottleneck restricting further miniaturization of packages and system-level heterogeneous integration.

[0004] To address these issues, efforts are typically focused on optimizing the layout of surface probe points or using more expensive low-loss dielectric materials. However, neither approach fundamentally changes the inherent structural defects caused by the test points being located on the surface. Therefore, existing technologies suffer from technical drawbacks such as long signal paths, poor impedance continuity, severe reflection noise, and the occupation of valuable surface wiring space. Summary of the Invention

[0005] In view of the above problems, this application provides a method for preparing detection points in an intermediary layer and an intermediary layer to solve the above technical problems.

[0006] In a first aspect, this application provides a method for preparing probe points in an intermediary layer, comprising: Probe pads are formed inside the interposer layer; The sides of the interposer are processed to expose the lateral surfaces of the probe pads, and a metallization structure is formed on the exposed lateral surfaces to form probe points located on the sides of the interposer.

[0007] In some embodiments, the step of processing the sides of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer includes: The sides of the intermediate layer are laminated in a stepped manner to form a stepped region with decreasing medium thickness; The stepped region is laser-ablated to form a high aspect ratio microgroove, which exposes the lateral surface of the probe pad. A seed layer is formed within the high aspect ratio microgroove and then electroplated with metal to form the metallized structure.

[0008] In some embodiments, the process parameters for the stepped lamination satisfy: The preheating temperature is 130℃ to 150℃, the lamination temperature is 180℃ to 200℃, and the lamination time is 45 minutes to 60 minutes. The lamination pressure from the initial time of lamination to the preset first time is 2.5 MPa, the lamination pressure from the preset first time to the preset second time is 3.5 MPa, and the lamination pressure from the preset second time to the end time of lamination is 1.5 MPa. The dielectric layer thickness in the stepped region decreases by 50 μm, with a tolerance of ±5 μm. The warpage after lamination is no greater than 30μm / 100mm.

[0009] In some embodiments, the laser ablation employs a 355nm picosecond laser, and the process parameters for the laser ablation satisfy the following: The pulse frequency is from 200kHz to 500kHz; The energy density is 1.5 J / cm³. 2 Up to 2.5 J / cm 2 ; The number of pulses is 300 to 500. The scanning speed is 200 mm / s to 300 mm / s; The experiment was conducted under nitrogen protection at a flow rate of 15 L / min. The aspect ratio of the high aspect ratio microgroove is not less than 5:1, and the depth tolerance is ±5μm.

[0010] In some embodiments, in the step of forming a seed layer in the high aspect ratio microgroove and then electroplating metal to fill it to form the metallized structure, the seed layer is formed by atomic layer deposition, and the process parameters of the seed layer satisfy the following: Deposition temperature was 120°C to 150°C; deposition pressure was 1 Torr to 5 Torr. The deposited seed layer consists of a titanium layer with a thickness of 20 nm ± 2 nm and a copper layer with a thickness of 80 nm ± 5 nm; The electroplated metal filler is produced using a pulse electroplating process, and the process parameters for the electroplated metal filler meet the following requirements: The electrolyte is a copper sulfate system, in which Cu 2+ The concentration is 50 g / L to 60 g / L; The pulse parameters are: peak current density of 8A / dm² to 10A / dm², on-time of 5ms, and off-time of 10ms. The annealing conditions were: 250℃ for 30 minutes, under a nitrogen atmosphere.

[0011] In some embodiments, the step of processing the sides of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer includes: The side of the interposer layer is cut to form a cross section that exposes the lateral surface of the probe pad; The cross section is subjected to surface metallization treatment to form the metallized structure.

[0012] In some embodiments, in the step of cutting the side of the interposer to form a cross-section that exposes the lateral surface of the probe pad, the cutting process parameters satisfy the following: The cutting speed is 2000 rpm, and the feed rate is 0.2 mm / s; In the step of performing surface metallization treatment on the cross section to form the metallized structure, the surface metallization treatment sequentially includes micro-etching, chemical copper plating, and pattern electroplating. The micro-etching process involves using a mixed solution of 5 wt% sodium persulfate and 3 wt% sulfuric acid, treated at 40°C for 60 seconds. The chemical copper plating forms a continuous conductive layer with a thickness of 0.5 μm ± 0.1 μm; The pattern electroplating was performed at a current density of 2A / dm² for 30 minutes to thicken the copper layer to 20μm±2μm.

[0013] In some embodiments, the step of processing the sides of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer includes: A semi-conductive via is pre-formed on the side of the intermediate layer; The semi-conductive via is electroplated to form a thickened conductive layer on the inner wall of the semi-conductive via; The metallization structure is formed by cutting along the axial direction of the semi-conductive hole to expose the conductive layer of the inner wall of the semi-conductive hole.

[0014] In some embodiments, the preset diameter of the semi-conductive via is 100 μm and the spacing between the vias is 150 μm; The electroplating employs a pulse electroplating process, and the process parameters for the electroplating satisfy the following: The peak current density was 8A / dm², the duty cycle was 30%, the time was 45 minutes, and the thickness of the copper plating layer formed was 25μm±3μm. The cutting is performed using a UV laser with a wavelength of 355nm, a pulse width of 20ns, and a cutting speed of 5mm / s. After cutting, the surface is treated with electroless nickel-palladium-gold plating, wherein the nickel layer thickness is 3μm to 5μm, the palladium layer thickness is 0.1μm to 0.2μm, and the gold layer thickness is 0.05μm to 0.1μm.

[0015] Secondly, this application provides an intermediary layer, which is prepared by the method described in the first aspect and includes at least one lateral detection point.

[0016] This application provides a method for preparing probe points in an interposer layer and an interposer layer itself. The method involves forming probe pads within the interposer layer and processing the sides of the interposer layer to expose the lateral surfaces of these pads. Subsequently, a metallization structure is constructed on the exposed lateral surfaces to form lateral probe points, achieving a structural transition of probe points from a two-dimensional surface space to a three-dimensional lateral space. Specifically, this method embeds the probe function as a node in the wiring network, fundamentally avoiding the detour paths and additional vertical interconnect structures required for connecting surface test points in traditional solutions. This allows high-speed signal paths to maintain maximum straightness and simplicity, significantly reducing impedance discontinuities introduced by path extension and increased vias and pad corners. Consequently, reflection noise and insertion loss during signal transmission are significantly suppressed, effectively ensuring the integrity of high-speed signals (such as LPDDR4 / 5). Meanwhile, by completely eliminating the surface test point pads and their leads, this method frees up surface wiring resources, creating conditions for increasing interposer wiring density, optimizing power distribution networks, or integrating passive devices and other functional chips on the surface. Furthermore, the metallized structure of the lateral probes naturally forms a certain shielding cavity, improving electromagnetic interference immunity. In short, this application solves the technical problems of long signal paths, impedance discontinuities, severe reflected noise, and occupied surface wiring space caused by traditional surface test points, achieving the technical effects of improved signal integrity, optimized package size, support for higher-density integration, and enhanced anti-interference capabilities.

[0017] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart of the method for preparing probe points in the intermediary layer provided in an embodiment of this application is shown.

[0020] Figure 2 A flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in an embodiment of this application is shown.

[0021] Figure 3 Another flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in the embodiments of this application is shown.

[0022] Figure 4 This paper shows another flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0025] This application provides a method for preparing probe points in an interposer layer, which is particularly suitable for scenarios requiring high frequency and high signal integrity, such as memory interfaces of LPDDR4, LPDDR5 and later versions, and interposers in 2.5D / 3D advanced packaging structures such as high-bandwidth memory (HBM).

[0026] Figure 1 A flowchart of the method for preparing probe points in the intermediary layer provided in this application embodiment is shown, as follows: Figure 1 As shown, the method for preparing probe points in the intermediary layer provided in this application embodiment includes: Step S100: Form probe pads inside the interposer layer. Optionally, while completing the pattern transfer and etching of the inner layer of the interposer to form high-speed signal lines, probe pads integrally connected to the signal lines are etched into the interposer layer. These pads are completely encapsulated by dielectric material, thus forming an embedded structure. This ensures that the probe points and the original signal path have natural impedance continuity, while the embedded structure effectively avoids the risk of contamination during subsequent processing.

[0027] In one implementation, step S100 is achieved through a patterning process of a printed circuit board (PCB) or integrated circuit packaging substrate.

[0028] Step S200: The sides of the interposer are processed to expose the lateral surfaces of the probe pads. A metallized structure is formed on the exposed lateral surfaces to constitute probe points located on the sides of the interposer. Optionally, by refactoring the probe function to the sides of the interposer, the signal detour problem caused by traditional surface test points is fundamentally avoided. This shortens the high-speed signal path, reduces impedance discontinuities introduced by path bends and excessive interconnect structures, thereby reducing signal reflection noise. At the same time, this structure frees up surface routing resources, creating conditions for increasing routing density or integrating other functional modules.

[0029] This application's embodiments solve the signal integrity degradation and space occupation problems caused by traditional surface test points by embedding and laterally metallizing the probe points, thus improving signal transmission quality, promoting packaging miniaturization, and supporting higher density integration.

[0030] In some embodiments, Figure 2 A flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in an embodiment of this application is shown, as follows: Figure 2 As shown, step S200: processing the side of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located on the side of the interposer, includes: Step S210: Perform stepped lamination on the sides of the interposer to form a stepped region with decreasing dielectric thickness. Optionally, step lamination can be performed on the side region corresponding to the probe pads. This reduces the dielectric layer thickness in that region, forming a precise stepped recess. This stepped region provides a controlled depth reference plane for subsequent laser ablation, ensuring that the laser accurately exposes the inner layer pads without over-cutting or under-cutting.

[0031] In some embodiments, step S210: Step lamination is performed on the sides of the interlayer to form a stepped region with decreasing dielectric thickness, wherein the process parameters for step lamination satisfy: The preheating temperature is 130℃ to 150℃, and the lamination temperature is 180℃ to 200℃; the lamination time is 45 minutes to 60 minutes. The lamination pressure from the initial time of lamination to the preset first time is 2.5 MPa, the lamination pressure from the preset first time to the preset second time is 3.5 MPa, and the lamination pressure from the preset second time to the end time of lamination is 1.5 MPa. The thickness of the dielectric layer in the stepped region decreases by 50 μm, with a tolerance of ±5 μm. The warpage after lamination is no greater than 30 μm / 100 mm. Optionally, the initial low pressure facilitates the expulsion of interlayer air; the intermediate high pressure ensures that the dielectric material is fully filled and achieves a strong interlayer bond; and the final low pressure is used to control stress during the cooling process to minimize warpage deformation. Strictly controlling the warpage within 30 μm / 100 mm ensures the coplanarity of subsequent high-precision laser ablation and detection points.

[0032] Step S220: Laser ablation is performed on the stepped area to form a high aspect ratio microgroove, which exposes the lateral surface of the probe pad.

[0033] In some embodiments, step S220: laser ablation is performed on the stepped region to form a high aspect ratio microgroove, the high aspect ratio microgroove exposing the lateral surface of the probe pad. The laser ablation uses a 355nm picosecond laser, and the laser ablation process parameters meet the following requirements: The pulse frequency is 200kHz to 500kHz; the energy density is 1.5J / cm² to 2.5J / cm²; the number of pulses is 300 to 500; the scanning speed is 200mm / s to 300mm / s; the operation is carried out under nitrogen protection at a flow rate of 15L / min; the aspect ratio of the high aspect ratio microgroove is not less than 5:1, and the depth tolerance is ±5μm. Optionally, a 355nm picosecond laser is used for ablation, utilizing its cold processing characteristics to minimize the heat-affected zone. The laser pulse frequency and scanning speed need to be precisely matched to ensure sufficient pulse overlap, thereby forming a continuous and uniform groove wall. A multi-pulse cumulative ablation strategy (e.g., 300 to 500 ablations) is used instead of a single high-energy ablation to achieve precise depth control and smooth sidewalls. The energy density is set at 1.5 to 2.5J / cm². 2 Within this range, an optimal balance is achieved between effectively removing the medium material and suppressing excessive thermal damage. Continuous nitrogen protection is crucial for blowing away ablation products and preventing tank wall carbonization and oxidation. The final result is a high aspect ratio (≥5:1) microgroove with tight depth tolerance (±5μm).

[0034] Step S230: A seed layer is formed in a high aspect ratio microgroove and electroplated metal is used to fill it to form a metallized structure.

[0035] In some embodiments, in step S230: forming a seed layer in a high aspect ratio microgroove and electroplating metal to fill it to form a metallized structure, the seed layer is formed by atomic layer deposition, and the process parameters of the seed layer satisfy the following: The deposition temperature is 120°C to 150°C; the deposition pressure is 1 Torr to 5 Torr; the deposited seed layer consists of a titanium layer with a thickness of 20 nm ± 2 nm and a copper layer with a thickness of 80 nm ± 5 nm.

[0036] The electroplating metal filling adopts a pulse electroplating process, and the process parameters for electroplating metal filling meet the following requirements: the electrolyte is a copper sulfate system, in which Cu... 2+ The concentration was 50 g / L to 60 g / L; the pulse parameters were: peak current density 8 A / dm² to 10 A / dm², on-time 5 ms, and off-time 10 ms; the annealing conditions were: temperature 250℃, time 30 minutes, and carried out under nitrogen atmosphere.

[0037] Optionally, in this embodiment, an atomic layer deposition (ALD) process is first used to conformally deposit a Ti / Cu seed layer. The step coverage capability of ALD technology ensures that a uniform and continuous conductive film is obtained on the inner wall of the micro-trenches, including the bottom and sidewalls. Subsequently, copper is filled using pulse electroplating. Pulse electroplating achieves preferential deposition at the bottom of the micro-trenches during the on-phase phase and allows the main ions to diffuse from the electrolyte bulk into the tank during the off-phase phase, thereby effectively suppressing void formation and achieving defect-free bottom filling. After filling, annealing is performed to eliminate electroplating stress and reduce contact resistance. A temperature and pressure window of 120°C to 150°C ensures that the precursor has a suitable saturated vapor pressure and surface reaction rate, which is a prerequisite for achieving atomic-level layer-by-layer deposition and obtaining excellent film quality and consistency. The titanium layer mainly serves as an adhesion and barrier layer, while the copper layer serves as a conductive layer. This thickness combination is optimized to provide sufficient conductivity to initiate subsequent electroplating while ensuring reliable adhesion and effective barrier, and to minimize the impact on the initial size of the micro-trenches. In the pulse electroplating process, Cu 2+ Concentration is fundamental to maintaining the stability of the electroplating solution and the deposition rate. Pulse electroplating, through precise control of the on and off times, preferentially deposits copper ions at the bottom of the micro-tank due to the higher current density during the on-time period, and allows copper ions from the bulk electrolyte outside the tank to diffuse into the less abundant tank during the off-time period. The subsequent annealing treatment is carried out under nitrogen protection to eliminate internal stress generated during electroplating, promote the recrystallization and growth of copper grains, thereby reducing resistivity and enhancing the bonding strength between the plating layer and the seed layer.

[0038] In some embodiments, Figure 3 Another flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in this application embodiment is shown, as follows: Figure 3 As shown, step S200: processing the side of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located on the side of the interposer, includes: Step S240: Cut the side of the interposer to form a cross-section that exposes the lateral surfaces of the probe pads. Optionally, embodiments of this application provide another technical path to achieve step S200, by precisely cutting the edge of the laminated interposer to form a cross-section in one step, thereby exposing the end faces of all inner layer probe pads. This method requires the cut cross-section to have high flatness and low roughness to facilitate subsequent metallization processing.

[0039] Step S250: Perform surface metallization treatment on the cross-section to form a metallized structure. Optionally, this surface metallization treatment is performed on the cut cross-section. First, the copper surface is roughened by micro-etching to enhance adhesion; then, an initial, continuous conductive layer is constructed on the entire cross-section (including the dielectric and copper) using a chemical copper plating process; finally, the conductive layer is thickened by pattern electroplating to form a metallized structure with sufficient current carrying capacity and mechanical strength, serving as a lateral detection point.

[0040] The method for preparing probe points in the intermediate layer provided in this embodiment offers a relatively simple process for preparing lateral probe points through overall cutting and cross-sectional metallization, providing more options for application scenarios with different cost and accuracy requirements.

[0041] In some embodiments, in step S240: cutting the side of the interposer to form a cross-section that exposes the lateral surface of the probe pad, the cutting process parameters satisfy the following: The cutting speed is 2000 rpm, and the feed rate is 0.2 mm / s. The surface metallization process to form a metallized structure includes micro-etching, chemical copper plating, and pattern plating. Micro-etching uses a mixed solution of 5 wt% sodium persulfate and 3 wt% sulfuric acid, treated at 40°C for 60 seconds. Chemical copper plating forms a continuous conductive layer with a thickness of 0.5 μm ± 0.1 μm. Pattern plating is performed at a current density of 2 A / dm² for 30 minutes, increasing the copper layer thickness to 20 μm ± 2 μm. Optionally, diamond tools are used for cutting at a low feed rate to obtain a smooth and flat cross-section. Micro-etching cleans and roughens the exposed surfaces of various materials, significantly increasing the specific surface area and thus improving the adhesion between the metal layer and the substrate. Chemical copper plating deposits an initial copper layer on the surface of a non-conductive dielectric material through a chemical reduction reaction, providing a conductive substrate for subsequent electroplating. For pattern electroplating, the copper layer is selectively thickened to about 20μm to ensure that the final lateral detection point has low contact resistance and excellent mechanical durability.

[0042] In some embodiments, Figure 4 This document illustrates another flowchart of step S200 of the method for preparing probe points in the intermediary layer provided in an embodiment of this application, as shown below. Figure 4 As shown, S200: The step of processing the side portion of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located on the side of the interposer includes: Step S260: Pre-form semi-conductive vias on the side of the interposer layer; Optionally, the embodiments of this application provide a new technical path to implement step S200, which is based on an improved PCB via process, and plans a semi-conductive via array on the board edge during the interposer layer design stage. As a mature technology in the field, a conductive prepreg is also required to be pre-embedded in the board edge area before lamination. This material will fill the semi-conductive vias during the lamination process to realize the electrical interconnection between each conductive layer and establish the necessary conductive path for subsequent electroplating processes.

[0043] Step S270: Electroplating is performed on the semi-conductive via to form a thickened conductive layer on the inner wall of the via. Optionally, the semi-conductive via is thickened by electroplating to form a dense copper plating layer on the inner wall. The purpose is to ensure that the exposed metal cross-section after subsequent cutting has sufficient thickness and mechanical strength to withstand repeated contact with the test probe and ensure stable conductivity.

[0044] Step S280: Cut along the axial direction of the semi-conductive via to expose the conductive layer on the inner wall of the via as a metallization structure. Optionally, a high-precision UV laser is used to cut along the precise centerline of the semi-conductive via to ensure that a complete and symmetrical semi-cylindrical metal surface is exposed after cutting, thereby forming an ideal lateral detection point. After cutting, surface treatments such as electroless nickel-palladium-gold plating are usually performed to further enhance solderability, prevent oxidation, and ensure long-term contact reliability.

[0045] This application provides a lateral detection point preparation scheme with high electrical connection reliability and good process robustness by utilizing mature through-hole electroplating and precision cutting technology.

[0046] In some embodiments, step S260: A semi-conductive via is pre-formed on the side of the interposer, wherein the via diameter is 100 μm and the via spacing is 150 μm. Optionally, this via diameter and via spacing design achieves a balance between ensuring mechanical strength and avoiding signal crosstalk, suitable for interposer designs with high-density wiring.

[0047] Step S270: Electroplating is performed on the semi-conductive via to form a thickened conductive layer on the inner wall of the semi-conductive via. The electroplating adopts a pulse electroplating process, and the electroplating process parameters meet the following requirements: With a peak current density of 8 A / dm², a duty cycle of 30%, and a time of 45 minutes, a copper plating layer thickness of 25 μm ± 3 μm was formed. Optionally, pulse plating is beneficial for forming a uniform and dense plating layer within the hole. The above parameters have been optimized to obtain a copper layer of the target thickness within a reasonable working time, while ensuring good conductivity and mechanical properties.

[0048] Step S280: Cutting is performed along the axial direction of the semi-conductive hole to expose the conductive layer of the inner wall of the semi-conductive hole as a metallization structure. The cutting is performed using a UV laser with a wavelength of 355 nm, a pulse width of 20 ns, and a cutting speed of 5 mm / s. After cutting, a nickel-palladium-gold electroless plating surface treatment is performed, where the nickel layer thickness is 3 μm to 5 μm, the palladium layer thickness is 0.1 μm to 0.2 μm, and the gold layer thickness is 0.05 μm to 0.1 μm. Optionally, UV lasers are well-suited for this type of precision cutting task due to their extremely small heat-affected zone and extremely high processing accuracy. The electroless nickel-palladium-gold plating surface treatment after cutting utilizes the nickel layer as the main barrier and wear-resistant layer, the palladium layer to prevent nickel oxidation and provide a good substrate for the gold layer, and the extremely thin gold layer to provide excellent contact surface and oxidation resistance, collectively ensuring the long-term reliability of the probe point.

[0049] This application also provides an intermediary layer. Specifically, the intermediary layer is prepared by the intermediary layer detection point preparation method described in the above embodiments and includes at least one lateral detection point.

[0050] Optionally, the interposer fabricated using the aforementioned method for preparing probe points exhibits a significant performance improvement due to its lateral probe point structure. Compared to traditional surface probe point solutions, the interposer with this structure shortens the high-speed signal path length, reduces the number of vias, lowers impedance discontinuities, increases eye diagram height and width margins, and reduces reflection noise. At the packaging level, the reduced interposer area frees up surface space for integrating power management modules or RF units, resulting in a reduced system-level package thickness. Furthermore, the lateral metallization structure naturally creates a certain electromagnetic shielding cavity, reducing external radiation.

[0051] The intermediate layer provided in this embodiment effectively overcomes the inherent defects of traditional structures by integrating lateral probe points, providing an excellent interconnect solution for fields such as high-performance computing and advanced memory packaging.

[0052] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A method for preparing detection points in an intermediary layer, characterized in that, include: Probe pads are formed inside the interposer layer; The sides of the interposer are processed to expose the lateral surfaces of the probe pads, and a metallization structure is formed on the exposed lateral surfaces to form probe points located on the sides of the interposer.

2. The method for preparing detection points in the intermediate layer as described in claim 1, characterized in that, The step of processing the side portion of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer, includes: The sides of the intermediate layer are laminated in a stepped manner to form a stepped region with decreasing medium thickness; The stepped region is laser-ablated to form a high aspect ratio microgroove, which exposes the lateral surface of the probe pad. A seed layer is formed within the high aspect ratio microgroove and then electroplated with metal to form the metallized structure.

3. The method for preparing detection points in the intermediate layer as described in claim 2, characterized in that, The process parameters for the stepped lamination satisfy: The preheating temperature is 130℃ to 150℃, the lamination temperature is 180℃ to 200℃, and the lamination time is 45 minutes to 60 minutes. The lamination pressure from the initial time of lamination to the preset first time is 2.5 MPa, the lamination pressure from the preset first time to the preset second time is 3.5 MPa, and the lamination pressure from the preset second time to the end time of lamination is 1.5 MPa. The dielectric layer thickness in the stepped region decreases by 50 μm, with a tolerance of ±5 μm. The warpage after lamination is no greater than 30μm / 100mm.

4. The method for preparing detection points in the intermediate layer as described in claim 2, characterized in that, The laser ablation uses a 355nm picosecond laser, and the process parameters for the laser ablation meet the following requirements: The pulse frequency is 200kHz to 500kHz; The energy density is 1.5 J / cm³. 2 Up to 2.5 J / cm 2 ; The number of pulses is 300 to 500. The scanning speed is 200 mm / s to 300 mm / s; The experiment was conducted under nitrogen protection at a flow rate of 15 L / min. The aspect ratio of the high aspect ratio microgroove is not less than 5:1, and the depth tolerance is ±5μm.

5. The method for preparing detection points in the intermediate layer as described in claim 2, characterized in that, In the step of forming a seed layer in the high aspect ratio microgroove and then electroplating it with metal to form the metallized structure, the seed layer is formed by atomic layer deposition, and the process parameters of the seed layer satisfy the following: Deposition temperature was 120°C to 150°C; deposition pressure was 1 Torr to 5 Torr. The deposited seed layer consists of a titanium layer with a thickness of 20 nm ± 2 nm and a copper layer with a thickness of 80 nm ± 5 nm; The electroplated metal filler is produced using a pulse electroplating process, and the process parameters for the electroplated metal filler meet the following requirements: The electrolyte is a copper sulfate system, in which the Cu²⁺ concentration is 50 g / L to 60 g / L; The pulse parameters are: peak current density of 8A / dm² to 10A / dm², on-time of 5ms, and off-time of 10ms. The annealing conditions were: 250℃ for 30 minutes, under a nitrogen atmosphere.

6. The method for preparing detection points in the intermediary layer as described in claim 1, characterized in that, The step of processing the side portion of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer, includes: The side of the interposer layer is cut to form a cross section that exposes the lateral surface of the probe pad; The cross section is subjected to surface metallization treatment to form the metallized structure.

7. The method for preparing detection points in the intermediary layer as described in claim 6, characterized in that, In the step of cutting the side of the interposer layer to form a cross-section that exposes the lateral surface of the probe pad, the cutting process parameters satisfy the following: The cutting speed is 2000 rpm, and the feed rate is 0.2 mm / s; In the step of performing surface metallization treatment on the cross section to form the metallized structure, the surface metallization treatment sequentially includes micro-etching, chemical copper plating, and pattern electroplating. The micro-etching process involves using a mixed solution of 5 wt% sodium persulfate and 3 wt% sulfuric acid, treated at 40°C for 60 seconds. The chemical copper plating forms a continuous conductive layer with a thickness of 0.5 μm ± 0.1 μm; The pattern electroplating was performed at a current density of 2A / dm² for 30 minutes to thicken the copper layer to 20μm±2μm.

8. The method for preparing detection points in the intermediary layer as described in claim 1, characterized in that, The step of processing the side portion of the interposer to expose the lateral surface of the probe pad, and forming a metallization structure on the exposed lateral surface to constitute a probe point located laterally to the interposer, includes: A semi-conductive via is pre-formed on the side of the intermediate layer; The semi-conductive via is electroplated to form a thickened conductive layer on the inner wall of the semi-conductive via; The metallization structure is formed by cutting along the axial direction of the semi-conductive hole to expose the conductive layer of the inner wall of the semi-conductive hole.

9. The method for preparing detection points in the intermediary layer as described in claim 8, characterized in that, The preset semi-conductive via diameter is 100μm and the via spacing is 150μm; The electroplating employs a pulse electroplating process, and the process parameters for the electroplating satisfy the following: The peak current density was 8A / dm², the duty cycle was 30%, the time was 45 minutes, and the thickness of the copper plating layer formed was 25μm±3μm. The cutting is performed using a UV laser with a wavelength of 355nm, a pulse width of 20ns, and a cutting speed of 5mm / s. After cutting, the surface is treated with electroless nickel-palladium-gold plating, wherein the nickel layer thickness is 3μm to 5μm, the palladium layer thickness is 0.1μm to 0.2μm, and the gold layer thickness is 0.05μm to 0.1μm.

10. An intermediary layer, characterized in that, The intermediate layer is prepared by the intermediate layer detection point preparation method as described in any one of claims 1 to 9, and includes at least one lateral detection point.

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