Scheduler to facilitate distributed unit power management in advanced communication networks

Abstract

A scheduler that facilitates distributed unit power management in advanced communication networks is provided herein. In one embodiment, a method includes selecting, by a network device comprising processors, a core processor of a core processor group for power management based on a processing load of the core processor group for a first transmission slot being determined to be below a threshold traffic, thereby obtaining an identified core processor. The selection of the core processor may be based on the identified configuration of the core processor. The method further includes controlling, by the network device, power consumption of the identified core processor during the second transmission slot based on the category assigned to the identified core processor. The network device includes a distributed unit, and control of power consumption is performed in a layer 2 scheduler of the distributed unit.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. nonprovisional patent application No. 18 / 473,599, filed September 25, 2023, entitled “FACILITATING A SCHEDULER FORDISTRIBUTED UNIT POWER MANAGEMENT IN ADVANCED COMMUNICATION NETWORKS”, the entire contents of which are incorporated herein by reference. Background Technology

[0002] Computing devices are ubiquitous. Given the explosive demand for computing networks and the emergence of advanced use cases (e.g., streaming media, gaming, etc.), the amount of data consumed continues to increase with the corresponding increase in server power consumption. Several mechanisms for reducing server power consumption have been used, which work well during long periods of low activity, but cannot be applied to short periods of inactivity and / or other times due to latency and downtime. Therefore, unique challenges related to power management exist given the upcoming fifth-generation (5G), new radio (NR), sixth-generation (6G), or other next-generation network communication standards.

[0003] The above context regarding communication networks is intended to provide only an overview of the current technology and is not intended to be exhaustive. Further contextual descriptions and corresponding benefits of some of the various non-limiting embodiments described herein will become more apparent after reading the following detailed description. Summary of the Invention

[0004] The following is a simplified overview of the disclosed subject matter to provide a basic understanding of some aspects of the various embodiments. This overview is not a comprehensive summary of the various embodiments. It is neither intended to identify key or essential elements of the various embodiments nor to define the scope of the various embodiments. Its sole purpose is to present some concepts of this disclosure in a simplified form as a prelude to the more detailed description that follows.

[0005] In one embodiment, a method is provided that includes selecting a core processor from the core processor group for power management based on a processing load for a first transmission time slot determined to be below a threshold traffic volume by a network device including processors, thereby obtaining an identified core processor. The selection of the core processor may be based on the configuration of the identified core processor. The method also includes controlling the power consumption of the identified core processor during a second transmission time slot by the network device based on the category assigned to the identified core processor. The network device includes distributed units, and the power consumption control is performed in a Layer 2 scheduler of the distributed units.

[0006] In one implementation, power control may include controlling the layer 2 cores of the distributed unit. According to some implementations, power control may include controlling the layer 1 cores of the distributed unit. In another implementation, power control may include controlling a layer 1 protocol for a computing entity separate from the cores of the distributed unit. According to some implementations, power control may include switching the mode of an identified core processor from an active mode to a sleep mode.

[0007] In some implementations, power consumption control may include determining a first state control parameter and a second state control parameter based on the processing load for the transmission slot at the end of scheduling for that transmission slot. Based on the determined first and second state control parameters, the method may include instructing the appropriate thread to perform power-saving actions for the identified core processor.

[0008] According to some implementations, before controlling power consumption, the method may include supplying a corresponding power management profile by a network device via a distributed unit instance of a core processor identified by an O1 interface. This supply may be based on power consumption control using a statistical model. In some implementations, core processor selection may be performed after the first transmission slot. In addition to these implementations, the method may also include the network device determining a frequency allocation for the next scheduling slot after the first transmission slot. The determination of the frequency allocation may be based on information obtained from a data structure including a recommended frequency group based on processing load, and the profile of the identified core processor.

[0009] According to some implementations, the method may include supplying a corresponding power management profile by a network device via a distributed unit instance of the core processor identified by an E2 interface. This supply can be performed before power consumption control and can be based on a machine learning model. Furthermore, the machine learning model can be trained based on historical data representing past power management settings.

[0010] In one example, the category assigned to the identified core processor is determined to be a category within a defined group of categories, which includes: a first category associated with polling level 1 cores, a second category associated with non-polling level 1 cores, a third category associated with polling level 2 cores, and a fourth category associated with non-polling level 2 cores. In another example, the processing load on the core processor group changes intermittently due to sporadic business patterns.

[0011] Another embodiment relates to a system including a processor and a memory storing executable instructions that, when executed by the processor, facilitate the execution of operations. The operations include determining that the processing load of a core processor group for a first transmission time slot is below the defined threshold processing load amount. The operations also include selecting at least one core processor from the core processor group for power management. The selection of the at least one core processor is based on the configuration of the at least one core processor. Furthermore, the operations include controlling the power consumption of the at least one core processor during a second transmission time slot. The power consumption control is based on a category assigned to the at least one core processor.

[0012] In some implementations, power control can be performed in the media access control scheduler of the distributed unit. In some implementations, power control may include controlling the layer 2 core of the distributed unit. According to some implementations, power control may include controlling the layer 1 protocol associated with the layer 1 core of the distributed unit.

[0013] According to some implementations, prior to power consumption control and based on the use of a statistical model for implementing control, the operation may include supplying appropriate power management profiles to distributed unit instances of at least one core processor via an O1 interface. In addition to these implementations, the operation may include determining a frequency allocation for the next scheduling slot based on information obtained from a data structure including a recommended frequency group based on processing load, and the profile of at least one core processor.

[0014] According to some implementations, prior to power consumption control and based on the use of a machine learning model for implementing control, the operation may include supplying appropriate power management profiles to distributed unit instances of at least one core processor via the E2 interface.

[0015] In some implementations, before controlling power consumption, the operation may include determining the category assigned to at least one core processor. Determining the category assigned to at least one core processor may include classifying the category as a polling level 1 core category, a non-polling level 1 core category, a polling level 2 core category, or a non-polling level 2 core category.

[0016] Another embodiment relates to a non-transitory machine-readable medium including executable instructions that facilitate the execution of operations when executed by a processor of a network device. The operations may include selecting a core processor from the core processor group for power management based on the determination that the processing load during a first time slot is below a threshold traffic volume, thereby obtaining an identified core processor. The selection of the core processor may be based on the configuration of the identified core processor. Furthermore, the operations may include controlling the power consumption of the identified core processor during a second time slot via a Layer 2 scheduler of the distributed unit, based on the category assigned to the identified core processor. According to some implementations, controlling power consumption may include controlling Layer 1 protocols associated with the Layer 1 cores of the distributed unit.

[0017] To achieve the foregoing and related objectives, the disclosed subject matter includes one or more of the features described more fully below. Certain illustrative aspects of this subject matter are set forth in detail in the following description and accompanying drawings. However, these aspects merely indicate a few of the various ways in which the principles of this subject matter can be employed. Other aspects, advantages, and novel features of the disclosed subject matter will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. It will also be understood that the detailed description may include additional or alternative embodiments beyond those described in the present invention. Attached Figure Description

[0018] Various non-limiting embodiments are further described with reference to the accompanying drawings, in which:

[0019] Figure 1 An example non-limiting system including a scheduler is illustrated according to one or more embodiments described herein;

[0020] Figure 2 An example of a statistical model configured via the O1 interface according to one or more embodiments described herein is illustrated;

[0021] Figure 3 The figure illustrates a frequency versus power graph for a 12-cell FDD 20MHz distributed cell instance according to one or more embodiments described herein;

[0022] Figure 4 The illustration shows an example non-limiting diagram of an FDD 20MHz cell with 50% physical resource block utilization according to one or more embodiments described herein;

[0023] Figure 5 The illustration shows a flowchart of an example non-limiting computer implementation of a scheduler for distributed cell power management according to one or more embodiments described herein;

[0024] Figure 6 The illustration shows a flowchart of an example non-limiting computer implementation of a method for facilitating power management according to one or more embodiments described herein;

[0025] Figure 7 The illustration shows an example non-limiting system for facilitating power management according to one or more embodiments described herein;

[0026] Figure 8 The illustration shows an example non-limiting computing environment in which one or more embodiments described herein may be facilitated; and

[0027] Figure 9 The illustration depicts an example non-limiting network environment in which one or more embodiments described herein may be facilitated. Detailed Implementation

[0028] One or more embodiments will be described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various embodiments. However, various embodiments may be practiced without these specific details. In other instances, well-known structures and devices are illustrated in block diagram form to facilitate the description of various embodiments.

[0029] Traditional central processing units (CPUs) offer several mechanisms to reduce server power consumption. However, when servers host low-latency applications, the opportunity to effectively utilize such CPUs decreases due to performance constraints. Some mechanisms that can be used to overcome this include the so-called C state and P state.

[0030] Various C states (e.g., power states) include active and idle states. Power states include the C0 state, which is an operational state. The idle state is the state the CPU core enters when it goes into sleep mode due to pending input / output (I / O) operations or application-initiated sleep. Idle or sleep states include the C1 state (e.g., paused state) and the C6 state (e.g., deep sleep state).

[0031] Server products are designed for deployment in 5G-NR Distributed Units (DU / gNB-DU / O-DU) that widely use these processors. The C state can be managed by the kernel's CPUIdle subsystem and can be provided using privileged instructions such as MWAIT / MONITOR / PAUSE. There are also other sub-states, called C0.1 and C0.2, which can be provisioned from user space using instructions such as UMWAIT / UMONITOR / TPAUSE.

[0032] The P state (also known as the performance state) is a core operating point with specific frequencies and voltage levels for instruction execution. Lower P states result in lower operating frequencies and voltages, thus achieving power savings at the cost of execution speed and, consequently, performance. The kernel's CPUFreq subsystem allows frequency scaling via a power regulator triggered by the operating system's (OS) virtual file system. Furthermore, the DPDK rte_power library provides routines for managing core frequencies from within the application.

[0033] DPDK (Data Plane Development Kit) is a set of open-source userspace libraries for low-latency and high-speed packet processing applications. A suite of libraries is available for NIC (Network Interface Card), accelerator, and CPU power management from various sources (e.g., vendors). There are also general-purpose libraries for memory management, synchronization, and telemetry, making it ideal for real-time applications such as DU.

[0034] Low-latency applications (such as DU) can utilize the C1 sleep state because the core can exit sleep and become active in a very short time. However, in the C6 state, the average exit latency from deep sleep is approximately 50-60 μs (microseconds), exceeding 100 μs in the worst case. This is far longer than the OFDM symbol duration, making it impractical for DU. The C1 state does offer some power savings, but not as much as the C6 state. Furthermore, these states are controlled by a power regulator, and applications can only invoke them indirectly via calls to the library function `usleep()`. For some packet processing cores that are always polled, entering the C1 state is impossible, as it would result in packet dropping. The C0.1 and C0.2 sub-states are more suitable for this situation, but this requires strict application control. Therefore, there are multiple control points that need to be coordinated between polling and non-polling threads to optimize the use of C states.

[0035] Frequency scaling in the P state is controlled by the kernel, but user-space applications can also use certain libraries to set the maximum and minimum frequencies. In this case, there are multiple control points because polling kernels can use the DPDK library, but non-polling kernels can only perform frequency changes through the power regulator.

[0036] Other power-saving methods include core reduction, carrier scaling, and shutting down servers during off-peak hours. All of these power-saving methods work well during long periods of low activity, but cannot be applied to short periods of inactivity at other times due to latency and downtime.

[0037] Based on these observations, there is a need for effective and coordinated use of power control to achieve optimal power savings. However, current implementations rely on the platform or infrastructure layer (Kubernetes / VMM) to leverage these processor characteristics, and applications are unaware of these details. Since the platform layer lacks an application-level view, it is not an ideal component for handling this functionality.

[0038] The disclosed embodiments provide enhancements to the Layer 2 (L2) scheduler to include power management of both the L2 and Layer 1 (L1) cores of the DU. The scheduler has a complete view of the processed load and is able to make appropriate decisions to coordinate power control at a finer granularity. It should be noted that, as used herein, L1 and L2 refer to gNB-DU Layer 1 and Layer 2 protocols (e.g., Layer 1 (PHY) and Layer 2 (MAC) protocols).

[0039] Figure 1 An example non-limiting system 100 including a scheduler is illustrated according to one or more embodiments described herein. Figure 1 System 100 depicts a high-level view of a distributed unit (DU) server with two containerized open RAN DUs (O-DUs), illustrated as a first O-DU 102 and a second O-DU 104, although the disclosed embodiments may use more than two O-DUs. Furthermore, although O-DUs are discussed, the disclosed embodiments are not limited to this implementation and other types of decomposition architectures may be utilized.

[0040] Each O-DU (e.g., first O-DU 102, second O-DU 104) includes an instance of an L2 scheduler, which includes its own power management module. Thus, first O-DU 102 includes a first scheduler 106 and a first power management module 108, and second O-DU 104 includes a second scheduler 110 and a second power management module 112. These modules have corresponding interfaces to both L1 and L2 processing entities (software threads or acceleration components). As shown, layer 1 (L1) accelerator 114 interacts with the first power management module 108 and the second power management module 112 in the respective schedulers.

[0041] The scheduler in each O-DU instance (e.g., first scheduler 106, second scheduler 110) controls the power management functions of the cores allocated to the container group (pod). The cores are divided into four groups, and each group has a different processing method based on its processing requirements: (1) polling L1 DPDK cores, (2) non-polling L1 cores pooled for high PHY processing, (3) polling L2 DPDK cores, and (4) non-polling L2 cores pooled for MAC / RLC and F1 processing.

[0042] At the end of scheduling for each time slot, the scheduler determines that power consumption can be controlled based on the load for that time slot and instructs each thread to perform power-saving actions for that core. In one example, power control may be C-state power control and / or P-state control; however, the disclosed embodiments are not limited to this particular example. In addition to this example, for groups 1 and 3, the TSC counter of the UMWAIT / TPAUSE instruction is calculated based on the sleep duration of the C0.1 / C0.2 states. For all groups, scaling core and non-core frequencies are determined based on power control parameters to satisfy the latency and CPU utilization budget for the service profile.

[0043] Based on these instructions, a thread or accelerator component requests the power regulator to take appropriate action on its behalf to enter the appropriate power control state. A general scheduler L1 interface is defined to accommodate any L1 acceleration implementation that can use its own power control based on inputs such as sleep duration and silicon-specific parameters such as clock frequency.

[0044] The power management profile for each O-DU instance is provided via one of the following interfaces: (1) the O1 interface for statistical models and (2) the E2 interface for ML models.

[0045] The profile consists of the minimum and maximum core / non-core frequencies for low, medium, and high loads, derived from the O-DU configuration. An O-DU instance of a medium-band carrier with parameter set 1 and a slot duration of 500 μs has a different configuration compared to a low-band carrier with parameter set 0 and slot duration of 1 ms. The scheduler implementation can use this as a fast-access lookup table to determine the frequency for the next scheduling slot. Figure 2 The table shows an example of a statistical model configured via the O1 interface. Table 200 depicts the corresponding results for two profiles: FDD 20MHz 4×4 MIMO and TDD 100MHz 4×4 MIMO.

[0046] The profile, derived using a machine learning model and configured via the E2 interface, will have more frequencies in the 100MHz range, representing the granularity of one or more power control states. Furthermore, the profile may include silicon-specific parameters for L1 acceleration.

[0047] The following results from a non-restricted experiment on a server with a CPU demonstrate that power savings were achieved through core frequency scaling when traffic was reduced by half. This example only shows core group 2 (non-polling L1 cores). Figure 3The illustration shows an example non-limiting graph 300 of an FDD 20MHz cell with 100% PRB utilization. The horizontal axis represents the core frequency 302 (in Hz), and the vertical axis represents power / performance 304. Figure 3 The graph shows the frequency versus power of a 12-cell FDD 20MHz DU instance. The first line 306 represents CPU power consumption (W), the second line 308 represents average core utilization (%), the third line 310 represents active cores, and the fourth line 312 represents PUSCH latency (μs).

[0048] Figure 4 The illustration shows an example non-limiting graph 400 of an FDD 20MHz cell with 50% PRB utilization. The horizontal axis represents the core frequency 402 (in Hz), and the vertical axis represents power / performance 404. Figure 4 The graph shows a 50% load reduction. The first line 406 represents CPU power consumption (W), the second line 408 represents average core utilization (%), the third line 410 represents active cores, and the fourth line 412 represents PUSCH latency (μs).

[0049] From these figures ( Figure 3 , Figure 4 As can be seen, at 2GHz, the CPU power consumption at full load is approximately 94W, and at half load, it is approximately 89.4W. However, if the CPU frequency is reduced to 1GHz with 50% PRB, the CPU power consumption is approximately 83.6W, about 6.5% lower than the unscaled frequency. When other core groups are considered together with the active power control states(s), the overall power savings are significantly greater.

[0050] The benefits of the embodiments provided herein (including scheduler enhancements) include, but are not limited to, the ability to apply power management for short durations (not just off-peak periods) during intermittent periods of low activity at any time of day. Another benefit is centralized control from within the scheduler, which has a comprehensive view of the real-time activity of all threads of the DU application. Another benefit is that by unifying power management within the scheduler, it can also be combined with other mechanisms, such as symbol blanking and delayed scheduling, to allow cores to enter longer sleep states, thereby activating deeper power control states (e.g., C6 states) for further power savings. Another benefit is that custom processing can be applied to different instances of the DU based on cell configuration and service profiles. An additional benefit is that the disclosed embodiments can be applied to bypass and fully inline L1 acceleration. If L1 operates outside the host processor, it can still benefit from silicon-specific power-saving processes through the proposed scheduler L1 interface.

[0051] Novel aspects of the disclosed embodiments include, but are not limited to, including server power management in the L2 scheduler to better utilize silicon-specific mechanisms for power saving. Other novel aspects include the configuration of power-saving profiles derived using statistical models via the O1 interface and / or power-saving profiles derived using machine learning models via the E2 interface. Another novel aspect includes lookup table-based profile definitions for faster orchestration in time-slot scheduling. Furthermore, another novel aspect includes a common scheduler L1 interface for power control commands.

[0052] Figure 5 A flowchart illustrating an example non-limiting computer implementation of a method 500 for facilitating distributed unit power management according to one or more embodiments described herein is shown. The computer-implemented method 500 and / or other methods discussed herein can be implemented by a network device including a processor. According to another example, the computer-implemented method can be implemented by a system including a processor and memory.

[0053] The processing load of the core processor group for the first transmission time slot is determined to be below a threshold traffic volume. The computer-implemented method 500 begins at 502 with the network device, including the processor, selecting a core processor from the core processor group for power management, thereby obtaining an identified core processor. The selection of the core processor can be based on the configuration of the identified core processor. Due to sporadic traffic patterns, the processing load of the core processor group can change intermittently.

[0054] Furthermore, based on the category of the core processor assigned to the identifier, the computer-implemented method 500 includes, at 504, the network device controlling the power consumption of the core processor during the second transmission time slot. The network device includes distributed units, and power consumption control is performed in the layer 2 scheduler of the distributed units.

[0055] The category assigned to the identified core processor is determined as a category within a defined category group, which includes: a first category associated with the polling layer 1 (PHY) protocol, a second category associated with non-polling level 1 cores, a third category associated with polling level 2 cores, and a fourth category associated with non-polling level 2 cores.

[0056] In some implementations, power control may include controlling the Layer 2 core of the distributed unit. In some implementations, power control may include controlling the Layer 1 core of the distributed unit. According to some implementations, power control may include controlling a Layer 1 protocol for a computational entity separate from the core of the distributed unit. For example, the Layer 1 protocol may be on a hardware block and / or another computational entity separate from the Layer 1 core.

[0057] According to some implementations, controlling power consumption may include changing the frequency of the identified core processor from a first frequency level to a second frequency level. For example, based on a comparison between the current load value and a previous load value, the second frequency level may be lower or higher than the first frequency level. According to some implementations, controlling power consumption may include changing the mode of the identified core processor from an active mode to a sleep mode.

[0058] According to some implementations, power consumption control may include determining a first state control parameter and a second state control parameter based on the processing load within the transmission slot at the end of scheduling for that transmission slot. Furthermore, based on the parameter determination, the corresponding thread is instructed to perform power-saving actions for the identified core processor.

[0059] According to some implementations, prior to power consumption control at 504, the computer-implemented method 500 may include the use of a statistical model based on the implementation control, with the network device supplying a corresponding power management profile via a distributed unit instance of the core processor identified by the O1 interface. In addition to these implementations, the selection of the core processor at 502 is performed after the first transmission time slot, and the computer-implemented method 500 includes the network device determining the frequency allocation for the next scheduling time slot after the first transmission time slot. The frequency allocation is determined based on information obtained from a data structure including a recommended frequency group based on processing load.

[0060] In some implementations, prior to controlling power consumption at point 504, the computer-implemented method 500 may include supplying a corresponding power management profile by a distributed unit instance of the core processor identified by a network device via an E2 interface. The supply of the corresponding power management profile may be based on the use of a machine learning model that implements the control. For example, the machine learning model may be trained based on historical data representing past power management settings.

[0061] Figure 6 A flowchart illustrating an exemplary, non-limiting computer-implemented method 600 for facilitating power management according to one or more embodiments described herein is shown. The computer-implemented method 600 and / or other methods discussed herein can be implemented by a network device including a processor. According to another example, the computer-implemented method can be implemented by a system including a processor and memory.

[0062] At 602, information indicating one or more processing loads of the processor group is obtained. At 604, it is determined whether the processing load of the core processor group for the first transmit slot is below a defined threshold processing load. If it is determined that the processing load is equal to or higher than the defined threshold ("No"), the computer-implemented method 600 returns to 602.

[0063] Alternatively, if at 604 it is determined that the processing load for the first transmission time is below a defined threshold processing load (“Yes”), then at 606, at least one core processor is selected from the core processor group for power management. The selection of at least one core processor may be based on the configuration of at least one core processor. For example, the configuration (or category) of the core processor may include a polling level 1 core category, a non-polling level 1 core category, a polling level 2 core category, or a non-polling level 2 core category.

[0064] Furthermore, at point 608, the power consumption of at least one core processor during the second transmission time slot is controlled. Power consumption control can be based on the category assigned to the at least one core processor.

[0065] Controlling power consumption at point 608 may include changing the frequency of at least one core processor from a first frequency level to a second frequency level. The second frequency level may be lower or higher than the first frequency level depending on the current load, compared to a previous load.

[0066] In some implementations, power control at point 608 may include changing the mode of at least one core processor from an active mode to a sleep mode. According to some implementations, power control may be performed in the media access control scheduler of the distributed unit. In some implementations, power control may include controlling the layer 2 cores of the distributed unit. In additional or alternative implementations, power control may include controlling the layer 1 protocol associated with the layer 1 cores of the distributed unit.

[0067] According to some implementations, the computer-implemented method 600 may include supplying a corresponding power management profile to a distributed unit instance of at least one core processor via an O1 interface before controlling power consumption. For example, the supply of the corresponding power management profile may be based on the use of a statistical model for implementing control. In addition to these implementations, the computer-implemented method 600 may also include determining a frequency allocation for the next scheduling slot based on information obtained from a data structure including a recommended frequency group based on processing load and the profile of at least one core processor.

[0068] Figure 7 An exemplary non-limiting system 700 for facilitating power management according to one or more embodiments described herein is illustrated. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. System 700 may include... Figure 1 System 100 Figure 5 500 computer-implemented methods Figure 6 The computer-implemented method 600 comprises one or more components and / or functions, or vice versa.

[0069] Aspects of the systems (e.g., system 700, etc.), devices, apparatuses, and / or processes explained in this disclosure may constitute multiple machine-executable components embodied within a machine (e.g., embodied in one or more computer-readable media associated with one or more machines). Such multiple components, when executed by one or more machines (e.g., multiple computers, multiple computing devices, multiple virtual machines, etc.), may cause the multiple machines to perform the described operations.

[0070] In various embodiments, system 700 can be any type of component, machine, device, facility, apparatus, and / or instrument, including a processor and / or capable of effective and / or operable communication with wired and / or wireless networks. Components, machines, apparatuses, devices, facilities, and / or instruments that can constitute system 700 may include tablet computing devices, handheld devices, server-level computing machines and / or databases, laptops, notebook computers, desktop computers, mobile phones, smartphones, consumer appliances and / or instruments, industrial and / or commercial equipment, handheld devices, digital assistants, multimedia internet-enabled telephones, multimedia players, etc.

[0071] System 700 may include a network device 702, which includes a category identifier component 704, a processing load determination component 706, a selection component 708, a power management component 710, at least one memory 712, at least one processor 714, at least one data storage unit 716 (or at least one storage device), and a transmitter / receiver component 718. The at least one memory 712 may store computer-executable components and instructions. The at least one processor 714 may facilitate the execution of instructions (e.g., computer-executable components and corresponding instructions) by the category identifier component 704, processing load determination component 706, selection component 708, power management component 710, transmitter / receiver component 718, and / or other system components. As shown, in some embodiments, one or more of the category identifier component 704, processing load determination component 706, selection component 708, power management component 710, at least one memory 712, at least one processor 714, at least one data storage unit 716, and transmitter / receiver component 718 may be electrically connected, communicatively connected, and / or operatively connected to each other to perform one or more functions of system 700.

[0072] The category identifier component 704 can determine the corresponding category associated with the corresponding core processor of the core processor group 720. The category determined by the category identifier component 704 may include, but is not limited to, polling level 1 core category, non-polling level 1 core category, polling level 2 core category, or non-polling level 2 core category.

[0073] The processing load determination component 706 can determine whether the processing load of the core processor group 720 for the first transmission time slot is lower than a defined threshold processing load amount. If the processing load is lower than the defined threshold processing load amount, the selection component 708 can select at least one core processor from the core processor group 720 for power management. The selection made by the selection component 708 can be based on the configuration of the selected core processor.

[0074] Furthermore, the power management component 710 can control the power consumption of the selected core processor during the second transmission time slot. The control performed by the power management component 710 can be based on the category assigned to the selected core processor.

[0075] To control power consumption, the power manager component 710 changes the frequency of the selected core processor. For example, the frequency of the selected core processor can be reduced from a first frequency level to a second frequency level, where the second frequency level is lower than the first frequency level. In another example, the frequency of the selected core processor can be increased from the first frequency level to the second frequency level, where the second frequency level is higher than the first frequency level. According to another example, to control power consumption, the power manager component 710 changes the mode of the selected core processor from an active mode to a sleep mode.

[0076] As shown in the figure, network device 702 may include a machine learning and inference component 722 that can be used to automate one or more of the disclosed aspects based on a trained model 724. The machine learning and inference component 722 may employ an automated learning and inference process (e.g., using an explicitly and / or implicitly trained statistical classifier) ​​by combining one or more aspects described herein to perform inference and / or probability determination and / or statistical determination.

[0077] For example, the machine learning and reasoning component 722 may employ principles of probability and decision theory reasoning. Alternatively or additionally, the machine learning and reasoning component 722 may rely on a predictive model (e.g., model 724) constructed using machine learning and / or automated learning processes. Logic-centered reasoning may also be used alone or in combination with probabilistic methods.

[0078] The machine learning and inference component 722 can infer the configuration of core processors allocated (or should be allocated) to the core processors in the core processor group and / or the category to which the corresponding core processors in the core processor group belong. The machine learning and inference component 722 can also infer which core processor (or more than one core processor) should be selected from the core processor group for power management. Based on this knowledge, the machine learning and inference component 722 can perform inference based on the type and amount of power consumption that should be applied.

[0079] As used herein, the term "inference" generally refers to the process of inferring or reasoning about the state of a system, component, module, environment, and / or device from a set of observations captured through events, reports, data, and / or other forms of communication. For example, inference can be used to identify power management patterns for one or more core processors, including the duration of power management, or to generate probability distributions of states. Inference can be probabilistic. For example, calculating probability distributions over states of interest based on considerations of data and / or events. Inference can also refer to techniques for combining higher-level events from a set of events and / or data. Such inference can lead to the construction of new events and / or actions from a set of observed events and / or stored event data, regardless of whether these events are temporally related or whether the events and / or data come from one or several event and / or data sources. Various classification schemes and / or systems (e.g., support vector machines, neural networks, logic-centric production systems, Bayesian belief networks, fuzzy logic, data fusion engines, etc.) can be employed in conjunction with the execution of automated and / or inference actions related to the disclosed aspects.

[0080] Various aspects (e.g., those related to reducing power consumption) can be implemented using a variety of AI-based approaches. For example, an automatic classifier system and process can be used to enable a process for determining whether a specific configuration of power management should be used.

[0081] A classifier is a function that maps an input attribute vector x = (x1, x2, x3, x4, xn) to a confidence level that the input belongs to a certain class. In other words, f(x) = confidence(class). This classification can employ probabilistic and / or statistical analysis (e.g., considering analytical utility and cost) to provide predictions and / or inferences about one or more actions that should be used to determine the type, amount, and duration of power management to be performed automatically.

[0082] Support Vector Machines (SVMs) are an example of classifiers that can be employed. SVMs operate by finding a hypersurface in the possible input space that attempts to separate triggering criteria from non-triggering events. Intuitively, this makes the classification correct for test data that may be similar to, but not necessarily identical to, the training data. Other directed and undirected model classification methods that provide different independent patterns can be employed (e.g., Naive Bayes, Bayesian networks, decision trees, neural networks, fuzzy logic models, and probabilistic classification models). The classification used in this paper can include statistical regression for developing prioritization models.

[0083] One or more aspects can employ both explicitly trained classifiers (e.g., using general training data) and implicitly trained classifiers (e.g., by acquiring current information, acquiring historical information, receiving external information, etc.). For example, an SVM can be configured through learning or training phases within a classifier builder and feature selection module. Thus, classifiers can be used to automatically learn and perform a variety of functions, including but not limited to determining which processing cores will benefit from power management, the type of power management to be applied, etc., based on predetermined criteria.

[0084] Alternatively or concurrently, implementation schemes (e.g., rules, policies, etc.) can be applied to control and / or regulate the power management described herein. In some implementations, rule-based implementations can automatically and / or dynamically apply power management processes based on predefined criteria. In response, rule-based implementations can automatically interpret and execute power management-related functions by employing (multiple) predefined and / or programmed rules based on any desired criteria.

[0085] According to some implementations, seed data (e.g., a dataset) can be used as initial input to model 724 to facilitate its training. In one example, if seed data is utilized, it can be obtained from one or more historical data associated with power utilization and / or other information indicating the core processing configuration. However, the disclosed embodiments are not limited to this implementation, and seed data is not necessary to facilitate model 724 training. Instead, model 724 can be trained on newly received data (e.g., via a feedback loop).

[0086] Data can be collected (e.g., seed data and / or new data, including feedback data), and optionally tagged with various metadata. For example, data can be tagged with indications of the core processor class used for communication or other data such as the identifier of the corresponding device providing one or more signals, the time of receiving one or more signals, the content of one or more signals, etc.

[0087] At least one memory 712 may be operatively connected to at least one processor 714. At least one memory 712 may store executable instructions and / or computer-executable components, and at least one processor 714 may be used to execute the computer-executable components stored in at least one memory 712.

[0088] For example, at least one memory 712 may store protocols associated with facilitating the automatic power management process as described herein. Furthermore, at least one memory 712 may facilitate actions for controlling communication between network device 702, other network devices, one or more core processors 720, and / or other user equipment, enabling system 700 to employ the stored protocols and / or algorithms to achieve improved overall performance based on the power management described herein.

[0089] It should be understood that the data storage (e.g., memory) components described herein can be volatile or non-volatile memory, or may include both. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) used as an external cache. By way of example, and not limitation, RAM comes in various forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory disclosed in this document is intended to include, but is not limited to, these and other suitable types of memory.

[0090] At least one processor 714 can facilitate the corresponding analysis of information related to promoting power management. At least one processor 714 can be a processor dedicated to analyzing and / or generating received information, a processor of one or more components of the control system 700, and / or a processor that analyzes and generates received information and controls one or more components of the control system 700.

[0091] The transmitter / receiver component 718 can receive information and / or return information indicating power management and related configurations. The transmitter / receiver component 718 can be configured to send data to and / or receive data from, for example, one or more network devices, one or more core processors, and / or one or more user equipments. Through the transmitter / receiver component 718, the system 700 can concurrently send and receive data, send and receive data at different times, or a combination thereof.

[0092] Referring to the flowcharts provided herein will provide a better understanding of the methods that can be implemented based on the disclosed subject matter. While these methods are shown and described as a series of processes and / or blocks for the sake of simplicity, it should be understood and recognized that the disclosed aspects are not limited by the number or order of processes and / or blocks, as some processes and / or blocks may occur substantially simultaneously with other blocks shown and described herein. Furthermore, implementing the disclosed methods does not require all of the processes and / or blocks shown. It should be understood that the functionality associated with the processes and / or blocks can be implemented by software, hardware, combinations thereof, or any other suitable component (e.g., device, system, process, component, etc.). Moreover, it should be further understood that the disclosed methods can be stored on an article of art to facilitate the transport and transfer of such methods to various devices. Those skilled in the art will understand and recognize that these methods can alternatively be represented as a series of interrelated states or events, such as in a state diagram.

[0093] As used herein, for example, the terms "storage device," "first storage device," "second storage device," "storage cluster node," and "storage system," etc. (e.g., node device), can include private or public cloud computing systems for storing data, as well as systems for storing data including and not including virtual infrastructure. The term "I / O request" (or simply "I / O") can refer to a request to read and / or write data.

[0094] As used in this document, the term "cloud" can refer to a cluster of nodes (e.g., a set of web servers) within an object storage system that communicates with and / or is operationally coupled to each other, and hosts a set of applications used to serve user requests. Typically, cloud computing resources can communicate with user devices via most wired and / or wireless communication networks to provide access to services based on cloud-based rather than local storage (e.g., on the user device). A typical cloud computing environment can include multiple layers aggregated together that interact with each other to provide resources to end users.

[0095] Furthermore, the term "storage device" can refer to any non-volatile memory (NVM) device, including hard disk drives (HDDs), flash memory devices (e.g., NAND flash memory devices), and next-generation NVM devices, where any device can be accessed locally and / or remotely (e.g., via a storage attached network (SAN)). In some embodiments, the term "storage device" can also refer to a storage array comprising one or more storage devices. In various embodiments, the term "object" refers to a collection of user data of any size that can be stored across one or more storage devices and accessed using I / O requests.

[0096] Furthermore, a storage cluster may include one or more storage devices. For example, a storage system may include one or more clients communicating with the storage cluster via a network. The network may include various types of communication networks or combinations thereof, including but not limited to networks using protocols such as Ethernet, Internet Small Computer System Interface (iSCSI), Fibre Channel (FC), and / or wireless protocols. Clients may include user applications, application servers, data management tools, and / or testing systems.

[0097] As used herein, “entity,” “client,” “user,” and / or “application” can refer to any system or individual that can send I / O requests to the storage system. For example, an entity can be one or more computers, the Internet, one or more systems, one or more businesses, one or more computers, one or more computer programs, one or more machines, machines, one or more participants, one or more users, one or more customers, one or more people, etc., and will be referred to as one or more entities as the context allows.

[0098] In order to provide context for the various aspects of the disclosed topic, Figure 8 The following discussion is intended to provide a brief, general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized.

[0099] refer to Figure 8 An example environment 810 for implementing various aspects of the above-described topics includes a computer 812. The computer 812 includes a processing unit 814, system memory 816, and a system bus 818. The system bus 818 couples system components, including but not limited to system memory 816, to the processing unit 814. The processing unit 814 can be any of a variety of available processors. Multi-core microprocessors and other multiprocessor architectures can also be used as the processing unit 814.

[0100] The system bus 818 can be any of several types of bus architectures, including memory bus or memory controller, peripheral bus or external bus, and / or local bus using various available bus architectures, including but not limited to 8-bit bus, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Advanced Graphics Port (AGP), PCMCIA Bus, and Small Computer System Interface (SCSI).

[0101] System memory 816 includes volatile memory 820 and non-volatile memory 822. The Basic Input / Output System (BIOS), which contains basic routines for transferring information between components within the computer 812, such as during startup, is stored in non-volatile memory 822. By way of example and not limitation, non-volatile memory 822 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable PROM (EEPROM), or flash memory. Volatile memory 820 includes random access memory (RAM) used as external cache memory. By way of illustration and not limitation, RAM can take many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct Rambus RAM (DRRAM).

[0102] Computer 812 also includes removable / non-removable volatile / non-volatile computer storage media. Figure 8 The illustration shows, for example, a disk storage device 824. Disk storage device 824 includes, but is not limited to, devices such as disk drives, floppy disk drives, magnetic tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Furthermore, disk storage device 824 may include a standalone storage medium or a storage medium combined with other storage media, including, but not limited to, optical disc drives such as optical disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewrite drives (CD-RW drives), or digital versatile disk ROM drives (DVD-ROM). To facilitate connection of disk storage device 824 to system bus 818, removable or non-removable interfaces, such as interface 826, are typically used.

[0103] It should be understood that Figure 8 Software that acts as an intermediary between a user and the basic computer resources described in a suitable operating environment 810 is described. Such software includes an operating system 828. The operating system 828, which may be stored on a disk storage device 824, is used to control and allocate the resources of the computer 812. System application 830 utilizes the management of resources by the operating system 828 through program modules 832 and program data 834 stored in system memory 816 or disk storage device 824. It should be understood that one or more embodiments of this disclosure can be implemented using various operating systems or combinations of operating systems.

[0104] Users input commands or information to computer 812 through input devices 836. Input devices 836 include, but are not limited to, pointing devices such as mice, trackballs, styluses, touchpads, keyboards, microphones, joysticks, gamepads, satellite dishes, scanners, TV tuner cards, digital cameras, digital camcorders, webcams, etc. These and other input devices are connected to processing unit 814 via system bus 818 through interface ports 838. Interface ports 838 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output devices 840 can use some of the ports of the same type as input devices 836. Thus, for example, a USB port can be used to provide input to computer 812 and output information from computer 812 to output device 840. Output adapter 842 is provided to illustrate that, in addition to other output devices 840, some output devices 840 (such as monitors, speakers, and printers) require special adapters. By way of illustration and not limitation, output adapter 842 includes a video and sound card that provides a means of connection between output device 840 and system bus 818. It should be noted that other devices and / or device systems provide both input and output capabilities, such as (multiple) remote computers 844.

[0105] Computer 812 can operate in a networked environment using logical connections to one or more remote computers (such as multiple remote computers 844). The multiple remote computers 844 can be personal computers, servers, routers, network PCs, workstations, microprocessor-based devices, peer-to-peer devices, or other common network nodes, and typically include many or all of the elements described relative to computer 812. For simplicity, only a memory storage device 846 with multiple remote computers 844 is illustrated. The multiple remote computers 844 are logically connected to computer 812 via network interface 848 and then physically connected via communication connection 850. Network interface 848 includes communication networks such as local area networks (LANs) and wide area networks (WANs). LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface, Ethernet / IEEE 802.3, Token Ring / IEEE 802.5, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks and variants such as Integrated Services Digital Network (ISDN), packet-switched networks, and Digital Subscriber Line (DSL).

[0106] (Multiple) communication connections 850 refer to the hardware / software used to connect network interface 848 to system bus 818. Although a communication connection 850 is shown inside computer 812 for clarity, it can also be outside computer 812. For illustrative purposes only, the hardware / software required for the connection to network interface 848 includes internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0107] Figure 9 This is a schematic block diagram of an example computing environment 900 with which the disclosed subject matter can interact. The example computing environment 900 includes one or more clients 902. The clients 902 may be hardware and / or software (e.g., threads, processes, computing devices). The example computing environment 900 also includes one or more servers 904. The servers 904 may also be hardware and / or software (e.g., threads, processes, computing devices). For example, the server 904 may accommodate threads to perform transformations by employing one or more embodiments described herein. One possible communication between the clients 902 and the server 904 may be in the form of data packets suitable for transmission between two or more computer processes. The example computing environment 900 includes a communication framework 906 that can be used to facilitate communication between the clients 902 and the servers 904. The clients 902 are operatively connected to one or more client data repositories 908, which can be used to store information local to the clients 902. Similarly, (multiple) servers 904 are operatively connected to one or more server data repositories 910, which can be used to store information locally on server 904.

[0108] Throughout this specification, the terms "an embodiment" or "embodiment" refer to a specific feature, structure, or characteristic associated with that embodiment being included in at least one embodiment. Therefore, the phrases "in one embodiment," "in one aspect," or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0109] As used in this disclosure, in some embodiments, the terms "component," "system," "interface," "manager," etc., are intended to refer to or include computer-related entities or entities associated with operating means having one or more specific functions, wherein the entity may be hardware, a combination of hardware and software, software or execution software and / or firmware. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, computer-executable instructions, a program, and / or a computer. By way of illustration and not limitation, applications running on a server and the server itself can both be components.

[0110] One or more components may reside in a process and / or execution thread, and components may be located on a single computer and / or distributed across two or more computers. Furthermore, these components may be executed from various computer-readable media on which various data structures are stored. Components may communicate via local and / or remote processes, such as according to signals having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or interacting with other systems via such signals through a network such as the Internet). As another example, a component may be a device having specific functions provided by mechanical parts operated by an electrical or electronic circuit system, operated by a software application or firmware application executed by one or more processors, wherein the processors may be internal or external to the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device providing specific functions through an electronic component without mechanical parts, the electronic component including a processor therein to execute software or firmware that at least partially endows the electronic component with the functions. In one aspect, components may be simulated via virtual machines (e.g., within a cloud computing system). Although the various components have been shown as individual components, it should be understood that, without departing from the example embodiments, multiple components may be implemented as a single component, or a single component may be implemented as multiple components.

[0111] Furthermore, the terms “example” and “exemplary” as used herein mean as an instance or illustration. Any embodiment or design described herein as an “example” or “exemplary” is not necessarily to be construed as superior to other embodiments or designs. Rather, the use of the terms “example” or “exemplary” is intended to present concepts in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or the context clearly indicates, “X uses A or B” is intended to mean any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses both A and B, then in any of the foregoing, “X uses A or B” holds true. In addition, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as “one or more” unless otherwise stated or clearly indicated from the context as a singular form.

[0112] As used herein, when the term “set (group)” is used (e.g., “carrier set (a group of carriers)”, “cell set (a group of cells)”, etc.), it means a non-zero set, “at least one”, or “one or more”. In a similar manner, when the term “subset” is used, it means a non-zero set, “at least one”, or “one or more”.

[0113] Furthermore, various embodiments can be implemented as methods, apparatus, or articles of art using standard programming and / or engineering techniques to produce software, firmware, hardware, or any combination thereof, thereby controlling a computer to implement the disclosed subject matter. The term "article of art" as used herein is intended to encompass any computer program accessible from any computer-readable device, machine-readable device, computer-readable carrier, computer-readable medium, machine-readable medium, or computer-readable (or machine-readable) storage / communication medium. For example, computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other storage technologies, solid-state drives (SSDs) or other solid-state storage technologies, magnetic storage devices such as hard disks; floppy disks; magnetic stripes; optical discs (e.g., optical discs (CDs), digital video discs (DVDs), Blu-ray Disc™ (BD)); smart cards; flash memory devices (e.g., card, stick, key drives); and / or analog storage devices and / or virtual devices of any of the aforementioned computer-readable media. Of course, those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope or spirit of the various embodiments.

[0114] The disclosed embodiments and / or aspects should not be presumed to exclude other disclosed embodiments and / or aspects, nor should they be presumed to exclude elements depicted in the devices and / or structures of one or more exemplary embodiments of this disclosure, unless the context clearly indicates otherwise. The scope of this disclosure is generally intended to include modifications to the depicted embodiments,, where appropriate, additions from other depicted embodiments, where appropriate, interoperability between or between the depicted embodiments, and where appropriate, addition of one or more components from one or more embodiments to another embodiment, or subtraction of one or more components from any depicted embodiment, where appropriate, aggregation of elements (or embodiments) into a single device to achieve aggregated functionality, or where appropriate, distribution of functionality of a single device across multiple devices. Furthermore, combinations, combinations, or modifications of devices or elements (e.g., components) described herein or modified as above, with devices, structures, or subsets thereof not expressly described herein but known in the art, or combinations, combinations, or modifications that are readily apparent to those skilled in the art from the context disclosed herein, are also considered within the scope of this disclosure.

[0115] The above description of the embodiments shown in this invention (including the content described in the abstract) is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. Although specific embodiments and examples have been described herein for illustrative purposes, various modifications are possible within the scope of these embodiments and examples, as will be appreciated by those skilled in the art.

[0116] In this regard, although the subject matter has been described herein in conjunction with various embodiments and corresponding drawings, it should be understood where applicable that other similar embodiments may be used, or modifications and additions may be made to the described embodiments to perform the same, similar, alternative, or substitutional functions of the disclosed subject matter without departing from the disclosure. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but should be interpreted broadly and broadly in accordance with the following appended claims.

Claims

1. A method comprising: The processing load for the first transmission slot based on the core processor group is determined to be below a threshold traffic volume, and the network device including the processor selects a core processor in the core processor group for power management, thereby obtaining an identified core processor, wherein the selection is based on the configuration of the identified core processor. as well as Based on the category of the core processor assigned to the identifier, the network device controls the power consumption of the core processor of the identifier during a second transmission time slot, wherein the network device includes a distributed unit, and wherein the control is performed in a layer 2 scheduler of the distributed unit.

2. The method according to claim 1, wherein the control includes controlling the layer 2 core of the distributed unit.

3. The method according to claim 1, wherein the control includes controlling the core of layer 1 of the distributed unit.

4. The method of claim 1, wherein the control includes a Layer 1 protocol for controlling computing entities separate from the core of the distributed unit.

5. The method of claim 1, wherein the control includes switching the mode of the identified core processor from an active mode to a sleep mode.

6. The method of claim 1, wherein the control comprises: When the scheduling for a transmission time slot ends, a first state control parameter and a second state control parameter are determined based on the processing load for the transmission time slot. as well as Based on the determination, the corresponding thread is instructed to perform a power-saving action on the core processor identified.

7. The method according to claim 1, further comprising: Prior to the control and based on the use of a statistical model for implementing the control, the network device supplies the corresponding power management profile to the distributed unit instance of the identified core processor via the O1 interface.

8. The method of claim 7, wherein the selection is performed after the first transmission time slot, and wherein the method further comprises: Based on information obtained from a data structure including a recommended frequency group based on the processing load, and a profile of the identified core processor, the network device determines the frequency allocation for the next scheduling slot following the first transmission slot.

9. The method according to claim 1, further comprising: Prior to the control and based on the use of a machine learning model used to implement the control, the network device supplies the corresponding power management profile to the distributed unit instance of the identified core processor via an E2 interface, wherein the machine learning model is trained based on historical data representing past power management settings.

10. The method of claim 1, wherein the category assigned to the core processor of the identifier is determined to be a category in a defined group of categories, the defined group of categories comprising: The first category is associated with polling level 1 cores, the second category is associated with non-polling level 1 cores, the third category is associated with polling level 2 cores, and the fourth category is associated with non-polling level 2 cores.

11. A system comprising: processor; as well as The memory stores executable instructions that, when executed by the processor, facilitate the execution of operations, including: Determine that the processing load of the core processor group for the first transmission slot is lower than the defined threshold processing load. At least one core processor is selected from the core processor group for power management, wherein the selection is based on the configuration of the at least one core processor; and Controlling the power consumption of the at least one core processor during a second transmission time slot, wherein the control is based on the category assigned to the at least one core processor.

12. The system of claim 11, wherein the control is performed in the media access control scheduler of the distributed unit.

13. The system of claim 12, wherein the control includes a layer 2 core that controls the distributed unit.

14. The system of claim 12, wherein the control includes controlling a Layer 1 protocol associated with the Layer 1 core of the distributed unit.

15. The system of claim 11, wherein the operation further comprises: Prior to the control and based on the use of a statistical model for implementing the control, a corresponding power management profile is supplied to the distributed unit instance of the at least one core processor via the O1 interface.

16. The system of claim 15, wherein the operation further comprises: Based on information obtained from a data structure including a recommended frequency group based on the processing load, and a profile of the at least one core processor, a frequency allocation for the next scheduling slot is determined.

17. The system of claim 11, wherein the operation further comprises: Prior to the control and based on the use of the machine learning model used to implement the control, a corresponding power management profile is supplied to the distributed unit instance of the at least one core processor via the E2 interface.

18. The system of claim 11, wherein the operation further comprises: Prior to the control, the category to be assigned to the at least one core processor is determined, wherein the determination of the category to be assigned to the at least one core processor includes: determining the category as a polling level 1 core category, a non-polling level 1 core category, a polling level 2 core category, or a non-polling level 2 core category.

19. A non-transitory machine-readable medium comprising executable instructions that, when executed by a processor of a network device, facilitate the execution of operations, said operations including: Based on the processing load of the core processor group during the first transmission time slot being determined to be below a threshold traffic volume, a core processor in the core processor group is selected for power management, thereby obtaining an identified core processor, wherein the selection is based on the configuration of the identified core processor. as well as Based on the category of the core processor assigned to the identifier, the power consumption of the core processor of the identifier during the second time slot is controlled via the layer 2 scheduler of the distributed unit.

20. The non-transitory machine-readable medium of claim 19, wherein the control includes controlling a Layer 1 protocol associated with the Layer 1 core of the distributed unit.

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