Semiconductor device

Abstract

[Problem] To provide a technique that facilitates the achievement of a semiconductor device provided with a via electrode and a wiring layer having a desired wiring structure and good electrical characteristics, and a method for manufacturing such a semiconductor device. [Solution] This semiconductor device comprises a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate arranged in a stacking direction, and the first semiconductor substrate is located on a first surface side of the second semiconductor substrate, and the third semiconductor substrate is located on a second surface side of the second semiconductor substrate. The second semiconductor substrate is provided, on the second surface side, with a wiring layer and a via electrode connected to the wiring layer. The wiring layer has a first wiring connected to a power source, and a second wiring serving as a signal line and having a width partially smaller than a width of the first wiring.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices comprising multiple stacked semiconductor substrates are known (see Patent Documents 1 to 3). Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-59834 Patent Document 2: Japanese Patent Application Publication No. 2009-43779 Patent Document 3: Japanese translation of PCT International Application Publication No. 2020-532095 Summary of the Invention The problem the invention aims to solve

[0004] Single damascene and dual damascene are widely used damascene methods for forming multilayer wiring on insulation layers.

[0005] In the single damascus process, the wiring in the wiring groove and the electrodes (through electrodes) in the via hole are formed through different processes. Therefore, the single damascus process inevitably increases the number of manufacturing steps, and the resistance increases due to the barrier metal between the wiring in the wiring groove and the electrodes in the via hole.

[0006] In comparison, the double damascene process is more advantageous than the single damascene process in that it reduces the number of manufacturing steps because conductive metal is deposited simultaneously in both the wiring trough and the via. Unfortunately, the double damascene process requires the formation of an insulating film after the wiring trough and via are formed. This means the insulating film is deposited not only in the via but also in the wiring trough, and specifically, narrower wiring troughs are completely filled with the insulating film. Therefore, while the double damascene technology can form wiring for wider wiring troughs, it may not be able to properly form wiring for narrower wiring troughs.

[0007] This disclosure provides techniques for realizing semiconductor devices comprising wiring layers and through electrodes having desired wiring structures and good electrical properties, as well as methods for manufacturing such semiconductor devices. Solution to the problem

[0008] One aspect of this disclosure relates to a semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate arranged sequentially in a stacking direction, the first semiconductor substrate being located on a first side of the second semiconductor substrate, and the third semiconductor substrate being located on a second side of the second semiconductor substrate, wherein the second semiconductor substrate includes a wiring layer disposed on the second side and a through electrode connected to the wiring layer, and the wiring layer includes a first wiring connected to a power supply and a second wiring used as a signal line and including a portion with a width smaller than that of the first wiring.

[0009] The second wiring may include a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0010] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position overlapping the pixel portion in the stacking direction.

[0011] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position that does not overlap with the pixel portion in the stacking direction.

[0012] The thickness of the insulating film on the second side can be less than the thickness of the insulating film on the first side.

[0013] The wiring layer may contain two or more wirings stacked in the stacking direction.

[0014] The areas of the first semiconductor substrate and the third semiconductor substrate in the direction perpendicular to the stacking direction can be equal.

[0015] The areas of the first semiconductor substrate and the third semiconductor substrate in a direction perpendicular to the stacking direction may be different from each other.

[0016] Another aspect of this disclosure relates to a semiconductor device comprising: a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate arranged sequentially in a stacking direction, wherein the first semiconductor substrate is located on a first side of the second semiconductor substrate, and the third semiconductor substrate is located on a second side of the second semiconductor substrate, wherein the second semiconductor substrate includes a wiring layer disposed on the second side and a through electrode integrally disposed with wiring disposed in the wiring layer.

[0017] The through electrode may be at least partially surrounded by blocking metal.

[0018] The wiring layer may include: a first wiring connected to a power source; and a second wiring used as a signal line, the second wiring including a portion that is narrower than the width of the first wiring.

[0019] The second wiring may include a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0020] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position overlapping the pixel portion in the stacking direction.

[0021] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position that does not overlap with the pixel portion in the stacking direction.

[0022] The thickness of the insulating film surrounding the through electrode on the second side can be less than the thickness of the insulating film on the first side.

[0023] The wiring layer may include two or more wirings stacked in the stacking direction.

[0024] The areas of the first semiconductor substrate and the third semiconductor substrate in the direction perpendicular to the stacking direction can be equal.

[0025] The areas of the first semiconductor substrate and the third semiconductor substrate in a direction perpendicular to the stacking direction may be different from each other.

[0026] Another aspect of this disclosure relates to a semiconductor device comprising: a first substrate including a first semiconductor layer and a first multilayer wiring layer; a second substrate including a second semiconductor layer, a second multilayer wiring layer, and a wiring layer; and a third substrate including a third semiconductor layer and a third multilayer wiring layer, wherein the first substrate and the second substrate are stacked facing each other, and the second substrate and the third substrate are stacked facing each other, the wiring layer being connected to a through electrode disposed in the semiconductor device, and the wiring layer including a first wiring and a second wiring, the first wiring being connected to a power supply, the second wiring serving as a signal line and including a portion with a width smaller than the width of the first wiring.

[0027] The second wiring may include a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0028] One aspect of this disclosure relates to a semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate arranged sequentially in a stacking direction, the first semiconductor substrate being located on a first side of the second semiconductor substrate, and the third semiconductor substrate being located on a second side of the second semiconductor substrate, wherein the second semiconductor substrate includes a wiring layer disposed on the second side and a through electrode connected to the wiring layer and surrounded by an insulating film, and the wiring layer includes a first wiring connected to a power source and a second wiring used as a signal line, the second wiring including a portion whose width is smaller than both the width of the first wiring and the thickness of the insulating film.

[0029] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position overlapping the pixel portion in the stacking direction.

[0030] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position that does not overlap with the pixel portion in the stacking direction.

[0031] The thickness of the insulating film on the second side can be smaller than the thickness of the insulating film on the first side.

[0032] The wiring layer may include two or more wirings stacked in the stacking direction.

[0033] The areas of the first semiconductor substrate and the third semiconductor substrate in the direction perpendicular to the stacking direction can be equal.

[0034] The areas of the first semiconductor substrate and the third semiconductor substrate in a direction perpendicular to the stacking direction may be different from each other.

[0035] Another aspect of this disclosure relates to a semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate arranged sequentially in a stacking direction, wherein the first semiconductor substrate is located on a first side of the second semiconductor substrate, and the third semiconductor substrate is located on a second side of the second semiconductor substrate, wherein the second semiconductor substrate includes a wiring layer disposed on the second side and a through electrode integrally disposed with wiring disposed in the wiring layer.

[0036] The wiring layer may include a first wiring connected to a power source and a second wiring used as a signal line, the second wiring including a portion whose width is smaller than the width of the first wiring and the thickness of the insulating film surrounding the through electrode.

[0037] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position overlapping the pixel portion in the stacking direction.

[0038] The first semiconductor substrate may include a pixel portion, the pixel portion including a plurality of photoelectric conversion elements, and the through electrode may be disposed at a position that does not overlap with the pixel portion in the stacking direction.

[0039] The thickness of the insulating film surrounding the through electrode on the second side can be less than the thickness of the insulating film on the first side.

[0040] The wiring layer may include two or more wirings stacked in the stacking direction.

[0041] The areas of the first semiconductor substrate and the third semiconductor substrate in the direction perpendicular to the stacking direction can be equal.

[0042] The areas of the first semiconductor substrate and the third semiconductor substrate in a direction perpendicular to the stacking direction may be different from each other.

[0043] Another aspect of this disclosure relates to a method for manufacturing a semiconductor device, the method comprising the steps of: forming an insulating film on a semiconductor substrate; forming an electrode hole on the semiconductor substrate surrounded by the insulating film; and forming a through electrode in the electrode hole.

[0044] After the insulating film is formed on the semiconductor substrate, a wiring layer pattern can be formed on the semiconductor substrate; and conductive members can be formed in the electrode holes and the wiring layer pattern, such that not only the through electrode is embedded in the electrode holes, but the wiring layer is also embedded in the wiring layer pattern.

[0045] The through electrode and the wiring disposed in the wiring layer can be integrally disposed.

[0046] The method for manufacturing a semiconductor device further includes the following steps: connecting another semiconductor substrate having a pixel portion including a plurality of photoelectric conversion elements to a first side of the semiconductor substrate; and connecting yet another semiconductor substrate to a second side of the semiconductor substrate, the second side being opposite to the first side. Attached Figure Description

[0047] Figure 1 This is a cross-sectional view showing a portion of an example of a solid-state camera device. Figure 2 yes Figure 1An enlarged cross-sectional view of the location (part of the intermediate logic substrate) indicated by the reference numeral "II" in the attached figure. Figure 3 It is shown schematically. Figure 2 A cross-sectional view of an example of a manufacturing method for the wiring structure shown (in particular, a through-electrode and redistribution line (RDL) layer). Figure 4 It is shown schematically. Figure 2 A cross-sectional view of an example of a manufacturing method for the wiring structure shown (in particular, through the electrode and the RDL layer). Figure 5 It is shown schematically. Figure 2 A cross-sectional view of an example of a manufacturing method for the wiring structure shown (in particular, through the electrode and the RDL layer). Figure 6 It is a schematic plan view showing the wiring of the electrode holes and wiring layer pattern, and shows the wiring layer pattern including wide wiring. Figure 7 It is a schematic plan view of the wiring, showing the electrode holes and wiring layer pattern, and also showing the wiring layer pattern including narrow wiring. Figure 8 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a single damask process. Figure 9 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a single damask process. Figure 10 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a single damask process. Figure 11 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a single damask process. Figure 12 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a double damask process. Figure 13 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a double damask process. Figure 14 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a double damask process. Figure 15 This is a schematic cross-sectional view illustrating an example of a method for fabricating through-electrodes and RDL layers using a double damask process. Figure 16 This is a cross-sectional view showing a portion of another example of a solid-state camera device. Figure 17 This is a cross-sectional view showing a portion of yet another example of a solid-state camera device. Figure 18 This is a cross-sectional view showing a portion of yet another example of a solid-state camera device. Figure 19 This is a cross-sectional view showing a portion of yet another example of a solid-state camera device. Figure 20A This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 20B It shows the view from above. Figure 20A A diagram showing an example of the planar shape of the insulating film. Figure 20C It shows the view from above. Figure 20A A diagram showing an example of the planar shape of the insulating film. Figure 20D It shows the view from above. Figure 20A A diagram showing an example of the planar shape of the insulating film. Figure 21 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 22 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 23 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 24 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 25 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 26 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 27 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 28 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 29 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 30 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 31 This is a cross-sectional view illustrating an example of a method for manufacturing a solid-state imaging device. Figure 32A It shows the relationship with Figure 20A Cross-sectional view of a modified example of the insulating film shown. Figure 32B It shows the view from above. Figure 32A A diagram showing an example of the planar shape of the insulating film. Figure 32C It shows the view from above. Figure 32A A diagram showing an example of the planar shape of the insulating film. Figure 32D It shows the view from above. Figure 32A A diagram showing an example of the planar shape of the insulating film. Detailed Implementation

[0048] The following description, with reference to the accompanying drawings, illustrates an implementation scheme that utilizes the technology disclosed herein.

[0049] Although the application of the technology disclosed herein in a solid-state imaging device will be described below, the technology described below can also be applied to other solid-state imaging devices and semiconductor devices (e.g., photodetectors) besides the solid-state imaging device described herein.

[0050] [Example of the first structure] Figure 1 This is a cross-sectional view showing a portion of an example of a solid-state camera device 10.

[0051] The solid-state imaging device 10 of this embodiment is a three-layer stacked semiconductor device comprising a CMOS image sensor (CIS) substrate (first semiconductor substrate) 11, an intermediate logic substrate (second semiconductor substrate) 12 and a bottom logic substrate (third semiconductor substrate) 13 arranged in the stacking direction Ds. Figure 1 The solid-state imaging device 10 shown uses a pixel section 17 (specifically, a photoelectric conversion element 19) to image from the back side of the CIS substrate 11. Figure 1 A back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor that converts light incident from the top side of the sensor into photoelectric signals.

[0052] CIS substrate 11 is located on the front side (first side) of intermediate logic substrate 12. Figure 1 The upper side), and the bottom logic substrate 13 is located on the back side of the middle logic substrate 12, the back side being the second side opposite to the first side (front side). Figure 1 (the lower side). Figure 1 The dashed line AA represents the bonding surface between the CIS substrate 11 and the intermediate logic substrate 12, and the dashed line BB represents the bonding surface between the intermediate logic substrate 12 and the bottom logic substrate 13.

[0053] These semiconductor substrates 11, 12, and 13 each include: a surface adjacent to a corresponding one of semiconductor layers 31, 32, and 33, also referred to as a back surface (back side surface); and a surface adjacent to a corresponding one of multilayer wiring layers 21, 22, and 23, also referred to as a front surface (front side surface). Furthermore, these semiconductor substrates 11, 12, and 13 each have a side containing the front surface, also referred to as a front side (front side); and a side containing the back surface, also referred to as a back side (back side).

[0054] The CIS substrate 11 includes: a photoelectric conversion element 19 that receives light (observation light) from the target being observed; and transistors, etc., that read out corresponding electrical signals (pixel signals) from the photoelectric conversion element 19. Various types of signal processing, such as analog-to-digital conversion (AD conversion), are performed on the pixel signals using a signal processing circuit.

[0055] The intermediate logic substrate 12 and the bottom logic substrate 13 are each provided with circuits for performing various types of signal processing related to the operation of the solid-state imaging device 10. While the intermediate logic substrate 12 and the bottom logic substrate 13 are each provided with logic circuits, they may also be provided with any other circuits. For example, a memory substrate including memory circuitry may be provided instead of the bottom logic substrate 13, which includes logic circuitry, as a third semiconductor substrate. The intermediate logic substrate 12 may also include a portion of a readout circuit, and each of the intermediate logic substrate 12 and the bottom logic substrate 13 may include memory circuitry.

[0056] The CIS substrate 11 (first substrate) includes a semiconductor layer 31 (first semiconductor layer) and a multilayer wiring layer 21 (first multilayer wiring layer) disposed on the semiconductor layer 31. Similarly, the intermediate logic substrate 12 and the bottom logic substrate 13 (second substrate and third substrate) also include semiconductor layers 32 and 33 (second semiconductor layer and third semiconductor layer) and multilayer wiring layers 22 and 23 (second multilayer wiring layer and third multilayer wiring layer) disposed on the respective semiconductor layers 32 and 33. The CIS substrate 11, the intermediate logic substrate 12, and the bottom logic substrate 13 have functional components (e.g., signal processing circuits such as transistors) that transmit and receive signals through one of the multilayer wiring layers 21, 22, and 23 respectively disposed on their front sides.

[0057] The semiconductor layers 31, 32, and 33, as well as the multilayer wiring layers 21, 22, and 23 disposed in the solid-state imaging device 10, can be made of any material. Typically, the semiconductor layers 31, 32, and 33 are made of silicon substrates (Si substrates), and the multilayer wiring layer 21 is made of copper wiring (Cu wiring), but the semiconductor layers 31, 32, and 33, as well as the multilayer wiring layers 21, 22, and 23, can be made of other materials.

[0058] The CIS substrate 11 includes: a pixel portion 17, which includes a plurality of photoelectric conversion elements (photodiodes) 19 for outputting image data (pixel signals); and a non-pixel portion 18. The pixel portion 17 includes a substrate extending in a direction perpendicular to the stacking direction Ds (e.g., Figure 1 Multiple pixels arranged in two dimensions on the left-right and depth directions of the paper.

[0059] The semiconductor layer 31 of the CIS substrate 11 includes a plurality of pixel isolation layers 20, each pixel isolation layer 20 having a deep trench isolation (DTI) structure separating the pixels, and each pixel isolation layer 20 being located on the boundary between the corresponding pixels. In addition, a color filter layer 15 and a microlens array 16 are mounted as photoelectric conversion elements 19 covering each pixel.

[0060] The semiconductor layer 31 of the CIS substrate 11 includes a surface on which an insulating film is stacked, and a multilayer wiring layer 21 is formed inside the insulating film. The multilayer wiring layer 21 includes signal line wiring for transmitting various signals (e.g., pixel signals and drive signals for driving transistors of drive circuits), power supply wiring connected to a power source, ground wiring (GND wiring) connected to ground, electrodes, and contacts, etc.

[0061] The multiple wiring layers disposed in the multilayer wiring layer 21 can actually be formed by repeatedly forming interlayer insulating films and forming wiring layers. These multiple interlayer insulating films are also simply referred to as insulating films, and the multiple wiring layers are also referred to as multilayer wiring layer 21. The entire power transmission line disposed in the multilayer wiring layer 21 (including signal wiring, power wiring, GND wiring, electrodes and contacts) can also be simply referred to as wiring.

[0062] Similarly, the semiconductor layer 32 of the intermediate logic substrate 12 is stacked with an insulating film having multiple wiring layers 22, and the semiconductor layer 33 of the bottom logic substrate 13 is stacked with an insulating film having multiple wiring layers 23. For example, the logic circuits provided in the intermediate logic substrate 12 and the bottom logic substrate 13 can perform various types of signal processing related to the operation of the solid-state imaging device 10, so as to control not only the driving signals for driving the pixel portion of the CIS substrate 11, but also the signal exchange with the outside.

[0063] Figure 2 It shows Figure 1 An enlarged cross-sectional view of the location indicated by reference numeral "II" in the attached drawing (a portion of the intermediate logic substrate 12). As shown... Figure 1 As shown, Figure 2 The through electrode 28 shown is disposed in the stacking direction Ds at a position that does not overlap with the pixel portion 17 (i.e., at a position that overlaps with the non-pixel portion 18).

[0064] The intermediate logic substrate 12 includes a redistribution line (RDL) layer 25 and through electrodes (e.g., through silicon vias (TSVs)) 28 disposed on its back side. The through electrodes 28 are integrally connected to the wiring in the RDL layer 25 and extend along the stacking direction Ds while being surrounded by an insulating film 40.

[0065] RDL layer 25 includes fine wiring (e.g., fine wiring with a width of 10 to 100 nm) and coarse wiring (e.g., coarse wiring with a width of 1 μm or more). For example, power wiring connected to a power source (first wiring) is classified as “coarse wiring” as mentioned herein, and signal wiring used as signal lines (second wiring) is classified as “fine wiring” as mentioned herein. In particular, the fine wiring in this embodiment includes portions that are narrower than the width of the power wiring (coarse wiring) and narrower than the film thickness of the insulating film 40.

[0066] The through electrode 28 is typically made of copper (Cu), but can also be made of any other metal (conductive component). The through electrode 28 extends through the semiconductor layer 32, to one end ( Figure 2 The wiring is connected to the RDL layer 25 in the interlayer insulating film 35 at the upper end of the middle layer (and at the other end) and the wiring is connected to the RDL layer 25 in the interlayer insulating film 35 at the other end ( Figure 2 The wiring 29 is connected to the multilayer wiring layer 22 in the interlayer insulating film 36 at the lower end of the layer.

[0067] Figure 2 The through electrode 28 shown is directly connected to the RDL layer 25 without passing through the blocking metal 39, and the through electrode 28 and the RDL layer 25 have a continuous structure that is integrally formed without seams between the through electrode 28 and the RDL layer 25.

[0068] Meanwhile, the through electrode 28 is connected to the wiring 29 of the multilayer wiring layer 22 via the barrier metal 39. The barrier metal 39 is configured to surround at least a portion of the through electrode 28 to prevent conductive components (e.g., conductive metals such as copper) from diffusing into the semiconductor layer 32. Figure 2 An example is shown in which a barrier metal 39 surrounding the through electrode 28 is disposed between the through electrode 28 and the semiconductor layer 32, and the barrier metal 39 is also disposed between the wiring of the RDL layer 25 and the semiconductor layer 32. Figure 2 The example shown illustrates a barrier metal 39 that is disposed not only on the side of the through electrode 28, but also at the bottom (i.e., between the through electrode 28 and the wiring 29 of the multilayer wiring layer 22), and is configured to surround the wiring 29 in the interlayer insulating film 36.

[0069] According to the above Figure 2The wiring structure shown has a through electrode 28 and an RDL layer 25 electrically connected without any obstructing metal 39 between them. Furthermore, the RDL layer 25 contains a mixture of fine and thick wiring. Therefore, a good electrical connection can be established between the through electrode 28 and the RDL layer 25 without being affected by the increased resistance caused by the obstructing metal 39.

[0070] Figures 3 to 5 These are schematic illustrations. Figure 2 A cross-sectional view of an example of a manufacturing method for the wiring structure shown (in particular, through electrode 28 and RDL layer 25). Figure 6 and Figure 7 The electrode hole 41 and wiring are schematically shown (see reference). Figure 4 (A floor plan of ). Figure 6 A wiring layer pattern 42 containing coarse wiring is shown, and Figure 7 A wiring layer pattern 42 containing fine wiring is shown.

[0071] In order to create Figure 2 The wiring structure shown in the figure has an insulating film 40 surrounding the through electrode 28 pre-formed (embedded) in the semiconductor layer 32 before the wiring layer pattern 42 and electrode via 41 are formed in the semiconductor layer 32. This is effective (see reference). Figure 3 That is, before forming the wiring layer pattern 42 for embedding the RDL layer 25 in the semiconductor layer 32, and before forming the electrode hole 41 for embedding the through electrode 28 in the semiconductor layer 32, an insulating film 40 is formed in the semiconductor film 32.

[0072] Then, as Figure 4 As shown, an electrode hole 41 is formed at a portion of the semiconductor layer 32, including the insulating film 40, where a through electrode 28 is planned to be embedded. The electrode hole 41 formed in this way is laterally defined by the insulating film 40 and connected to the wiring layer pattern 42.

[0073] When forming the electrode aperture 41, a portion of the insulating film 40 can be removed. The insulating film 40 after removing this portion in this way is not limited in terms of film thickness. For example, a portion of the insulating film 40 can be removed so that an insulating film 40 with a film thickness of about 300 nm remains in the electrode aperture 41.

[0074] The thickness distribution of the insulating film 40 in the stacking direction Ds is unrestricted, and the insulating film 40 can have a uniform film thickness in the stacking direction Ds, or it can have a continuously varying film thickness in the stacking direction Ds. For example, when using an opening for the electrode hole 41 ( Figure 4In cases where a portion of the insulating film 40 is removed using a method that allows for smoother removal of the insulating film 40 (with the upper opening), the film thickness of the insulating film 40 can decrease towards the opening of the electrode hole 41. In this case, the thickness of the insulating film 40 decreases from the front side (first side): Figure 4 (Lower side) facing the back side (second side: Figure 4 (The upper side) decreases.

[0075] Then, as Figure 5 As shown, the deposition of barrier metal 39 and conductive components are performed sequentially on electrode hole 41 and wiring layer pattern 42 to embed through electrode 28 and RDL layer 25.

[0076] The above Figures 3 to 5 A manufacturing method is shown in which conductive components are simultaneously deposited on electrode holes 41 and wiring layer patterns 42. Therefore, this manufacturing method can also be said to be based on a double damask process, which has the advantage of reducing the number of manufacturing steps compared to a single damask process.

[0077] In addition, before forming the wiring layer pattern 42, the following steps are performed: Figures 3 to 5 The manufacturing method shown forms an insulating film 40 surrounding the through electrode 28, thus eliminating the need for a step of forming the insulating film 40 after the wiring layer pattern 42 is formed. Therefore, the wiring layer pattern 42 is not unintentionally embedded by the insulating film before the conductive components are embedded in it, thereby enabling the conductive components to be properly embedded in the coarse wiring of the wiring layer pattern 42 (see reference). Figure 6 ) and fine wiring (refer to Figure 7 Therefore, it is possible to appropriately form an RDL layer 25 that includes the required fine wiring and the required coarse wiring.

[0078] Figures 8 to 11 These are cross-sectional views schematically illustrating an example of a method for fabricating through-electrode 28 and RDL layer 25 using a single damask process.

[0079] When the through electrode 28 and the RDL layer 25 are formed by a single damask process, the manufacturing process of forming the through electrode 28 is performed, and then the manufacturing process of forming the RDL layer 25 is performed.

[0080] That is, such as Figure 8 As shown, electrode holes 41 are first formed in the semiconductor layer 32, and then an insulating film 40 is deposited and formed. Typically, the insulating film 40 is more likely to be deposited closer to the opening of the electrode holes 41. Figure 8 The insulating film 40 has a greater thickness closer to the opening of the electrode hole 41 (at the upper end of the opening). In this case, the thickness of the insulating film 40 increases from the front side ( Figure 8 (lower side) facing the back side ( Figure 8(The upper side of the middle) increases. Figure 8 An example is shown where a portion of the barrier metal 39 of the interlayer insulating film 36 surrounding the wiring 29 of the multilayer wiring layer 22 is exposed through the electrode hole 41.

[0081] Then, as Figure 9 As shown, a blocking metal 39 is formed in the electrode hole 41, and a conductive member is embedded to form a through electrode 28.

[0082] Then, an interlayer insulating film 35 is formed on the semiconductor layer 32. Figure 10 After forming a wiring layer pattern on the interlayer insulating film 35, the barrier metal 39 and conductive components are embedded in the wiring layer pattern to form the RDL layer 25. Figure 11 ).

[0083] As described above, since the through electrode 28 and the RDL layer 25 are formed separately, the single damask process has the disadvantage of having more manufacturing steps than the double damask process. Furthermore, because there is a barrier metal 39 between the through electrode 28 and the RDL layer 25, the single damask process also has the disadvantage that the increased resistance caused by the barrier metal 39 affects the electrical connection between the through electrode 28 and the RDL layer 25.

[0084] Furthermore, the single damask process allows the insulating film 40 surrounding the through electrode 28 to be formed before the wiring layer pattern of the RDL layer 25 is formed. Therefore, the single damask process enables the conductive components to be appropriately embedded in the coarse wiring of the wiring layer pattern 42 (see reference). Figure 6 ) and fine wiring (refer to Figure 7 In ), and can form an RDL layer 25 including the required fine wiring and coarse wiring.

[0085] Figures 12 to 15 These are cross-sectional views schematically illustrating an example of a method for fabricating through-electrode 28 and RDL layer 25 using a double damask process.

[0086] When forming the through electrode 28 and the RDL layer 25 using a double damask process, conductive components constituting the through electrode 28 and the RDL layer 25 are simultaneously embedded.

[0087] That is, firstly, a wiring layer pattern 42 is formed on the interlayer insulating film 35 on the semiconductor layer 32 (refer to...). Figure 12 ), and electrode holes 41 are formed in semiconductor layer 32 (see reference) Figure 13 The electrode holes 41 and wiring layer pattern 42 formed in this way are connected to each other. The wiring layer pattern 42 includes fine grooves and coarse grooves corresponding to the wiring that constitutes the RDL layer 25 to be formed.

[0088] Then, an insulating film 40 is deposited and formed (refer to...) Figure 14 Therefore, the insulating film 40 can be deposited on the defined area surface of the electrode aperture 41. However, the insulating film 40 can also be deposited on the wiring layer pattern 42. Therefore, the finer portions of the wiring layer pattern 42 will be completely filled by the insulating film 40. For example, when an insulating film 40 with a thickness of approximately 300 nm is deposited in the electrode aperture 41, portions of the wiring layer pattern 42 with a width of less than 600 nm may be filled by the insulating film.

[0089] Therefore, when the conductive component is then embedded in the electrode hole 41 and the wiring layer pattern 42 (see reference) Figure 15 The through electrode 28 and the RDL layer 25 can be integrally formed. However, there is a concern that only a portion of the wiring in the RDL layer 25 is formed. That is, the conductive component is embedded in the coarse groove portion of the wiring layer pattern 42 (see reference). Figure 6 However, due to the fine groove portion (see reference) Figure 7 The insulating film has already been embedded in the groove, so the conductive components are not embedded in the fine groove. Therefore, it is impossible to form the RDL layer 25 with the required wiring structure.

[0090] As mentioned above, Figures 12 to 15 The double damask process shown can form coarse wiring in RDL layer 25, but it cannot form fine wiring. For example, although wiring with a width of more than 1 μm can be formed in RDL layer 25 using the double damask process, it is difficult or virtually impossible to form wiring with a width of less than 1 μm using the double damask process.

[0091] Furthermore, by simultaneously embedding conductive components in the electrode hole 41 and the wiring layer pattern 42, the double damascene process integrally forms the through electrode 28 and the RDL layer 25, eliminating the obstructing metal 39 between the through electrode 28 and the RDL layer 25. Therefore, the advantage of the double damascene process is that the electrical connection between the through electrode 28 and the RDL layer 25 is not affected by the increased resistance caused by the obstructing metal 39.

[0092] Next, another structural example of the solid-state camera device 10 will be described.

[0093] [Example of the second structure] Figure 16 This is a cross-sectional view showing a portion of another example of the solid-state camera device 10. Figure 16 The solid-state imaging device 10 shown includes the above-mentioned... Figure 1 The solid-state imaging device 10 shown in the first structural example has the same or corresponding elements, which are indicated by the same reference numerals as in the first structural example, and their details will not be described further.

[0094] RDL layer 25 may include two or more wirings stacked in the stacking direction Ds (multilayer wiring). Figure 16 The example shown illustrates an RDL layer 25 disposed in an intermediate logic substrate 12 and including three layers of wiring arranged side-by-side in the stacking direction Ds.

[0095] [Example of a third structure] Figure 17 This is a cross-sectional view showing a portion of yet another example of the solid-state imaging device 10. Figure 17 The solid-state imaging device 10 shown includes the above-mentioned... Figure 1 and Figure 16 The solid-state imaging devices 10 shown in the figures contain the same or corresponding elements, which are composed of the same elements as those in the figures. Figure 1 and Figure 16 The same reference numerals are used in the accompanying drawings, and their details will not be explained further.

[0096] The solid-state imaging device 10 may include four or more semiconductor substrates stacked in the stacking direction Ds. Figure 17 The solid-state imaging device shown is a four-layer stacked semiconductor device with a first intermediate substrate 12A and a second intermediate substrate 12B disposed between a CIS substrate 11 and a bottom logic substrate 13.

[0097] The first intermediate substrate 12A is connected to the CIS substrate 11 on the front side and to the second intermediate substrate 12B on the back side. The second intermediate substrate 12B is connected to the first intermediate substrate 12A on the front side and to the bottom logic substrate 13 on the back side.

[0098] The first intermediate substrate 12A includes: a multilayer wiring layer 22A formed in an insulating film on a semiconductor layer 32A; a through electrode 28A extending through the semiconductor layer 32A; and an RDL layer 25A connected to the through electrode 28A on the side opposite to the multilayer wiring layer 22A. Similarly, the second intermediate substrate 12B includes: a multilayer wiring layer 22B formed in an insulating film on a semiconductor layer 32B; a through electrode 28B extending through the semiconductor layer 32B; and an RDL layer 25B connected to the through electrode 28B on the side opposite to the multilayer wiring layer 22B.

[0099] Through electrodes 28A and 28B and RDL layers 25A and 25B respectively disposed on intermediate substrates 12A and 12B have through electrodes 28 and RDL layers 25 (see reference) of the intermediate logic substrate 12. Figure 2 Similar constructions (e.g., etc.).

[0100] exist Figure 17 In the example shown, the RDL layers 25A and 25B of the intermediate substrates 12A and 12B have the same characteristics as... Figure 1The example shown is a similar single-layer wiring construction, but it can also have similar characteristics. Figure 16 The example shown is a multilayer wiring construction (e.g., a three-layer wiring construction).

[0101] Furthermore, each of the first intermediate substrate 12A and the second intermediate substrate 12B may be configured as a logic substrate containing logic circuits, or may be configured as a semiconductor substrate containing any other functional circuits (e.g., a memory substrate containing memory circuits).

[0102] [Example of the fourth structure] Figure 18 This is a cross-sectional view showing a portion of yet another example of the solid-state imaging device 10. Figure 18 The solid-state imaging device 10 shown includes the above-mentioned... Figure 1 , Figure 16 and Figure 17 The solid-state imaging devices 10 shown in the figures contain the same or corresponding elements, which are composed of the same elements as those in the figures. Figure 1 , Figure 16 and Figure 17 The same reference numerals are used in the accompanying drawings, and their details will not be explained further.

[0103] Although the first to third structural examples described above show that the CIS substrate 11 and the bottom logic substrate 13 connected by the intermediate logic substrate 12 have equal areas in the substrate extension direction (the direction perpendicular to the stacking direction Ds), the areas of the substrates in the substrate extension direction may be different. Here, each of the semiconductor substrates 11, 12, 13 and 14 has an area in the substrate extension direction (hereinafter also referred to as "substrate extension direction area"), which is equal to the projected area of ​​the semiconductor substrates 11, 12, 13 and 14 when viewed along the stacking direction Ds.

[0104] Figure 18 The example shown illustrates that the bottom logic substrate 13 includes a plurality of bottom logic substrates 13A and 13B arranged side-by-side in the substrate extension direction. Each of the plurality of bottom logic substrates 13A and 13B has a smaller substrate extension direction area than the CIS substrate 11, and on the front side ( Figure 18 The upper side of the middle logic board 12 is connected to the middle logic board 12, and the back side ( Figure 18 The lower side of the middle is connected to the support substrate 14.

[0105] although Figure 18 Two bottom logic substrates 13A and 13B are shown, but the boundary between these bottom logic substrates 13A and 13B is not shown.

[0106] With the aforementioned bottom logic substrate 13 (refer to) Figure 1 (etc.) similar, Figure 18The bottom logic substrates 13A and 13B shown include multilayer wiring layers 23A and 23B, respectively.

[0107] Furthermore, despite Figure 18 The RDL layer 25 of the intermediate logic substrate 12 shown has a relationship with Figure 16 The example shown is similar to a multilayer wiring configuration (three-layer wiring configuration), but RDL layer 25 can also have the same... Figure 1 The example shown is a single-layer wiring configuration.

[0108] [Example of the fifth structure] Figure 19 This is a cross-sectional view showing a portion of yet another example of the solid-state imaging device 10. Figure 19 The solid-state imaging device 10 shown includes the above-mentioned... Figure 1 and Figures 16 to 18 The solid-state imaging device 10 shown in the figures contains the same or corresponding elements, which are composed of the same elements as those in the figures. Figure 1 and Figures 16 to 18 The same reference numerals are used in the accompanying drawings, and their details will not be explained further.

[0109] As mentioned above Figure 1 and Figures 16 to 18 As shown, the through electrode 28 can be disposed at a position in the stacking direction Ds that does not overlap with the pixel portion 17, or it can be disposed at a position in the stacking direction Ds that overlaps with the pixel portion 17. Furthermore, the above-mentioned... Figure 1 and Figures 16 to 18 Only the through-electrode 28, located at a position that does not overlap with the pixel portion 17, is shown. However, Figure 1 and Figures 16 to 18 The solid-state imaging device 10 may actually include a through electrode 28 disposed at a position that overlaps with the pixel portion 17 in the stacking direction Ds.

[0110] Figure 19 The through electrode 28A, which is disposed at a position that does not overlap with the pixel portion 17 in the stacking direction Ds, and the through electrode 28B, which is disposed at a position that overlaps with the pixel portion 17 in the stacking direction Ds, are clearly shown by way of example.

[0111] Figure 19 The example shown illustrates wiring in RDL layer 25 including: power line 29A connected to a through electrode 28A located at a position not overlapping with pixel portion 17; and signal line 29B connected to a through electrode 28B located at a position overlapping with pixel portion 17. Power line 29A is classified as the aforementioned coarse wiring, and signal line 29B is classified as the aforementioned fine wiring.

[0112] Such coarse wiring (power wiring 29A, etc.) and fine wiring (signal wiring 29B, etc.) can actually be set at any location in the RDL layer 25, and can exist at one or both of the locations that overlap with the pixel portion 17 and the locations that do not overlap with the pixel portion 17 in the stacking direction Ds.

[0113] Furthermore, despite Figure 19 The RDL layer 25 of the intermediate logic substrate 12 in the example shown has a similar structure to... Figure 1 The example shown is a single-layer wiring, but RDL layer 25 can have the same... Figure 16 The example shown is similar to a multilayer wiring construction (e.g., a three-layer wiring construction).

[0114] [Manufacturing Method] Next, an example of the manufacturing method of the solid-state camera device 10 will be described.

[0115] Figures 20A to 31 These are figures illustrating an example of the manufacturing method of the solid-state imaging device 10. Figure 20A and Figures 21 to 31 These are cross-sectional views, and Figures 20B to 20D The views shown from above are respectively Figure 20A An example of the planar shape of the insulating film 40 shown. Figure 32A It shows the relationship with Figure 20A Cross-sectional view of a modified example of the insulating film 40 shown. Figures 32B to 32D The views shown from above are respectively Figure 32A An example of the planar shape of the insulating film 40 shown.

[0116] First, such as Figure 20A As shown, on the surface of the semiconductor layer 32 of the intermediate logic substrate 12 (a surface extending in the substrate extension direction) Figure 20A An insulating film 40 is embedded and formed in the upper part of the semiconductor layer 32, and an element isolation portion 61 is formed therein. As described above, the insulating film 40 ultimately surrounds the through electrode 28 between the through electrode 28 and the semiconductor layer 32.

[0117] Figure 20A The example shown illustrates that the insulating film 40 extends in a cylindrical shape in the stacking direction Ds and is configured to surround a portion of the semiconductor layer 32. The shape of the insulating film 40 is not particularly limited, and for example, the insulating film 40 may have a circular planar shape (see Figure 1). Figure 20B ), Quadrilateral planar shape (refer to) Figure 20C ), octagonal planar shape ( Figure 20D (or any other planar shape.)

[0118] like Figure 32AAs shown, the insulating film 40 can also extend in a solid columnar shape in the stacking direction Ds. In this case, the insulating film 40 can also have a circular planar shape (see Figure 1). Figure 32B ), quadrilateral planar shape ( Figure 32C ), an octagonal planar shape or any other planar shape.

[0119] Although there is no particular limitation on the size of the insulating film 40, the insulating film 40 has a size sufficient to ultimately and properly surround the through electrode 28. Considering the typical size of the through electrode 28, the insulating film 40 can have a maximum width of 200 to 500 nm (size in the substrate extension direction) or a total depth of 3 to 5 μm (size in the stacking direction Ds).

[0120] The specific composition of the insulating film 40 is not particularly limited. The insulating film 40 can typically contain silicon nitride (SiN:Si3N4), silicon oxide (SiO:SiO2), silicon oxynitride (SiON), or silicon oxycarbide (SiOC). In particular, for insulating films 40 and device isolation portions 61 with the same composition (e.g., SiO), the insulating film 40 and the device isolation portion 61 can be formed simultaneously in the semiconductor layer 32.

[0121] Then, as Figure 21 As shown, on the semiconductor layer 32 of the intermediate logic substrate 12 (particularly on the surface where the insulating film 40 and the component isolation portion 61 are located), a multilayer wiring layer 22, functional components such as transistors, and connection pads (e.g., Cu) 63 are formed together with the insulating film.

[0122] Next, as Figure 22 As shown, when the connection pads 63 of the intermediate logic substrate 12 and the connection pads 73 of the CIS substrate 11 are bonded to each other, the intermediate logic substrate 12 and the CIS substrate 11 are bonded to each other. Before bonding the CIS substrate 11 to the intermediate logic substrate 12, a semiconductor layer 31, a multilayer wiring layer 21, and a pixel isolation layer 20 are pre-formed on the CIS substrate 11. Therefore, the CIS substrate 11 is bonded to the intermediate logic substrate 12 in a state including the semiconductor layer 31, the multilayer wiring layer 21, and the pixel isolation layer 20.

[0123] Next, as Figure 23 As shown, a portion of the semiconductor layer 32 of the intermediate logic substrate 12 is removed to reduce the film thickness of the semiconductor layer 32 in the stacking direction Ds. In this way, the semiconductor layer 32 is thinned so that the insulating film 40 is exposed together with the semiconductor layer 32 on the surface (back side) of the intermediate logic substrate 12 near the semiconductor layer 32.

[0124] Next, as Figure 24As shown, an interlayer insulating film 35 is stacked on the semiconductor layer 32 of the intermediate logic substrate 12, and a wiring layer pattern 42 is disposed on the interlayer insulating film 35. The wiring layer pattern 42 formed in this way has a groove shape corresponding to the aforementioned RDL layer 25.

[0125] Next, as Figure 25 As shown, through-holes are formed in the interlayer insulating film 35 and the semiconductor layer 32 of the intermediate logic substrate 12 to form electrode holes 41 surrounded by the insulating film 40 in the semiconductor layer 32.

[0126] Next, as Figure 26 As shown, a barrier metal 39 and conductive components are deposited on the back side of the intermediate logic substrate 12 to stack a conductive metal layer 65. When the conductive components are disposed to the electrode via 41 and the wiring layer pattern 42 in this manner, the steps of embedding a through electrode 28 in the electrode via 41 and embedding an RDL layer 25 in the wiring layer pattern 42 are performed simultaneously. Therefore, the through electrode 28 is integrally formed with the wiring disposed in the RDL layer 25.

[0127] Next, a planarization process is performed to remove the conductive metal layer 65. For example... Figure 27 As shown, as a result of this planarization process, the conductive components embedded in the wiring layer pattern 42 are left as wiring constituting the RDL layer 25, but other conductive components on the RDL layer 25 (i.e., conductive components not embedded in the wiring layer pattern 42) are removed.

[0128] Next, as Figure 28 As shown, as the thickness of the interlayer insulating film 35 of the intermediate logic substrate 12 increases in the stacking direction Ds, connection pads (e.g., Cu) 67 are formed. The connection pads 67 formed in this way are located on the back side of the intermediate logic substrate 12. Figure 28 The way the image is exposed (above) is set.

[0129] Next, as Figure 29 As shown, the intermediate logic substrate 12 and the bottom logic substrate 13 are bonded to each other simultaneously (e.g., Cu-Cu junction) by bonding the connection pads 67 of the intermediate logic substrate 12 and the connection pads 77 of the bottom logic substrate 13 to each other. Before bonding the bottom logic substrate 13 to the intermediate logic substrate 12, a semiconductor layer 33 and a multilayer wiring layer 23 are pre-formed on the bottom logic substrate 13. Therefore, the bottom logic substrate 13 is bonded to the intermediate logic substrate 12 while containing the semiconductor layer 33 and the multilayer wiring layer 23.

[0130] Next, as Figure 30 As shown, a portion of the semiconductor layer 31 of the CIS substrate 11 is removed to reduce the film thickness of the semiconductor layer 31 in the stacking direction Ds, thereby making the semiconductor layer 31 thinner.

[0131] Next, as Figure 31 As shown, the exposed surface of the semiconductor layer 31 is formed ( Figure 31 The color filter layer 15 and microlens array 16 (above) in the middle.

[0132] As described above, a series of processes, including connecting the bottom logic substrate 13 to the back side of the intermediate logic substrate 12 and connecting the CIS substrate 11 to the front side of the intermediate semiconductor substrate 12, are performed to manufacture a three-layer stacked solid-state imaging device 10. The solid-state imaging device 10 manufactured in this manner includes a CIS substrate 11 and an intermediate logic substrate 12, which are stacked together facing each other with multilayer wiring layers 21 and 22, and electrically connected to each other via connection pads 63 and 73 between them. Furthermore, the intermediate logic substrate 12 and the bottom logic substrate 13 are stacked together facing each other with RDL layers 25 and multilayer wiring layers 23, and electrically connected to each other via connection pads 67 and 77 between them.

[0133] Specifically, after the insulating film 40 is formed in the intermediate logic substrate 12 (refer to...) Figure 20A and Figure 32A A wiring layer pattern 42 is provided in the intermediate logic substrate 12. Figure 24 Therefore, when the insulating film 40 is formed, the wiring layer pattern 42 (specifically, the shallow groove portion) is not filled with insulating material. Thus, when conductive members are disposed in the electrode hole 41 and the wiring layer pattern 42, conductive members can be appropriately embedded in the coarse and fine groove portions of the wiring layer pattern 41, thereby enabling the formation of an RDL layer 25 with the desired wiring structure together with the through electrode 28.

[0134] As described above, this embodiment enables the formation of an insulating film 40 in the semiconductor layer 32 prior to the formation of the wiring layer pattern 42 and the electrode via 41, and the embedding of the RDL layer 25 and the through electrode 28 in the wiring layer pattern 42 and the electrode via 41, respectively. This configuration not only allows the simultaneous formation of the RDL layer 25 in the wiring layer pattern 42 and the through electrode 28 in the electrode via 41, but also allows for the appropriate formation of coarse and fine wiring in the RDL layer 25.

[0135] As described above, the technology according to this embodiment is advantageous for manufacturing a solid-state imaging device 10 comprising an RDL layer 25 having the required wiring structure and good electrical characteristics and a through electrode 28, and is advantageous for implementing the manufacturing method of the solid-state imaging device 10 as described above.

[0136] It should be noted that the embodiments and modifications disclosed herein are illustrative in all respects and should not be construed as limiting. The above embodiments and modifications may be omitted, substituted, or changed in various forms without departing from the scope and spirit of the appended claims. For example, the above embodiments and modifications may be combined in whole or in part, and embodiments other than those described above may be combined with them. Furthermore, the effects of this disclosure as described herein are merely illustrative and may produce other effects.

[0137] The types of technologies embodying the above-described technical ideas are not limited. For example, the above-described technical ideas can be implemented by a computer program that enables a computer to execute one or more processes (steps) included in a method for manufacturing or using the above-described apparatus. Furthermore, the above-described technical ideas can be implemented by a computer-readable non-transient recording medium on which such a computer program is recorded.

[0138] [Additional Explanation] The following construction modes also fall within the technical scope of this disclosure.

[0139] [Method 1] A semiconductor device comprising: A first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are arranged sequentially in a stacking direction, with the first semiconductor substrate located on a first side of the second semiconductor substrate and the third semiconductor substrate located on a second side of the second semiconductor substrate. The second semiconductor substrate has a wiring layer disposed on the second surface and a through electrode connected to the wiring layer. The wiring layer includes a first wiring and a second wiring, the first wiring being connected to a power source, and the second wiring serving as a signal line and including a portion with a width smaller than that of the first wiring.

[0140] [Method 2] In the semiconductor device described in method 1, wherein, The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0141] [Method 3] In the semiconductor device described in method 1 or 2, wherein... The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is positioned at a location that overlaps with the pixel portion in the stacking direction.

[0142] [Method 4] The semiconductor device described in any one of methods 1 to 3, wherein... The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is positioned in the stacking direction at a location that does not overlap with the pixel portion.

[0143] [Method 5] The semiconductor device described in any one of methods 2 to 4, wherein... The thickness of the insulating film on the second side is less than the thickness of the insulating film on the first side.

[0144] [Method 6] In any one of methods 1 to 5, the semiconductor device wherein... The wiring layer comprises two or more wirings stacked in the stacking direction.

[0145] [Method 7] In any one of methods 1 to 6, the semiconductor device wherein... The areas of the first semiconductor substrate and the third semiconductor substrate are equal in the direction perpendicular to the stacking direction.

[0146] [Method 8] The semiconductor device described in any one of methods 1 to 7, wherein... The areas of the first semiconductor substrate and the third semiconductor substrate are different from each other in a direction perpendicular to the stacking direction.

[0147] [Method 9] A semiconductor device comprising: A first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are arranged sequentially in a stacking direction, with the first semiconductor substrate located on a first side of the second semiconductor substrate and the third semiconductor substrate located on a second side of the second semiconductor substrate. The second semiconductor substrate includes a wiring layer disposed on the second surface and a through electrode integrally disposed with the wiring disposed in the wiring layer.

[0148] [Method 10] In the semiconductor device described in method 9, wherein... The through electrode is at least partially surrounded by blocking metal.

[0149] [Method 11] In the semiconductor device described in method 9 or 10, wherein... The wiring layer includes: The first wiring connected to the power supply; and A second wiring used as a signal line, the second wiring including a portion that is narrower than the width of the first wiring.

[0150] [Method 12] In the semiconductor device described in method 11, wherein... The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0151] [Method 13] The semiconductor device described in any one of methods 9 to 12, wherein... The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is disposed at a position that overlaps with the pixel portion in the stacking direction.

[0152] [Method 14] The semiconductor device described in any one of methods 9 to 13, wherein... The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is disposed at a position that does not overlap with the pixel portion in the stacking direction.

[0153] [Method 15] The semiconductor device described in any one of methods 12 to 14, wherein... The thickness of the insulating film surrounding the through electrode on the second side is less than the thickness of the insulating film on the first side.

[0154] [Method 16] The semiconductor device described in any one of methods 9 to 15, wherein... The wiring layer includes two or more wirings stacked in the stacking direction.

[0155] [Method 17] The semiconductor device described in any one of methods 9 to 16, wherein... The areas of the first semiconductor substrate and the third semiconductor substrate are equal in the direction perpendicular to the stacking direction.

[0156] [Method 18] The semiconductor device described in any one of methods 9 to 17, wherein... The areas of the first semiconductor substrate and the third semiconductor substrate are different from each other in a direction perpendicular to the stacking direction.

[0157] [Method 19] A semiconductor device comprising: The first substrate includes a first semiconductor layer and a first multilayer wiring layer; A second substrate, comprising a second semiconductor layer, a second multilayer wiring layer, and a wiring layer; and The third substrate includes a third semiconductor layer and a third multilayer wiring layer. The first substrate and the second substrate are stacked with the first multilayer wiring layer and the second multilayer wiring layer facing each other. The second substrate and the third substrate are stacked with the wiring layer and the third multilayer wiring layer facing each other. The wiring layer is connected to a through electrode disposed in the semiconductor device, and The wiring layer includes a first wiring and a second wiring, the first wiring being connected to a power source, and the second wiring serving as a signal line and including a portion with a width smaller than that of the first wiring.

[0158] [Method 20] In the semiconductor device described in method 19, wherein... The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

[0159] [Method 21] A method for manufacturing a semiconductor device, the method comprising the following steps: An insulating film is formed on a semiconductor substrate; Electrode holes surrounded by the insulating film are formed on the semiconductor substrate; and A through electrode is formed in the electrode hole.

[0160] [Method 22] The method for manufacturing the semiconductor device described in method 21 further includes the following step: After forming the insulating film on the semiconductor substrate, a wiring layer pattern is formed on the semiconductor substrate; and Conductive components are disposed in the electrode holes and the wiring layer pattern such that not only are the through electrodes embedded in the electrode holes, but the wiring layer is also embedded in the wiring layer pattern.

[0161] [Method 23] In the method of manufacturing a semiconductor device described in method 22, wherein... The through electrode is integrally disposed with the wiring disposed in the wiring layer.

[0162] [Method 24] The method for manufacturing a semiconductor device according to any of methods 21 to 23 further includes the following step: Another semiconductor substrate having a pixel portion including multiple photoelectric conversion elements is connected to the first side of the semiconductor substrate; and Another semiconductor substrate is connected to a second side of the semiconductor substrate, the second side being opposite to the first side. List of reference numerals

[0163] 10 Solid-state imaging devices 11 CIS substrate 12 Intermediate Logic Board 12A First Intermediate Substrate 12B Second Intermediate Substrate 13 Bottom logic board 13A Bottom Logic Board 13B Bottom Logic Board 14 Supporting substrate 15 Color Filter Layers 16 microlens array 17 pixels 18 Non-pixel section 19 Photoelectric conversion element 21 Multilayer Wiring 22-layer wiring harness 22A Multilayer Wiring 22B Multilayer Wiring 23 Multilayer Wiring 25. Redistribution Line (RDL) Layer 25A RDL layer 25B RDL layer 28 Through-electrode 28A Through Electrode 28B Through Electrode 29 Wiring 29A power wiring 29B Signal Wiring 31 Semiconductor layer 32 Semiconductor Layer 32A Semiconductor Layer 32B semiconductor layer 33 Semiconductor layer 35-layer interlayer insulation film 36-layer interlayer insulation film 39. Blocking metal 40 Insulating film 41 Electrode holes 42 Wiring layer pattern 61 Component Isolation Section 63 Connecting pads 65 Conductive metal layer 67 Connecting pads 73 Connecting pads 77 Connecting pads Ds Stacking Direction

Claims

1. A semiconductor device comprising: A first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are arranged sequentially in a stacking direction, with the first semiconductor substrate located on a first side of the second semiconductor substrate and the third semiconductor substrate located on a second side of the second semiconductor substrate. The second semiconductor substrate has a wiring layer disposed on the second surface and a through electrode connected to the wiring layer. The wiring layer includes a first wiring and a second wiring, the first wiring being connected to a power source, and the second wiring serving as a signal line and including a portion with a width smaller than that of the first wiring.

2. The semiconductor device according to claim 1, wherein, The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

3. The semiconductor device according to claim 1, wherein, The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is positioned at a location that overlaps with the pixel portion in the stacking direction.

4. The semiconductor device according to claim 1, wherein, The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is positioned in the stacking direction at a location that does not overlap with the pixel portion.

5. The semiconductor device according to claim 2, wherein, The thickness of the insulating film on the second side is less than the thickness of the insulating film on the first side.

6. The semiconductor device according to claim 1, wherein, The wiring layer comprises two or more wirings stacked in the stacking direction.

7. The semiconductor device according to claim 1, wherein, The areas of the first semiconductor substrate and the third semiconductor substrate are equal in the direction perpendicular to the stacking direction.

8. The semiconductor device according to claim 1, wherein, The areas of the first semiconductor substrate and the third semiconductor substrate are different from each other in a direction perpendicular to the stacking direction.

9. A semiconductor device comprising: A first semiconductor substrate, a second semiconductor substrate, and a third semiconductor substrate are arranged sequentially in a stacking direction, with the first semiconductor substrate located on a first side of the second semiconductor substrate and the third semiconductor substrate located on a second side of the second semiconductor substrate. The second semiconductor substrate includes a wiring layer disposed on the second surface and a through electrode integrally disposed with the wiring disposed in the wiring layer.

10. The semiconductor device according to claim 9, wherein, The through electrode is at least partially surrounded by blocking metal.

11. The semiconductor device according to claim 9, wherein, The wiring layer includes: The first wiring connected to the power supply; and A second wiring used as a signal line, the second wiring including a portion that is narrower than the width of the first wiring.

12. The semiconductor device according to claim 11, wherein, The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

13. The semiconductor device according to claim 9, wherein, The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is disposed at a position that overlaps with the pixel portion in the stacking direction.

14. The semiconductor device according to claim 9, wherein, The first semiconductor substrate includes a pixel portion, and the pixel portion includes a plurality of photoelectric conversion elements, and The through electrode is disposed at a position that does not overlap with the pixel portion in the stacking direction.

15. The semiconductor device according to claim 12, wherein, The thickness of the insulating film surrounding the through electrode on the second side is less than the thickness of the insulating film on the first side.

16. The semiconductor device according to claim 9, wherein, The wiring layer includes two or more wirings stacked in the stacking direction.

17. The semiconductor device according to claim 9, wherein, The areas of the first semiconductor substrate and the third semiconductor substrate are equal in the direction perpendicular to the stacking direction.

18. The semiconductor device according to claim 9, wherein, The areas of the first semiconductor substrate and the third semiconductor substrate are different from each other in a direction perpendicular to the stacking direction.

19. A semiconductor device comprising: The first substrate includes a first semiconductor layer and a first multilayer wiring layer; The second substrate includes a second semiconductor layer, a second multilayer wiring layer, and a wiring layer. as well as The third substrate includes a third semiconductor layer and a third multilayer wiring layer. The first substrate and the second substrate are stacked with the first multilayer wiring layer and the second multilayer wiring layer facing each other. The second substrate and the third substrate are stacked with the wiring layer and the third multilayer wiring layer facing each other. The wiring layer is connected to a through electrode disposed in the semiconductor device, and The wiring layer includes a first wiring and a second wiring, the first wiring being connected to a power source, and the second wiring serving as a signal line and including a portion with a width smaller than that of the first wiring.

20. The semiconductor device of claim 19, wherein, The second wiring includes a portion whose width is smaller than the thickness of the insulating film surrounding the through electrode.

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