Time pulse generation device and time pulse generation method

Abstract

The invention provides a time pulse generation device and a time pulse generation method, and relates to the technical field of time synchronization. A reference time code generation unit in the time pulse generation device is used for generating a time code reference signal according to a time code standard signal and a local clock signal, and outputting the time code reference signal to a phase-locked loop; the phase-locked output end of the phase-locked loop is connected with the control end of the reference time code generation unit, and the phase-locked loop is used for generating a phase locking signal according to a time code reference signal and a local clock signal and outputting the phase locking signal to the reference time code generation unit; and the phase-locked loop is also used for generating a target clock signal and a target pulse per second signal according to the time code reference signal and the local clock signal. By analyzing the punctual edge of the time code standard signal and combining a phase locking mechanism of the phase-locked loop, the time reference of the finally output target clock signal and the time reference of the time code standard signal are kept synchronous, and time offset caused by independent operation of a local clock is avoided.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology, and more specifically, to a time pulse generation device and a time pulse generation method. Background Technology

[0002] In fields such as power systems where time synchronization accuracy is critical, the IRIG-B code, as the standard time code developed by the Inter-Range Instrumentation Group (IRIG) in the United States, has become the core encoding format for frequency calibration and time synchronization between devices, and is widely used in various systems that require precise time coordination.

[0003] Currently, the mainstream technology for extracting Pulse Per Second (PPS) from IRIG-B code in the industry uses a local high-speed clock to oversample the IRIG-B signal. It then analyzes the pulse width characteristics of the sampled signal to parse the IRIG-B message, pinpoint the exact pulse timing, and generate the PPS. However, this technology does not synchronize the generated PPS signal with the IRIG-B source clock; instead, it uses the local clock as a reference. The inherent difference between the local clock and the source clock introduces synchronization errors, ultimately resulting in a large error in the generated PPS signal. This time synchronization accuracy cannot meet the high-precision time synchronization requirements of scenarios such as power systems.

[0004] Therefore, there is an urgent need for a second pulse extraction technology that can avoid local clock interference and improve the synchronization accuracy with the IRIG-B source clock, so as to solve the core defects of the existing technology. Summary of the Invention

[0005] This application addresses the shortcomings of the prior art by providing a time pulse generation device and a time pulse generation method to solve the problems existing in the prior art.

[0006] The technical solution adopted in the embodiments of this application is as follows: In a first aspect, embodiments of this application provide a time pulse generation device, including: a reference time code generation unit and a phase-locked loop; The first input terminal of the reference time code generation unit is used to receive a time code standard signal, and the second input terminal of the reference time code generation unit is used to receive a local clock signal; the reference time code generation unit is used to generate a time code reference signal according to the time code standard signal and the local clock signal; the output terminal of the reference time code generation unit is connected to the phase-locked loop and is used to output the time code reference signal to the phase-locked loop. The phase-locked loop's output terminal is connected to the control terminal of the reference time code generation unit. The phase-locked loop is used to generate a phase-locked signal based on the time code reference signal and the local clock signal, and outputs the phase-locked signal to the reference time code generation unit, so that the reference time code generation unit can determine the state of the phase-locked loop based on the phase-locked signal. The phase-locked loop is also used to generate a target clock signal and a target second pulse signal based on the time code reference signal and the local clock signal, and to output the target clock signal and the target second pulse signal.

[0007] In one embodiment, the reference time code generation unit is used to parse the time code standard signal according to the local clock signal to obtain a punctual edge pulse signal and a duty cycle second pulse signal, and to perform logical processing on the punctual edge pulse signal, the duty cycle second pulse signal and the time code standard signal to obtain the time code reference signal.

[0008] In one embodiment, the reference timecode generation unit includes: a programmable logic device, an AND gate, and an OR gate; The first input terminal of the programmable logic device is the first input terminal of the reference time code generation unit, used to receive the time code standard signal; the second input terminal of the programmable logic device is the second input terminal of the reference time code generation unit, used to receive the local clock signal. The programmable logic device is used to parse the time code standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; the first output terminal of the programmable logic device is used to output the punctual edge pulse signal, and the second output terminal of the programmable logic device is used to output the duty cycle second pulse signal. The first input terminal of the AND gate is connected to the first input terminal of the programmable logic device, and the second input terminal of the AND gate is connected to the first output terminal of the programmable logic device. The AND gate is used to perform AND logic processing on the punctual edge pulse signal and the time code standard signal to obtain a pulse signal including the punctual edge. The output of the AND gate is connected to the first input of the OR gate, and the second input of the OR gate is connected to the second output of the programmable logic device. The OR gate is used to perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal to obtain the time code reference signal. The output of the OR gate is the output of the reference time code generation unit, used to output the time code reference signal.

[0009] In one embodiment, the reference timecode generation unit includes: a programmable logic device; The programmable logic device is used to parse the time code standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; to perform AND logic processing on the punctual edge pulse signal and the time code standard signal to obtain a pulse signal including the punctual edge; and to perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal to obtain the time code reference signal.

[0010] In one embodiment, the phase-locked loop includes: a phase detector, a frequency divider, and a voltage-controlled oscillator; The first input terminal of the phase detector is used to receive the time code reference signal, and the voltage-controlled oscillator is connected to the second input terminal of the phase detector through the frequency divider; the voltage-controlled oscillator inputs the local clock signal to the frequency divider, and the frequency divider is used to perform frequency division processing on the local clock signal to generate the target second pulse signal, and outputs the target second pulse signal to the phase detector; The first output terminal of the phase detector is connected to the input terminal of the voltage-controlled oscillator. The phase detector is used to generate a clock adjustment signal based on the time code reference signal and the target second pulse signal, and output the clock adjustment signal to the voltage-controlled oscillator. The voltage-controlled oscillator is used to generate and output the target clock signal based on the clock adjustment signal and the local clock signal. The phase detector is also used to generate a phase-locked signal based on the time code reference signal and the local clock signal. The second output terminal of the phase detector is used to output the phase-locked signal to the reference time code generation unit.

[0011] In one embodiment, the phase-locked loop further includes: a low-pass filter; The first output of the phase detector is connected to the input of the voltage-controlled oscillator via the low-pass filter.

[0012] Secondly, embodiments of this application provide a time pulse generation method, applied to the time pulse generation apparatus described in any of the above embodiments, the method comprising: The reference time code generation unit in the time pulse generation device generates a time code reference signal based on the time code standard signal and the local clock signal. Using the phase-locked loop in the time pulse generation device, a phase-locked signal is generated and output to the reference time code generation unit based on the time code reference signal and the local clock signal, so that the reference time code generation unit can determine the state of the phase-locked loop based on the phase-locked signal. Using the phase-locked loop in the time pulse generation device, a target clock signal and a target second pulse signal are generated and output based on the time code reference signal and the local clock signal.

[0013] In one embodiment, the step of using the reference time code generation unit in the time pulse generation device to generate a time code reference signal based on the time code standard signal and the local clock signal includes: Using the reference time code generation unit, the time code standard signal is parsed according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; The reference time code generation unit performs logical processing on the punctual edge pulse signal, the duty cycle second pulse signal, and the time code standard signal to obtain the time code reference signal.

[0014] In one embodiment, the step of using the reference timecode generation unit to perform logical processing on the punctual edge pulse signal, the duty cycle second pulse signal, and the timecode standard signal to obtain the timecode reference signal includes: The punctual edge pulse signal and the time code standard signal are subjected to AND logic processing to obtain a pulse signal including the punctual edge; The time code reference signal is obtained by performing an OR logic process on the pulse signal including the punctual edge and the duty cycle second pulse signal.

[0015] In one embodiment, the step of using the phase-locked loop in the time pulse generation device to generate and output a target clock signal and a target second pulse signal based on the time code reference signal and the local clock signal includes: The target second pulse signal is obtained by using the phase-locked loop in the time pulse generation device to perform frequency division processing on the local clock signal; The target clock signal is generated using the phase-locked loop in the time pulse generation device, based on the target second pulse signal and the time code reference signal.

[0016] The beneficial effects of this application are as follows: This application provides a time pulse generation device, which analyzes the punctual edge of the time code standard signal by referencing the time code generation unit, and combines the phase locking mechanism of the phase-locked loop to ensure that the time phase of the final output target clock signal and the time code standard signal are synchronized, avoiding the time offset caused by the independent operation of the local clock. Furthermore, through the phase detection adjustment of the phase-locked loop, the phase of the final output target second pulse signal is precisely aligned with the punctual edge of the time code standard signal, which greatly reduces the jitter of the PPS signal. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the time pulse generation device provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the reference timecode generation unit provided in the embodiments of this application; Figure 3 This is a schematic diagram of the phase-locked loop provided in an embodiment of this application; Figure 4 This is a schematic diagram of the overall structure of the time pulse generation device provided in the embodiments of this application; Figure 5 One of the flowcharts for the time pulse generation method provided in the embodiments of this application; Figure 6 A second schematic flowchart illustrating the time pulse generation method provided in this application embodiment; Figure 7 The third schematic flowchart of the time pulse generation method provided in the embodiments of this application; Figure 8 The fourth flowchart illustrates the time pulse generation method provided in this application embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can be a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0025] First, let's explain the IRIG-B code. IRIG-B is a time code standard developed by the US Range Instrument Group (IRIG) for time synchronization between different devices and systems. IRIG-B is a serial time code that transmits at a rate of one frame per second. Each symbol is 10ms wide, and a time frame period includes 100 symbols. IRIG-B uses pulse-width encoding, and each symbol has three code types: binary "0", "1", and a position identifier. The time information contained in IRIG-B includes year, day, hour, minute, and second, providing high-precision time synchronization information. Each symbol has an identifier; for example, the first symbol is identified as P0, the second as P1, the third as P2, and so on.

[0026] There are two types of IRIG-B codes: the modulated B code is usually called IRIG-B (AC) code, and the unmodulated B code is usually called IRIG-B (DC) code. The synchronization accuracy of IRIG-B (DC) code can reach the tens of nanoseconds level, and the interface usually adopts TTL interface and RS422 (V.11) interface. The synchronization accuracy of IRIG-B (AC) code is generally between 10ms and 20ms, and the interface adopts a balanced interface.

[0027] IRIG-B code is widely used in various aspects of power systems and is the standard time code encoding format for frequency calibration and time synchronization. However, only the first edge after P0 is an on-time edge; other edges are not guaranteed to be synchronized with the source clock. Therefore, the on-time edge mentioned in the following embodiments of this application refers to the first edge of the IRIG-B code after P0.

[0028] The embodiments of this application are illustrated below with reference to the accompanying drawings and through multiple examples. Figure 1 This is a schematic diagram of the structure of the time pulse generation device provided in the embodiments of this application, as shown below. Figure 1 As shown, the time pulse generation device includes a reference time code generation unit (Complex Programmable Logic Device, CPLD) and a phase-locked loop (PLL).

[0029] The first input terminal of the reference timecode generation unit is used to receive the timecode standard signal IRIGB-DC, and the second input terminal of the reference timecode generation unit is used to receive the local clock signal. The reference timecode generation unit is used to generate the timecode reference signal IRIGB-REF based on the timecode standard signal and the local clock signal.

[0030] Specifically, the reference time code generation unit can, for example, parse the time code standard signal according to the local clock signal to obtain the on-time pulse signal (ON TIME PULSE) and the duty cycle second pulse signal (PPS), and perform logical processing on the on-time pulse signal ON TIME PULSE, the duty cycle second pulse signal PPS and the time code standard signal IRIGB-DC to obtain the time code reference signal IRIGB-REF.

[0031] The output of the reference time code generation unit is connected to the phase-locked loop (PLL) and is used to output the time code reference signal IRIGB-REF to the PLL.

[0032] The phase-locked loop's output terminal is connected to the control terminal of the reference time code generation unit. The phase-locked loop generates a phase-locked signal LOCKED based on the time code reference signal IRIGB-REF and the local clock signal, and outputs the phase-locked signal LOCKED to the reference time code generation unit, so that the reference time code generation unit can determine the state of the phase-locked loop based on the phase-locked signal.

[0033] The phase-locked loop is also used to generate the target clock signal CLK_OUT and the target second pulse signal IRIGB-PPS based on the time code reference signal IRIGB-REF and the local clock signal, and outputs the target clock signal CLK_OUT and the target second pulse signal IRIGB-PPS.

[0034] In summary, this embodiment provides a time pulse generation device. By analyzing the punctual edge of the time code standard signal IRIGB-DC through a reference time code generation unit and combining it with the phase-locked loop (PLL) phase-locking mechanism, the final output target clock signal CLK_OUT is synchronized with the time phase of IRIGB-DC, avoiding time offset caused by independent operation of the local clock. Furthermore, through the phase detection adjustment of the PLL, the final output target second pulse signal IRIGB-PPS is precisely aligned with the punctual edge of IRIGB-DC, significantly reducing the jitter of the PPS signal.

[0035] Figure 2 This is a schematic diagram of the structure of the reference timecode generation unit provided in the embodiments of this application, as shown below. Figure 2 As shown, the reference timecode generation unit includes a programmable logic device, an AND gate, and an OR gate.

[0036] The first input terminal of the programmable logic device is the first input terminal of the reference time code generation unit, used to receive the time code standard signal IRIGB-DC; the second input terminal of the programmable logic device is the second input terminal of the reference time code generation unit, used to receive the local clock signal.

[0037] The programmable logic device is used to parse the time code standard signal IRIGB-DC according to the local clock signal to obtain the punctual edge pulse signal ON TIME PULSE and the duty cycle second pulse signal PPS; the first output terminal of the programmable logic device is used to output the punctual edge pulse signal ON TIME PULSE, and the second output terminal of the programmable logic device is used to output the duty cycle second pulse signal PPS.

[0038] The first input of the AND gate is connected to the first input of the programmable logic device, and the second input of the AND gate is connected to the first output of the programmable logic device. The AND gate is used to perform AND logic processing on the punctual edge pulse signal ON TIME PULSE and the time code standard signal IRIGB-DC to obtain a pulse signal including the punctual edge.

[0039] The output of the AND gate is connected to the first input of the OR gate, and the second input of the OR gate is connected to the second output of the programmable logic device. The OR gate is used to perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal PPS to obtain the time code reference signal IRIGB-REF. The output of the OR gate is the output of the reference time code generation unit, which is used to output the time code reference signal.

[0040] In one embodiment, the reference timecode generation unit may also include a programmable logic device. The programmable logic device is used to parse the timecode standard signal IRIGB-DC according to the local clock signal to obtain the punctual edge pulse signal ONTIME PULSE and the duty cycle second pulse signal PPS. Then, it performs AND logic processing on the punctual edge pulse signal ONTIME PULSE and the timecode standard signal IRIGB-DC to obtain a pulse signal including the punctual edge. Finally, it performs OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal PPS to obtain the timecode reference signal IRIGB-REF.

[0041] Figure 3 This is a schematic diagram of the phase-locked loop provided in the embodiments of this application, as shown below. Figure 3 As shown, a phase-locked loop includes a phase detector (PD), a frequency divider (FD), and a voltage-controlled oscillator (VCO).

[0042] The first input terminal of the phase detector is used to receive the time code reference signal IRIGB-REF. The voltage-controlled oscillator is connected to the second input terminal of the phase detector through a frequency divider. The voltage-controlled oscillator inputs the local clock signal to the frequency divider, which is used to divide the local clock signal to generate the target second pulse signal IRIGB-PPS and outputs the target second pulse signal to the phase detector.

[0043] The first output of the phase detector is connected to the input of the voltage-controlled oscillator (VCO). The phase detector generates a clock adjustment signal based on the time code reference signal IRIGB-REF and the target second pulse signal IRIGB-PPS, and outputs the clock adjustment signal to the VCO. The VCO generates and outputs the target clock signal CLK_OUT based on the clock adjustment signal and the local clock signal. The phase detector also generates a phase-locked signal LOCKED based on the time code reference signal and the local clock signal. The second output of the phase detector outputs the phase-locked signal LOCKED to the reference time code generation unit.

[0044] Continue to refer to Figure 3The phase-locked loop also includes a low-pass filter (LPF). The first output of the phase detector is connected to the input of the voltage-controlled oscillator (VCO) through the low-pass filter. The low-pass filter is used to filter out high-frequency noise in the phase detector output signal, obtaining a smooth signal to drive the VCO and avoiding high-frequency noise interference from affecting the stability of the phase-locked loop.

[0045] In conclusion, Figure 4 This is a schematic diagram of the overall structure of the time pulse generation device provided in the embodiments of this application, as shown below. Figure 4 As shown, the device uses a programmable logic device to parse the time code standard signal and generates a time code reference signal through AND and OR gates; the phase-locked loop locks the phase through a phase detector, a low-pass filter, a voltage-controlled oscillator, and a frequency divider, and outputs the target clock signal and the target second pulse signal to achieve precise time synchronization.

[0046] Optionally, this application also provides a time pulse generation system, including at least the time pulse generation device described in the above embodiments. This system integrates the time pulse generation device provided in the above embodiments, can access the time code standard signal IRIGB-DC, and is adaptable to scenarios such as power frequency calibration and equipment time synchronization. The system analyzes the signal through a reference time code generation unit (CPLD), extracts the punctual timing edge, and generates a time code reference signal IRIGB-REF through logical operations. Then, a phase-locked loop locks the phase, outputting a low-jitter target second pulse signal IRIGB-PPS synchronized with IRIGB-DC and a highly stable target clock signal CLK_OUT. This solves the problems of large jitter and poor synchronization in the prior art, providing technical support for high-precision time synchronization requirements.

[0047] Figure 5 This is one of the flowcharts illustrating the time pulse generation method provided in the embodiments of this application, such as... Figure 5 As shown, this application also provides a time pulse generation method, applied to the time pulse generation apparatus provided in any of the above embodiments, the method comprising: S101. The reference time code generation unit in the time pulse generation device generates a time code reference signal based on the time code standard signal and the local clock signal.

[0048] The reference time code generation unit (CPLD) in the time pulse generation device receives the time code standard signal IRIGB-DC and the local clock signal. Through signal preprocessing, pulse width measurement, punctual edge extraction and logic operation, a time code reference signal IRIGB-REF with a 1Hz frequency, 50% duty cycle and containing the punctual edge (ON TIME) of IRIGB-DC is generated.

[0049] S102. Using the phase-locked loop in the time pulse generation device, a phase-locked signal is generated and output to the reference time code generation unit based on the time code reference signal and the local clock signal.

[0050] The device employs a phase-locked loop (PLL) that uses the generated time code reference signal IRIGB-REF as a reference input. Combined with the local clock signal, phase detection is performed to generate a phase-locked signal LOCKED, which is then fed back to the reference time code generation unit. The reference time code generation unit uses this LOCKED signal to determine whether the PLL is in a phase-locked state, ensuring the stability of subsequent signal processing.

[0051] S103. Using the phase-locked loop in the time pulse generation device, the target clock signal and the target second pulse signal are generated and output according to the time code reference signal and the local clock signal.

[0052] A phase-locked loop (PLL) is used to adjust the output frequency of the voltage-controlled oscillator (VCO) based on the phase detection results of the time code reference signal IRIGB-REF and the local clock signal, thereby generating and outputting a highly stable target clock signal CLK_OUT (e.g., 10MHz) and a target second pulse signal IRIGB-PPS.

[0053] The phase of IRIGB-PPS is synchronized with the ON IME of IRIGB-DC, and the duty cycle is 50%.

[0054] This embodiment can output a target second pulse signal IRIGB-PPS synchronized with the punctual edge of IRIGB-DC and a stable target clock signal CLK_OUT through a reference time code generation unit and a phase-locked loop, overcoming the defects of large PPS jitter and poor local clock stability in the prior art.

[0055] Figure 6 This is a second schematic flowchart of the time pulse generation method provided in the embodiments of this application, as shown below. Figure 6 As shown, S101, which uses a reference time code generation unit in a time pulse generation device to generate a time code reference signal based on a time code standard signal and a local clock signal, may include: S201. A reference time code generation unit is used to parse the time code standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal.

[0056] The reference code generation unit first performs filtering preprocessing on the IRIGB-DC signal, and then uses the local clock signal to measure the positive pulse width of the IRIGB-DC signal to distinguish between three pulse width types: 2ms, 5ms, and 8ms. After detecting two consecutive 8ms pulse widths, the P0 identifier and the ON TIME punctual edge are parsed out, and a punctual edge pulse signal (ON TIME PULSE, which goes high on the falling edge of P0 and goes low on the falling edge of ONTIME) and a duty cycle second pulse signal (PPS, which goes high on the rising edge of ON TIME and goes low on the rising edge of P6, with a duty cycle of 50%) are generated.

[0057] S202. A reference time code generation unit is used to perform logical processing on the punctual edge pulse signal, the duty cycle second pulse signal and the time code standard signal to obtain the time code reference signal.

[0058] The reference time code generation unit performs two-step logic operations on the timing edge pulse signal, the duty cycle second pulse signal, and the original IRIGB-DC signal to finally generate an IRIGB-REF time code reference signal that meets the input requirements of the phase-locked loop.

[0059] This embodiment accurately extracts the on-time pulse signal and the duty cycle second pulse signal (PPS), achieving effective separation of key timing information in the IRIGB-DC signal. This provides data support for subsequent logic processing. Furthermore, the key signals are integrated through logic processing to generate a reference signal that meets the input requirements of the phase-locked loop. This preserves the phase accuracy of the on-time pulse and satisfies the duty cycle and frequency requirements of the phase-locked loop for the reference signal.

[0060] Figure 7 This is the third flowchart illustrating the time pulse generation method provided in the embodiments of this application, as shown below. Figure 7 As shown, S202 specifically includes: S301 performs AND logic processing on the timing edge pulse signal and the time code standard signal to obtain a pulse signal including the timing edge.

[0061] Perform an AND logic operation on the timing edge pulse signal ON TIME PULSE and the time code standard signal IRIGB-DC to filter out pulse signals that include the IRIGB-DC timing edge (ON TIME), ensuring that timing edge information is not lost.

[0062] S302. Perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal to obtain the time code reference signal.

[0063] The pulse signal obtained from S301, including the punctual edge, is ORed with the duty cycle second pulse signal (PPS) generated from S201 to extend the high level of the pulse to 0.5s, finally obtaining the 1Hz, 50% duty cycle, and punctual edge phase-preserving time code reference signal IRIGB-REF.

[0064] In this embodiment, the pulse signal containing only the IRIGB-DC on-time edge is filtered out by AND logic processing, eliminating irrelevant signal interference, ensuring the purity of the on-time edge information, and avoiding phase deviation; the pulse high level is extended to 0.5s by OR logic processing to form a standard 1Hz signal with a 50% duty cycle, which is adapted to the phase detection frequency requirements of the phase-locked loop, while fully preserving the phase characteristics of the on-time edge.

[0065] Figure 8 This is the fourth flowchart illustrating the time pulse generation method provided in the embodiments of this application, as shown below. Figure 8 As shown, S103, which uses a phase-locked loop in a time pulse generation device to generate and output a target clock signal and a target second pulse signal based on a time code reference signal and a local clock signal, may include: S401. The phase-locked loop in the time pulse generator is used to divide the local clock signal to obtain the target second pulse signal.

[0066] The frequency divider inside the phase-locked loop divides the local clock signal (the output clock of the voltage-controlled oscillator) to generate a 1Hz, 50% duty cycle second pulse signal, which serves as the prototype of the target second pulse signal IRIGB-PPS.

[0067] S402. The phase-locked loop in the time pulse generator is used to generate the target clock signal based on the target second pulse signal and the time code reference signal.

[0068] The phase detector compares the phase difference between the target second pulse signal IRIGB-PPS and the time code reference signal IRIGB-REF. After filtering by a low-pass filter, the output frequency of the voltage-controlled oscillator is adjusted so that the second pulse signal after frequency division is completely synchronized with the phase of IRIGB-REF. Finally, it is determined to be the target second pulse signal IRIGB-PPS. At the same time, the VCO outputs a stable target clock signal CLK_OUT.

[0069] This embodiment generates a second-level pulse prototype through frequency division processing, providing a comparison benchmark with the same frequency as the reference signal for the phase-locked loop, laying the foundation for phase synchronization; by adjusting the voltage-controlled oscillator (VCO) frequency through phase detection, the target clock signal is phase-locked with the IRIGB-REF, ultimately achieving synchronization between the local clock signal and the source clock of the IRIGB-DC, while obtaining a low-jitter PPS signal.

[0070] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time pulse generating device, characterized in that include: Reference timecode generation unit, phase-locked loop; The first input terminal of the reference time code generation unit is used to receive the time code standard signal, and the second input terminal of the reference time code generation unit is used to receive the local clock signal. The reference time code generation unit is used to generate a time code reference signal based on the time code standard signal and the local clock signal; The output of the reference time code generation unit is connected to the phase-locked loop and is used to output the time code reference signal to the phase-locked loop. The phase-locked loop's output terminal is connected to the control terminal of the reference time code generation unit. The phase-locked loop is used to generate a phase-locked signal based on the time code reference signal and the local clock signal, and outputs the phase-locked signal to the reference time code generation unit, so that the reference time code generation unit can determine the state of the phase-locked loop based on the phase-locked signal. The phase-locked loop is also used to generate a target clock signal and a target second pulse signal based on the time code reference signal and the local clock signal, and to output the target clock signal and the target second pulse signal.

2. The time pulse generating device according to claim 1, characterized in that, The reference timecode generation unit is used to parse the timecode standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal, and to perform logical processing on the punctual edge pulse signal, the duty cycle second pulse signal and the timecode standard signal to obtain the timecode reference signal.

3. The time pulse generating device according to claim 2, characterized in that, The reference timecode generation unit includes: a programmable logic device, an AND gate, and an OR gate; The first input terminal of the programmable logic device is the first input terminal of the reference time code generation unit, used to receive the time code standard signal; the second input terminal of the programmable logic device is the second input terminal of the reference time code generation unit, used to receive the local clock signal. The programmable logic device is used to parse the time code standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; the first output terminal of the programmable logic device is used to output the punctual edge pulse signal, and the second output terminal of the programmable logic device is used to output the duty cycle second pulse signal. The first input terminal of the AND gate is connected to the first input terminal of the programmable logic device, and the second input terminal of the AND gate is connected to the first output terminal of the programmable logic device. The AND gate is used to perform AND logic processing on the punctual edge pulse signal and the time code standard signal to obtain a pulse signal including the punctual edge. The output of the AND gate is connected to the first input of the OR gate, and the second input of the OR gate is connected to the second output of the programmable logic device. The OR gate is used to perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal to obtain the time code reference signal. The output of the OR gate is the output of the reference time code generation unit, used to output the time code reference signal.

4. The time pulse generating device according to claim 2, characterized in that, The reference timecode generation unit includes: a programmable logic device; The programmable logic device is used to parse the time code standard signal according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; to perform AND logic processing on the punctual edge pulse signal and the time code standard signal to obtain a pulse signal including the punctual edge; and to perform OR logic processing on the pulse signal including the punctual edge and the duty cycle second pulse signal to obtain the time code reference signal.

5. The time pulse generating device according to claim 1, characterized in that, The phase-locked loop includes: a phase detector, a frequency divider, and a voltage-controlled oscillator; The first input terminal of the phase detector is used to receive the time code reference signal, and the voltage-controlled oscillator is connected to the second input terminal of the phase detector through the frequency divider; the voltage-controlled oscillator inputs the local clock signal to the frequency divider, and the frequency divider is used to perform frequency division processing on the local clock signal to generate the target second pulse signal, and outputs the target second pulse signal to the phase detector; The first output terminal of the phase detector is connected to the input terminal of the voltage-controlled oscillator. The phase detector is used to generate a clock adjustment signal based on the time code reference signal and the target second pulse signal, and output the clock adjustment signal to the voltage-controlled oscillator. The voltage-controlled oscillator is used to generate and output the target clock signal based on the clock adjustment signal and the local clock signal. The phase detector is also used to generate a phase-locked signal based on the time code reference signal and the local clock signal. The second output terminal of the phase detector is used to output the phase-locked signal to the reference time code generation unit.

6. The pulse generating device according to claim 5, characterized in that, The phase-locked loop further includes: a low-pass filter; The first output of the phase detector is connected to the input of the voltage-controlled oscillator via the low-pass filter.

7. A method for generating time pulses, characterized in that, The method, applied to the time pulse generating apparatus according to any one of claims 1 to 6, comprises: The reference time code generation unit in the time pulse generation device generates a time code reference signal based on the time code standard signal and the local clock signal. Using the phase-locked loop in the time pulse generation device, a phase-locked signal is generated and output to the reference time code generation unit based on the time code reference signal and the local clock signal, so that the reference time code generation unit can determine the state of the phase-locked loop based on the phase-locked signal. Using the phase-locked loop in the time pulse generation device, a target clock signal and a target second pulse signal are generated and output based on the time code reference signal and the local clock signal.

8. The pulse generation method according to claim 7, characterized in that, The step of using the reference time code generation unit in the time pulse generation device to generate a time code reference signal based on the time code standard signal and the local clock signal includes: Using the reference time code generation unit, the time code standard signal is parsed according to the local clock signal to obtain the punctual edge pulse signal and the duty cycle second pulse signal; The reference time code generation unit performs logical processing on the punctual edge pulse signal, the duty cycle second pulse signal, and the time code standard signal to obtain the time code reference signal.

9. The pulse generation method according to claim 8, characterized in that, The reference timecode generation unit performs logical processing on the punctual edge pulse signal, the duty cycle second pulse signal, and the timecode standard signal to obtain the timecode reference signal, including: The punctual edge pulse signal and the time code standard signal are subjected to AND logic processing to obtain a pulse signal including the punctual edge; The time code reference signal is obtained by performing an OR logic process on the pulse signal including the punctual edge and the duty cycle second pulse signal.

10. The time pulse generation method according to claim 7, characterized in that, The step of using the phase-locked loop in the time pulse generation device to generate and output a target clock signal and a target second pulse signal based on the time code reference signal and the local clock signal includes: The target second pulse signal is obtained by using the phase-locked loop in the time pulse generation device to perform frequency division processing on the local clock signal; The target clock signal is generated using the phase-locked loop in the time pulse generation device, based on the target second pulse signal and the time code reference signal.

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