Timer management method and electronic equipment
By providing multiple independent slots and a dual-storage timing variable mechanism for timer management, the problems of multi-instance management, data storage, and reset mode in timer software design are solved, achieving resource isolation, timing continuity, and extended hardware lifespan, thus adapting to diverse scenario requirements.
Patent Information
- Application Number
- CN202511945322.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-04-17
AI Technical Summary
Existing timer software designs suffer from a lack of multi-instance management capabilities, insufficient data storage reliability, and a single reset mode. These issues lead to resource conflicts, timing synchronization deviations, RAM overflows, timing data loss, and poor scenario adaptability, affecting device stability and reliability.
By providing multiple independent slots for timer management methods, filtering available slots when creating timer instances, and employing a dual storage mechanism of real-time timing variables and calibration timing variables, combined with different update cycles and reset mode configurations, resource isolation, timing continuity, and flexible scenario adaptation are achieved.
It enables stable operation of multiple timed tasks, avoids resource conflicts, ensures timing continuity, extends hardware lifespan, reduces development costs, and adapts to diverse scenario requirements.
Smart Images
Figure CN121879510A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the technical field of timer software design, such as a timer management method and electronic device. Background Technology
[0002] As a core component for task scheduling, periodic detection, and delay control, the performance of timers directly determines the operational stability and functional integrity of the equipment they belong to. However, the timer software design provided by related technologies still has many technical shortcomings in practical applications, making it difficult to meet the complex usage requirements of electronic devices such as industrial control modules, IoT sensing terminals, and smart meters. Specific problems are as follows: The lack of multi-instance management capabilities can easily lead to resource conflicts. Most of the timers provided by related technologies are designed for single instances. Multi-task concurrent timing requires users to define their own management logic, which not only increases development and adaptation costs, but also easily leads to resource conflicts such as RAM (Random Access Memory) overflow and timing synchronization deviation, affecting the stable operation of the device.
[0003] Insufficient data storage reliability makes it difficult to balance hardware lifespan and timing continuity. Related technologies typically rely solely on RAM to store timing values. However, RAM is volatile; once the device loses power, the stored timing data is completely lost, requiring reinitialization upon power-up. This inability to resume the timing progress before power failure leads to interruptions and failures in long-cycle timed tasks. While some solutions support storing timing data in Flash memory, they employ a "real-time write" strategy, triggering Flash erase and write operations with each timing value update. Frequent erase and write operations significantly shorten Flash lifespan and increase the risk of data write failures, impacting overall device reliability and long-term operational stability.
[0004] The reset mode is limited and has poor scenario adaptability. The timer reset mechanism provided by related technologies only supports two fixed states: "restart" or "stop". It lacks flexible mode configuration capabilities and is difficult to adapt to diverse scenarios such as fault reset continuation and factory reset task clearing. Users need to develop additional adaptation logic, which increases costs and is prone to timing errors, thus limiting scenario coverage.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0007] This disclosure provides a timer management method and electronic device that can specifically solve at least one of the following problems in related technologies: lack of multi-instance management of timers, insufficient data storage reliability, and single reset mode.
[0008] According to a first aspect of this disclosure, a timer management method is provided, comprising: In response to a timer creation request, it iterates through multiple pre-created independent slots and selects the target slot that is currently idle. When a target slot is found, a timer instance is created based on the target slot. The timer instance is configured with a real-time timing variable and a calibration timing variable. The real-time timing variable is stored in a temporary storage, while the calibration timing variable is stored in both temporary storage and persistent storage. In response to a timer run request, start the timer instance to begin timing; After each of the first update cycles, the real-time timing variable is incremented and updated. After each second update cycle, the real-time timing variable in the temporary storage is assigned to the calibration timing variable in the temporary storage, and then the calibration timing variable in the temporary storage is stored in the persistent storage. The second update cycle is longer than the first update cycle.
[0009] In some embodiments, when a target slot is found, a timer instance is created based on the target slot, including: When a target slot is found, update the status of the target slot to the stopped state; Configure initial independent and global parameters for the timer instance corresponding to the target slot. The independent parameters are a set of parameters for timing logic and state management specific to each timer instance, while the global parameters include real-time timing variables and calibration timing variables.
[0010] In some embodiments, the independent parameters of the timer instance include the timing end point, and the timer management method further includes: In response to the remaining time query event, the calibration timing variable stored in persistent storage is read and the read calibration timing variable is assigned to the real-time timing variable in temporary storage. The remaining time value of the timer instance is calculated based on the timer instance's timing end point and the reassigned real-time timing variable.
[0011] In some embodiments, the timer management method further includes: In response to a reset event, determine the current reset mode; Update the independent parameters and real-time timing variables of the timer instance based on the type of the current reset mode.
[0012] In some embodiments, the independent parameters of a timer instance include a timing start point, a timing end point, and a timer start duration, while the global parameters of the timer instance include a global stop threshold. Based on the type of the current reset mode, the independent parameters and real-time timing variables of the timer instance are updated, including: When the current reset mode is the stop timing mode, update the status of all slots to the stop state, set the global stop threshold, timing start, timing end and timer start duration of all timer instances to zero, keep the calibration timing variables of each timer instance in the persistent memory unchanged and assign them to their respective real-time timing variables. When the current reset mode is re-timing mode, the calibration timing variables of each timer instance in persistent memory are assigned to their respective real-time timing variables. The timing start and timing end points are recalculated based on the real-time timing variables of each timer instance, and each timer instance starts timing again. When the current reset mode is the continue timing mode, the calibration timing variable of each timer instance in the persistent memory is assigned to its respective real-time timing variable, the timing start and timing end points of each timer instance before the reset are retained, and each timer instance continues timing from the timing state before the reset.
[0013] In some embodiments, the independent parameters of a timer instance include a timing start point, a timing end point, and a timer start duration; the global parameters of a timer instance include a global stop threshold; the timer management method further includes: Iterate through the timing endpoints of each timer instance and set the largest timing endpoint as the global stop threshold shared by all timer instances; Real-time monitoring of the numerical relationship between the calibration timing variables of each timer instance and the global stop threshold; When the calibration timing variable of any timer instance is greater than the global stop threshold, the state of all timer instances is uniformly set to the stop state; When a new timer instance is created and started, and the timing endpoint of the new timer instance is greater than the current global stop threshold, the timing endpoint of the new timer instance is immediately updated to the new global stop threshold. At the same time, the stop status control of all timer instances is restored, and the status determination mechanism based on the global stop threshold is reactivated.
[0014] In some embodiments, storing calibration timing variables in temporary storage memory to persistent storage includes: Perform an unlock operation on the persistent memory, and erase the preset fixed sectors in the persistent memory after the unlock is completed; After the fixed sector is erased, the calibration timing variable in the temporary storage is written to the fixed sector of the persistent storage. After the calibration timing variables are written, a locking operation is performed on the persistent memory.
[0015] In some embodiments, the timer management method further includes: In response to the reset mode configuration event, the reset mode configuration interface function is invoked; Determine the timer start status of the timer instance; If the timer instance has not started timing, the reset mode is directly updated based on the reset mode configuration interface function. If the timer instance has already started timing, determine whether to include the reset mode parameter when calling the reset mode configuration interface function; If a reset mode parameter is provided, the variable value of the reset mode will be modified to that reset mode parameter; if no reset mode parameter is provided, the reset mode to be used subsequently will be configured as the default reset mode.
[0016] According to a second aspect of this disclosure, an electronic device is provided, comprising a processor, a temporary storage memory, and a persistent memory, both of which are communicatively connected to the processor, and the processor is configured to execute the timer management method provided in the first aspect of this disclosure.
[0017] In some embodiments, the electronic device is an embedded device.
[0018] The timer management method and electronic device provided in this disclosure can achieve the following technical effects: By pre-creating multiple independent slots, dedicated resource space is provided for multiple timer instances created concurrently by multiple timed tasks, eliminating the need for user-defined management logic and significantly reducing development and adaptation costs. When a new timer instance needs to be created, iteratively selecting available target slots to create the instance, with each instance running on an independent slot, achieving resource isolation and fundamentally avoiding resource conflicts such as temporary storage overflow and timing synchronization deviation, ensuring stable operation of the electronic device. Furthermore, dual timing variables are configured for the timer instances: a real-time timing variable and a calibration timing variable. The calibration timing variable employs a dual storage mechanism of temporary storage and persistent storage. Even if the electronic device is powered off, the calibration timing variable stored in the persistent storage will not be lost. After power-on, the timing progress before the power outage can be resumed based on the calibration timing variable, preventing long-cycle timed tasks from being interrupted and ensuring timing continuity. Furthermore, the real-time timing variable is updated incrementally with a shorter first update cycle to ensure the real-time performance of the timing; the calibration timing variable is updated with a longer second update cycle. This variable update mechanism with differentiated cycles avoids frequent erasure and writing of persistent memory, greatly reduces hardware wear and tear, extends its service life, and at the same time ensures data security through periodic synchronization, achieving a balance between hardware lifespan and data reliability.
[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this disclosure. Attached Figure Description
[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of an electronic device provided in an embodiment of this disclosure; Figure 2 This is a flowchart illustrating a timer management method provided in an embodiment of this disclosure; Figure 3 This is a flowchart illustrating another timer management method provided in an embodiment of this disclosure; Figure 4 This is a flowchart illustrating another timer management method provided in an embodiment of this disclosure; Figure 5 This is a flowchart illustrating another timer management method provided in an embodiment of this disclosure. Detailed Implementation
[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0023] Unless otherwise stated, the term "multiple" means two or more.
[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0027] like Figure 1 As shown, this disclosure provides an electronic device including a processor, a temporary storage memory, and a persistent memory, both of which are communicatively connected to the processor. The processor, as the core control and execution entity, can respond to various events such as timer creation, execution, querying, and reset to complete target slot selection, timer instance creation and startup, manage differentiated updates of dual timing variables and dual storage synchronization (driving real-time timing variables to increment according to different periods and writing calibration timing variables to persistent memory), handle the configuration and execution logic of the reset mode and update timer parameters and timing status according to the reset mode, and simultaneously implement the setting and monitoring of the global stop threshold and the secure control of persistent memory read / write operations.
[0028] In some embodiments, the device is an embedded device. For example, the electronic device may specifically include industrial control devices (such as PLC controllers, servo drive control units), Internet of Things sensing terminals (such as environmental monitoring nodes, smart door lock control modules), smart meters (such as smart meters, gas meters, hydrological monitoring instruments), and may also include vehicle-mounted embedded units (such as vehicle-mounted sensor control modules, vehicle electronic control units), medical embedded devices (such as portable medical testing instrument control modules), etc.
[0029] In conjunction with the electronic device provided in this disclosure embodiment, this disclosure embodiment provides a timer management method, wherein the execution subject of the timer management method is the processor in the electronic device, such as... Figure 2 As shown, the timer management methods include: S201, In response to the timer creation request, the processor traverses multiple pre-created independent slots and selects the target slot that is currently idle.
[0030] In this embodiment, multiple independent slots can be constructed using a global static array or a Java instance object, with each slot uniquely corresponding to a timer instance. The number of slots can be determined according to actual design needs; for example, 32 slots can be constructed, with the index of the timer instance corresponding to each slot starting at 0 and reaching a maximum of 31.
[0031] In this embodiment, all slots are initially set to "idle" by default, forming a standardized instance resource pool. When a timer instance is created based on a slot, the slot's state switches to "non-idle." The "non-idle" state is an identifier of slot occupancy, and its core function is to lock the current slot resource, preventing the system from creating a new timer instance based on that slot and avoiding resource conflicts. The specific type of the "non-idle" state can be flexibly defined according to actual design requirements and timer operation scenarios. For ease of understanding and description, slots currently in the "idle" state are uniformly referred to as "target slots," which are the core resource slots to be allocated when the processor responds to a timer creation request.
[0032] S202, when the processor finds the target slot, it creates a timer instance (DSTimer) based on the target slot.
[0033] In this embodiment, the timer instance is configured with a real-time timing variable (SysTimerValue) and a calibration timing variable (StaticDSTimerValue), both of which are two long integers. The real-time timing variable is stored in temporary storage, while the calibration timing variable is stored in both temporary and persistent storage. The calibration timing variable serves as both a "calibration baseline" and a "backup copy" of the timing data, and its value can be kept synchronized with the real-time timing variable.
[0034] In the embodiments of this disclosure, temporary storage memory may be RAM (Random Access Memory), SRAM (Static Random Access Memory), or DRAM (Dynamic Random Access Memory); persistent storage memory may be Flash Memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), NAND Flash (NAND-type Flash Memory), or SD card (Secure Digital Memory Card), etc.
[0035] S203, In response to the timer run request, the processor starts a timer instance to start timing.
[0036] S204: The processor drives the real-time timing variable to increment and update every time the first update cycle is completed.
[0037] S205, after each second update cycle, the processor assigns the real-time timing variable in the temporary storage to the calibration timing variable in the temporary storage, and then stores the calibration timing variable in the temporary storage to the persistent storage.
[0038] In this embodiment, the second update cycle is longer than the first update cycle. For example, the first update cycle is 1 second, and the second update cycle is 60 seconds. Both the real-time timing variable and the calibration timing variable are counted starting from 0. The real-time timing variable can be updated by the processor's SysTick interrupt. The SysTick interrupt cycle is preset to 1 second. Each time an interrupt is triggered, a corresponding function (such as DSTimer_UpdateSysTime) is called to increment the real-time timing variable by 1, ensuring the continuity and real-time performance of the timing. Furthermore, the increment error of the real-time timing variable is ≤10ms / second, meeting the second-level timing accuracy requirements of embedded scenarios. A synchronization process between the real-time timing variable and the calibration timing variable is triggered every 60 seconds. The real-time timing variable in the temporary storage is assigned to the calibration timing variable in the temporary storage, and then a corresponding function (such as DSTimer_WriteFlas) is called to store the calibration timing variable in the temporary storage to persistent storage. This 60-second cycle design avoids shortening the hardware lifespan caused by frequent erasure and writing of persistent memory, and ensures that only 60 seconds of timing data are lost in the event of a power outage, with a synchronization error of ≤5ms.
[0039] The timer management method provided in this disclosure pre-creates multiple independent slots, providing dedicated resource space for multiple timer instances created concurrently by multiple timed tasks. This eliminates the need for user-defined management logic, significantly reducing development and adaptation costs. When a new timer instance needs to be created, it iterates through available target slots to create the instance. Each instance runs on an independent slot, achieving resource isolation and fundamentally avoiding resource conflicts such as temporary storage overflow and timing synchronization deviations, ensuring stable operation of the electronic device. Furthermore, dual timing variables are configured for each timer instance: a real-time timing variable and a calibration timing variable. The calibration timing variable employs a dual storage mechanism of temporary storage and persistent storage. Even if the electronic device is powered off, the calibration timing variable stored in persistent storage will not be lost. Upon power-up, the timing progress before the power outage can be resumed based on the calibration timing variable, preventing long-cycle timed tasks from being interrupted and ensuring timing continuity. Furthermore, the real-time timing variable is updated incrementally with a shorter first update cycle to ensure the real-time performance of the timing; the calibration timing variable is updated with a longer second update cycle. This variable update mechanism with differentiated cycles avoids frequent erasure and writing of persistent memory, greatly reduces hardware wear and tear, extends its service life, and at the same time ensures data security through periodic synchronization, achieving a balance between hardware lifespan and data reliability.
[0040] In some embodiments, when a target slot is found, a timer instance is created based on the target slot, including: updating the state of the target slot to a stopped state when the target slot is found; and configuring initial independent parameters and global parameters for the timer instance corresponding to the target slot. Here, independent parameters are a set of parameters for timing logic and state management specific to each timer instance, and global parameters include real-time timing variables and calibration timing variables.
[0041] When creating an instance, the target slot is updated from "idle" to "stopped" status, explicitly marking the slot as occupied. This effectively prevents other creation requests from repeatedly allocating the slot, avoiding resource conflicts in multi-instance concurrent scenarios from the source. By uniformly configuring initial independent parameters and global parameters for timer instances, the parameter system of each timer instance is ensured to be complete and formatted consistently, avoiding timing logic disorder caused by missing parameters or inconsistent configurations.
[0042] like Figure 3 As shown in the embodiments of this disclosure, another timer management method is provided, which includes: S301, in response to the timer creation request, the processor traverses multiple pre-created independent slots and selects the target slot that is currently idle.
[0043] S302, when the processor finds a target slot, it updates the status of the target slot to the stopped state.
[0044] S303, the processor configures the initial independent and global parameters for the timer instance corresponding to the target slot.
[0045] S304, In response to a timer run request, the processor starts a timer instance to begin timing.
[0046] In the S305, the processor drives the real-time timing variable to increment and update every time the first update cycle is completed.
[0047] S306: Every second update cycle, the processor assigns the real-time timing variable in the temporary storage to the calibration timing variable in the temporary storage, and then stores the calibration timing variable in the temporary storage to the persistent storage.
[0048] In some embodiments, the independent parameters of the timer instance include the timing end point, and the timer management method further includes: in response to a remaining time query event, reading the calibration timing variable stored in persistent storage, assigning the read calibration timing variable to a real-time timing variable in temporary storage; and calculating the remaining time value of the timer instance based on the timing end point of the timer instance and the reassigned real-time timing variable.
[0049] like Figure 4 As shown in the embodiments of this disclosure, another timer management method is provided, which includes: S401, in response to the timer creation request, the processor traverses multiple pre-created independent slots and selects the target slot that is currently idle.
[0050] S402, when the processor finds a target slot, it updates the status of the target slot to the stopped state.
[0051] S403, the processor configures the initial independent and global parameters for the timer instance corresponding to the target slot.
[0052] S404, In response to a timer run request, the processor starts a timer instance to begin timing.
[0053] In the S405, the processor drives the real-time timing variable to increment and update every time the first update cycle is completed.
[0054] S406: Every second update cycle, the processor assigns the real-time timing variable in the temporary storage to the calibration timing variable in the temporary storage, and then stores the calibration timing variable in the temporary storage to the persistent storage.
[0055] S407, in response to the remaining time query event, the processor reads the calibration timing variable stored in persistent memory and assigns the read calibration timing variable to the real-time timing variable in temporary memory.
[0056] S408, the processor calculates the remaining time value of the timer instance based on the timer instance's timing end point and the reassigned real-time timing variable.
[0057] In this embodiment, when it is necessary to query the remaining time, the remaining time query interface function (DSTimer_GetRemainingTime) can be called to read the calibration timing variable stored in persistent storage and assign it to the real-time timing variable in temporary storage. The difference between the timing end of the timer instance and the real-time timing variable is calculated, and this difference is used as the remaining time value of the timer instance. If the difference is negative, it indicates that the timer instance has timed out, and the timer instance is marked as stopped.
[0058] In some embodiments, storing calibration timing variables in temporary storage memory to persistent storage memory includes: performing an unlock operation on persistent storage memory, and erasing a preset fixed sector in persistent storage memory after unlocking; writing the calibration timing variables in temporary storage memory to a fixed sector in persistent storage memory after the fixed sector is erased; and performing a lock operation on persistent storage memory after the calibration timing variables are written.
[0059] By establishing standardized processes for unlocking, erasing, writing, and locking, a closed-loop storage operation logic is constructed. The unlocking operation ensures that the persistent storage is in a writable state, avoiding write failures due to hardware locking; the targeted erasure of preset fixed sectors can clear historical invalid data in those sectors, preventing storage errors caused by the superposition of old and new data, and providing a clean storage environment for new data writing; the locking operation after writing directly blocks subsequent erroneous operations, ensuring the data integrity after the calibration timing variable is written, and avoiding storage anomalies caused by missing processes.
[0060] like Figure 5 As shown in the embodiments of this disclosure, another timer management method is provided, which includes: S501: In response to a timer creation request, the processor traverses multiple pre-created independent slots and selects the target slot that is currently idle.
[0061] S502: When the processor finds a target slot, it creates a timer instance based on the target slot.
[0062] S503: In response to a timer run request, the processor starts a timer instance to perform timing.
[0063] In the S504, the processor drives the real-time timing variable to increment and update every time the first update cycle is completed.
[0064] In S505, every second update cycle, the processor assigns the real-time timing variable in the temporary storage to the calibration timing variable in the temporary storage.
[0065] S506, the processor performs an unlock operation on the persistent memory, and after the unlock is completed, erases the preset fixed sectors in the persistent memory.
[0066] S507: After the processor finishes erasing the fixed sector, it writes the calibration timing variable from the temporary storage to the fixed sector of the persistent storage.
[0067] After the processor has finished writing the timing variables to be calibrated, it performs a locking operation on the persistent memory.
[0068] In some embodiments, the timer management method further includes: the processor responding to a reset event to determine the current reset mode; and the processor updating the independent parameters and real-time timing variables of the timer instance according to the type of the current reset mode.
[0069] The independent parameters of a timer instance include the timing start point (long TimerStartValue), the timing end point (long TimerEndValue), and the timer start duration (byte TimerLong). The global parameters of a timer instance include the real-time timing variable, the calibration timing variable, and the global stop threshold (static long StaticTimeStopValue).
[0070] The reset modes include Stop Timing mode, Reset Timing mode, and Continue Timing mode. Stop Timing mode terminates the timing of all timer instances after a reset; Reset Timing mode starts a new timing cycle based on the calibration timing value stored in persistent memory after a reset; Continue Timing mode retains the original timing parameters of all timer instances after a reset, continuing the timing progress from before the reset.
[0071] When the current reset mode is the stop timing mode, the processor updates the state of all slots to the stop state, sets the global stop threshold, timing start, timing end, and timer start duration of all timer instances to zero, keeps the calibration timing variables of each timer instance in persistent memory unchanged, and assigns them to their respective real-time timing variables.
[0072] When the current reset mode is re-timing mode, the processor assigns the calibration timing variables of each timer instance in persistent memory to their respective real-time timing variables, recalculates the timing start and timing end based on the real-time timing variables of each timer instance, and each timer instance starts timing again.
[0073] When the current reset mode is the continue timing mode, the processor assigns the calibration timing variables of each timer instance in the persistent memory to their respective real-time timing variables, retains the timing start and timing end points of each timer instance before the reset, and each timer instance continues timing from the timing state before the reset.
[0074] In this embodiment, three configurable modes—stop timing, restart timing, and continue timing—are provided to meet reset requirements in different business scenarios, covering all scenarios such as factory reset, daily restart, and fault recovery. For example, when the equipment is shut down for maintenance, the stop timing mode can be selected to terminate all timing tasks without the need to develop additional differentiated reset processing logic; when the equipment is restarted after an abnormal power outage, the continue timing mode can be selected to retain the timing progress of the business process; and when the equipment is reset after a functional upgrade, the restart timing mode can be selected to start a new timing cycle.
[0075] In some embodiments, the type of reset mode (TimerDefaultMode) can be dynamically configured. Specifically, in response to a reset mode configuration event, the processor calls the reset mode configuration interface function (DSTimer_SetTimerDefaultMode); determines the timing start status of the timer instance; if the timer instance has not started timing, the processor directly updates the reset mode based on the reset mode configuration interface function; if the timer instance has started timing, the processor determines whether the reset mode parameter (TimerMode) is carried when calling the reset mode configuration interface function; if the reset mode parameter is carried, the variable value of the reset mode is modified to the reset mode parameter; if the reset mode parameter is not carried, the reset mode used subsequently is configured as the default reset mode.
[0076] When configuring the reset mode type, two scenarios were fully considered: timer instances that have not started timing and those that have started timing. A corresponding reset mode adjustment method was set for each scenario. For timer instances that have started timing, the reset mode configuration can be completed regardless of whether the reset mode parameter is included when calling the reset mode configuration interface function. This allows developers to precisely specify the reset mode according to specific business scenarios, and also allows the reuse of the default mode when no custom configuration is needed. This effectively reduces the redundancy of parameter passing during development and improves the usability of the solution. Furthermore, for timer instances that have started timing, dynamic configuration only updates the mode parameters without changing the current timing parameters or running status, ensuring continuous execution of timing tasks and avoiding timing deviations or task failures caused by mode adjustments. For instances that have not started timing, the default mode can be directly updated, and the new configuration will be automatically used upon subsequent startups without additional secondary configuration operations. This reduces the complexity of the configuration process and ensures the consistency of mode configuration.
[0077] In some embodiments, the timer management method further includes: the processor iterating through the timing endpoints of each timer instance and setting the largest timing endpoint as a global stop threshold shared by all timer instances; real-time monitoring of the numerical relationship between the calibration timing variable of each timer instance and the global stop threshold; when the calibration timing variable of any timer instance is greater than the global stop threshold, the processor uniformly sets the state of all timer instances to the stopped state; when a new timer instance is created and started timing, and the timing endpoint of the new timer instance is greater than the current global stop threshold, the processor immediately updates the timing endpoint of the new timer instance to the new global stop threshold, and at the same time restores the control over the stopped state of all timer instances, and reactivates the state determination mechanism based on the global stop threshold.
[0078] This embodiment sets the maximum timing endpoint as a global stop threshold shared by all timer instances. This eliminates the need to monitor the timing progress of each timer instance individually. When the calibration timing variable exceeds the global stop threshold, all timer instances are uniformly set to a stopped state, avoiding logical redundancy and scheduling overhead caused by scattered monitoring of multiple timer instances, thus improving system efficiency. This design solves the problem of individually determining the timeout status of multiple timer instances, reducing the frequency of timer status checks by the processor. Furthermore, when a new timer instance starts, if its timing endpoint exceeds the current global stop threshold, the threshold is immediately updated and the status determination mechanism is reactivated, ensuring that the timing requirements of the new instance are promptly incorporated into global management without affecting the normal operation of existing timer instances. Whether it's a new long-cycle timer instance or a short-term task instance, the global stop threshold can be adaptively adjusted without manual configuration of threshold parameters, improving the solution's adaptability to diverse timing tasks.
[0079] In some embodiments, the validity of the calibration timing variable needs to be verified each time it is read from the persistent storage. Specifically, it can be determined whether the calibration timing variable exceeds a preset calibration timing variable range; if the calibration timing variable does not exceed the calibration timing variable range, the calibration timing variable is considered valid; otherwise, the calibration timing variable is considered invalid. For example, the calibration timing variable range is 0 to 1 × 10⁻⁶. 9 When the calibration timing variable is between 0 and 1 × 10 9 When the time interval is within a certain range, the calibration timing variable is considered valid; when the calibration timing variable is less than 0 or greater than 1×10⁻⁶, the calibration timing variable is considered valid. 9 If this occurs, the calibration timing variable is deemed invalid.
[0080] In some embodiments, the electronic device executes a timer instance scanning process each time it is powered on. The timer instance scanning process includes: reading each calibration timing variable in persistent memory and initializing the global stop threshold to 0; traversing each timer instance, if the timer instance is valid, reading its reset mode, initializing the timing start point according to the corresponding reset mode, initializing the timing end point using the timer start duration; and finally updating the global stop threshold.
[0081] In some embodiments, after each second update cycle, the real-time timing variable in the temporary storage is assigned to the calibration timing variable in the temporary storage, and then the calibration timing variable in the temporary storage is stored in the persistent storage. If the calibration timing variable is not successfully stored in the persistent storage, the number of failures is recorded and the process is retried after the second update cycle. The number of retries does not exceed a preset number (e.g., 3 times).
[0082] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.
[0083] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0084] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces. The indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0085] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the figures. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the figures, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer commands.
Claims
1. A timer management method, characterized by, include: In response to a timer creation request, it iterates through multiple pre-created independent slots and selects the target slot that is currently idle. When a target slot is found, a timer instance is created based on the target slot. The timer instance is configured with a real-time timing variable and a calibration timing variable. The real-time timing variable is stored in a temporary storage, while the calibration timing variable is stored in both temporary storage and persistent storage. In response to a timer run request, start the timer instance to begin timing; After each of the first update cycles, the real-time timing variable is incremented and updated. After each second update cycle, the real-time timing variable in the temporary storage is assigned to the calibration timing variable in the temporary storage, and then the calibration timing variable in the temporary storage is stored in the persistent storage. The second update cycle is longer than the first update cycle.
2. The timer management method according to claim 1, characterized in that, When a target slot is found, a timer instance is created based on the target slot, including: When a target slot is found, update the status of the target slot to the stopped state; Configure initial independent and global parameters for the timer instance corresponding to the target slot. The independent parameters are a set of parameters for timing logic and state management specific to each timer instance, while the global parameters include real-time timing variables and calibration timing variables.
3. The timer management method according to claim 2, characterized in that, The independent parameters of a timer instance include the timing end point, and timer management methods also include: In response to the remaining time query event, the calibration timing variable stored in persistent storage is read and the read calibration timing variable is assigned to the real-time timing variable in temporary storage. The remaining time value of the timer instance is calculated based on the timer instance's timing end point and the reassigned real-time timing variable.
4. The timer management method according to claim 2, characterized in that, Timer management methods also include: In response to a reset event, determine the current reset mode; Update the independent parameters and real-time timing variables of the timer instance based on the type of the current reset mode.
5. The timer management method of claim 4, wherein, The independent parameters of a timer instance include the timing start point, timing end point, and timer start duration. The global parameters of a timer instance include the global stop threshold. Based on the current reset mode type, the independent parameters and real-time timing variables of the timer instance are updated, including: When the current reset mode is the stop timing mode, update the status of all slots to the stop state, set the global stop threshold, timing start, timing end and timer start duration of all timer instances to zero, keep the calibration timing variables of each timer instance in the persistent memory unchanged and assign them to their respective real-time timing variables. When the current reset mode is re-timing mode, the calibration timing variables of each timer instance in persistent memory are assigned to their respective real-time timing variables. The timing start and timing end points are recalculated based on the real-time timing variables of each timer instance, and each timer instance starts timing again. When the current reset mode is the continue timing mode, the calibration timing variable of each timer instance in the persistent memory is assigned to its respective real-time timing variable, the timing start and timing end points of each timer instance before the reset are retained, and each timer instance continues timing from the timing state before the reset.
6. The timer management method of claim 2, wherein, The independent parameters of a timer instance include the timer start point, timer end point, and timer start duration; the global parameters of a timer instance include the global stop threshold; timer management methods also include: Iterate through the timing endpoints of each timer instance and set the largest timing endpoint as the global stop threshold shared by all timer instances; Real-time monitoring of the numerical relationship between the calibration timing variables of each timer instance and the global stop threshold; When the calibration timing variable of any timer instance is greater than the global stop threshold, the state of all timer instances is uniformly set to the stop state; When a new timer instance is created and started, and the timing endpoint of the new timer instance is greater than the current global stop threshold, the timing endpoint of the new timer instance is immediately updated to the new global stop threshold. At the same time, the stop status control of all timer instances is restored, and the status determination mechanism based on the global stop threshold is reactivated.
7. The timer management method of claim 1, wherein, Storing calibration timing variables from temporary storage to persistent storage includes: Perform an unlock operation on the persistent memory, and erase the preset fixed sectors in the persistent memory after the unlock is completed; After the fixed sector is erased, the calibration timing variable in the temporary storage is written to the fixed sector of the persistent storage. After the calibration timing variables are written, a locking operation is performed on the persistent memory.
8. The timer management method of claim 1, wherein, Also includes: In response to the reset mode configuration event, the reset mode configuration interface function is invoked; Determine the timer start status of the timer instance; If the timer instance has not started timing, the reset mode is directly updated based on the reset mode configuration interface function. If the timer instance has already started timing, determine whether to include the reset mode parameter when calling the reset mode configuration interface function; If a reset mode parameter is provided, modify the variable value of the reset mode to that reset mode parameter. If no reset mode parameter is provided, the reset mode to be used subsequently will be the default reset mode.
9. An electronic device, comprising: It includes a processor, temporary storage, and persistent storage, both of which are communicatively connected to the processor, which is configured to execute the timer management method as described in any one of claims 1 to 8.
10. The electronic device of claim 9, wherein, The electronic device is an embedded device.