Clock monitoring for memory devices

Abstract

Clock monitoring for memory devices is described herein. Clock signals of those components (e.g., logic blocks) of the memory device that are identified as being associated with causing a failure of other components can be selectively monitored. This eliminates the need to monitor all of the components, which may be unnecessary to monitor at least a portion of the components may not be fully used while the memory device is in an autonomous mode.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory systems and subsystems, and more specifically, to clock monitoring for memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices.

[0003] Vehicles are increasingly reliant on memory subsystems to provide storage for previously mechanical, stand-alone, or non-existent components. Vehicles may include computing systems, which may serve as the host for the memory subsystems. The computing system may run applications that provide component functionality. Vehicles may be driver-operated, driverless (autonomous), and / or partially autonomous. The computing systems within vehicles may make extensive use of memory devices. Summary of the Invention

[0004] On one hand, this disclosure provides a method for clock monitoring, comprising: determining whether a corresponding clock signal provided to a first group of logic blocks is identified by a failure analysis; and in response to determining that the clock signal of one or more logic blocks provided to the first group of logic blocks is identified by the failure analysis, selectively routing the identified clock signal to a monitoring circuit system to monitor the clock signal.

[0005] On the other hand, this disclosure provides a device for clock monitoring, comprising: a first group of logic blocks configured to operate during a first operating state of the device; and a controller configured to selectively route corresponding clock signals of one or more logic blocks in the first group to a monitoring circuit system to monitor the corresponding clock signals, wherein the corresponding clock signals are identified as being associated with a related failure of a logic block in the first group.

[0006] On the other hand, this disclosure provides a device for clock monitoring, comprising: a first group of logic blocks configured to operate based on a first clock signal during the autonomous mode of the device; and a controller configured to monitor selected clock signals provided to one or more logic blocks in the first group and identified as being associated with a related failure of a logic block in the first group. Attached Figure Description

[0007] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the various embodiments thereof.

[0008] Figure 1 The description includes examples of computing systems that include a memory subsystem having a clock monitoring component operating according to some embodiments of the present disclosure.

[0009] Figure 2 Examples of systems according to some embodiments of the present disclosure are described, illustrating at least a portion of a controller for monitoring clock signal failures of logic blocks associated with operating a computing system.

[0010] Figure 3 This is a flowchart of an example method for clock monitoring of a memory device according to some embodiments of the present disclosure.

[0011] Figure 4 Examples of systems including a computing system in a vehicle are described according to some embodiments of the present disclosure. Detailed Implementation

[0012] This disclosure relates to clock monitoring for memory devices. A memory subsystem can be a storage system, a storage device, a memory module, or a combination thereof. Examples of memory subsystems are storage systems, such as solid-state drives (SSDs), universal flash memory (UFS) drives, etc. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem. As an example, a vehicle may include a memory subsystem, such as an SSD, UFS, etc. The memory subsystem can be used for data storage by various components of the vehicle (such as applications running on the vehicle's host system).

[0013] Accurate and reliable clock signals are indispensable for the operation of autonomous devices (e.g., autonomous vehicles, drones, vacuum cleaners, industrial robots, medical robots, etc.) because they ensure synchronization across multiple electronic control units, allowing for the coordinated operation necessary for autonomous driving tasks. Precise clock signals maintain the exact timing of communication protocols, ensuring seamless data exchange between sensors, processors, and actuators. More specifically, this accuracy is crucial for the real-time decision-making processes of autonomous vehicles, such as collision avoidance, lane keeping, and adaptive cruise control. Autonomous vehicles rely on accurate clock signals to process sensor and camera inputs in real time, enabling timely responses and enhancing overall safety and reliability during autonomous operation.

[0014] To ensure the reliability of clock signals, some methods may include clock monitoring systems designed to detect any clock failures that may indicate hardware or system malfunctions during the autonomous operation of these devices. While these monitoring systems are typically used continuously to maintain reliability, they can lead to significant power consumption. Furthermore, such systems (which require continuous monitoring of numerous hardware blocks) can be complex and relatively large, potentially increasing the overall design complexity of the computing systems used in autonomous devices.

[0015] This disclosure addresses the aforementioned and other problems by selectively monitoring clock signals, for example, depending on whether the clock signal is a "necessary" signal for autonomous operation of the device. For example, according to embodiments of this disclosure, the clock monitoring system can continuously monitor clock signals whose failure is likely to cause the failure of other components of the autonomous device (among those "necessary" signals). However, non-necessary clock signals are monitored periodically as needed. Compared to a clock monitoring system that operates continuously for each clock signal, this reduces the power consumption and area required by the clock monitoring system, for example, by 5%. Furthermore, the clock monitoring system of this disclosure is designed to be relatively compact and less complex, thereby simplifying the overall design complexity of the computing system used in the autonomous device.

[0016] In various embodiments, the clock monitoring system is implemented as a hardware component, such as a dedicated circuit system, thereby eliminating reliance on firmware-based (e.g., periodic) clock monitoring. This design improves system efficiency by enhancing response time to the host. Additionally, because clock monitoring operates independently of other components (e.g., the central processing unit (CPU) and static random access memory (SRAM)), it is unaffected by failures in these components, ensuring continuous operation and significantly improving system reliability and robustness.

[0017] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, 112 could refer to... Figure 1 Component "12" in the text, and similar components can be found in the text. Figure 2 The figure is labeled 212. Similar elements within the figure can be referenced using hyphens and additional numbers or letters. Such similar elements can typically be referenced without hyphens and additional numbers or letters. For example, Figure 2Elements 222-1, 222-2, ..., 222-N in the figures may be collectively referred to as 222. As used herein, particularly with respect to the reference numerals in the figures, the designations “N,” “M,” “P,” “X,” or “Q” may indicate several specific features as thus specified. It will be understood that elements shown herein in various embodiments may be added, interchanged, and / or deleted to provide several additional embodiments of the present disclosure. Furthermore, it will be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be interpreted in a limiting sense.

[0018] Figure 1 This description describes an example computing system 100 that includes a memory subsystem 104 (alternatively referred to as memory device 104) operating according to some embodiments of this disclosure. The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car, or other means of transport), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer contained in a vehicle, industrial equipment, or networked business device), or such a computing device including memory and processing power.

[0019] The computing system 100 includes a host system 102 coupled to one or more memory subsystems 104. For example, the host system 102 may be a computing system included in a vehicle, and the computing system may run applications that provide component functionality for the vehicle. In some embodiments, the host system 102 is coupled to different types of memory subsystems 104. Figure 1 This describes an example of a host system 102 coupled to a memory subsystem 104. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including, for example, electrical, optical, magnetic, and similar connections.

[0020] Host system 102 includes or is coupled to processing resources, memory resources, and network resources. As used herein, a “resource” is a physical or virtual component with limited availability within computing system 100. For example, processing resources include processing devices, memory resources include a memory subsystem 104 for secondary storage and a main memory device (not specifically described) for primary storage, and network resources include network interfaces (not specifically described). The processing device may be one or more processor chipsets capable of executing a software stack. The processing device may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, etc.). Host system 102 uses memory subsystem 104, for example, to write data to and read data from memory subsystem 104.

[0021] The host system 102 may run one or more applications. For example, the applications may run on an operating system (not specifically described) executed by the host system 102. An operating system is system software that manages computer hardware and software resources and provides public services to applications. An application is a collection of instructions that can be executed to perform a specific task. For example, an application may be a black-box application for a vehicle; however, the embodiments are not limited to this.

[0022] Host system 102 can be coupled to memory subsystem 104 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 102 and memory subsystem 104. When memory subsystem 104 is coupled to host system 102 via a PCIe interface, host system 102 can further utilize an NVM Fast (NVMe) interface to access non-volatile memory device 116. The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 104 and the host system 102. Figure 1 For example, memory subsystem 104 is described. Generally, host system 102 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] like Figure 1 As described herein, host 102 and memory subsystem 104 are further coupled to device control 118. For example, when one or more devices (e.g., autonomous devices) are operated autonomously or partially autonomously, device control 118 can manage physical control of the devices (based on requests, commands, etc. received from host 102 or input data received from memory subsystem 104). In an example where the computing system 100 corresponds to an autonomous vehicle, the physical control of the vehicle, which can be managed by the device control unit 118, may include switching ignition or start control to control the starting of the vehicle; turning the steering wheel or steering device to control the steering of the vehicle; the route or direction of the vehicle; increasing or decreasing the speed of the vehicle by throttle or acceleration or throttle control, thereby changing the speed of the vehicle; applying or releasing the brakes; turning the turn signals on / off; controlling the lights on the vehicle (e.g., by turning the headlights, parking brake, fog lights, etc. on / off); activating warning signals (e.g., honking the horn; hazard warning lights); locking or unlocking doors; activating the windshield wipers; parking sensors or controls; and / or changing the gears of the vehicle, etc.

[0024] Host system 102 can control memory subsystem 104 and / or send requests (e.g., commands) to memory subsystem 104, for example, to store data in or read data from memory subsystem 104. For example, host system 102 can use memory subsystem 104 to provide storage for black-box applications. Data to be written to or read, as specified by a host request, is referred to as "host data". A host request may contain logical address information. Logical address information may be a logical block address (LBA), which may include or be accompanied by a partition number. Logical address information is the location associated between the host system and the host data. Logical address information may be part of the metadata of the host data. The LBA may also correspond to (e.g., dynamically mapped to) a physical address indicating the physical location of the host data in memory, such as a physical block address (PBA).

[0025] The memory subsystem 104 may include media, such as one or more volatile memory devices 115, one or more non-volatile memory devices 116, or a combination thereof. The volatile memory device 115 may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and resistive DRAM (RDRAM).

[0026] The memory subsystem 104 can be a storage device, a memory module, or a combination of both. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] Examples of non-volatile memory device 116 include NAND flash memory. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND). Non-volatile memory device 116 can be other types of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and three-dimensional cross-point memory. The cross-point array of the non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells.

[0028] Each of the non-volatile memory devices 116 may comprise one or more arrays of memory cells. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the non-volatile memory devices 116 may comprise one or more arrays of memory cells (e.g., SLC, MLC, TLC, PLC, or any combination thereof). In some embodiments, a particular memory device may comprise an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the non-volatile memory device 116 may be grouped into pages, where a page may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] The memory subsystem controller 106 (or simply controller 106) can communicate with the non-volatile memory device 116 to perform operations such as reading data, writing data, erasing data, and other such operations at the non-volatile memory device 116. The memory subsystem controller 106 may include hardware, such as one or more integrated circuits and / or discrete components or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 106 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable circuit systems.

[0030] The memory subsystem controller 106 may include a processing device 108 (e.g., a processor, which may be a central processing unit (CPU)), which may include processing resources and be configured to execute instructions stored in local memory 110. Local memory 110 may be, for example, static random access memory (SRAM). In the illustrated example, the local memory 110 of the memory subsystem controller 106 is an embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 104 (including handling communication between the memory subsystem 104 and the host system 102). For example, local memory 110 may store instructions executable by processor 108 and / or operating components 114, as will be further described herein.

[0031] In some embodiments, local memory 110 may include memory registers storing memory pointers, fetched data, etc. For example, local memory 110 may also include ROM for storing microcode. Although Figure 1The instance memory subsystem 104 has been described as including a memory subsystem controller 106, but in another embodiment of this disclosure, the memory subsystem 104 may not include a memory subsystem controller 106, but may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem 104). In some embodiments, the memory subsystem 104 may be a managed NAND (MNAND) device, wherein an external controller (e.g., controller 106) is packaged with one or more NAND dies (e.g., non-volatile memory devices 116).

[0032] Generally, the memory subsystem controller 106 can receive information or operations from the host system 102 and translate the information or operations into instructions or appropriate information to enable the desired access to the non-volatile memory device 116 and / or the volatile memory device 115. The memory subsystem controller 106 may be responsible for other operations associated with the non-volatile memory device 116, such as wear leveling operations, error detection and / or correction operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses) and physical addresses (e.g., physical block addresses). The memory subsystem controller 106 may further include a host interface circuitry for communicating with the host system 102 via a physical host interface. The host interface circuitry can translate queries received from the host system 102 into commands for accessing the non-volatile memory device 116 and / or the volatile memory device 115, and translate responses associated with the non-volatile memory device 116 and / or the volatile memory device 115 into information for the host system 102.

[0033] like Figure 1 As shown, the memory subsystem 104 may include a clock monitoring component 112 and an operation component 114. Although Figure 1 The accompanying drawings are not shown to avoid obscuring the actual contents, but the clock monitoring component 112 may include various circuit systems to facilitate the aspects of this disclosure described herein. In some embodiments, the clock monitoring component 112 and / or the operation component 114 may include firmware, dedicated circuit systems in the form of ASICs, FPGAs, state machines, hardware processing devices, and / or other logic circuit systems that allow the clock monitoring component 112 and / or the operation component 114 to orchestrate and / or perform the operations described herein.

[0034] Operation component 114 (which may be firmware or hardware or any combination thereof) manages and / or controls the operation of computing system 100 (e.g., an autonomous device). In some embodiments, at least a portion of operation component 114 may be a part (e.g., an integrated portion) of processor 108 (e.g., CPU). Operation component 114 may include various logic blocks (e.g., Figure 2The logic blocks 222-1, ..., 222-N, 224-1, ..., 224-M, 226-1, ..., 226-X described herein are used to ensure that the operation of the computing system 100 meets, for example, the security standards defined by the security standard ISO 26262, the requirements for autonomous or non-autonomous operation of the computing system 100, or any combination thereof.

[0035] Clock monitoring component 112 can monitor clock signals supplied to (e.g., being supplied to) operating component 114 to detect any clock signal failure (referred to simply as "clock failure" and alternatively as "erroneous clock signal"). Once clock signals themselves fail, it may depend on whether they play a critical role in the autonomous operation of computing system 100 and / or whether they are identified as potentially causing other components (e.g., Figure 2 The logic blocks 222, 224, and 226 described herein are disabled to selectively perform clock signal monitoring. (Combined) Figure 2 Further details describe the monitoring of logic blocks 222, 224, and 226.

[0036] Figure 2 This section describes an example of a system 200 (e.g., similar to computing system 100) according to some embodiments of the present disclosure, illustrating at least a portion of a controller 206 (e.g., similar to controller 106) for monitoring clock signal failures in logic blocks associated with operating the computing system. More specifically, Figure 2 A portion of the controller 206 described herein may be Figure 1 The clock monitoring component 112 described herein.

[0037] System 200 may include one or more clock sources, such as clock sources 220-1, ..., 220-P (collectively referred to as clock source 220 and in... Figure 2The clock signal generated at clock source 220 may be (e.g., a crystal oscillator, RC oscillator, LC oscillator, ring oscillator, etc.), phase-locked loop (PLL), or any combination thereof. The clock signal generated at clock source 220 may be (e.g., selectively) provided to clock control component 221 and monitoring circuitry 227. Furthermore, the clock signal generated at clock control component 221 may be further (e.g., selectively) provided to monitoring circuitry 227. In some embodiments, clock control component 221 may include firmware, a dedicated circuitry in the form of an ASIC, FPGA, state machine, hardware processing means, and / or other logic circuitry that allows clock control component 221 to orchestrate and / or perform the operations described herein. More specifically, clock control component 221 may be clock control logic for managing system blocks (which may be located inside and / or outside controller 206 of system 200) to enable or disable clock signals and perform clock division as needed.

[0038] In some embodiments, clock control component 221 may (at least partially) be a clock divider. As used herein, the term "clock divider" refers to an electronic circuit or device that accepts an input clock signal and generates an output clock signal that may have a different (e.g., lower) frequency. For example, clock signals generated at clock source 220 may be received at control component 221 as corresponding input clock signals, which may be further used to generate output clock signals at control component 221. Although in Figure 2 The description states that the clock source 220 and control component 221 are located outside the controller 206, but the embodiments are not limited thereto. For example, the clock source 220 and control component 221 may reside on the memory subsystem controller 206 and / or be part of the memory subsystem controller 206.

[0039] The output clock signal generated at control component 221 is further propagated and provided to the memory subsystem (e.g., Figure 1 The memory subsystem 104 described herein contains various components, logic blocks, etc., which may include a processor 208 (similar to...). Figure 1 The processor 108 described herein, the first logic blocks 222-1, ..., 222-N (collectively referred to as logic block 222), the second logic blocks 224-1, ..., 224-M (collectively referred to as logic block 224), and the third logic blocks 226-1, ..., 226-X (collectively referred to as logic block 226) are described herein. As used herein, the term "logic block" refers to a unit of hardware (e.g., physical) component (typically accompanied by corresponding firmware) that performs a specific function that may be necessary for the overall operation of the system (e.g., the operation of system 200).

[0040] Logic block 222 (alternatively referred to as "mission mode logic") may be configured to and / or be responsible for actively executing autonomous (e.g., in autonomous mode) the operating system 200 (e.g., Figure 1 The computing system 100 described herein and / or those logical blocks that perform tasks required to meet safety requirements (as defined by ISO 26262) when the system 200 operates in autonomous mode. As used herein, the term "autonomous mode" (alternately referred to as "mission mode") refers to an operational state in which an autonomous device actively performs its predefined tasks or missions with reduced human intervention. For example, an autonomous device may perform various specific operations specific to autonomous mode, such as autonomous navigation, decision-making, operations suitable for safety and efficiency, and the execution of actions required to achieve specific goals set by the user or system, but embodiments are not limited thereto. Furthermore, as used herein, the term "non-autonomous mode" (alternately referred to as "non-mission mode") refers to an operational state in which an autonomous device does not actively perform its predefined tasks or missions, which may require additional human intervention during system operation. Although embodiments are not limited thereto, logic block 222 may also include processing resources, such as firmware, CPU, or any combination thereof (e.g., Figure 1 The processor / processing resource 108 described in the document.

[0041] Logic block 224 may be those logic blocks configured to and / or responsible for actively performing tasks required by the non-autonomous (e.g., in non-autonomous mode) operating system 200. This may include ensuring that the non-autonomous operating system 200 meets safety requirements as defined by ISO 26262. For example, although embodiments are not limited thereto, logic block 224 may include a safety microcontroller (e.g., configured for error detection, correction, etc. to ensure the reliability of operating the autonomous device), logic blocks for controlling brake-by-wire or steering-by-wire systems, safety power supply units (e.g., ensuring uninterrupted power supply to various components of the autonomous device), functional safety monitors (e.g., monitoring the performance and health of critical systems, detecting faults and initiating safety measures), logic blocks for controlling health monitoring systems (e.g., monitoring the performance of the autonomous device, ensuring operation within safety parameters and initiating corrective actions when deviations are detected), logic blocks for controlling emergency stop systems (e.g., emergency braking systems), logic blocks for controlling fail-safe actuators (e.g., brake actuators), and / or logic blocks for controlling driver assistance systems (e.g., advanced driver assistance systems (ADAS)), etc.

[0042] Logic block 226 may be those logic blocks configured to and / or responsible for actively performing tasks required by the autonomous and / or non-autonomous operating system 200 (regardless of whether system 200 is in autonomous or non-autonomous mode). For example, although embodiments are not limited thereto, logic block 226 may include logic blocks for controlling the battery management system (BMS), communication modules configured for wireless communication, for example, via cellular, Wi-Fi, and V2X, power distribution units (PDUs), inertial measurement units (IMUs), logic blocks for controlling or communicating with sensors (e.g., LiDAR, cameras, radar, ultrasonic sensors, etc.), logic blocks for controlling user interfaces (UIs), displays, etc., and / or logic blocks for controlling cooling systems, etc.

[0043] In several embodiments, logic block 222 may be primarily "enabled" during the autonomous mode of system 200, and logic block 224 may be primarily "enabled" during the non-autonomous mode of system 200. Alternatively, logic block 222 may be primarily "disabled" during the non-autonomous mode of system 200, and logic block 224 may be primarily "disabled" during the autonomous mode of system 200. In some embodiments, one or more logic blocks 226 may remain "enabled" regardless of whether system 200 is in autonomous or non-autonomous mode.

[0044] The embodiments are not limited to a specific mode in which logic blocks 222, 224, and 226 can be primarily "enabled" or "disabled". Therefore, embodiments of this disclosure provide selective routing of clock signals from logic blocks 222, 224, and 226 to monitoring circuitry system 227, regardless of whether system 200 is in autonomous or non-autonomous mode (which is irrelevant). Instead, routing can be performed solely based on indications (e.g., identification) from the failure analysis described herein.

[0045] Failure analysis (alternatively referred to as a "failure analysis operation") can be performed on clock signals that are provided (e.g., are being provided) to a logic block (e.g., logic block 222). For example, the failure analysis can be performed outside of computing system 200 and the results of the failure analysis can be used in relation to the operation of system 200.

[0046] While embodiments are not limited thereto, failure analysis may be related failure analysis (DFA). As used herein, the term "related failure analysis" or "DFA" refers to a failure analysis used to assess the impact of related (e.g., non-independent) failures. As used herein, the term "related failure" refers to a failure in which two or more components (e.g., logic blocks 222, 224, 226) are attributable to a common cause or interdependence between them. In one instance, multiple components may fail due to a single common cause (which may be referred to as a common cause failure (CCF)). In another instance, a failure of one component (e.g., clock source 220, logic blocks 222, 224, 226, etc.) may cause the failure of another component (which may be referred to as a cascading failure). For example, a failure of a clock source 220 (alternatively referred to as a "shared resource") from which clock signals are supplied (e.g., shared) to multiple logic blocks (e.g., logic block 222) may ultimately cause the failure of those logic blocks (e.g., related failure). Furthermore, the failure of a clock source can typically lead to the failure or malfunction of error notification logic (e.g., CPU 208), which could further disrupt the error management capabilities of computing system 100 (e.g., by interrupting the ability of host 102 to be used as a decision-making entity). Therefore, the executed DFA can identify those clock sources (e.g., clock source 220) and / or blocks (e.g., logic blocks 222, 224, 226) associated with the relevant failures, which are crucial for the autonomous operation of computing system 100 (e.g., autonomous device, such as an autonomous vehicle).

[0047] Control logic 219 is communicatively coupled to monitoring circuitry 227 and multiplexer 223. Figure 2 The signal routing is coordinated based at least on the results of a failure analysis performed on the clock signals of logic blocks 222, 224, and 226. For example, control logic 219 may receive information associated with those logic blocks (e.g., logic block 222) identified through failure analysis (e.g., identified as being associated with related failures causing other logic blocks 222). Furthermore, control logic 219 may selectively route clock signals (being provided to one or more logic blocks 222, 224, and 226) to monitoring circuitry 227 so that monitoring circuitry 227 selectively monitors the routed clock signals. As used herein, the clock signals provided to logic blocks (e.g., logic blocks 222, 224, and 226) may alternatively be referred to as "the clock signal of the logic block".

[0048] In an example, when the computing system 100 operates autonomously or in autonomous mode, control logic 219 may route clock signals provided to those logic blocks 222 (e.g., those logic blocks 222) identified through failure analysis (e.g., DFA) (e.g., identified as potentially causing correlation) to monitoring circuitry 227. Alternatively, clock signals from clock sources 220 and / or logic blocks 222 that are not identified through failure analysis may not necessarily be routed to monitoring circuitry 227 (so that they are not monitored). In some embodiments, monitoring circuitry 227 may continuously or intermittently monitor clock signals used by one or more logic blocks 222 (e.g., the opposite of periodic or periodic monitoring).

[0049] In an example, control logic 219 may route clock signals provided to one or more logic blocks 224, 226 (e.g., one or more logic blocks 224, 226) to monitoring circuitry 227. For example, a multiplexer coupled between monitoring circuitry 227 and logic blocks 224, 226 may selectively provide selected clock signals of logic blocks 224, 226 to monitoring circuitry 227 to allow monitoring circuitry 227 to monitor clock signals. In some embodiments, selected clock signals of logic blocks 224, 226 may be monitored periodically or periodically (e.g., the opposite of continuous or continuous monitoring).

[0050] As used herein, the terms “continuously” or “in a continuous manner” mean occurring without interruption. For example, if an operation (e.g., monitoring) is performed “continuously” or “in a continuous manner,” then this means that the operation is running without any substantial and / or intentional pauses or suspensions. As used herein, the terms “periodically” or “in a periodic manner” mean occurring at regular intervals. For example, if an operation (e.g., monitoring) is performed “periodically” or “in a periodic manner,” then this means that the individual occurrences of the operation have consistent time intervals between their respective occurrences (e.g., intentionally introduced).

[0051] Monitoring circuitry 227 can identify clock failures (or clock errors) on those clock signals monitored by monitoring circuitry 227. In one example, monitoring circuitry 227 can identify clock failures by comparing the corresponding clock signal received from clock source 220 and / or clock control component 221 with an expected frequency or phase. A clock failure is identified when a selected clock signal of a logic block exhibits a deviation from an expected frequency or phase determined (e.g., calculated) based on the clock signal received from the clock source.

[0052] For example, once a clock failure is detected (e.g., which may negatively impact the mission mode logic and security mechanisms of system 200), monitoring circuitry 227 can trigger signal abort (alternatively referred to as "link abort") by outputting a trigger signal. As used herein, the term "signal abort" refers to the loss (e.g., intentional loss) of communication between two entities (e.g., between host 102 and memory subsystem 104). Signal abort can be achieved, for example, by resetting memory subsystem 104 or placing it in a reduced-power state (e.g., inactive, power-off, or power-down state). Signal abort triggered by monitoring circuitry 227 prevents host 102 from making decisions based on faulty or incorrect data that would otherwise be provided by memory subsystem 104. This helps avoid security risks, especially when host 102 relies on real-time data from memory subsystem 104 for its decision-making. By ensuring that only accurate data is used, particularly within short time frames, the overall security and reliability of computing system 100 are enhanced.

[0053] Logic blocks 224 and 226 may be coupled to error management circuitry 228. Error management circuitry 228 may provide various security mechanisms for logic blocks 224 and 226, such as correcting and / or detecting errors in data received from logic blocks 224 and / or 226, but embodiments are not limited thereto. Error management circuitry 228 may comprise dedicated circuitry in the form of an ASIC, FPGA, state machine, hardware processing device, and / or other logic circuitry that allows error management circuitry 228 to orchestrate and / or perform operations (e.g., error correction and / or detection operations using parity bits, cyclic redundancy check (CRC) bits). Error management circuitry 228 may further utilize a "timeout" mechanism that alerts host 102 to errors when the error correction and / or detection process (e.g., single error correction and double error detection (SECDED)) exceeds a predefined time period (e.g., the time taken is longer than the predefined time period). Although the embodiments are not limited thereto, the error management circuitry system 228 may further include a temperature sensor and a voltage monitor (e.g., to monitor the output voltage of the regulator of the computing system 200).

[0054] Error management circuitry 228 can also trigger signal abort. For example, error management circuitry 228 can be configured to trigger signal abort for some types of errors that may be critical to the autonomous operation of computing system 200. Additionally or alternatively, error management circuitry 228 can report errors to host 102 via a sideband channel (e.g., communication channel 229), which may include data and one or more pins, such as general purpose input / output (GPIO) pins. In some embodiments, in addition to the primary communication channel, the communication channel may also be an auxiliary communication channel (e.g., a sideband channel). Communication channels acting as sideband channels can operate in parallel with the primary communication channel, which improves the control of host 102 and / or vehicle control systems (e.g., Figure 1 The response time of the vehicle control system 118 described herein.

[0055] Communication channel 229 can be used as a component to convey further error details / information to host 102 (e.g., error source (e.g., from a temperature sensor), the type of error detected, the severity of the error, the timestamp when the error occurred, etc.). For example, host 102 may detect signal abort after detecting no communication from controller 106 for a specific time period. In this case, host 102, which is constantly monitoring controller 106 (e.g., an automotive system application), may request or poll for error details from controller 106 and may provide the details back to host 102 via sideband channel 229.

[0056] Figure 3 It is based on some embodiments of this disclosure for managing and operating a computing system (e.g., Figure 1 The flowchart illustrates an example method 330 for resolving errors associated with a computing system 100. The method can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the method is performed by or uses... Figures 1 to 2 and the memory subsystem controllers 106, 206, and 406 shown in section 4 respectively (e.g., Figure 1 The clock monitoring component 112 shown in the illustration performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0057] At position 332, the logical block provided to the first group can be determined (e.g., Figure 2Whether the corresponding clock signal of logic block 222 described herein is identified by failure analysis (e.g., identified or indicated as being associated with a related failure causing other logic blocks in the first group). At 334, the clock signals provided to one or more logic blocks 222 in the first group may be selectively routed to the monitoring circuitry (e.g., Figure 2 The monitoring circuitry 227 described herein allows the clock signals of one or more logic blocks 222 to be monitored. Clock signals to be routed to the monitoring circuitry 227 can be selected based on failure analysis operations. The selected clock signals provided to one or more logic blocks can be continuously monitored (by the monitoring circuitry 227). Furthermore, signal abort can be triggered in response to determining that the clock signals of one or more logic blocks 222 are faulty.

[0058] In some embodiments, during autonomous mode, logic blocks 222 of a first group configured to operate during autonomous mode may be enabled, while logic blocks (e.g., Figure 2 One or more logic blocks in the second group of logic blocks 224, 226 described herein. In some embodiments, during non-autonomous mode, logic block 222 of the first group may be disabled, while logic blocks 224, 226 of the second group configured to operate during non-autonomous mode may be enabled.

[0059] In this example, during autonomous mode, clock signals from one or more logic blocks 224, 226 in the second group can be selectively routed to monitoring circuitry 227 so that the clock signals from one or more logic blocks 224, 226 in the second group are monitored by monitoring circuitry 227. The clock signals from logic blocks 224, 226 in the second group can be monitored periodically (by monitoring circuitry 227).

[0060] Figure 4 This section describes an example of a system 446 comprising a computing system 400 in a vehicle, according to some embodiments of the present disclosure. The computing system 400 may include a memory subsystem 404, which, for simplicity, is described as including a controller 406 and a non-volatile memory device 416, but is similar to... Figure 1The memory subsystem 104 is described herein. The computing system 400 and therefore the host 402 may be directly (as illustrated for sensors 444-4) or via transceiver 452 (as illustrated for sensors 444-1, 444-2, 444-3, 444-5, 444-6, 444-7, 444-8, ..., 444-Q (collectively referred to as sensors 444)). The transceiver 452 is capable of wirelessly receiving data from the sensors 444, for example, via radio frequency communication. In at least one embodiment, each of the sensors 444 may wirelessly communicate with the computing system 400 via the transceiver 452. In at least one embodiment, each of the sensors 444 is directly connected to the computing system 400 (e.g., via a wire or optical fiber).

[0061] Vehicle 450 can be a car (e.g., a sedan, van, truck, etc.), a connected vehicle (e.g., a vehicle with computing power to communicate with an external server), an autonomous vehicle (e.g., a vehicle with self-automation capabilities, such as autonomous driving), a drone, an aircraft, a ship, and / or anything used to transport people and / or goods. Sensor 444 is in Figure 4 The term is described as including instance attributes. For example, sensors 444-1, 444-2, and 444-3 are cameras that collect data from the front of vehicle 450. Sensors 444-4, 444-5, and 444-6 are microphone sensors that collect data from the front, middle, and rear of vehicle 450. Sensors 444-7, 444-8, and 444-Q are cameras that collect data from the rear of vehicle 450. As another example, sensors 444-5 and 444-6 are tire pressure sensors. As another example, sensor 444-4 is a navigation sensor, such as a Global Positioning System (GPS) receiver. As another example, sensor 444-6 is a speedometer. As another example, sensor 444-4 represents several engine sensors, such as a temperature sensor, pressure sensor, voltmeter, ammeter, tachometer, fuel gauge, etc. As another example, sensor 444-4 represents a camera. Video data can be received from any of the sensors 444, including the camera, associated with vehicle 450. In at least one embodiment, the host 402 may compress the video data before providing it to the memory subsystem 404.

[0062] The host computer 402 can execute instructions to provide an overall control system and / or operating system for the vehicle 450. The host computer 402 may be a controller designed to assist the automation efforts of the vehicle 450. For example, the host computer 402 may be an Advanced Driver Assistance System (ADAS) controller. ADAS can monitor data to prevent accidents and provide warnings of potential unsafe situations. For example, ADAS can monitor sensors in the vehicle 450 and control the operation of the vehicle 450 to avoid accidents or injuries (e.g., to avoid accidents in the event of a user incapacitation). The host computer 402 may need to act quickly and make decisions to avoid accidents. The memory subsystem 404 can store reference data in a non-volatile memory device 416, allowing the host computer 402 to compare data from the sensor 444 with the reference data to make quick decisions.

[0063] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. An algorithm herein is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, although not strictly necessary, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily for common use.

[0064] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and converts data represented as physical (electronic) quantities in computer system registers and memories into other data similarly represented as physical quantities in computer system memories or registers or other such information storage systems.

[0065] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored therein. This computer program may be stored in a machine-readable storage medium, such as, but not limited to, several types of disks, semiconductor-based memories, magnetic cards or optical cards, or other types of media suitable for storing electronic instructions.

[0066] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes mechanisms for storing information in a machine-readable (e.g., computer-readable) form.

[0067] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A method for clock monitoring, comprising: Determine whether the corresponding clock signals provided to the logic blocks (222-1, 222-2, 222-3, 222-N) in the first group have been identified by failure analysis; and In response to determining that a clock signal provided to one or more logic blocks in the first group is identified by the failure analysis, the identified clock signal is selectively routed to the monitoring circuitry (227) so that the clock signal is monitored.

2. The method of claim 1, further comprising triggering a signal abort in response to determining that the clock signal of the one or more logic blocks is faulty.

3. The method according to any one of claims 1 to 2, wherein: During autonomous mode: Enable the logic blocks of the first group configured to operate during the autonomous mode; and Selectively enable one or more logic blocks in the second group (224-1, 224-2, 224-M, 226-1, 226-2, 226-X).

4. The method of claim 3, further comprising during the autonomous mode: The clock signals of one or more logic blocks provided to the second group are selectively routed to the monitoring circuit system so that the clock signals of the one or more logic blocks in the second group are monitored by the monitoring circuit system.

5. The method of claim 3, further comprising during non-autonomous mode: Deactivate the logic blocks of the first group; and Enable the logic blocks of the second group that are configured to operate during the non-autonomous mode.

6. The method of claim 3, further comprising during the autonomous mode: The clock signal provided to the logic block in the second group is periodically monitored.

7. The method according to any one of claims 1 to 2, further comprising continuously monitoring selected clock signals provided to the one or more logic blocks.

8. A device (100; 400) for clock monitoring, comprising: The logic blocks of the first group (222-1, 222-2, 222-3, 222-N) are configured to operate during a first operating state of the device; and A controller (219) is configured to selectively route corresponding clock signals of one or more logic blocks in the first group to a monitoring circuit system to monitor the corresponding clock signals, wherein the corresponding clock signals are identified as being associated with a related failure of a logic block in the first group.

9. The device of claim 8, wherein the corresponding clock signal is identified by the related failure analysis (DFA).

10. The device according to any one of claims 8 to 9, wherein the monitoring circuitry is configured to output a trigger signal to trigger signal termination of the device in response to at least one of the respective clock signals being determined to be faulty.

11. The device according to any one of claims 8 to 9, wherein the clock signal of the logic block of the first group comprises a clock signal provided to the logic block of the first group from one or more clock sources (220-1, 220-2, 220-3, 220-4, 220-5, 220-P), a clock divider (221), or any combination thereof.

12. The device according to any one of claims 8 to 9, further comprising: The logic blocks of the second group (224-1, 224-2, 224-M, 226-1, 226-2, 226-X) are configured to operate during the second operating state of the device; and A multiplexer (223) is coupled between the monitoring circuit system and the logic blocks of the second group; The controller is configured to: Control the multiplexer to selectively route at least one of the clock signals of the logic blocks of the second group to the monitoring circuit system; At least one of the clock signals of the logic blocks of the second group is selectively routed to the monitoring circuit system so that at least one of the clock signals of the second group is periodically monitored.

13. A device for clock monitoring (100; 400), which includes: The logic blocks of the first group (222-1, 222-2, 222-3, 222-N) are configured to operate based on a first clock signal during the autonomous mode of the device; and A controller (219) is configured to monitor selected clock signals provided to one or more logic blocks in the first group and identified as being associated with a related failure of a logic block in the first group.

14. The device of claim 13, wherein the controller is further configured to trigger a signal abort in response to a clock failure detected on the selected clock signal.

15. The device according to any one of claims 13 to 14, further comprising: The logic blocks of the second group (224-1, 224-2, 224-M, 226-1, 226-2, 226-X) are configured to operate during the non-autonomous mode of the device; and The controller is configured to monitor selected clock signals of logic blocks in the second group.

16. The device of claim 15, wherein the controller is further configured to: In response to the detection of one or more errors in the data provided from the logic blocks of the second group, a signal abort is triggered; and Information associated with one or more errors in the logical blocks associated with the second group is provided to the host (102; 402).

17. The device of claim 15, wherein the controller is further configured to periodically monitor the selected clock signal of the logic block in the second group.

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