Approximate Link adder circuit based on parallel prefix topology
By designing an approximate Ling adder circuit based on parallel prefix topology, the correctness and integration issues of approximate adders in low-bit processing in existing technologies are solved, achieving critical path optimization and hardware efficiency improvement, and making it suitable for error-tolerant scenarios such as image/video processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI UNIV OF TECH
- Filing Date
- 2025-12-24
- Publication Date
- 2026-04-17
AI Technical Summary
Existing approximate adders often sacrifice too much correctness in low-bit processing or are difficult to integrate seamlessly with standard prefix trees, resulting in limited system-level availability.
Design an approximate Ling adder circuit based on parallel prefix topology. The intermediate signal is calculated by a preprocessing module, the prefix calculation module is divided into approximate and accurate units, the carry signal is generated by a postprocessing module, the logic is simplified by an approximate prefix operator, and the critical path is optimized by combining parallel prefix topology.
It significantly shortens the critical path, reduces fan-out and cross-layer routing, improves hardware efficiency, and achieves a trade-off between performance, area/power consumption, and accuracy, making it suitable for error-tolerant scenarios such as image/video processing and neural network inference.
Smart Images
Figure CN121879712A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of approximate calculation technology, and in particular to an approximate Ling adder circuit based on parallel prefix topology. Background Technology
[0002] Adders are crucial foundational modules in arithmetic logic units (ALUs) and digital signal processing (DSPs), and their performance has a decisive impact on processor clock speed, power consumption, and area. Parallel prefix adders generate carry signals at logarithmic depth by constructing prefix trees; typical topologies include Kogge-Stone, Brent-Kung, Sklansky, Han-Carlson, and Knowles. Ling adders replace traditional carry representations with Ling carry H, reducing cascading depth and critical path while maintaining the same bit width; however, their gate-level implementation typically introduces additional combinations, leading to increased local area and fan-out.
[0003] With the increasing application of approximate computation in error-tolerant scenarios such as image / video processing, neural network inference, and sensor fusion, further shortening the critical path and reducing energy consumption while maintaining controllable accuracy loss has become a direction for optimizing parallel prefix-type adders. Existing approximate adders, such as Low Or Adders (LOA) and Error Tolerant Adders (ETA), often sacrifice too much correctness in low-bit processing or are difficult to integrate seamlessly with standard prefix trees, resulting in limited system-level availability. Therefore, proposing an approximate adder that can simultaneously inherit the logarithmic carry generation advantage of parallel prefix topology and the critical path optimization characteristics of Ling adders is a valuable research direction. Summary of the Invention
[0004] The technical problem to be solved by this invention is: how to solve the problem that existing approximate adders often sacrifice too much correctness in low-bit processing or are difficult to integrate seamlessly with standard prefix trees, resulting in limited system-level availability.
[0005] This invention solves the above-mentioned technical problems through the following technical solution: an approximate Ling adder circuit based on parallel prefix topology, comprising: The preprocessing module is configured to be based on two Bit binary number , The values of each bit are used to calculate the generated signal. , transmission signal Half and signal And based on the generated signal , transmission signal Calculate the intermediate generated signal Intermediate transmission signal , and It is an integer; The prefix calculation module is configured to calculate based on parameters. Divided into approximate elements and exact elements, , where the approximate unit is based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit , and Integer; precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit , and It is an integer; The post-processing module is configured to base its output on the propagation signals of adjacent bits. and Ling carry Generate carry signal And according to the carry signal sum and half signal Generate the sum of each bit.
[0006] Preferably, a signal is generated. , transmission signal Half and signal They are respectively: ; ;
[0007] in, Representing binary numbers The Middle Position value and The Middle Bitwise AND operation Representing binary numbers The Middle Position value and The Middle Bitwise OR operation Representing binary numbers The Middle Position value and The Middle The bitwise XOR operation.
[0008] Preferably, an intermediate signal is generated. Intermediate transmission signal for: ;
[0009] in, Indicates the first Bit generation signal With the Bit generation signal OR operation, Indicates the first Position propagation signal With the Position propagation signal AND operation.
[0010] Preferably, the approximate unit is based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit The method is as follows: , and It is an integer.
[0011] Preferred, Ling carry in the least significant bit even-numbered digits Generate a signal for the middle of an even number of bits. , Ling carry in the least significant bit odd-numbered positions Generate a signal for the middle of an odd-numbered position. , .
[0012] Preferred, precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit The method is as follows: and and It is an integer.
[0013] Preferred, Ling carry in the most significant bit even-numbered digits and Ling carry in the most significant bit odd-numbered positions They are respectively:
[0014]
[0015] .
[0016] Preferably, the carry signal for:
[0017] Everyone and for:
[0018] in, Indicates adjacent The propagation signal of position and Ling carry AND operation, Indicates carry signal With half and signal The XOR operation, , .
[0019] Preferred parameters The larger the value, the shorter the critical path and the lower the area and power consumption, but the higher the probability of bit error introduced by the approximation.
[0020] Preferably, the prefix calculation module adopts a parallel prefix topology, which can be any one of Brent-Kung, Kogge-Stone, Beaumont-Smith, Sklansky, Han-Carlson, or Knowles.
[0021] The advantages provided by this invention are: 1. The approximate Ling prefix computation proposed in this invention adopts a logic simplification strategy of approximate prefix operators in the low bit, which significantly shortens the critical path and reduces fan-out and cross-layer routing. Compared with the pure precise parallel prefix Ling adder, it can obtain better timing margin and lower power consumption area under the same process and bit width conditions.
[0022] 2. This invention has good versatility and integrability: without changing the overall connection paradigm of the prefix tree, it can seamlessly migrate between various topologies such as Brent-Kung, Kogge-Stone, Beaumont-Smith, Sklansky, Han-Carlson, and Knowles, and only the low-order nodes are locally replaced, resulting in high reusability of the layout.
[0023] 3. This invention provides an adjustable approximate bit width K, achieving a trade-off between performance, area / power consumption, and accuracy; for error-tolerant scenarios such as image / video, voice / sensor signal processing, and fault-tolerant calculations, it significantly reduces latency and power consumption while meeting application layer quality indicators. Attached Figure Description
[0024] Figure 1 An architecture diagram of an approximate Ling adder circuit based on parallel prefix topology provided for an embodiment of the present invention; Figure 2 shows examples of the prefix processing stage of the approximate Ling adder circuit based on parallel prefix topology provided in the embodiments of the present invention, using different parallel prefix topology structures. In Figure 2(a), it is the Kogge-Stone structure, Figure 2(b) is the Brent-Kung structure, Figure 2(c) is the Beaumont-Smith structure, and Figure 2(d) is the Sklansky structure. Figure 3 shows the core intermediate quantities in the PPLA architecture of the approximate Ling adder circuit based on parallel prefix topology provided in the embodiment of the present invention. α and β The generation method, where Figure 3(a) shows the core intermediate quantity when there is 1 input. and The generation method is shown in Figure 3(b), which illustrates the core intermediate quantity with 2 inputs. and The generation method is shown in Figure 3(c), which illustrates the core intermediate quantity with 3 inputs. and The generation method is shown in Figure 3(d), which illustrates the core intermediate quantity with 4 inputs. and The generation method; Figure 4 This is a working example of an approximate Ling adder circuit based on parallel prefix topology provided in this embodiment of the invention (assuming...). n =16、 K =8), where, Figure 4 (a) represents the input and the expected output. Figure 4 (b) is an example diagram of the Sklansky topology. Figure 4 (c) is a schematic diagram of the preprocessing module circuit. Figure 4 (d) is the core intermediate quantity α , β A schematic diagram of the generation circuit. Figure 4 (e) is a schematic diagram of the Ling carry circuit. Figure 4 (f) is a schematic diagram of the AxPO circuit. Figure 4 (g) is a schematic diagram of the post-processing module circuit. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0026] like Figure 1 As shown, this embodiment provides an approximate Ling adder circuit based on a parallel prefix topology, including: The preprocessing module is configured to be based on two Bit binary number , The values of each bit are used to calculate the generated signal. , transmission signal Half and signal And based on the generated signal , transmission signal Calculate the intermediate generated signal Intermediate transmission signal , and It is an integer. , ... , , Representing binary numbers respectively Each value from the most significant bit to the least significant bit. , ... , , Representing binary numbers respectively Each value from the most significant bit to the least significant bit.
[0027] Among them, the signal is generated , transmission signal Half and signal They are respectively: ; ;
[0028] in, Representing binary numbers The Middle Position value and The Middle Bitwise AND operation Representing binary numbers The Middle Position value and The Middle Bitwise OR operation Representing binary numbers The Middle Position value and The Middle The bitwise XOR operation is defined as follows. , .
[0029] Ling proposed a carry generation method, the core of which simplifies the carry calculation logic by defining a recursive expression and based on the carry recursive relation. The carry in Ling can be represented as: This can be further expanded into a recursive form:
[0030] To simplify the above expression, two intermediate signals are defined for each bit during the preprocessing stage, namely the intermediate generation signal and the intermediate generation signal. Intermediate transmission signal Signal generated in the middle Intermediate transmission signal for: ;
[0031] in, Indicates the first Bit generation signal With the Bit generation signal OR operation, Indicates the first Position propagation signal With the Position propagation signal AND operation.
[0032] Combine intermediate signals Intermediate transmission signal Ling carry can be broken down into a more concise expression based on parity, where even-numbered bits... for:
[0033] odd number for:
[0034] The preprocessing stage employs precise logical operations to provide reliable input for subsequent stages, through the analysis of two... Bit binary number A and B Each bit simultaneously calculates the propagation signal. Generate signal With half and signal And based on the Ling equation Mapped to local intermediate transmission signal ( (i.e., generating a signal in the middle) Intermediate transmission signal ， Signal generated in the middle Intermediate transmission signal As a unified input interface for the prefix calculation module, it can reduce cross-layer fan-out and connection congestion; when the bit width is At that time, the preprocessing module can complete the process within one clock cycle. Parallel generation of path signals, and intermediate generation signals Intermediate transmission signal Provided to subsequent modules.
[0035] The prefix calculation module is configured to calculate based on parameters. Divided into approximate elements and exact elements, , where the approximate unit is based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit , and Integer; precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit , and It is an integer.
[0036] Approximate bit width of the present invention From 1 to Configurable integer parameters; when As the size increases, the critical path is further shortened, and the area and power consumption decrease, but the probability of bit error introduced by the approximation increases. This can be addressed based on application-layer perceptual indicators (such as...). PSNR / MSSIM Or task accuracy threshold) setting parameters The upper limit.
[0037] Among them, the approximate element is based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit The method is as follows: , and It is an integer.
[0038] Precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit The method is as follows: and and It is an integer.
[0039] The prefix calculation module employs a parallel prefix topology to deploy prefix operators, generating intermediate signals from the preprocessing module's output. Intermediate transmission signal Perform grouping reduction operations and iteratively generate Ling carry values at each level. Specifically, it includes an approximate part, a precise part, and boundary concatenation, where the approximate part (lower bits) The bit) is configured with an approximate prefix operator (AxPO) so that the bit) Ling carries over Only rely on the intermediate generation of the local position to generate the signal By omitting the cascading dependency on lower-order signals, at least one layer of AND / OR gate circuitry is reduced, while the critical path is shortened. The approximate prefix operator (AxPO), after Boolean equivalence simplification, exhibits a low error probability and good computational accuracy. The precise part (higher-order bits) The high-order Ling carry is generated by using an exact prefix operator and reducing the corresponding series depth on the parallel prefix topology. Boundary cascading approximates the boundary of the approximate portion by carrying over the approximate portion. As the initial input condition for the precise part, it ensures the accuracy and timing continuity of the full-width summation operation.
[0040] Unlike the Precise Parallel Ling Adder (PPLA), this invention uses parameters... The prefix calculation stage is divided into an exact part and an approximate part, where... High-precision bits employ precise logical operations to ensure the target accuracy requirements are met. The lower precision bits improve hardware efficiency through approximation operations. These two parts involve the carry-over from the approximation unit to the precision unit. Achieve connection. The precise prefix processing unit can generate accurate ling carry. and The Ling carry in the approximate unit and Then, by the approximate prefix operator (AxPO), it simplifies to: , .
[0041] The prefix calculation module of this invention adopts a parallel prefix topology. Figure 2 shows an example diagram of the prefix processing stages of the parallel prefix Ling adders (PPLAs) using different parallel prefix topologies. The PPLA architecture reduces logic levels and improves computation speed by dividing the prefix processing stages into odd-numbered and even-numbered bits, thereby reducing wiring congestion and fan-out. The parallel prefix topology can be any one of Brent-Kung, Kogge-Stone, Beaumont-Smith, Sklansky, Han-Carlson, and Knowles, or other parallel prefix topologies. Figure 2(a) shows the Brent-Kung architecture, which uses 2-bit grouping iterative calculation, gradually merging into 4-bit and 8-bit group prefixes, with a logic level of [number missing]. With low fan-in and fan-out and low wiring congestion, it is suitable for hardware resource-sensitive scenarios. Figure 2(b) shows the Kogge-Stone architecture, which uses a regular grid as its topology. Each bit prefix is calculated independently and advanced synchronously, resulting in high computational efficiency, low fan-out, and strong hardware stability, making it suitable for high-speed data processing. Figure 2(c) shows the Beaumont-Smith architecture, which is based on a low logic depth design. It directly integrates multiple sets of local prefixes through a multi-fan-in structure, reducing critical path latency and interconnect length, achieving a balance between speed and resources, and adapting to general scenarios. Figure 2(d) shows the Sklansky architecture, also known as a divide-and-conquer architecture. It splits bits into sub-modules in powers of 2, calculates them in parallel, and then merges them. It can optimize intermediate prefix latency, but the fan-out of each level doubles, which can easily cause fan-out problems. It needs to be used in conjunction with buffer units for high-speed demand scenarios. Figure 3 supplements the illustration of the core intermediate quantities in PPLA. α and β The generation method, i.e. the operation method of the black dots in the figure, covers four typical scenarios: 1 input, 2 inputs, 3 inputs and 4 inputs, and gives the corresponding logical expressions. Figure 3(a) shows the core intermediate quantity when there is 1 input. and The generation method is as follows: , Figure 3(b) shows the core intermediate values when there are 2 inputs. and The generation method is as follows: , Figure 3(c) shows the core intermediate values with 3 inputs. and The generation method is as follows: , Figure 3(d) shows the core intermediate values with 4 inputs. and The generation method is as follows: , These intermediate quantities are the core foundation for subsequent Ling carry calculations, and their generation logic must match the topological characteristics of the prefix processing architecture to ensure that the signal can be transmitted efficiently and accurately within the architecture. This invention, through the flexible selection of the aforementioned topology, can adapt to the speed and area balance requirements in different scenarios.
[0042] The post-processing module is configured to base its output on the propagation signals of adjacent bits. and Ling carry Generate carry signal And according to the carry signal sum and half signal Generate the sum of each bit. The post-processing module consists of lightweight combinational logic, based on the carrying of adjacent bits. With propagation signal Restore the equivalent carry relationship and output the sum of each bit. This module does not introduce multi-cycle feedback, ensuring that the single-cycle summation path is closed.
[0043] Carry signal for:
[0044] Everyone and for:
[0045] in, Indicates adjacent The propagation signal of position and Ling carry The AND operation is implemented using an AND gate. Indicates carry signal With half and signal The XOR operation is implemented using an XOR gate. It calculates the sum of each bit. Then, the output can be obtained. for .
[0046] In the post-processing stage, the Ling carry generated in the prefix processing stage is used as a basis. Propagation signals in the preprocessing stage Half and signal This stage performs addition operations and also employs precise logical operations to ensure the accuracy of the final output.
[0047] Theoretically speaking, the approximate part contains the first... The carry in the first position depends only on the carry in the second position. The position and the first The fact that the input includes the current bit significantly reduces the logical complexity of carry generation. Table 1 is a truth table comparing the exact prefix operator (PO) and the approximate prefix operator (AxPO) of this invention, with the input including the current bit. , The previous one , and carry The output includes the current carry. Carry over from the previous digit And and As can be seen from the truth table, the difference between AxPO and exact PO exists only in 5 special input combinations (marked "..."). (The situation is described in the original text).
[0048] For example, when , , , , At that time, accurate PO output , , AxPO output , , .when , , , , At that time, accurate PO output , , AxPO output , , .when , , , , At that time, accurate PO output , , AxPO output , , .when , , , , At that time, accurate PO output , , AxPO output , , .when , , , , At that time, accurate PO output , , AxPO output , , According to statistics, this design enables signals... The error probability is approximately 3.125%, carry signal The error probability is approximately 12.5%, reflecting the precision design concept of this invention. In specific implementation, for the lower bits (assuming an approximate number of bits K), AxPO simplifies the logic of the precise prefix operator, directly applying the preprocessing stage... The connection is for Ling carry. ,Right now , .
[0049] Table 1. Truth table comparing the exact prefix operator (PO) and the approximate prefix operator (AxPO) of this invention.
[0050] Figure 4 This is a working example of the AxPPLA proposed in this invention, used to illustrate the working principle of the approximately parallel prefix Ling adders (AxPPLAs) based on the proposed architecture. This example uses a Sklansky topology, with the adder bit width set to... n =16, approximate number of digits set to K =8. Where: Figure 4 (a) shows the input and expected output, with a 16-bit input A = (49225). 10 (Binary 1100000110001001), B=(61940) 10 (Binary 1111010000110100), expected exact sum S = (111165) 10 (Binary 11011001000111001). Figure 4 (b) is an example diagram of the Sklansky topology. In the preprocessing stage, intermediate signals for each bit of the operand are generated according to the Ling formula calculation expression. , and .like Figure 4 As shown in (c), the preprocessing stage consists of simple logic gates, including AND gates, OR gates and XOR gates. The preprocessing circuits of all bits work in parallel to ensure the real-time generation of the signal.
[0051] for K =8 least significant bits, through Figure 4The approximate prefix operator (AxPO) shown in (f) directly converts the signal... As Ling carries over The approximation unit ignores the cascading dependency of low-order ling carry, optimizes the ling carry expression by eliminating AND and OR operations, and passes the signal generated in the preprocessing stage to the postprocessing stage; at the same time, it provides a 1-bit ling carry for the precision unit. . Figure 4 (d) and Figure 4 (e) Used for precise units, generating Precise Ling Carry of the Highest Significant Bit This unit achieves accurate transmission of high-order Ling carry through iterative calculations using a tree structure. Figure 4 (g) is a schematic diagram of the post-processing module circuit. The sum and carry output are achieved through AND and XOR operations. Through the above steps, the sum and carry are... Using approximate calculations, Precise calculations are employed. Based on these Ling carry, AxPPLA... SK The final conclusion is with Figure 4 (a) The same approximation and value, where, in special cases , All post-processing circuits operate in parallel to ensure high-speed addition operations.
[0052] Compared with existing technologies, the present invention has the following advantages: 1. The approximate Ling prefix computation proposed in this invention adopts the logic simplification strategy of the approximate prefix operator (AxPO) in the low bit, which significantly shortens the critical path and reduces fan-out and cross-layer routing. Compared with the pure precise parallel prefix Ling adder, it can obtain better timing margin and lower power consumption area under the same process and bit width conditions.
[0053] 2. This invention has good versatility and integrability: without changing the overall connection paradigm of the prefix tree, it can seamlessly migrate between various topologies such as Kogge-Stone, Brent-Kung, Sklansky, Han-Carlson, and Knowles, and only the low-order nodes are locally replaced, resulting in high reusability of the layout.
[0054] 3. This invention provides an adjustable approximate bit width K, achieving a trade-off between performance, area / power consumption, and accuracy; for error-tolerant scenarios such as image / video, voice / sensor signal processing, and fault-tolerant calculations, it significantly reduces latency and power consumption while meeting application layer quality indicators.
[0055] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. An approximate Ling adder circuit based on parallel prefix topology, characterized in that: include: The preprocessing module is configured to be based on two Bit binary number , The values of each bit are used to calculate the generated signal. , transmission signal Half and signal And based on the generated signal , transmission signal Calculate the intermediate generated signal Intermediate transmission signal , and It is an integer; The prefix calculation module is configured to calculate based on parameters. Divided into approximate elements and exact elements, , where the approximate unit is based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit , and Integer; precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit , and It is an integer; The post-processing module is configured to base its output on the propagation signals of adjacent bits. and Ling carry Generate carry signal And according to the carry signal sum and half signal Generate the sum of each bit.
2. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: Generate signal , transmission signal Half and signal They are respectively: ； ； in, Representing binary numbers The Middle Position value and The Middle Bitwise AND operation Representing binary numbers The Middle Position value and The Middle Bitwise OR operation Representing binary numbers The Middle Position value and The Middle The bitwise XOR operation.
3. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: Signal generated in the middle Intermediate transmission signal for: ； in, Indicates the first Bit generation signal With the Bit generation signal OR operation, Indicates the first Position propagation signal With the Position propagation signal AND operation.
4. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: Approximate unit based on The intermediate signal corresponding to the least significant bit is generated. generate Ling carry in the least significant bit The method is as follows: , and It is an integer.
5. The approximate Ling adder circuit based on parallel prefix topology according to claim 4, characterized in that: Ling carry in the least significant bit even-numbered digits Generate a signal for the middle of an even number of bits. , Ling carry in the least significant bit odd-numbered positions Generate a signal for the middle of an odd-numbered position. , .
6. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: Precise unit according to The intermediate signal corresponding to the most significant bit is generated. Intermediate transmission signal and Ling carry generate Ling carry in the most significant bit The method is as follows: and and It is an integer.
7. The approximate Ling adder circuit based on parallel prefix topology according to claim 6, characterized in that: Ling carry in the most significant bit even-numbered digits and Ling carry in the most significant bit odd-numbered positions They are respectively: 。 8. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: Carry signal for: Everyone and for: in, Indicates adjacent The propagation signal of position and Ling carry AND operation, Indicates carry signal With half and signal The XOR operation, , .
9. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: parameter The larger the value, the shorter the critical path and the lower the area and power consumption, but the higher the probability of bit error introduced by the approximation.
10. The approximate Ling adder circuit based on parallel prefix topology according to claim 1, characterized in that: The prefix calculation module adopts a parallel prefix topology, which can be any one of Brent-Kung, Kogge-Stone, Beaumont-Smith, Sklansky, Han-Carlson, or Knowles.