Log-likelihood ratio dynamic quantization method and system for flash memory

Abstract

The invention discloses a log-likelihood ratio dynamic quantization method for a flash memory, which comprises the following steps of: after acquiring an initial log-likelihood ratio data set, classifying all log-likelihood ratios by utilizing a clustering analysis method, dividing the log-likelihood ratios into intervals with different amplitude ranges, and then dynamically adjusting quantization factors according to the sizes of the log-likelihood ratios and the categories of the log-likelihood ratios, for the log-likelihood ratios of different regions, refined quantization factors are adopted to enhance the resolution, so that the error correction capability of a decoder on the key data is improved, and higher quantization precision is allocated for the log-likelihood ratios on the premise of not damaging the relative size relationship of the original log-likelihood ratios; therefore, the quality of the log-likelihood ratio information sent into the LDPC decoder is integrally optimized, and the error correction capability of the decoder is improved.

Description

Technical Field

[0001] This invention belongs to the field of flash memory storage error correction technology, and relates to a method and system for dynamic quantization of log-likelihood ratio for flash memory. Background Technology

[0002] To meet the ever-increasing demand for data storage, Triple-Level Cell (TLC) NAND flash memory has become the mainstream storage medium due to its high capacity and low cost. However, the increased storage density and cell levels also lead to a higher raw bit error rate. To ensure data reliability, Low-Density Parity-Check (LDPC) codes with strong error correction capabilities are widely integrated into TLC NAND flash memory controllers. The core performance of an LDPC decoder lies in the accuracy of its iterative calculation of the Log-Likelihood Ratio (LLR) information output by the flash channel. The LLR directly reflects the likelihood relationship between the received codeword and the original codeword, and its accuracy is crucial to the decoding success rate.

[0003] In the hardware implementation of LDPC decoding, due to limitations in hardware resources (such as memory and computation unit bit width), it is usually necessary to quantize the theoretical floating-point LLR into a fixed-point number with a finite bit width. This quantization process inevitably causes a loss of LLR precision, especially when the hardware bit width is narrow, the loss of numerical precision is more significant, thereby directly weakening the error correction capability of the LDPC decoder and leading to a decrease in decoding performance.

[0004] To mitigate the performance loss caused by quantization, the academic community has proposed various optimization schemes. These schemes mainly revolve around two directions: First, optimizing the generation or calculation process of LLR itself to improve its accuracy. For example, some studies have improved numerical resolution by modifying the normalized minimum sum algorithm to limit the magnitude of the minimum value in the check node update; other works have considered the interference characteristics of flash memory channels and incorporated them into the LLR calculation model to improve its accuracy. Second, utilizing the error mode characteristics of flash memory to optimize LLR.

[0005] While existing technologies have improved the quantization problem of LLR to some extent, they fail to finely distinguish the reliability differences of LLR data. In the flash memory threshold voltage distribution, data in the central region has high reliability and a larger corresponding LLR value; while data in the intersection region of adjacent states is highly prone to errors, resulting in a smaller and difficult-to-distinguish LLR value. Existing uniform quantization or simple non-uniform quantization strategies fail to provide higher resolution for these critical but error-prone small-amplitude LLR values, leading to insufficient error correction capability of the decoder for the most critical error bits. Summary of the Invention

[0006] The purpose of this invention is to address the problem that existing uniform quantization or simple non-uniform quantization strategies in the prior art fail to provide higher resolution for these critical but error-prone small amplitude LLR values, resulting in insufficient error correction capability of the decoder for the most critical error bits. This invention provides a log-likelihood ratio dynamic quantization method and system for flash memory.

[0007] To achieve the above objectives, the present invention employs the following technical solution: A dynamic quantization method for log-likelihood ratio in flash memory includes the following steps: Obtain the threshold voltage information in the flash memory, convert the threshold voltage information into a log-likelihood ratio, and obtain the initial log-likelihood ratio dataset; Based on different quantization bit widths, cluster analysis was performed on the initial log-likelihood ratio dataset to divide all log-likelihood ratios into multiple intervals with different amplitude ranges. Based on the interval division results, for each interval ratio, a dynamic quantization factor is generated, and based on the dynamic quantization factor and the corresponding log-likelihood ratio within the interval, a quantized log-likelihood ratio is generated, thus completing the dynamic quantization of the log-likelihood ratio.

[0008] A further improvement of the present invention is that: The process of acquiring threshold voltage information within the flash memory, converting the threshold voltage information into a log-likelihood ratio, and obtaining an initial log-likelihood ratio dataset includes: Threshold voltage information is read from the NAND flash memory channel. For the three page types LSB, CSB and MSB in TLC flash memory, the corresponding log-likelihood ratio calculation model is constructed to obtain the floating-point log-likelihood ratio. The log-likelihood ratio (LLR) information corresponding to the MSB page is converted using the following formula:

[0009] The log-likelihood ratio information corresponding to the CSB page is converted using the following formula:

[0010] The log-likelihood ratio information corresponding to the LSB page is converted using the following formula:

[0011] in, Characterizing programming state The threshold voltage probability density function; The left reference voltage boundary represents the detection threshold voltage state; This represents the right-hand reference voltage boundary of the detection threshold voltage state.

[0012] The initial log-likelihood ratio dataset is clustered based on the quantization bit width, dividing all log-likelihood ratios into multiple intervals with different amplitude ranges, including: When the bit width is 3 bits, no category distinction is made; When the bit width is 4 bits, the LLR amplitude range is [0, 7]. After cluster analysis, it is divided into two intervals: [0, 3] and [3, 7]. When the bit width is 5 bits, the LLR amplitude range is [0, 15]. After cluster analysis, it is divided into three intervals: [0, 3], [3, 10] and [10, 15]. When the bit width is 6 bits, the LLR amplitude range is [0, 31]. After cluster analysis, it is divided into three intervals: [0, 9], [9, 20], and [20, 31].

[0013] The dynamic quantification factor corresponding to each interval ratio based on the interval division results includes: Define a set of candidate quantization factors for each interval, and use each candidate quantization factor in the set as the initial log-likelihood ratio for the current interval to obtain the quantized log-likelihood ratio. The quantized log-likelihood ratio is input into the LDPC decoder for decoding, and the bit error rate of the decoded output is calculated. Compare the bit error rates of all candidate quantization factors in the current interval, and select the candidate quantization factor with the lowest bit error rate as the optimal quantization factor for the current interval.

[0014] The generated quantized log-likelihood ratio, based on the dynamic quantization factor and the corresponding log-likelihood ratio within the interval, is expressed by the following formula:

[0015] in, This is the optimal quantization factor assigned to the i-th LLR interval.

[0016] A log-likelihood ratio dynamic quantization system for flash memory, comprising: The initial data acquisition module is used to acquire threshold voltage information in flash memory, convert the threshold voltage information into log-likelihood ratio, and obtain the initial log-likelihood ratio dataset. The clustering analysis module is used to perform clustering analysis on the initial log-likelihood ratio dataset based on different quantization bit widths, dividing all log-likelihood ratios into multiple intervals with different amplitude ranges. The dynamic quantization factor matching module is used to generate a quantized log-likelihood ratio based on the dynamic quantization factor corresponding to each interval matching result and the log-likelihood ratio within the corresponding interval, thus completing the dynamic quantization of the log-likelihood ratio.

[0017] The processing steps of the clustering analysis module include: When the bit width is 3 bits, no category distinction is made; When the bit width is 4 bits, the log-likelihood ratio amplitude ranges from [0, 7]. After cluster analysis, it is divided into two intervals: [0, 3] and [3, 7]. When the bit width is 5 bits, the log-likelihood ratio range is [0, 15]. After cluster analysis, it is divided into three intervals: [0, 3], [3, 10], and [10, 15]. When the bit width is 6 bits, the log-likelihood ratio range is [0, 31]. After cluster analysis, it is divided into three intervals: [0, 9], [9, 20], and [20, 31].

[0018] A computer program product includes a computer program, characterized in that the computer program, when executed by a processor, implements the method described in any one of the present invention.

[0019] A terminal device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described in this invention.

[0020] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described in this invention.

[0021] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a dynamic quantization method for log-likelihood ratios in flash memory. After obtaining an initial log-likelihood ratio dataset, cluster analysis is used to classify all log-likelihood ratios into intervals with different amplitude ranges. Then, the quantization factor is dynamically adjusted according to the magnitude of the log-likelihood ratio values ​​and their respective categories. For log-likelihood ratios in different regions, a refined quantization factor is used to enhance their resolution, thereby improving the decoder's error correction capability for this type of key data. Without destroying the relative magnitude relationship of the original log-likelihood ratios, higher quantization precision is assigned to these log-likelihood ratios, thereby optimizing the overall quality of the log-likelihood ratio information fed into the LDPC decoder and improving the decoder's error correction capability. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a general framework diagram disclosed in the embodiments of the present invention; Figure 2 This is a comparison chart of the number of iterations for different decoding mechanisms with 3 bits and 4 bits as disclosed in the embodiments of the present invention; Figure 3 This is a comparison chart of the number of iterations for different decoding mechanisms with 5 bits and 6 bits as disclosed in the embodiments of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0029] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0030] The present invention will now be described in further detail with reference to the accompanying drawings: See Figure 1 This invention discloses a dynamic log-likelihood ratio quantization method for flash memory, specifically a classification-based dynamic log-likelihood ratio quantization method for three-dimensional TLC NAND flash memory. By improving the quantization accuracy of key data with limited hardware bit width, it enhances the error correction capability of the LDPC decoder and reduces the average decoding latency without significantly increasing hardware overhead.

[0031] In this embodiment, LLR stands for Log-Likelihood Ratio.

[0032] The core of the quantization method disclosed in this embodiment lies in abandoning the traditional fixed-bit-width or simple non-uniform LLR quantization strategy and instead adopting a data-driven quantization method. Specifically, after the initial LLR calculation, a clustering algorithm is used to classify the LLR values, and the quantization factor is dynamically adjusted according to the magnitude of the LLR value and its category: for LLR values ​​in different regions, a refined quantization factor is used to enhance their resolution, thereby improving the decoder's error correction capability for this type of critical data. Without disrupting the relative magnitude relationship of the original LLRs, higher quantization precision is assigned to these LLRs, thereby optimizing the overall quality of the LLR information fed into the LDPC decoder.

[0033] Specifically, the following steps are included: See Figure 1 This embodiment discloses a dynamic quantization method for the log-likelihood ratio of flash memory, including the following steps: Step 1: Initial Quantization and LLR Data Acquisition Threshold voltage information is read from the NAND flash memory channel and converted into initial floating-point LLR information. TLC flash memory contains three types of pages. By establishing differentiated LLR calculation models for LSB pages, CSB pages, and MSB pages, a floating-point LLR derivation method based on the analytical relationship between the probability density function and the reference voltage is proposed, as shown in formulas (1)-(3): Furthermore, the log-likelihood ratio information corresponding to the MSB page is transformed using the following formula:

[0034] in, Characterizing programming state The threshold voltage probability density function, and These represent the left and right reference voltage boundaries for the detection threshold voltage state, respectively.

[0035] Step 2: Cluster-based LLR classification Unsupervised clustering analysis was performed on the initial LLR dataset obtained in step 1 using the k-means clustering algorithm. All LLR data were divided into different categories based on the distribution characteristics of the LLR values. Since the initial LLR values ​​differed under different quantization bit widths, clustering analysis was performed separately for each quantization bit width to achieve differentiated interval division of the LLR value range. The clustering results are as follows: 3-bit quantization: The sign of the LLR value is not considered. The LLR amplitude range is small, [0,3]. No category classification is performed, and it is processed uniformly.

[0036] 4-bit quantization: The LLR amplitude range is [0,7], which is divided into two intervals [0,3] and [3,7] based on the clustering results.

[0037] 5-bit quantization: The LLR amplitude range is [0, 15]. Experiments have verified that a multi-interval division strategy is adopted, namely [0, 3], [3, 10], and [10, 15].

[0038] 6-bit quantization: The LLR amplitude range is [0, 31]. Experiments have verified that a multi-interval division strategy is adopted, namely [0, 9], [9, 20], and [20, 31].

[0039] This step can screen out key LLRs with small amplitudes and overlapping threshold voltage distributions, providing a structural basis for subsequent quantization.

[0040] Step 3: Dynamic Quantization Factor Allocation and Fine Quantization Based on the clustering and interval partitioning results in step 2, the core of this step is to configure a specific linear quantization (amplification) factor, optimized through simulation, for each partitioned LLR numerical interval. This strategy aims to improve the numerical resolution of the threshold voltage distribution crossover region (corresponding to small-amplitude LLR) through non-uniform quantization, thereby alleviating the problem of insufficient sensitivity of decoding algorithms such as Min-Sum to small LLR values ​​and enhancing the decoder's discrimination and error correction capabilities. Specifically, it includes the following steps: Furthermore, this embodiment discloses the quantization factor configuration rule: the quantization process adopts non-uniform quantization, and the formula is as follows: (4) in, This refers to the quantization factor assigned to the i-th LLR interval. The specific value of the quantization factor is not set manually, but is automatically optimized through exhaustive search simulation, as described later, with the criterion of minimizing the decoding error rate.

[0041] Furthermore, embodiments of the present invention disclose an optimization selection mechanism for the quantization factor: Optimal for each interval The optimal quantization factor is determined through a performance feedback-based optimization process. Specifically, a simulation search algorithm is used to define a set of candidate factors for each interval. Then, through iterative simulation, the quantized LLR obtained after applying different factors is fed into an LDPC decoder for decoding, and the corresponding bit error rate is calculated. Finally, the candidate factor that minimizes the system bit error rate is independently selected for each interval as the final optimized quantization factor for that interval. This method ensures that the quantization parameters achieve optimal matching with specific channel characteristics, flash memory technology, and decoding algorithms.

[0042] In this embodiment, the simulation search algorithm steps include: Obtain the original LLR dataset from step 1, the pre-divided interval boundaries from step 2, and the set of candidate quantization factors for each interval.

[0043] For each interval divided in step 2, perform a simulation search: First, each candidate quantization factor corresponding to the interval is applied to the original LLR data of the interval in turn to generate the quantized LLR sequence; Subsequently, the quantized complete LLR sequence is input into the LDPC decoder for decoding, and the bit error rate of the decoded output is calculated.

[0044] Finally, the decoding error rates corresponding to all candidate quantization factors in the interval are compared, and the candidate factor that produces the lowest error rate is selected as the optimal quantization factor for the interval. Finally, the set of optimal quantization factors for all intervals is output.

[0045] Step 4: LDPC Decoding Execution The final LLR value, after dynamic fine quantization processing in step 3, is fed into the LDPC decoder for iterative decoding. To illustrate the implementation of this invention and verify its effectiveness, in a preferred embodiment, the following decoding system configuration is used: This embodiment also discloses LDPC code parameters: an LDPC code with a code rate of 0.9 is used, and the length of its encoded information block is 3.6K bits.

[0046] Core decoding algorithm: Min-Sum algorithm is used, with a maximum number of iterations of 30.

[0047] Application of quantization parameters: The classification quantization factors with different quantization bit widths (e.g., 3, 4, 5, 6 bits) obtained in the preceding steps of this invention are applied to the initial LLR message quantization in the corresponding scenario. During this process, the relative magnitude relationship between different LLR values ​​is strictly maintained.

[0048] This embodiment discloses an LDPC dynamic quantization decoding optimization scheme based on k-means classification: cluster analysis is performed on the initially calculated LLR information, and dynamic quantization is implemented accordingly. This maintains the relative size relationship of the original LLRs while accurately improving the quantization resolution of key LLR regions. This enhances the decoder's error correction capability, especially its ability to handle small LLR information, and avoids excessive quantization noise. Experimental data shows that the scheme described in this invention can reduce the average number of decoding iterations by 43.6%.

[0049] The overall process of this scheme begins with the initial log-likelihood ratio (LLR) obtained from the flash memory channel. First, the system uses k-means to perform unsupervised classification of the initial LLR values ​​of the channel, dividing them into three categories with different reliability characteristics: Category 1 (small LLR), Category 2 (medium LLR), and Category 3 (large LLR). Then, fine-grained quantization factors are applied to the data characteristics of different categories, performing dynamic and precise quantization. This quantization process can be flexibly configured with different quantization bit widths, such as 3 bits, 4 bits, or 5 or 6 bits, depending on resource and performance requirements. Finally, the optimized fine-grained LLR is fed into the LDPC decoder to complete the error correction decoding process, thereby achieving the goal of significantly improving decoding performance with limited hardware resources. See Figure 2The number of decoding iterations under different RBER conditions was compared when the initial LLR bit width was 3 bits and 4 bits. The results show that with a 3-bit bit width, the min-sum algorithm with minimum optimization has the lowest number of iterations, and the proposed method (classification-based dynamic LDPC, CDLDPC) outperforms the standard algorithm. When the bit width increases to 4 bits, the number of iterations of CDLDPC drops to the lowest among the three, and is significantly less than that of the standard algorithm; in contrast, the min-sum algorithm with minimum optimization only shows a slight improvement.

[0050] See Figure 3 This further demonstrates the comparison of iteration counts under initial LLR widths of 5 bits and 6 bits. Under the 5-bit condition, the standard algorithm has the highest number of iterations, the min-sum algorithm for optimizing the minimum value is not significantly different, while CDLDPC achieves a significant reduction. When the bit width reaches 6 bits, CDLDPC remains optimal, and the min-sum algorithm for optimizing the minimum value still performs close to the standard algorithm. Quantitative analysis shows that as the LLR bit width increases from 3 bits to 5 bits, the iteration reduction of CDLDPC compared to the standard algorithm gradually increases from 16.3% to 44.7%; at a bit width of 6 bits, the number of iterations is still reduced by 6%.

[0051] This embodiment also discloses a log-likelihood ratio dynamic quantization system for flash memory, comprising: The initial data acquisition module is used to acquire threshold voltage information in flash memory, convert the threshold voltage information into log-likelihood ratio, and obtain the initial log-likelihood ratio dataset. The clustering analysis module is used to perform clustering analysis on the initial log-likelihood ratio dataset based on different quantization bit widths, dividing all log-likelihood ratios into multiple intervals with different amplitude ranges. The dynamic quantization factor matching module is used to generate a quantized log-likelihood ratio based on the dynamic quantization factor corresponding to each interval matching result and the log-likelihood ratio within the corresponding interval, thus completing the dynamic quantization of the log-likelihood ratio.

[0052] A schematic diagram of a terminal device according to an embodiment of the present invention. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps in the various method embodiments described above. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the various device embodiments described above.

[0053] The computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention.

[0054] The terminal device can be a desktop computer, laptop computer, cloud server, or other device with strong computing power. The terminal device may include, but is not limited to, a processor and memory.

[0055] The optimal choice for the processor is a multi-core high-speed central processing unit (CPU).

[0056] The memory can be used to store the computer program and / or module. The processor implements various functions of the terminal device by running or executing the computer program and / or module stored in the memory and calling the data stored in the memory.

[0057] If the modules / units integrated into the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0058] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic quantization method for log-likelihood ratio in flash memory, characterized in that, Includes the following steps: Obtain the threshold voltage information in the flash memory, convert the threshold voltage information into a log-likelihood ratio, and obtain the initial log-likelihood ratio dataset; Based on different quantization bit widths, cluster analysis was performed on the initial log-likelihood ratio dataset to divide all log-likelihood ratios into multiple intervals with different amplitude ranges. Based on the interval division results, for each interval ratio, a dynamic quantization factor is generated, and based on the dynamic quantization factor and the corresponding log-likelihood ratio within the interval, a quantized log-likelihood ratio is generated, thus completing the dynamic quantization of the log-likelihood ratio.

2. The log-likelihood ratio dynamic quantization method for flash memory according to claim 1, characterized in that, The process of acquiring threshold voltage information within the flash memory, converting the threshold voltage information into a log-likelihood ratio, and obtaining an initial log-likelihood ratio dataset includes: Threshold voltage information is read from the NAND flash memory channel. For the three page types LSB, CSB and MSB in TLC flash memory, the corresponding log-likelihood ratio calculation model is constructed to obtain the floating-point log-likelihood ratio. The log-likelihood ratio (LLR) information corresponding to the MSB page is converted using the following formula: The log-likelihood ratio information corresponding to the CSB page is converted using the following formula: The log-likelihood ratio information corresponding to the LSB page is converted using the following formula: in, Characterizing programming state The threshold voltage probability density function; The left reference voltage boundary represents the detection threshold voltage state; This represents the right-hand reference voltage boundary of the detection threshold voltage state.

3. The log-likelihood ratio dynamic quantization method for flash memory according to claim 1, characterized in that, The initial log-likelihood ratio dataset is clustered based on the quantization bit width, dividing all log-likelihood ratios into multiple intervals with different amplitude ranges, including: When the bit width is 3 bits, no category distinction is made; When the bit width is 4 bits, the LLR amplitude range is [0, 7]. After cluster analysis, it is divided into two intervals: [0, 3] and [3, 7]. When the bit width is 5 bits, the LLR amplitude range is [0, 15]. After cluster analysis, it is divided into three intervals: [0, 3], [3, 10] and [10, 15]. When the bit width is 6 bits, the LLR amplitude range is [0, 31]. After cluster analysis, it is divided into three intervals: [0, 9], [9, 20], and [20, 31].

4. The log-likelihood ratio dynamic quantization method for flash memory according to claim 1, characterized in that, The dynamic quantification factor corresponding to each interval ratio based on the interval division results includes: Define a set of candidate quantization factors for each interval, and use each candidate quantization factor in the set as the initial log-likelihood ratio for the current interval to obtain the quantized log-likelihood ratio; The quantized log-likelihood ratio is input into the LDPC decoder for decoding, and the bit error rate of the decoded output is calculated. Compare the bit error rates of all candidate quantization factors in the current interval, and select the candidate quantization factor with the lowest bit error rate as the optimal quantization factor for the current interval.

5. The log-likelihood ratio dynamic quantization method for flash memory according to claim 4, characterized in that, The generated quantized log-likelihood ratio, based on the dynamic quantization factor and the corresponding log-likelihood ratio within the interval, is expressed by the following formula: in, This is the optimal quantization factor assigned to the i-th LLR interval.

6. A log-likelihood ratio dynamic quantization system for flash memory, characterized in that, include: The initial data acquisition module is used to acquire threshold voltage information in flash memory, convert the threshold voltage information into log-likelihood ratio, and obtain the initial log-likelihood ratio dataset. The clustering analysis module is used to perform clustering analysis on the initial log-likelihood ratio dataset based on different quantization bit widths, dividing all log-likelihood ratios into multiple intervals with different amplitude ranges. The dynamic quantization factor matching module is used to generate a quantized log-likelihood ratio based on the dynamic quantization factor corresponding to each interval matching result and the log-likelihood ratio within the corresponding interval, thus completing the dynamic quantization of the log-likelihood ratio.

7. A log-likelihood ratio dynamic quantization system for flash memory according to claim 6, characterized in that, The processing steps of the clustering analysis module include: When the bit width is 3 bits, no category distinction is made; When the bit width is 4 bits, the log-likelihood ratio amplitude ranges from [0, 7]. After cluster analysis, it is divided into two intervals: [0, 3] and [3, 7]. When the bit width is 5 bits, the log-likelihood ratio range is [0, 15]. After cluster analysis, it is divided into three intervals: [0, 3], [3, 10], and [10, 15]. When the bit width is 6 bits, the log-likelihood ratio range is [0, 31]. After cluster analysis, it is divided into three intervals: [0, 9], [9, 20], and [20, 31].

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-5.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-5.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-5.

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