Scheduling method and device for direct memory access and electronic equipment

Abstract

The embodiment of the invention provides a direct memory access scheduling method and device and electronic equipment. The method comprises the steps that in response to the fact that a preset starting condition is met, at least one channel is selected from a channel queue from front to back to serve as a second channel, and the channel queue is initially formed by arranging N first channels; for each second channel, deleting the second channel in the channel queue, driving the control unit to schedule a physical port of the direct memory access controller to read the data to the cache, and writing the data to a destination address of direct memory access from the cache; and in response to the second equipment accessed to each second channel completing direct memory access, adding each second channel to the tail of the channel queue, and in response to the preset starting condition being reached again, returning to execute the step of selecting at least one channel from the channel queue as the second channel according to the sequence from front to back. The reduction of direct memory access efficiency caused by unbalanced physical port resource allocation can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit (IC) technology, and in particular to a scheduling method, apparatus and electronic device for direct memory access. Background Technology

[0002] To expand the host's functionality, various external devices with different functions can be connected to the host. These external devices need to interact with the host's memory to perform their functions, and these accesses often require the intervention of the host's Central Processing Unit (CPU). This data interaction can lead to excessive CPU load, affecting the normal operation of the host.

[0003] In related technologies, a Direct Memory Access Controller (DMAC) can be built into the host machine, enabling data exchange between external devices and host memory without CPU intervention. This data exchange method is called direct memory access.

[0004] When multiple external devices are connected to the host, these devices can be assigned to different physical ports of the DMAC, allowing each physical port to independently handle direct memory access for its respective external device. However, different external devices consume different amounts of bandwidth when performing direct memory access, resulting in some physical ports experiencing lower bandwidth loads while others face higher loads, thus affecting the efficiency of direct memory access. Summary of the Invention

[0005] The purpose of this application is to provide a scheduling method, apparatus, and electronic device for direct memory access, so as to reduce the efficiency degradation of direct memory access caused by uneven allocation of physical port resources. The specific technical solution is as follows:

[0006] This application provides a direct memory access scheduling method applied to a direct memory access controller in a first device. The direct memory access controller includes N first channels, a control unit, and a cache. Each first channel is connected to a different second device, where N is greater than 1. The method includes:

[0007] In response to the achievement of a preset start-up condition, at least one channel is selected from the channel queue in a front-to-back order as a second channel, wherein the channel queue is initially formed by the N first channels arranged together;

[0008] For each of the second channels, the second channel is deleted from the channel queue, and the control unit is driven to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device accessing the memory in the first device.

[0009] In response to the second device accessing each of the second channels completing direct memory access, each of the second channels is added to the end of the channel queue.

[0010] In one possible embodiment, the first device maintains a software switch for each of the first channels, the software switch being used to switch the associated first channel between an on state and an off state;

[0011] The step of adding each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access includes:

[0012] In response to the completion of direct memory access by the second device connected to each of the second channels, the state of each of the second channels is determined respectively;

[0013] The second channel, which is in the "on" state, is added to the end of the channel queue.

[0014] In one possible embodiment, the direct memory access controller includes M channels, where M is not less than N; the N first channels are all the channels among the M channels that are initially in the enabled state; the method further includes:

[0015] In response to the completion of direct memory access by the second device connected to each of the second channels, if at least one of the M channels is switched to the enabled state during the completion of direct memory access, the channel queue is cleared and all channels in the enabled state are sequentially added to the channel queue; and when the preset start condition is met again, at least one channel is selected from the channel queue in front-to-back order as the second channel.

[0016] If none of the M channels are switched to the enabled state during the completion of direct memory access, then the state of each of the second channels is determined.

[0017] In one possible embodiment, the method further includes:

[0018] If a preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then after sequentially adding all the channels in the M channels that are in the open state to the channel queue, at least one channel is selected from the channel queue in order from front to back as the second channel.

[0019] If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the open state among the M channels to the channel queue, then wait until the preset start condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel.

[0020] In one possible embodiment, reading the data requested by direct memory access into the cache and writing it from the cache to the destination address of direct memory access includes: performing read and write operations in parallel until both read and write operations are completed;

[0021] The read operation includes: obtaining the source address and target data length of the direct memory access; reading data from the source address in batches until the target data length is read, and writing it into the cache, wherein the length of the data read in each batch does not exceed a preset first length threshold;

[0022] The write operation includes: obtaining the destination address of the direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold.

[0023] In one possible embodiment, the method further includes:

[0024] If an interrupt signal is received during the parallel execution of read and write operations, the read operation is terminated in response to the completion of reading the current batch of data; and the write operation is terminated in response to the completion of writing the current batch of data.

[0025] After the read and write operations are terminated, the cache is cleared and each of the second channels is added to the end of the channel queue.

[0026] This application embodiment also provides a direct memory access scheduling device, applied to a direct memory access controller in a first device. The direct memory access controller includes N first channels, a control unit, and a cache. Each first channel is connected to a different second device, wherein N is greater than 1. The device includes:

[0027] The channel selection module is used to select at least one channel from the channel queue as a second channel in order from front to back in response to the achievement of a preset start condition, wherein the channel queue is initially formed by the N first channels arranged in sequence;

[0028] The channel deletion module is used to delete the second channel from the channel queue for each second channel, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device accessing the memory in the first device.

[0029] The channel addition module is used to add each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access.

[0030] In one possible embodiment, the first device maintains a software switch for each of the first channels, the software switch being used to switch the associated first channel between an on state and an off state;

[0031] The step of adding each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access includes:

[0032] In response to the completion of direct memory access by the second device connected to each of the second channels, the state of each of the second channels is determined respectively;

[0033] The second channel, which is in the "on" state, is added to the end of the channel queue.

[0034] In one possible embodiment, the direct memory access controller includes M channels, where M is not less than N; the N first channels are all the channels among the M channels that are initially in the enabled state; the device further includes:

[0035] The channel clearing module is used to respond to the completion of direct memory access by the second device connected to each of the second channels. If at least one of the M channels is switched to the open state during the completion of direct memory access, the channel queue is cleared and all the channels in the open state are added to the channel queue in sequence. When the preset start condition is met again, at least one channel is selected from the channel queue in front-to-back order as the second channel.

[0036] The channel determination module is used to determine the state of each of the second channels if none of the M channels are switched to the open state during the completion of direct memory access.

[0037] In one possible embodiment, the device further includes:

[0038] The execution module is configured to, if a preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then after sequentially adding all the channels in the M channels that are in the open state to the channel queue, select at least one channel from the channel queue in a front-to-back order as the second channel.

[0039] If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the open state among the M channels to the channel queue, then wait until the preset start condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel.

[0040] In one possible embodiment, reading the data requested by direct memory access into the cache and writing it from the cache to the destination address of direct memory access includes: performing read and write operations in parallel until both read and write operations are completed;

[0041] The read operation includes: obtaining the source address and target data length of the direct memory access; reading data from the source address in batches until the target data length is read, and writing it into the cache, wherein the length of the data read in each batch does not exceed a preset first length threshold;

[0042] The write operation includes: obtaining the destination address of the direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold.

[0043] In one possible embodiment, the device further includes:

[0044] An operation termination module is configured to terminate the read operation if an interrupt signal is received during the parallel execution of read and write operations, in response to the completion of reading the current batch of data in the read operation; and to terminate the write operation in response to the completion of writing the current batch of data in the write operation.

[0045] The cache clearing module is used to clear the cache and add each of the second channels to the end of the channel queue after the read operation and the write operation are terminated.

[0046] This application also provides an electronic device, including:

[0047] Memory, used to store computer programs;

[0048] A processor, when executing a program stored in memory, implements any of the direct memory access scheduling methods described above.

[0049] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the direct memory access scheduling methods described above.

[0050] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute any of the direct memory access scheduling methods described above.

[0051] Beneficial effects of the embodiments in this application:

[0052] This application provides a direct memory access scheduling method, apparatus, and electronic device. After each preset startup condition is met, a second channel is selected from the front of the channel queue, and these second channels are subsequently added back to the end of the channel queue, thus ensuring that each first channel can be selected as a second channel. Since each first channel is connected to a different second device, and the second device connected to the second channel will perform direct memory access (i.e., the drive control unit schedules the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache and write it from the cache to the destination address of the direct memory access), selecting the second channel can be considered as selecting a second device for direct memory access. Furthermore, since the selected second channel is different each time, it can be considered as selecting a different second device for direct memory access each time. Since each direct memory access is implemented through the same batch of physical ports, it can be considered as reusing the same batch of physical ports in the DMAC to implement direct memory access for different second devices; that is, each physical port is no longer used only for direct memory access of a fixed second device. In this way, even if different second devices use different bandwidths when performing direct memory access, the bandwidth pressure between each physical port can be flexibly balanced to reduce the decrease in direct memory access efficiency caused by uneven allocation of physical port resources.

[0053] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0055] Figure 1 A schematic diagram of a first flowchart of a direct memory access scheduling method provided in an embodiment of this application;

[0056] Figure 2 A second flowchart illustrating the scheduling method for direct memory access provided in an embodiment of this application;

[0057] Figure 3 A third flowchart illustrating the scheduling method for direct memory access provided in this application embodiment;

[0058] Figure 4 A schematic diagram of the fourth process of the direct memory access scheduling method provided in the embodiments of this application;

[0059] Figure 5 A fifth flowchart illustrating the direct memory access scheduling method provided in this application embodiment;

[0060] Figure 6 A schematic diagram of a direct memory access scheduling device provided in an embodiment of this application;

[0061] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0062] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0063] To reduce the efficiency degradation of direct memory access caused by uneven allocation of physical port resources, this application provides a direct memory access scheduling method applied to a direct memory access controller in a first device. The direct memory access controller includes N first channels, a control unit, and a cache. Each first channel is connected to a different second device, where N is greater than 1. See also... Figure 1 The methods include:

[0064] S101, in response to the achievement of the preset start condition, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0065] The channel queue is initially formed by arranging N first channels.

[0066] S102, for each second channel, delete the second channel in the channel queue, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write the destination address of the direct memory access from the cache, so as to realize the direct memory access of the second device connected to the second channel to the memory in the first device.

[0067] S103, in response to the second device accessing each second channel completing direct memory access, adds each second channel to the end of the channel queue.

[0068] By applying the embodiments of this application, a second channel can be selected from the front of the channel queue each time the preset startup conditions are met, and these second channels can then be added back to the end of the channel queue, thus ensuring that each first channel can be selected as a second channel. Since each first channel connects to a different second device, and the second device connected to the second channel will perform direct memory access (DMI), meaning the drive control unit schedules the physical ports of the DMI controller to read the data requested by DMI into the cache and write it from the cache to the destination address of DMI, selecting a second channel can be considered as selecting a second device for DMI. Furthermore, since the selected second channel is different each time, it can be considered as selecting a different second device for DMI each time. Since each DMI is implemented through the same batch of physical ports, it can be considered as reusing the same batch of physical ports in the DMAC to implement DMI access for different second devices; that is, each physical port is no longer used only for DMI access of a fixed second device. Thus, even if different second devices occupy different bandwidths when performing DMI, the bandwidth pressure between the various physical ports can be flexibly balanced to reduce the decrease in DMI access efficiency caused by uneven allocation of physical port resources.

[0069] The following will provide exemplary descriptions of S101-S103 respectively:

[0070] In S101, the preset start condition may refer to receiving an access request sent by the second device. In this embodiment, after receiving the access request sent by the second device, the DMAC responds to the access request by selecting at least one channel from the channel queue in order from front to back as the second channel.

[0071] The preset startup condition can also refer to the DMAC generating a startup signal. In this embodiment, after receiving an access request sent by the second device, the DMAC generates a startup signal and, in response to the generated startup signal, selects at least one channel from the channel queue in order from front to back as the second channel.

[0072] The maximum number of channels that DMAC can select at any given time is defined as the number of direct memory accesses from the second device to the memory of the first device that DMAC supports in parallel execution. For example, if DMAC supports only 3 direct memory accesses from the second device to the memory of the first device at a time, then the maximum number of channels that DMAC can select at any given time is 3. For ease of description, this maximum number of channels that DMAC can select at any given time will be referred to as the selection limit.

[0073] Specifically, if the number of received access requests is less than the selection limit, the DMAC selects the same number of channels as the number of received access requests. For example, assuming the selection limit is 3, and the DMAC receives 2 access requests from the second device (i.e., the number of received access requests is 2), which is less than the selection limit, then in this example, the DMAC, in response to the received access requests, selects 2 channels from the channel queue in reverse order as the second channel.

[0074] If the number of received access requests is not less than the selection limit, the number of channels selected by DMAC is the selection limit, so as to enable the second device accessing the selected channel to directly access the memory in the first device (that is, to process the access request). After the second device accessing the selected channel completes the direct memory access (that is, to process the access request), in response to the unprocessed access request, DMAC reselects the channel.

[0075] For example, suppose the maximum number of channels that DMAC can select at a time is 3. DMAC receives 5 access requests from second devices, meaning the total number of received access requests is 5, which exceeds the selection limit. In this example, in response to the received access requests, DMAC selects 3 channels from the channel queue in sequential order as the second channels. These 3 second channels are each connected to a second device, enabling direct memory access from the second device to the memory of the first device. At this point, 2 of the previously received 5 access requests remain unprocessed.

[0076] For the two unprocessed access requests, DMAC can reselect channels after all three second devices connected to the second channel have completed their direct memory accesses. In this embodiment, since DAMC is not executing direct memory accesses from the second devices to the memory of the first device, DAMC can execute direct memory accesses from the three second devices to the memory of the first device. Therefore, DMAC can select two channels from the channel queue in sequential order as the second channels to process the two unprocessed access requests.

[0077] DMAC can also reselect a channel in response to the two unprocessed access requests after a second device connected to the second channel completes a direct memory access. In this embodiment, since DAMC is executing two direct memory accesses from the second device to the memory of the first device, DAMC can only execute one more direct memory access from the second device to the memory of the first device. Therefore, DMAC can only select one channel from the channel queue as the second channel in order from front to back. This second channel is connected to a second device to realize the direct memory access from the second device to the memory of the first device. At this time, one of the two unprocessed access requests remains unprocessed. Subsequently, after a second device connected to the second channel completes a direct memory access, DMAC responds to the remaining unprocessed access request by selecting one channel from the channel queue in order from front to back as the second channel, and processes the remaining unprocessed access request through the selected second channel.

[0078] In S102, after selecting a second channel, the DMAC removes each second channel from the channel queue. Furthermore, the DMAC has a built-in arbitrator that can obtain the real-time busy level of each physical port of the DMAC, i.e., determine whether each physical port is in a working or idle state. Then, for each second channel, the control unit in the DMAC drives the idle physical ports to enable the second device accessing the memory of the first device via direct memory access. Specifically, the DMAC drive control unit schedules the idle physical ports to read the data requested by the direct memory access into the DMAC's cache through the idle physical ports, and writes the data in the DMAC's cache to the destination address of the direct memory access. Through this method of scheduling physical ports, autonomous scheduling of physical ports can be achieved reasonably based on their busy levels, ensuring a balanced distribution of the DMAC's bus bandwidth and avoiding channel blockage. In other possible embodiments, other components can be built into the DMAC to replace the arbitrator, allowing the real-time acquisition of the busy level of each physical port of the DMAC through these built-in components.

[0079] For example, suppose the DMAC has 10 physical ports, denoted as Port 1 to Port 10, and the second channel is Channel 1, Channel 2, and Channel 3. Assume that Ports 1 to 3 are currently active, while Ports 4 to 10 are idle. Then, for Channel 1, port 4 is scheduled to enable direct memory access to the memory of the first device by the second device connected to Channel 1; for Channel 2, port 5 is scheduled to enable direct memory access to the memory of the first device by the second device connected to Channel 2; and for Channel 3, port 6 is scheduled to enable direct memory access to the memory of the first device by the second device connected to Channel 3.

[0080] In S103, each time a second device connected to the second channel completes a direct memory access, that second channel is added to the end of the channel queue. For example, assuming the channel queue contains five channels (channels 1-5) arranged in order from front to back, in response to the preset startup condition being met, channels 1 and 2 are selected as the second channels and removed from the channel queue. That is, at this point, the channel queue is: Channel 3, Channel 4, Channel 5. Then, if a second device connected to channel 2 completes a direct memory access, channel 2 is added to the end of the channel queue. That is, at this point, the channel queue is: Channel 3, Channel 4, Channel 5, Channel 2. Then, if a second device connected to channel 1 completes a direct memory access, channel 1 is added to the end of the channel queue. That is, at this point, the channel queue is: Channel 3, Channel 4, Channel 5, Channel 2, Channel 1.

[0081] After adding each second channel to the end of the channel queue, if the preset start condition is met again, at least one channel can be selected from the channel queue as a second channel in order from front to back in response to the preset start condition being met again. That is, in response to the preset start condition being met again, the process returns to the execution of the aforementioned step S101.

[0082] To facilitate understanding of the direct memory access scheduling method provided in this application, the following will provide an exemplary description of the direct memory access scheduling method provided in this application with specific examples.

[0083] Assume the channel queue initially consists of 10 first channels, numbered Channel 1 through Channel 5 according to their order in the queue. The maximum number of channels DMAC can select at any given time is 3. Initially, DMAC receives access requests from 4 second devices, numbered Second Device 1 through Second Device 4 according to the chronological order of their reception. In response to the received access requests, DMAC selects Channels 1, 2, and 3 as second channels, removes them from the channel queue, and schedules idle physical ports to allow Second Device 1 (Channel 1) to access the memory of the first device, Second Device 2 (Channel 2) to access the memory of the first device, and Second Device 3 (Channel 3) to access the memory of the first device.

[0084] Subsequently, if the second device 2 connected to channel 2 completes direct memory access, channel 2 is added to the end of the channel queue. That is, at this point, the channel queue consists of: channel 4, channel 5, and channel 2. Furthermore, since the access request received by DMAC from the second device 4 has not been processed, the preset startup conditions have been met. Therefore, DMAC can select channel 4 as the second channel from the channel queue, remove channel 4 from the channel queue, and schedule idle physical ports of DMAC to enable the second device 4 connected to channel 4 to directly access the memory in the first device. Afterward, once the second devices connected to each second channel complete their direct memory access, each second channel is added to the end of the channel queue. By repeating the above process, balanced resource allocation of the DMAC physical ports is achieved.

[0085] The above-described S101-S103 have been illustrated by example. It is understandable that if one or more second devices are temporarily not required to operate, this will result in a larger number of first channels, meaning that redundancy of the first channels is likely to occur. This leads to a decrease in the utilization rate of each first channel, resulting in a decrease in the resource utilization efficiency of the DMAC. Furthermore, since the first channels consume DMAC bus bandwidth and generate dynamic power consumption of related internal circuits, redundant first channels will cause greater DMAC bus bandwidth consumption and more dynamic power consumption of related internal circuits, further reducing the resource utilization efficiency of the DMAC.

[0086] Therefore, to reduce the reduced resource utilization efficiency of DMAC due to redundancy of the first channel, in one possible embodiment, the first device maintains a software switch for each first channel. The software switch is used to switch the corresponding first channel between an on and off state. See also... Figure 2 The direct memory access scheduling method provided in this application includes:

[0087] S101, in response to the achievement of the preset start condition, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0088] The channel queue is initially formed by arranging N first channels.

[0089] S102, for each second channel, delete the second channel in the channel queue, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the second device connected to the second channel to directly access the memory in the first device.

[0090] S101-S102 have been described by example above and will not be repeated here.

[0091] S1031, in response to the second device accessing each second channel completing direct memory access, determine the state of each second channel respectively.

[0092] S1032, add the second channel, which is in the open state, to the end of the channel queue.

[0093] In S1031-S1032, the state of the first channel can be identified in any way. For example, the state of the first channel can be identified by a channel switch signal. When the first channel is in the closed state, the channel switch signal is 0; when the first channel is in the open state, the channel switch signal is 1. Alternatively, when the first channel is in the closed state, the channel switch signal is 1; when the first channel is in the open state, the channel switch signal is 0.

[0094] For each second channel, after the second device connected to the second channel completes memory access, the state of the second channel is determined. If the second channel is in the open state, it means that the second channel will still be needed to implement direct memory access in the future, and the second channel needs to be added to the end of the channel queue.

[0095] If the second channel is in a closed state, it indicates that one or more second devices are temporarily not needed. Since there are a large number of channels currently available, and this second channel is closed, it will not be used for direct memory access in the future. In this case, there is no need to add this second channel to the channel queue. Since channels for direct memory access are selected from the channel queue, this second channel, which is not added to the queue, will not be used for direct memory access.

[0096] After adding the second channel, which is in the active state, to the end of the channel queue, if the preset start condition is met again, at least one channel can be selected from the channel queue as the second channel in order from front to back. That is, in response to the preset start condition being met again, the process returns to the execution of the aforementioned step S101.

[0097] In this embodiment, the first device maintains a software switch to toggle the first channel between the on and off states, and only adds the second channel in the on state to the channel queue. In this way, the redundant first channel is turned off, so that the redundant first channel is not used to implement direct memory access, thereby releasing the bus bandwidth to the first channel in the on state, reducing the occupation of scheduling resources by the redundant first channel, and reducing the dynamic power consumption of the DMAC internal circuits caused by the redundant first channel. This also reduces the reduction in DMAC resource utilization efficiency caused by the redundancy of the first channel.

[0098] In other possible embodiments, hardware switches for each first channel may be provided on the first device, which are used to switch the corresponding first channel between an on state and an off state.

[0099] Understandably, when the second device, which was temporarily not needed, resumes operation, the first channel, which was originally in a closed state, needs to be switched to an open state to avoid a decrease in direct memory access efficiency due to a insufficient number of first channels. Furthermore, the first channel switched to an open state needs to be added to the channel queue to ensure that it can be used normally for direct memory access. Based on this, in one possible embodiment, the direct memory access controller includes M channels. In this embodiment, see [link to relevant documentation]. Figure 3 The direct memory access scheduling method provided in this application includes:

[0100] S101, in response to the achievement of the preset start condition, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0101] The channel queue is initially formed by arranging N first channels out of M channels; the N first channels are all channels that are initially in the open state among the M channels.

[0102] S102, for each second channel, delete the second channel in the channel queue, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the second device connected to the second channel to directly access the memory in the first device.

[0103] S101-S102 have been described by example above and will not be repeated here.

[0104] S1033, in response to the second device connected to each second channel completing direct memory access, if no channel among the M channels is switched to the open state during the completion of direct memory access, then the state of each second channel is determined respectively.

[0105] S1034, add the second channel, which is in the open state, to the end of the channel queue.

[0106] If none of the M channels are switched to the open state during the direct memory access process, it means that the first channel that is not currently switched to the open state needs to be added to the channel queue. In this case, it is only necessary to determine whether each second channel has been switched to the closed state. That is, in this case, it is necessary to determine the state of each second channel and add the second channel that is in the open state to the end of the channel queue.

[0107] The difference between S1033-S1034 and the aforementioned S1031-S1032 lies only in the timing of execution. Specifically, S1033-S1034 is executed when the second device connected to each second channel completes direct memory access, and during the direct memory access process, none of the M channels are switched to the enabled state. S1031-S102 is executed when the second device connected to each second channel completes direct memory access. The method for determining the state of each second channel in S1033-S1034 and the method for adding the enabled second channel to the end of the channel queue are the same as those in S1031-S1032, and therefore will not be repeated here.

[0108] S1035, in response to the second device connected to each second channel completing direct memory access, if at least one of the M channels is switched to the open state during the completion of direct memory access, the channel queue is cleared, and all the channels in the open state among the M channels are added to the channel queue in sequence. When the preset start condition is met again, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0109] If at least one of the M channels is switched to the enabled state during the completion of direct memory access, it means that the first channel that has been switched to the enabled state needs to be added to the channel queue. In this case, the channel queue can be cleared and all the channels that are enabled among the M channels can be added to the channel queue in sequence. This method ensures that all the first channels that are enabled can be added to the channel queue.

[0110] For example, suppose the DMAC includes 10 channels, referred to as channel 1 to channel 10. Channels 1 to 8 are in the open state, while channels 9 and 10 are in the closed state. A second device connected to channel 1 is performing direct memory access on the memory of the first device, and a second device connected to channel 2 is performing direct memory access on the memory of the first device. During the direct memory access process, channel 9 is switched to the open state.

[0111] Subsequently, in response to a second device connected to the second channel completing a direct memory access, the channel queue is cleared, and all channels in the M channels that are currently active are sequentially added to the channel queue. That is, assuming the second device connected to channel 1 completes a direct memory access, in response to this, and during the completion of the direct memory access, one channel (channel 9) is switched to the active state, the channel queue is cleared, and all channels that are active and have completed direct memory access—that is, channels 1, 3 through 9—are sequentially added to the channel queue. Then, after the second device connected to channel 2 completes its direct memory access, channel 2, which is currently active, is added to the end of the channel queue.

[0112] Alternatively, in response to all second devices connected to the second channel completing direct memory access, the channel queue is cleared, and all channels in the M channels that are in the open state are sequentially added to the channel queue. That is, if the second device connected to channel 1 completes direct memory access, and the second device connected to channel 2 completes direct memory access, and during the completion of direct memory access, one channel (channel 9) is switched to the open state, then the channel queue is cleared, and all channels in the open state that have completed direct memory access, i.e., channels 1 to 9, are sequentially added to the channel queue.

[0113] Understandably, in practical applications, the preset startup conditions may be met when the channel queue is cleared. In this case, since the first channel is not included in the channel queue, it cannot be scheduled for direct memory access, causing the direct memory access process to fail. Therefore, to ensure the normal operation of the direct memory access process, see [link to relevant documentation]. Figure 4 The aforementioned S1035 includes Figure 4 In S1036-S1038, the direct memory access scheduling method provided in this application includes:

[0114] S101, in response to the achievement of the preset start condition, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0115] The channel queue is initially formed by arranging N first channels.

[0116] S102, for each second channel, delete the second channel in the channel queue, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the second device connected to the second channel to directly access the memory in the first device.

[0117] S1033, in response to the second device connected to each second channel completing direct memory access, if no channel among the M channels is switched to the open state during the completion of direct memory access, then the state of each second channel is determined respectively.

[0118] S1034, add the second channel, which is in the open state, to the end of the channel queue.

[0119] S101-S102 and S1033-S1034 have been described by example above, and will not be repeated here.

[0120] S1036, in response to the second device connected to each second channel completing direct memory access, if at least one of the M channels is switched to the open state during the completion of direct memory access, then the channel queue is cleared, and all the channels in the open state among the M channels are added to the channel queue in sequence.

[0121] S1037 If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the open state among the M channels to the channel queue, then wait until the preset start condition is met again, and select at least one channel from the channel queue in the order from front to back as the second channel.

[0122] If the preset startup condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, the situation that the first channel cannot be scheduled for direct memory access will not occur because the channel queue does not include the first channel. Therefore, at this time, we can wait until the preset startup condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel, that is, return to execute the aforementioned S101.

[0123] S1038, if the preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then after sequentially adding all the channels in the M channels that are in the open state to the channel queue, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0124] If the preset startup condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then since the preset startup condition has already been met, at this time, in response to the preset startup condition met above, the aforementioned S101-S102 should be executed directly after all the channels in the M channels that are in the open state are sequentially added to the channel queue, so as to realize the second device connected to the second channel directly accessing the memory in the first device.

[0125] The above process is equivalent to: pausing the preset start conditions reached during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue (i.e., back pressure), and after all the channels in the M channels that are in the open state are sequentially added to the channel queue, that is, after the channel queue is reset, in response to the preset start conditions that were paused, the aforementioned S101-S102 are executed to realize the direct memory access of the second device connected to the second channel to the memory in the first device.

[0126] By using this embodiment, if the preset startup condition is met during the step of clearing the channel queue and sequentially adding all the M channels in the open state to the channel queue, the process can directly return to the step of selecting at least one channel from the channel queue as the second channel in the order from front to back after all the M channels in the open state have been added to the channel queue. This eliminates the need to wait for the preset startup condition to be met again before processing the previously met preset startup condition, avoiding the situation where the processing of the previously met preset startup condition is not timely due to long waiting time, and also reducing the decrease in direct memory access efficiency caused by long waiting time.

[0127] The above text has already discussed Figure 4 The embodiments are described exemplarily. The following will exemplarily describe a method for implementing direct memory access of the memory in the first device by a second device connected to the second channel. The method for reading data requested by direct memory access into a cache and writing it from the cache to the destination address of the direct memory access includes: performing read and write operations in parallel until both read and write operations are completed.

[0128] The read operation includes: obtaining the source address and target data length of the direct memory access; reading data from the source address in batches until the target data length is read, and writing it into the cache of the direct memory access controller, wherein the length of the data read in each batch does not exceed a preset first length threshold.

[0129] The write operation includes: obtaining the destination address for direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold.

[0130] The access request sent by the second device contains configuration information, including the source address, target data length, and destination address of the direct memory access required by the second device. DMAC can obtain these information by reading the configuration information from the access request sent by the second device.

[0131] The first and second length thresholds can be configured according to user needs. For example, the first length threshold can be configured to 8 bytes, 16 bytes, etc., and the second length threshold can be configured to 8 bytes, 16 bytes, etc. The first and second length thresholds can be equal or unequal.

[0132] The cache of the direct memory access controller is a first-in, first-out (FIFO) queue, which means that the data read in each batch is written into the FIFO.

[0133] To facilitate understanding of the read and write operations described above, specific examples will be provided below to illustrate each operation. Assume the first length threshold is equal to the second length threshold, and denote the first and second length thresholds as `burst`.

[0134] For a read operation, when reading data from the source address for the first time, the remaining amount of data to be read (denoted as remain_len) is the target data length. In response to the read start (rstart) signal initiated by DMAC, if remain_len is less than burst, then the amount of data to be transferred in this read (denoted as dma_rsize) is remain_len. Only one read is needed to read the target data length. The data read in this read is written into the cache of the direct memory access controller, and the read operation is completed.

[0135] If remain_len is greater than burst, then dma_rsize for this read is burst, which is the upper limit of the data length read in each batch. The data read in this read is written into the cache of the direct memory access controller, and then a second read is required.

[0136] During the second read, `remain_len` is the target data length minus `burst`. If `remain_len` is less than `burst`, then `dma_rsize` is `remain_len` for this read. After the second read, the target data length is read and written to the direct memory access controller's cache, completing the read operation. If `remain_len` is greater than `burst`, then `dma_rsize` is `burst` for this read, and the read data is written to the direct memory access controller's cache. A third read is then required.

[0137] During the third read, `remain_len` is the target data length - 2 `burst`. If `remain_len` is less than `burst`, then `dma_rsize` is `remain_len` for this read. After the third read, the target data length is read, and the data is written to the direct memory access controller's cache, completing the read operation. If `remain_len` is greater than `burst`, then `dma_rsize` is `burst` for this read, and the data is written to the direct memory access controller's cache. A fourth read is then required. This process is repeated until the read operation is complete.

[0138] For write operations, in response to the data in the cache reaching the burst, DMAC initiates a write start (wstart) signal, and in response to the wstart signal, DMAC begins the write operation. After completing a write operation that moves the burst length of data from the cache to the destination address, DMAC checks if the data in the cache has reached the burst. If the data in the cache has reached the burst, DMAC executes the step of writing the burst length of data from the cache to the destination address. If the data in the cache has not reached the burst, and the read operation is not yet complete, DMAC waits for the data in the cache to reach the burst before executing the step of writing the burst length of data from the cache to the destination address. If the data in the cache has not reached the burst, and the read operation is complete, it means that the amount of data to be transferred in the current write operation (denoted as dma_wsize) is the amount of data stored in the cache, and the current write operation can be completed with this write operation. In other words, if the data in the cache has not reached the burst, and the read operation is complete, the amount of data stored in the cache is written to the destination address, and the write operation is complete.

[0139] In one possible embodiment, if an interrupt signal is received during the parallel execution of read and write operations, the read operation is terminated in response to the completion of reading the current batch of data in the read operation; and the write operation is terminated in response to the completion of writing the current batch of data in the write operation; after the read and write operations are terminated, the buffer is cleared and the step of adding each second channel to the end of the channel queue is performed.

[0140] In this embodiment, after receiving an interrupt signal while performing read and write operations in parallel, the reading of the current batch of data continues. The reading of the current batch of data is completed without writing it into the DMAC's cache, and then the read operation is terminated. This method reduces one data writing operation to the cache, thereby increasing the cache's lifespan.

[0141] If an interrupt signal is received during the parallel execution of read and write operations, the writing of the current batch of data continues, and the write operation terminates after the current batch of data is written. After the read and write operations terminate, the data cached in the DMAC is cleared, and the second channel connected to the second device is added to the end of the channel queue.

[0142] In one possible embodiment, the flowchart of the direct memory access scheduling method provided in this application can be as follows: Figure 5 As shown, it includes:

[0143] S501, power on.

[0144] S502, write all channel numbers into the spipe.

[0145] The spipe is the aforementioned channel queue. Initially, all the first channels that are in the open state are written into the spipe.

[0146] S503, waiting for DMA start signal.

[0147] S504, determine if a start signal has been received?

[0148] If yes, that is, a start signal is received, then execute S505; if no, that is, no start signal is received, then execute S503 and continue to wait for a start signal. The situation of receiving a start signal here is equivalent to the aforementioned meeting of the preset start conditions.

[0149] S505, retrieves channel number allocation from the pipe sequence.

[0150] S505 is equivalent to the aforementioned S101-S102, and the relevant descriptions of S101-S102 can be found above, so they will not be repeated here. For example, the x channel, y channel, and z channel can be selected as the second channel, and for each second channel, the second channel is deleted from the channel queue, and the physical port of the direct memory access controller is scheduled to enable the second device connected to the second channel to directly access the memory in the first device.

[0151] S506: When the channel switch is 1, the channel is released back to the pipe; when the channel switch is 0, the channel is not rewritten to the pipe.

[0152] The channel switch is the aforementioned channel switch signal, where 1 indicates that the channel is in the open state and 0 indicates that the channel is in the closed state. S506 is equivalent to S1031-S1032 mentioned above, and you can refer to the relevant explanations of S1031-S1032 above, which will not be repeated here.

[0153] S507, all channels have ended and the channel switches have changed.

[0154] S507 is equivalent to determining whether any of the M channels were switched to the open state during the direct memory access process. If yes, then execute S508; otherwise, return to execute S503.

[0155] S508 clears the spike and writes the enabled channel numbers into the spike in sequence according to the channel switch.

[0156] S508 is equivalent to the aforementioned S1035. Please refer to the previous explanation of S1035, which will not be repeated here.

[0157] Corresponding to the aforementioned direct memory access scheduling method, this application also provides a direct memory access scheduling device, applied to a direct memory access controller in a first device. The direct memory access controller includes N first channels, a control unit, and a cache, with each first channel connected to a different second device, where N is greater than 1. See also... Figure 6 The device includes:

[0158] The channel selection module 601 is used to select at least one channel from the channel queue as a second channel in order from front to back in response to the achievement of a preset start condition. The channel queue is initially formed by N first channels.

[0159] The channel deletion module 602 is used to delete the second channel in the channel queue for each second channel, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device connected to the second channel to the memory in the first device.

[0160] The channel addition module 603 is used to add each second channel to the end of the channel queue in response to the second device accessing each second channel completing direct memory access.

[0161] In one possible embodiment, the first device maintains a software switch for each first channel, the software switch being used to switch the corresponding first channel between an on state and an off state.

[0162] In response to the completion of direct memory access by the second device connected to each second channel, each second channel is added to the end of the channel queue, including:

[0163] In response to the second device connected to each second channel completing direct memory access, the state of each second channel is determined respectively;

[0164] Add the second channel, which is currently active, to the end of the channel queue.

[0165] In one possible embodiment, the direct memory access controller includes M channels, where M is not less than N; the N first channels are all the channels that are initially enabled among the M channels; the device further includes:

[0166] The channel clearing module is used to respond to the second device connected to each second channel completing direct memory access. If at least one of the M channels is switched to the open state during the completion of direct memory access, the channel queue is cleared and all the channels in the open state are added to the channel queue in sequence. When the preset start condition is met again, at least one channel is selected from the channel queue in the order from front to back as the second channel.

[0167] The channel determination module is used to determine the state of each second channel if none of the M channels are switched to the open state during the completion of direct memory access.

[0168] In one possible embodiment, the device further includes:

[0169] The execution module is used to select at least one channel from the channel queue as the second channel if the preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue.

[0170] If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the open channels out of the M channels to the channel queue, then wait until the preset start condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel.

[0171] In one possible embodiment, reading the data requested by direct memory access into a cache and writing it from the cache to the destination address of direct memory access includes: performing read and write operations in parallel until both read and write operations are completed;

[0172] The read operation includes: obtaining the source address and target data length for direct memory access; reading data from the source address in batches until the target data length is reached, and writing it into the cache, wherein the length of each batch of data read does not exceed a preset first length threshold;

[0173] The write operation includes: obtaining the destination address for direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold.

[0174] In one possible embodiment, the device further includes:

[0175] The operation termination module is used to terminate the read operation if an interrupt signal is received during the parallel execution of read and write operations, in response to the completion of reading the current batch of data in the read operation; and to terminate the write operation in response to the completion of writing the current batch of data in the write operation.

[0176] The cache clearing module is used to clear the cache after read and write operations are terminated and add each second channel to the end of the channel queue.

[0177] This application also provides an electronic device, such as... Figure 7 As shown, it includes:

[0178] Memory 701 is used to store computer programs;

[0179] When processor 702 executes a program stored in memory 701, it performs the following steps:

[0180] In response to the achievement of the preset start-up conditions, at least one channel is selected from the channel queue in a front-to-back order as the second channel, wherein the channel queue is initially formed by N first channels arranged in order;

[0181] For each second channel, the second channel is deleted from the channel queue, and the control unit is driven to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device connected to the second channel to the memory in the first device;

[0182] In response to the completion of direct memory access by the second device connected to each second channel, each second channel is added to the end of the channel queue.

[0183] Furthermore, the aforementioned electronic device may also include a communication bus and / or a communication interface, with the processor 702, the communication interface, and the memory 701 communicating with each other via the communication bus.

[0184] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0185] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0186] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0187] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0188] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the direct memory access scheduling methods described above.

[0189] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the direct memory access scheduling methods described in the above embodiments.

[0190] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a solid-state drive (SSD), etc.

[0191] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0192] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, computer-readable storage media, and computer program products containing instructions are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0193] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A scheduling method for direct memory access, characterized in that, A direct memory access controller applied in a first device, the direct memory access controller comprising N first channels, a control unit, and a cache, each first channel being connected to a different second device, wherein N is greater than 1; the method includes: In response to the achievement of a preset start-up condition, at least one channel is selected from the channel queue in a front-to-back order as a second channel, wherein the channel queue is initially formed by the N first channels arranged together; For each of the second channels, the second channel is deleted from the channel queue, and the control unit is driven to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device accessing the memory in the first device. In response to the second device accessing each of the second channels completing direct memory access, each of the second channels is added to the end of the channel queue.

2. The method according to claim 1, characterized in that, The first device maintains a software switch for each of the first channels, and the software switch is used to switch the corresponding first channel between an on state and an off state; The step of adding each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access includes: In response to the completion of direct memory access by the second device connected to each of the second channels, the state of each of the second channels is determined respectively; The second channel, which is in the "on" state, is added to the end of the channel queue.

3. The method according to claim 2, characterized in that, The direct memory access controller includes M channels, where M is not less than N; the N first channels are all the channels among the M channels that are initially in the enabled state; the method further includes: In response to the completion of direct memory access by the second device connected to each of the second channels, if at least one of the M channels is switched to the enabled state during the completion of direct memory access, the channel queue is cleared and all channels in the enabled state are sequentially added to the channel queue; and when the preset start condition is met again, at least one channel is selected from the channel queue in front-to-back order as the second channel. If none of the M channels are switched to the enabled state during the completion of direct memory access, then the state of each of the second channels is determined.

4. The method according to claim 3, characterized in that, The method further includes: If a preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then after sequentially adding all the channels in the M channels that are in the open state to the channel queue, at least one channel is selected from the channel queue in order from front to back as the second channel. If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the open state among the M channels to the channel queue, then wait until the preset start condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel.

5. The method according to any one of claims 1-4, characterized in that, The step of reading the data requested by direct memory access into the cache and writing it from the cache to the destination address of direct memory access includes: performing read and write operations in parallel until both read and write operations are completed; The read operation includes: obtaining the source address and target data length of the direct memory access; reading data from the source address in batches until the target data length is read, and writing it into the cache, wherein the length of the data read in each batch does not exceed a preset first length threshold. The write operation includes: obtaining the destination address of the direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold.

6. The method according to claim 5, characterized in that, The method further includes: If an interrupt signal is received during the parallel execution of read and write operations, the read operation is terminated in response to the completion of reading the current batch of data; and the write operation is terminated in response to the completion of writing the current batch of data. After the read and write operations are terminated, the cache is cleared and each of the second channels is added to the end of the channel queue.

7. A scheduling device for direct memory access, characterized in that, A direct memory access controller (DMC) is applied in a first device, the DMC comprising N first channels, a control unit, and a cache, each first channel being connected to a different second device, wherein N is greater than 1; the device includes: The channel selection module is used to select at least one channel from the channel queue as a second channel in order from front to back in response to the achievement of a preset start condition, wherein the channel queue is initially formed by the N first channels arranged in sequence; The channel deletion module is used to delete the second channel from the channel queue for each second channel, and drive the control unit to schedule the physical port of the direct memory access controller to read the data requested by the direct memory access into the cache, and write it from the cache to the destination address of the direct memory access, so as to realize the direct memory access of the second device accessing the memory in the first device. The channel addition module is used to add each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access.

8. The apparatus according to claim 7, characterized in that, The first device maintains a software switch for each of the first channels, and the software switch is used to switch the corresponding first channel between an on state and an off state; The step of adding each of the second channels to the end of the channel queue in response to the second device accessing each of the second channels completing direct memory access includes: In response to the completion of direct memory access by the second device connected to each of the second channels, the state of each of the second channels is determined respectively; Add the second channel, which is in the "on" state, to the end of the channel queue; The direct memory access controller includes M channels, where M is not less than N; the N first channels are all the channels among the M channels that are initially in the enabled state; the device further includes: The channel clearing module is used to respond to the completion of direct memory access by the second device connected to each of the second channels. If at least one of the M channels is switched to the open state during the completion of direct memory access, the channel queue is cleared and all the channels in the open state are added to the channel queue in sequence. When the preset start condition is met again, at least one channel is selected from the channel queue in front-to-back order as the second channel. The channel determination module is used to determine the state of each of the second channels if none of the M channels are switched to the open state during the completion of direct memory access. The device further includes: The execution module is configured to, if a preset start condition is met during the step of clearing the channel queue and sequentially adding all the channels in the M channels that are in the open state to the channel queue, then after sequentially adding all the channels in the M channels that are in the open state to the channel queue, select at least one channel from the channel queue in a front-to-back order as the second channel. If the preset start condition is not met during the step of clearing the channel queue and sequentially adding all the channels in the open state of the M channels to the channel queue, then wait until the preset start condition is met again, and then select at least one channel from the channel queue in the order from front to back as the second channel. The step of reading the data requested by direct memory access into the cache and writing it from the cache to the destination address of direct memory access includes: performing read and write operations in parallel until both read and write operations are completed; The read operation includes: obtaining the source address and target data length of the direct memory access; reading data from the source address in batches until the target data length is read, and writing it into the cache, wherein the length of the data read in each batch does not exceed a preset first length threshold. The write operation includes: obtaining the destination address of the direct memory access; and writing the data in the cache to the destination address in batches in response to the data in the cache reaching a preset second length threshold, wherein the length of the data written in each batch does not exceed the second length threshold. The device further includes: An operation termination module is configured to terminate the read operation if an interrupt signal is received during the parallel execution of read and write operations, in response to the completion of reading the current batch of data in the read operation; and to terminate the write operation in response to the completion of writing the current batch of data in the write operation. The cache clearing module is used to clear the cache and add each of the second channels to the end of the channel queue after the read operation and the write operation are terminated.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the method of any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 1-6.

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