Method, device, test equipment and storage medium for determining storage space size

Abstract

The application provides a storage space size determination method and device, test equipment and a storage medium, and relates to the chip test technical field. The method comprises the following steps: obtaining test data, and sending the test data to a target chip to trigger the firmware to configure a direct memory access module; in the configuration process of the direct memory access module, determining a first part of data quantity corresponding to a first part of test data automatically received by a hardware circuit module; the first part of test data is data in the test data automatically received by the hardware circuit module; and based on the first part of data quantity, the storage space size of a front-end cache module is determined. The application solves the problem that the area cost and data transmission performance of the chip cannot be considered in the related art.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and more specifically, to a method, apparatus, testing equipment, and storage medium for determining the size of storage space. Background Technology

[0002] With the rapid development of smart terminals and embedded systems, more stringent requirements have been placed on the read / write performance and manufacturing cost of memory chips such as embedded MultiMediaCard (eMMC). In the integrated circuit (IC) design of memory chips, a front end buffer (FE buffer) module is usually set up. This front end buffer module is generally implemented using static random-access memory (SRAM) and is used to act as a data buffer hub between the host and the memory chip.

[0003] Current IC design practices face a serious trade-off between area cost and transmission performance. On the one hand, the cost of SRAM physical silicon area is extremely high. To save on the overall manufacturing cost of memory chips and increase profit margins, designers usually tend to compress the size of the front-end cache module as much as possible. However, if the front-end cache module is designed to be too small, it will cause a precipitous drop in 4KB random write performance, i.e., the number of input / output operations per second (IOPS).

[0004] However, if the capacity of the front-end cache module is maximized by adopting a redundant design approach in order to ensure the continuity of data transmission, it will result in a serious waste of chip area and keep the hardware cost high.

[0005] As can be seen from the above, the problem of not being able to balance chip area cost and data transmission performance still needs to be solved. Summary of the Invention

[0006] This application provides a method, apparatus, testing equipment, and computer-readable storage medium for determining storage space size, which can solve the problem in related technologies that cannot simultaneously consider chip area cost and data transmission performance. The technical solutions are as follows:

[0007] According to one aspect of this application, a method for determining storage space size is applied to a test device for testing a target chip; the target chip includes a hardware circuit module, a direct memory access module, and a front-end cache module, and the target chip runs firmware; the method includes: acquiring test data and sending the test data to the target chip to trigger the firmware to configure the direct memory access module; during the configuration of the direct memory access module, determining a first portion of data corresponding to a first portion of test data automatically received by the hardware circuit module; the first portion of test data being the data automatically received by the hardware circuit module within the test data; and determining the storage space size of the front-end cache module based on the first portion of data.

[0008] According to one aspect of this application, a storage space size determination device is configured in a testing device for testing a target chip; the target chip includes a hardware circuit module, a direct memory access module, and a front-end cache module, and the target chip runs firmware; the device includes: a data acquisition module for acquiring test data and sending the test data to the target chip to trigger the firmware to configure the direct memory access module; a first determination module for determining, during the configuration process of the direct memory access module, a first portion of data corresponding to a first portion of test data automatically received by the hardware circuit module; the first portion of test data being the data automatically received by the hardware circuit module from the test data; and a space determination module for determining the storage space size of the front-end cache module based on the first portion of data.

[0009] According to one aspect of this application, a testing device includes at least one processor and at least one memory, wherein the memory stores a computer program that, when executed by the processor, implements the method for determining the storage space size as described above.

[0010] According to one aspect of this application, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by one or more processors, implements the method for determining the storage space size as described above.

[0011] In the above technical solution, test data with a known total data volume is acquired and sent to the target chip to trigger the firmware to configure the direct memory access module. The first part of the data volume automatically received by the hardware circuit module during the configuration of the direct memory access module is derived. Based on the accurately calculated first part of the data volume, the storage space size of the front-end cache module is determined. This ensures that the front-end cache module will not experience data overflow before the direct memory access module is fully configured and started, thereby avoiding the target chip triggering a transmission blocking signal to the test device (or host), maintaining the continuity of data transmission, and preventing read / write performance degradation due to bus stagnation. On the other hand, it effectively eliminates invalid storage space redundancy, allowing the storage space size of the front-end cache module to closely match actual needs, reducing the area occupied by the front-end cache module in the chip, and lowering manufacturing costs. This effectively solves the problem in related technologies where chip area cost and data transmission performance cannot be balanced. Attached Figure Description

[0012] Figure 1 This is a schematic diagram based on the implementation environment involved in this application;

[0013] Figure 2 This is a hardware structure diagram of an electronic device according to an exemplary embodiment;

[0014] Figure 3 This is a flowchart illustrating a method for determining storage space size according to an exemplary embodiment;

[0015] Figure 4 yes Figure 3 Timing diagram of data transmission involved in the corresponding embodiment;

[0016] Figure 5 yes Figure 3 A schematic diagram illustrating the specific implementation of the data transmission link involved in the corresponding embodiment;

[0017] Figure 6 This is a structural block diagram of a storage space size determination device according to an exemplary embodiment;

[0018] Figure 7 This is a structural block diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0020] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0021] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0022] As mentioned earlier, current IC design practices face a serious trade-off between area cost and transmission performance.

[0023] In practical applications, 4K Write is one of the most frequent Input / Output (I / O) operations in operating systems and applications. When a test device initiates a 4KB data write request to the memory chip, the firmware (FW) within the memory chip needs to consume a certain number of processing cycles to parse the bus command and configure the registers of the Direct Memory Access (DMA) module inside the memory chip. Before the firmware completes its configuration, the hardware (HW) module of the memory chip automatically and temporarily stores the test data continuously sent by the host in the front-end cache module.

[0024] If the front-end cache module's storage space is designed to be too small, it will be quickly filled with data sent from the host before the FW completes DMA configuration. To prevent data overflow, the underlying hardware will have to send a blocking signal to the host to force it to pause data transmission. This interruption will severely slow down the entire pipeline's processing efficiency, causing a precipitous drop in 4K write performance.

[0025] While maximizing the capacity of the front-end cache module avoids host waiting, it inevitably leads to a large amount of expensive SRAM resources being idle during the steady-state phase of the pipeline, resulting in a serious waste of chip area and keeping hardware costs high.

[0026] As can be seen from the above, there is still a shortcoming in the related technologies that cannot balance chip area cost and data transmission performance.

[0027] Therefore, the method for determining the storage space size provided in this application can accurately determine the storage space size of the front-end cache module. Accordingly, the method for determining the storage space size is applicable to the storage space size determination device, which can be deployed on a test device. The electronic device can be a computer device configured with a von Neumann architecture, such as a desktop computer, a laptop computer, a server, an automated test equipment (ATE), etc.

[0028] Figure 1 This is a schematic diagram illustrating an implementation environment related to a method for determining storage space size. It should be noted that this implementation environment is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of the invention.

[0029] The implementation environment includes the target chip 110 and the test equipment 130.

[0030] Specifically, the target chip 110 can also be considered as the chip for which the storage space size of the front-end cache module is to be designed. The target chip can be a storage chip such as eMMC or UFS (Universal Flash Storage), and no specific limitation is made here.

[0031] The testing device 130 can be an electronic device such as a desktop computer, laptop computer, or server, or it can be a computer cluster consisting of multiple servers, or even a cloud computing center consisting of multiple servers. The testing device 130 is used to provide backend services, such as, but not limited to, services for determining storage space size.

[0032] The test device 130 and the target chip 110 establish a network communication connection in advance via wired or wireless means, and data transmission between the test device 130 and the target chip 110 is realized through this network communication connection. The transmitted data includes, but is not limited to, test data, etc.

[0033] In one application scenario, the target chip includes a hardware circuit module, a direct memory access module, and a front-end cache module, and the target chip runs firmware. Test equipment 130 acquires test data and sends the test data to the target chip 110 to trigger firmware configuration of the direct memory access module. During the configuration of the direct memory access module, the amount of a first portion of test data automatically received by the hardware circuit module is determined. The first portion of test data is the data automatically received by the hardware circuit module within the test data. Based on the first portion of data, test equipment 130 can determine the storage space size of the front-end cache module, thereby reducing hardware manufacturing costs while ensuring the continuity of data transmission during DMA module configuration. This effectively solves the problem in related technologies where chip area cost and data transmission performance cannot be balanced.

[0034] Please see Figure 2 , Figure 2 This is a hardware structure diagram of an electronic device according to an exemplary embodiment. This electronic device is suitable for... Figure 1 The test equipment 130 in the implementation environment is shown.

[0035] It should be noted that this electronic device is merely an example adapted to this application and should not be construed as providing any limitation on the scope of use of this application. Furthermore, this electronic device should not be interpreted as requiring or depending on any specific feature. Figure 2 One or more components of the exemplary electronic device 200 shown.

[0036] The hardware structure of electronic device 200 can vary considerably due to differences in configuration or performance, such as... Figure 2 As shown, the electronic device 200 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0037] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 200.

[0038] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. For example, to perform... Figure 1 The diagram illustrates the interaction between the target chip 110 and the test equipment 130 in the implementation environment.

[0039] Of course, in other examples adapted in this application, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 2 As shown, this does not constitute a specific limitation.

[0040] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0041] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 200, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0042] Application 253 is a computer program formed by computer-readable instructions based on operating system 251 to perform at least one specific task, and may include at least one module ( Figure 2 (Not shown), each module can contain corresponding computer-readable instructions. For example, the device for determining the storage space size can be considered as an application program 253 deployed on electronic device 200.

[0043] Data 255 can be photos, pictures, etc. stored on a disk, or test data, etc., stored in memory 250.

[0044] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer programs stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, the method of determining the storage space size can be accomplished by the central processing unit 270 reading the application program 253 stored in the memory 250.

[0045] Furthermore, this application can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of this application is not limited to any specific hardware circuit, software, or combination thereof.

[0046] Please see Figure 3 This application provides a method for determining storage space size. This method is applicable to testing equipment, for example, the electronic device may be... Figure 1 The test device 130 shown in the implementation environment has a hardware structure that can be as follows: Figure 2 As shown.

[0047] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0048] like Figure 3 As shown, the method may include the following steps:

[0049] Step 310: Acquire test data and send the test data to the target chip to trigger the firmware to configure the direct memory access module.

[0050] First, it should be noted that the testing equipment is used to test the target chip, which can be the chip whose storage space size of the front-end cache module is to be designed, or it can be an eMMC chip, without any limitation.

[0051] The target chip includes a hardware circuit module (HW module), a direct memory access module (DMA module), and a front-end cache module (FE Buffer module), and the target chip runs firmware (FW).

[0052] The test data can be used to simulate data flow in real-world application scenarios (such as a 4KB random write scenario).

[0053] Step 330: During the configuration process of the direct memory access module, determine the amount of the first part of the data corresponding to the first part of the test data automatically received by the hardware circuit module.

[0054] The first part of the test data consists of data automatically received by the hardware circuit module.

[0055] During the design of the storage space size of the chip's front-end memory module, the inventors discovered that due to inherent physical or software differences in system clock frequency scheduling, firmware code execution efficiency, and system interrupt response between different batches or models of chips, the configuration time for the FW to wake up and completely complete the DMA module register configuration varies. This directly results in the amount of data (i.e., the first part of the data) that is automatically received by the HW module according to the communication protocol and accumulated in the front-end cache module before the DMA module actually takes over data transfer being an uncontrollable variable that dynamically fluctuates with the individual chip and the operating environment.

[0056] Figure 4 A timing diagram of data transmission is shown, such as... Figure 4As shown, after the host sends test data to the target chip, the FW inside the target chip needs to perform a series of configuration operations, specifically including parsing the command, judging the rationality of the command, and starting the Front-End Direct Memory Access (FE DMA) module. The total time taken for the above FW configuration process is denoted as T3. While the FW is performing the above configuration process, the HW module automatically starts receiving test data sent by the host and continuously stores it in the front-end cache module until the front-end cache module reaches full load. The time taken for receiving test data and filling the front-end cache in this stage is denoted as T1 (the received test data can be regarded as the first part of the test data).

[0057] Because the front-end cache module's storage space is designed to be relatively small, the time T1 is less than the time T3 for configuring the DMA module in the firmware. This means that the front-end cache module is already full before the firmware completes the DMA module configuration and officially starts data transfer. To prevent data overflow errors, the target chip's underlying hardware must send a pause or block signal to the host, forcing the host to stop data transmission. This is represented in the timing diagram as a data transmission standstill area (blank area) between T1 and T2.

[0058] Only after time period T3 ends, i.e., after the DMA module is successfully started and the data stored in the front-end cache module is transferred to the subsequent storage node, will the front-end cache module release available space again. At this time, the host can resume data transmission, and the front-end cache module continues to receive the remaining data in the 4KB test data excluding the previously received data (i.e., it can be regarded as the second part of the test data). The time taken to receive the remaining data in this stage is recorded as T2.

[0059] If a uniform maximum redundancy space based on the worst-case scenario is set for the front-end cache modules of all chips, it can cover those chips with longer configuration times and large amounts of accumulated data in the early stages to prevent data overflow. However, this will inevitably lead to a waste of a large amount of expensive SRAM physical area for those chips with shorter configuration times, causing the overall manufacturing cost of the chips to rise sharply.

[0060] Conversely, if a uniform, minimal space configuration is blindly adopted in order to control costs, the limited front-end cache module will be instantly filled with data sent from the host if the firmware configuration is slightly slow. At this time, the underlying hardware will have to send a signal to the host to prevent data overwriting, which will directly lead to the break in the data transmission pipeline and severely degrade the chip's performance in core scenarios such as 4K random writes.

[0061] Therefore, after research, the inventors discovered that to achieve a perfect balance between chip area cost and data transmission performance, it is necessary to abandon the static space estimation method. The optimal space size of the front-end cache module should not be an empirical value, but rather depends on the sum of the initial data accumulation caused by the firmware configuration time (i.e., the first part of the data volume) and the amount required to balance the input data volume of the front-end cache module and the output data volume of the DMA module after the pipeline starts. Based on this discovery, the inventors transformed the internal timing overlap state, which is difficult to quantify directly, into a data volume relationship that can be accurately solved, thereby accurately calculating the minimum required storage space for each target chip without causing pipeline interruption.

[0062] In one embodiment, step 330 may further include: determining the second part of the test data based on the transmission process of the test data within the target chip; and determining the first part of the data based on the total amount of test data and the second part of the data.

[0063] The second part of the test data consists of the test data excluding the first part. In other words, the second part of the test data is the remaining test data besides the part automatically received by the hardware circuit module.

[0064] It is understood that the test data is actively generated and distributed by the test device to determine the storage space size. Therefore, the total amount of test data is a known and definite value for the test device. Thus, as long as the amount of the second part of the data can be accurately determined, the amount of the first part of the data can be deduced by subtracting the total amount of data from the amount of the second part.

[0065] It is important to note that the reason for adopting this mechanism of first determining the amount of the second part of the data and then deriving the amount of the first part is determined by the underlying physical interaction characteristics of the target chip:

[0066] First, the amount of data in the first part is objectively difficult to measure directly. This first part of the test data is automatically received blindly by the HW module during the FW's DMA module configuration process. Because the test equipment is located outside the target chip, and the microsecond-level execution time of the FW's code within the target chip is affected by multiple dynamic factors such as current system interrupts and CPU load, the test equipment cannot accurately capture from the outside the exact moment the FW completes the DMA module configuration. Therefore, it is impossible for the external test equipment to directly quantify how much of the first part of the test data has been automatically received at the instant the DMA module configuration is completed.

[0067] Secondly, the second part of the data provides the physical conditions for establishing a deterministic model. Unlike the first part of the data transmission, which cannot be quantitatively obtained, the second part of the test data is transmitted in a pipeline jointly initiated by the front-end interface module and the DMA module after the DMA module is configured. In this pipeline transmission stage, the transmission of test data is no longer a disordered accumulation, but is constrained by the input rate of the front-end interface module (first transmission rate) and the output rate of the DMA module (second transmission rate). Since these two hardware rates are relatively fixed in steady state, and the pipelined method does not overflow under the condition of dynamic balance in the input and output timing, the amount of the second part of the data that can be accommodated in the pipeline steady state can be accurately solved by utilizing the known rate and timing overlap relationship.

[0068] In summary, this solution cleverly avoids the technical blind spot of directly measuring the first part of the data volume. Instead, it uses the deterministic physical laws of the pipeline transmission stage to calculate the second part of the data volume, and then deduces the first part of the data volume. This indirect derivation method not only greatly reduces the implementation difficulty of the test plan, but also completely eliminates the interference caused by system environment fluctuations on space estimation, ensuring the accuracy of the final determined storage space size of the front-end cache module.

[0069] In one embodiment, the target chip includes a front-end interface module and a transmission sector buffer module; the method further includes: determining a first transmission rate; obtaining a second transmission rate; obtaining a data transmission balance model, and inputting the first transmission rate and the second transmission rate into the data transmission balance model to determine the second part of the data volume.

[0070] The first transmission rate refers to the transmission rate at which test data is transmitted from the front-end interface module to the front-end cache module; the second transmission rate refers to the transmission rate at which test data is transferred from the front-end cache module to the transmission sector cache module via the direct memory access module.

[0071] It should be noted that the test equipment can determine the first and second transmission rates by reading the target chip's device capability register and parsing the preset configuration file corresponding to the chip's specification. It can also directly receive externally input design limit values ​​to determine the first and second transmission rates, but no specific limitations are made here.

[0072] Figure 5 A schematic diagram illustrating a specific implementation of a data transmission link is shown, such as... Figure 5 As shown, in a data writing scenario, the transmission process of test data from the host to the final storage medium specifically includes the following three stages:

[0073] Phase 1: Front-end receiving phase. Test data is first sent by the test device (HOST), transmitted through the front-end interface (FE) module and temporarily stored in the front-end buffer (FE Buffer) module. The physical transmission rate supported by the front-end interface module (i.e. the aforementioned first transmission rate) is 400MB / s.

[0074] The second stage: internal transfer stage. The Direct Memory Access (DMA) module will transfer the test data in the front-end cache module to the Transport Sector Cache (TSB) module. The transfer rate supported by the DMA module (i.e. the aforementioned second transfer rate) is 800MB / s.

[0075] The third stage: the back-end writing stage. Finally, the data temporarily stored in the transfer sector cache module is formally written into the underlying NAND flash memory module via the back-end interface (BE) module. The transfer rate of the back-end interface module is 533MB / s.

[0076] Depend on Figure 5 It is evident that the second transfer rate of the direct memory access module (800MB / s) is significantly higher than the first transfer rate of the front-end interface module (400MB / s). This rate difference provides the necessary physical basis for subsequently enabling pipelined data transfer. Specifically, when the direct memory access module and the front-end interface module operate synchronously, the internal pumping rate is much greater than the external inflow rate. This ensures that the amount of data remaining in the front-end cache module will not continuously increase when establishing the data transfer balance model, thus making it possible to determine the optimal space size of the front-end cache module by accurately calculating the first part of the test data.

[0077] In one embodiment, the front-end caching module includes multiple caching units, and the transmission sector caching module includes multiple data sectors; the storage space size of the caching units and the data sectors is equal; the above method may further include: under the condition that the first duration of the first duration period is equal to the second duration of the second duration period, establishing a data transmission balancing model based on the storage space size of the caching units.

[0078] The first duration period refers to the time period during which the front-end interface module stores the second part of the test data into the corresponding cache units; the second duration period refers to the time period during which the direct memory access module transfers the second part of the test data stored in each cache unit to the corresponding data sector.

[0079] In one embodiment, the first duration and the second duration overlap in timing; wherein, under the condition that the first duration and the second duration are equal, the amount of the second part of the test data input by the front-end interface module to the cache unit and the amount of the second part of the test data output by the direct memory access module to the data sector are dynamically balanced.

[0080] Specifically, the front-end interface module first continuously writes the initial portion of the second set of test data into the first cache unit of the front-end cache module. When the first cache unit is just full, the front-end interface module immediately switches to the second cache unit of the front-end cache module to continue storing subsequent test data. Simultaneously, the direct memory access module synchronously intervenes in the first cache unit, which has just filled up, and begins transferring the data within that cache unit to the first data sector of the transport sector cache module. While the front-end interface module is storing data into the third cache unit, the direct memory access module is simultaneously transferring the data from the second cache unit to the second data sector.

[0081] Similarly, the front-end interface module and the direct memory access module form a relay mechanism of spatial misalignment and temporal parallelism on different cache units. Therefore, the total time taken for the front-end interface module to store the second part of the test data (i.e., the first duration) and the total time taken for the direct memory access module to remove the same data (i.e., the second duration) overlap in timing. This pipeline design ensures that limited cache units can be reused at high frequency, thereby supporting the continuous transmission of large amounts of data without bus congestion, and thus establishing a data transmission balance model.

[0082] Furthermore, since the first duration of the first continuous period and the second duration of the second continuous period are in an equal correspondence under the above pipeline steady state, the total amount of data input by the front-end interface module to the front-end cache module within this overlapping time window must be equal to the total amount of data removed by the direct memory access module from the front-end cache module.

[0083] In one implementation, the expression for the data transmission balancing model is as follows:

[0084]

[0085] The total data volume of the test data is D. total X represents the first part of the test data, V1 represents the first transmission rate, and V2 represents the second transmission rate. Based on the aforementioned relationship between the test data volumes, during the pipeline transmission phase, the remaining data volume that the front-end interface module needs to continue receiving (i.e., the second part of the second part of the test data) can be expressed as: Meanwhile, let U be the unit storage space size of a single cache unit of the front-end cache module and a single data sector of the transmission sector cache module; during pipeline transmission, the total number of data sectors occupied by the direct memory access module to remove the second part of the test data is N, then the total amount of data removed by the direct memory access module can be expressed as N×U; the left side of the equation is used to characterize the second time required for the direct memory access module to transfer all the second part of the test data to each data sector, and the right side of the equation is used to characterize the first time required for the front-end interface module to store all the remaining test data after deducting the first part of the data into each cache unit.

[0086] Therefore, by solving the data transmission balance model, the test equipment can test the data based on the known total data volume D. total Given the unit storage space size U, the total number of data sectors N, and fixed rates V1 and V2, the first part of the data X automatically received by the hardware circuit module during firmware configuration of the target chip can be directly and accurately calculated.

[0087] Step 350: Based on the amount of data in the first part, determine the storage space size of the front-end cache module.

[0088] In one embodiment, step 350 may further include: converting the amount of the first part of the data based on the storage space size of the cache unit in the front-end cache module to obtain the required number of basic units; rounding up the number of basic units to obtain the target number of units; and determining the storage space size of the front-end cache module based on the target number of units and the storage space size of the cache unit.

[0089] It's understandable that since cache units are allocated according to fixed capacity specifications, the storage space size of a cache unit is deterministic. Therefore, the number of basic units can be determined by converting the first part of the data volume. The number of basic units indicates the minimum number of cache units. If the actual number of cache units configured in the design is lower than this number of basic units, the front-end cache module will experience data overflow before the direct memory access module starts, leading to data transmission interruption.

[0090] Furthermore, since there are no half-sized or decimal storage units at the physical level of a cache unit, if the number of basic units has a decimal (e.g., 2.3 cache units are needed), this indicates that the total amount of the first part of the data has exceeded the capacity limit of 2 cache units. If we don't round up (i.e., allocate only 2 cache units), the extra 0.3 cache units of data will have nowhere to be stored, inevitably leading to cache overflow and immediately triggering bus blocking. Therefore, we must round up (allocate 3 cache units) to provide a complete additional physical block to accommodate all the remaining data, ensuring the continuity of data writing.

[0091] Through the above process, test data with a known total data volume is obtained and sent to the target chip to trigger the firmware to configure the direct memory access module. The first part of the data volume automatically received by the hardware circuit module during the configuration of the direct memory access module is derived. Based on the accurately calculated first part of the data volume, the storage space size of the front-end cache module is determined. This ensures that the front-end cache module will not experience data overflow before the direct memory access module is fully configured and started, thereby preventing the target chip from triggering a transmission blocking signal to the test device (or host), maintaining the continuity of data transmission, and preventing read / write performance degradation due to bus stagnation. On the other hand, it effectively eliminates invalid storage space redundancy, allowing the storage space size of the front-end cache module to closely match actual needs, reducing the area occupied by the front-end cache module in the chip, and reducing manufacturing costs. This effectively solves the problem in related technologies where chip area cost and data transmission performance cannot be balanced.

[0092] The following is a detailed implementation description of a method for determining storage space size in an application scenario. This application scenario determines the storage space size of the front-end cache module based on 4K write performance testing of the eMMC chip.

[0093] The smallest buffer unit of the FE buffer module is 512B. The FE rate (i.e., the first transfer rate) is 400MB / s, the DMA module has a bit width of 32 bits, and the AHB bus (Advanced High-performance Bus) is 200MHz. Therefore, the second transfer rate is 800MB / s.

[0094] Assume the storage space size of the FE buffer module is X KB.

[0095] The first step is for the testing equipment to send test data to the eMMC chip. The size of the test data is 4KB.

[0096] The second step is that the HW module starts data transmission and receives X KB of data from the test device (i.e., the first part of the test data). At this time, the test device still has (4-X) KB of test data that has not been transmitted.

[0097] The third step involves the firmware completing the configuration of the DMA module and starting the DMA module. The FE buffer module then collects the remaining (4-X)KB of test data (i.e., the second part of the test data) from the test device and sends the test data to the TSB module through the DMA module.

[0098] The fourth step is to send the test data in the buffer unit to the first transmission sector of the TSB module through the DMA module within the FE buffer module.

[0099] In the fifth step, the FE buffer module frees up one buffer unit. At this time, the free buffer unit continues to receive the remaining (4-X) KB. Meanwhile, the test data in other buffer units is sent to the second transmission sector of the TSB module through the DMA module, and so on.

[0100] In the sixth step, the FE buffer module receives the last part of the data, which is (4-X)KB. At the same time, the DMA module sends the test data in the buffer unit to the second-to-last transmission sector of the TSB module.

[0101] The seventh step is to send the test data in the cache unit to the penultimate transmission sector of the TSB module via the DMA module.

[0102] It is understandable that the timing configuration of the front-end buffer module depends on two steps: the fifth and the seventh. That is, the time it takes for the FE buffer module to send the data to the 2nd to 7th transmission sectors of the TSB, which is 6 transmission sectors, is equal to the time it takes for the FE buffer module to receive the remaining (4-X) KB of test data.

[0103] As mentioned earlier, the data transmission model is as follows:

[0104]

[0105] Substituting the above data into the data transmission balance model:

[0106]

[0107] Then we can get X = 2.5KB.

[0108] Therefore, 2.5KB can be determined as the storage space size of the front-end cache module, and based on 2.5KB and the 512B of the cache unit, the basic number of cache units is determined to be 5.

[0109] In this application scenario, during the hardware design phase, by establishing a parameterized data transmission balance model, the first portion of test data generated during firmware configuration can be accurately determined for different future hardware design speeds (i.e., the first transmission rate and the second transmission rate). This allows for customized allocation of storage space for chips of different specifications and quantitative calculation of the optimal storage space size for the front-end cache module. On the one hand, the precisely determined storage space size ensures that the front-end cache module has sufficient capacity to carry all received data before the direct memory access module starts, guaranteeing data transmission continuity. On the other hand, by eliminating invalid redundant space, the physical area of ​​the front-end cache module in the chip is effectively compressed, directly reducing hardware manufacturing costs.

[0110] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0111] The following are embodiments of the apparatus described in this application, which can be used to execute the method for determining the storage space size involved in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the method embodiments of the method for determining the storage space size involved in this application.

[0112] Please see Figure 6 This application provides a storage space size determination device 900, configured in a test device, which is used to test a target chip; the target chip includes a hardware circuit module, a direct memory access module and a front-end cache module, and the target chip runs firmware;

[0113] The storage space size determination device 900 includes, but is not limited to: a data acquisition module 910, a first determination module 930, and a space determination module 950.

[0114] Among them, the data acquisition module 910 is used to acquire test data and send the test data to the target chip to trigger the firmware to configure the direct memory access module;

[0115] The first determining module 930 is used to determine, during the configuration process of the direct memory access module, the amount of the first part of test data automatically received by the hardware circuit module; the first part of test data is the data automatically received by the hardware circuit module in the test data.

[0116] The space determination module 950 is used to determine the storage space size of the front-end cache module based on the amount of data in the first part.

[0117] In one exemplary embodiment, the first determining module further includes:

[0118] The second determining unit is used to determine the amount of the second part of the test data based on the transmission process of the test data in the target chip; the second part of the test data is the data in the test data other than the first part of the test data.

[0119] The third determining unit is used to determine the first part of the data volume based on the total data volume of the test data and the second part of the data volume.

[0120] It should be noted that the storage space size determination device provided in the above embodiments is only illustrated by the division of the above functional modules when determining the storage space size. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the storage space size determination device will be divided into different functional modules to complete all or part of the functions described above.

[0121] Furthermore, the embodiments of the storage space size determination device and the storage space size determination method provided in the above embodiments belong to the same concept, and the specific way in which each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0122] Please see Figure 7 This application provides an electronic device 4000, which may include: testing equipment, etc.

[0123] exist Figure 7 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0124] Data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus.

[0125] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.

[0126] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0127] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing computer programs having instruction or data structure forms and accessible by electronic device 400, but not limited to these.

[0128] The memory 4003 stores a computer program, and the processor 4001 can read the computer program stored in the memory 4003 through the communication bus 4002.

[0129] The computer program is executed by one or more processors 4001 to implement the method for determining the storage space size in the above embodiments.

[0130] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0131] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0132] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD-ROMs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0133] While the principles herein have been illustrated in various embodiments, numerous modifications to the structure, arrangement, proportions, elements, materials, and components, particularly suited to specific environmental and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document.

[0134] The foregoing specific descriptions have been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, considerations for this disclosure are to be illustrative rather than restrictive, and all such modifications are to be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term “comprising” and any other variations thereof as used herein are non-exclusive inclusion, meaning that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of the process, method, system, article, or apparatus. Furthermore, the term “coupled” and any other variations thereof as used herein refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and / or any other connections.

[0135] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of the invention. Therefore, the scope of the invention should be determined only by the claims.

Claims

1. A method for determining the size of a storage space, characterized in that, The device is used in a testing equipment to test a target chip; the target chip includes a hardware circuit module, a direct memory access module, and a front-end cache module, and the target chip runs firmware. The method includes: Acquire test data and send the test data to the target chip to trigger the firmware to configure the direct memory access module; During the configuration of the direct memory access module, the amount of a first portion of data corresponding to the first portion of test data automatically received by the hardware circuit module is determined; the first portion of test data is the data automatically received by the hardware circuit module from the test data. Based on the first portion of data, the storage space size of the front-end cache module is determined.

2. The method as described in claim 1, characterized in that, During the configuration process of the direct memory access module, determining the amount of the first portion of data corresponding to the first portion of test data automatically received by the hardware circuit module includes: Based on the transmission process of the test data within the target chip, the amount of the second part of the test data is determined; the second part of the test data is the data in the test data excluding the first part of the test data. The first part of the data volume is determined based on the total data volume of the test data and the second part of the data volume.

3. The method as described in claim 2, characterized in that, The target chip includes a front-end interface module and a transmission sector cache module; The process of determining the second portion of the test data based on the transmission of the test data within the target chip includes: Determine the first transmission rate; Obtain the second transmission rate; Obtain a data transmission balance model, and input the first transmission rate and the second transmission rate into the data transmission balance model to determine the second part of the data volume; Wherein, the first transmission rate refers to the transmission rate at which the test data is transmitted from the front-end interface module to the front-end cache module; the second transmission rate refers to the transmission rate at which the test data is transferred from the front-end cache module to the transmission sector cache module through the direct memory access module.

4. The method as described in claim 3, characterized in that, The front-end cache module includes multiple cache units, and the transmission sector cache module includes multiple data sectors; the storage space of the cache units is equal to that of the data sectors; The method for obtaining a data transmission balancing model includes: Under the condition that the first duration of the first continuous period is equal to the second duration of the second continuous period, the data transmission balance model is established based on the storage space size of the cache unit; Wherein, the first duration period refers to the time period during which the front-end interface module stores the second part of the test data into the corresponding cache units; the second duration period refers to the time period during which the direct memory access module transfers the second part of the test data stored in each cache unit to the corresponding data sector.

5. The method as described in claim 4, characterized in that, The first duration and the second duration overlap in time sequence; wherein, under the condition that the first duration and the second duration are equal, the amount of the second part of the test data input by the front-end interface module to the cache unit and the amount of the second part of the test data output by the direct memory access module to the data sector achieve a dynamic balance.

6. The method according to any one of claims 1 to 5, characterized in that, Determining the storage space size of the front-end cache module based on the first portion of data includes: The amount of the first part of the data is converted based on the storage space size of the cache unit in the front-end cache module to obtain the required number of basic units; The number of basic units is rounded up to obtain the target number of units; The storage space size of the front-end cache module is determined based on the number of target units and the storage space size of the cache unit.

7. A device for determining the size of a storage space, characterized in that, The device is configured in a test equipment for testing a target chip; the target chip includes a hardware circuit module, a direct memory access module, and a front-end cache module, and the target chip runs firmware. The device includes: A data acquisition module is used to acquire test data and send the test data to the target chip to trigger the firmware to configure the direct memory access module; The first determining module is used to determine, during the configuration process of the direct memory access module, the amount of a first portion of data corresponding to the first portion of test data automatically received by the hardware circuit module; the first portion of test data is the data automatically received by the hardware circuit module in the test data. The space determination module is used to determine the storage space size of the front-end cache module based on the first part of the data volume.

8. The apparatus as claimed in claim 7, characterized in that, The first determining module further includes: The second determining unit is used to determine the second part of the test data based on the transmission process of the test data within the target chip; the second part of the test data is the data in the test data excluding the first part of the test data. The third determining unit is used to determine the first part of the data volume based on the total data volume of the test data and the second part of the data volume.

9. A testing device, characterized in that... include: Memory, used to store computer programs; A processor for implementing the method as described in any one of claims 1-6 by executing the computer program stored in the memory.

10. A storage medium, characterized in that, The medium stores a computer program that can be executed by a processor to implement the method as described in any one of claims 1-6.

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