Winding method for optimizing high-speed signal crosstalk and chip test carrier plate
By improving the routing method of the chip test carrier board and changing the in-disk hole of the ground pin to a fan-out small hole, the routing path of high-speed signals was optimized, the crosstalk problem between high-speed signals was solved, the insertion loss bandwidth of signal vias was improved, and the number of routing layers and design difficulty were avoided.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 零壹半导体技术(常州)有限公司
- Filing Date
- 2026-03-19
- Publication Date
- 2026-07-10
AI Technical Summary
In high-performance, high-density signal transmission scenarios, how can we effectively suppress crosstalk between high-speed signals while improving the insertion loss bandwidth of signal vias, and avoid increasing the number of wiring layers and design complexity?
A routing method is adopted to change the in-panel holes of the corresponding ground pins in adjacent rows of high-speed differential signal pins to two fan-out holes that are symmetrically distributed vertically or horizontally with the ground pin as the center, and to allow the wiring path to pass through the gaps between these fan-out holes. The signal pin array is arranged in a standard or staggered manner, and the ground pin rows and mixed rows are arranged alternately.
It effectively avoids crosstalk between high-speed signals in the same and different rows, improves the insertion loss bandwidth of signal vias, avoids increasing the number of wiring layers and design difficulty, and optimizes the wiring path.
Smart Images
Figure CN121881968B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing, and more specifically to a winding method for optimizing high-speed signal crosstalk and a chip testing substrate. Background Technology
[0002] With the continuous increase in high-speed signal rates, traditional low-speed transmission methods (such as NRZ encoding with rates below 10 Gbps) are no longer sufficient to meet the current data rate requirements. High-speed signal technologies, represented by 112 Gbps PAM4, place higher demands on the electrical performance of various high-speed interconnect interfaces and high-frequency signal transmission structures, bringing new design challenges.
[0003] In high-performance, high-density signal transmission scenarios (such as the design of chip test substrates), high-speed signals are typically transmitted differentially. The large number and dense layout of pins result in extremely limited routing space around the pins. Simultaneously, extremely high isolation is required between signal pins, necessitating consideration not only of mutual interference between pins but also of parasitic coupling between signal lines and pins. Due to the sheer number of signals, meeting isolation requirements often necessitates the use of multiple routing layers for high-speed signal placement. However, increasing the number of routing layers leads to increased signal via length, which in turn degrades the insertion loss performance of the signal vias and limits available bandwidth.
[0004] Therefore, in differential signal loopback designs that require high performance and have a large number of high-speed signal pins, effectively suppressing crosstalk between signals while improving the insertion loss bandwidth of signal vias has become a key technical problem that urgently needs to be solved. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a winding method for optimizing crosstalk between high-speed signals. It can effectively avoid crosstalk between high-speed signals without occupying other wiring channels or increasing the number of wiring layers and design difficulty.
[0006] To solve the above-mentioned technical problems, the technical solution of the present invention is: a winding method for optimizing high-speed signal crosstalk, wherein the signal pin array includes multiple sets of high-speed differential signal pins and multiple ground pins surrounding each set of high-speed differential signal pins; the method includes:
[0007] The in-panel holes of the corresponding ground pins in the adjacent row of the high-speed differential signal pins are changed to two fan-out holes that are symmetrically distributed vertically with the ground pins as the center.
[0008] High-speed differential signal pins use the gap between the two fan-out holes of the corresponding pins in adjacent rows as part of their wiring path.
[0009] Furthermore, the method also includes: changing the in-disk hole of the corresponding ground pin in the same row as the high-speed differential signal pin to two fan-out holes that are symmetrically distributed horizontally with the ground pin as the center.
[0010] Furthermore, the signal pin array is a standard array.
[0011] Furthermore, the signal pin array is an interleaved array.
[0012] Furthermore, in the signal pin array, ground pin rows and mixed rows are arranged alternately; among them, the ground pin rows contain only ground pins, while the mixed rows contain both ground pins and high-speed differential signal pins.
[0013] Furthermore, the signal pin array is used for electrical connection with the high-speed chip under test.
[0014] Furthermore, the vias in the corresponding ground pins located in the adjacent rows of the high-speed differential signal pins are changed to two fan-out vias that are symmetrically distributed vertically with the ground pins as the center; specifically:
[0015] The in-panel vias located in adjacent rows of high-speed differential signal pins and near other high-speed differential signal ground pins are replaced with two fan-out vias symmetrically distributed vertically around the ground pins.
[0016] Furthermore, the high-speed differential signal pins use the gap between the two fan-out holes of the corresponding pins in adjacent rows as part of their routing path; specifically:
[0017] High-speed differential signal pins use the gap between two fan-out holes in adjacent rows and near the ground pin of their sensitive signal as part of their wiring path.
[0018] Furthermore, the vias of the corresponding ground pins in the same row as the high-speed differential signal pins are changed to two fan-out vias that are symmetrically distributed horizontally with the ground pins as the center; specifically:
[0019] When two sets of high-speed differential signal pins located in the same row and adjacent to each other are separated by only one ground pin, the in-disk hole of the ground pin is changed to two fan-out holes that are symmetrical about the ground pin and horizontally distributed.
[0020] The present invention also relates to a chip test carrier board, which uses the aforementioned winding method for optimizing high-speed signal crosstalk for winding.
[0021] By adopting the above technical solution, the present invention changes the ground vias of the corresponding ground pins in adjacent rows of high-speed differential signal pins to two vertically distributed fan-out vias, and allows the wiring to pass through the middle. This avoids crosstalk between high-speed signals distributed in the same row, as well as crosstalk between high-speed signals distributed in different rows, and does not occupy other wiring channels, nor does it increase the number of wiring layers or design difficulty. Attached Figure Description
[0022] Figure 1 This is a diagram showing the pin arrangement of a high-speed chip.
[0023] Figure 2 This is a diagram showing the pinout of a high-speed differential signal chip and its ground pins.
[0024] Figure 3 This is a diagram showing the arrangement of the signal pin array of the present invention when it is a standard array;
[0025] Figure 4 This is a diagram showing the arrangement of the signal pin array of the present invention when it is an interleaved array;
[0026] Figure 5 This is the wiring diagram when the signal pin array of the present invention is a standard array;
[0027] Figure 6 This is the wiring diagram for the signal pin array of the present invention when it is an interleaved array;
[0028] Figure 7 This is the signal pin array diagram for application case one;
[0029] Figure 8 This is a wiring diagram after winding using the method of this invention in application case one;
[0030] Figure 9 This is the wiring diagram after using the traditional method in Application Case 1;
[0031] Figure 10 This is a single-ended insertion loss bandwidth diagram from Application Case 1;
[0032] Figure 11 The diff1 and diff2 crosstalk diagrams in application case one;
[0033] Figure 12 This is the signal pin array diagram for application case two;
[0034] Figure 13 This is a wiring diagram after winding using the method of this invention in application case two;
[0035] Figure 14 This is a wiring diagram after using the traditional method in application case two;
[0036] Figure 15 This is an alternative wiring diagram after using the traditional method in Application Case 2;
[0037] Figure 16 This is the crosstalk diagram of diff2 and diff5 in application case 2;
[0038] Figure 17 This is the crosstalk diagram of diff2 and diff6 in application case 2;
[0039] in, Figure 1 In the diagram, (a) shows the pins of a high-speed chip arranged in a standard array; (b) shows one arrangement of the pins of a high-speed chip arranged in an interlaced array; and (c) shows another arrangement of the pins of a high-speed chip arranged in an interlaced array. Detailed Implementation
[0040] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0041] It should be noted that, in this application, the terms "row" and "column" are used to describe two sets of intersecting arrangement directions in a signal pin array. For ease of description, one set of parallel lines is referred to as a "row," and the other set of intersecting parallel lines is referred to as a "column." Those skilled in the art should understand that "row" and "column" here do not refer to absolute horizontal and vertical directions, but rather to two orthogonal (or intersecting) arrangement directions formed by the chip in any placement orientation.
[0042] like Figures 3-8 as well as Figure 13 As shown, a winding method for optimizing high-speed signal crosstalk is disclosed. The signal pin array includes multiple sets of high-speed differential signal pins and multiple ground pins surrounding each set of high-speed differential signal pins. The method includes:
[0043] The in-panel holes of the corresponding ground pins in the adjacent row of the high-speed differential signal pins are changed to two fan-out holes that are symmetrically distributed vertically with the ground pins as the center.
[0044] High-speed differential signal pins use the gap between the two fan-out holes of the corresponding pins in adjacent rows as part of their wiring path.
[0045] This method is applicable as long as the layout of the signal vias and ground vias meets the requirements of array arrangement and crosstalk needs to be considered. That is, this winding method can be applied to high-speed signal boards, such as chip test carrier boards, AI servers, supercomputer motherboards, GPU / HPC motherboards, switch / router motherboards, and all high-speed (e.g., 112 Gbps, 224 Gbps, etc.) and high-density circuit boards.
[0046] Facing the high-performance requirements of 112Gbps high-speed signal networks, there are numerous high-speed signals, and the crosstalk between these signals is a critical factor. In practical designs, the number of cabling channels is limited. The signal lines of the inner ring signals (high-speed differential signal pins near the center of the signal pin array) will inevitably pass through the outer ring signals (outer high-speed differential signal pins), thus inevitably introducing crosstalk between signals. The higher the speed, the stronger the crosstalk, ultimately preventing the achievement of high-speed transmission. While it's possible to utilize other cabling channels to avoid crosstalk between inner and outer ring signals, this introduces several problems: firstly, it wastes cabling channels, increasing the number of cabling layers and thus production costs; secondly, it increases design complexity and time; and thirdly, if other cabling channels also carry high-speed signals, new crosstalk problems will arise.
[0047] This embodiment replaces the ground vias of the corresponding ground pins in adjacent rows of high-speed differential signal pins with two vertically distributed fan-out vias, allowing the wiring to pass through the middle. This avoids crosstalk between high-speed signals distributed in the same row, as well as between high-speed signals distributed in different rows, without occupying other wiring channels, and without increasing the number of wiring layers or design complexity.
[0048] In some examples, such as Figures 3-8 as well as Figure 13 As shown, the method also includes: changing the in-disk hole of the corresponding ground pin in the same row as the high-speed differential signal pin to two fan-out holes that are symmetrically distributed horizontally with the ground pin as the center.
[0049] High-speed signal boards are characterized by long via lengths, which can reduce the frequency range of the single-ended insertion loss bandwidth of high-speed via signals. This embodiment addresses this by replacing the via in the corresponding ground pin in the same row as the high-speed differential signal pin with two horizontally distributed ground vias (fan-out vias) symmetrically centered on the ground pin. This reduces the spacing between the signal vias and ground vias, increasing their coupling and thus improving the frequency range of the single-ended insertion loss bandwidth of the signal vias.
[0050] In some examples, the vias in the corresponding ground pins located in adjacent rows of high-speed differential signal pins are replaced with two fan-out vias that are symmetrically distributed vertically around the ground pins; specifically, this can be:
[0051] For ground pins located in adjacent rows of high-speed differential signal pins and close to other high-speed differential signals, or for all ground pins located in adjacent rows of high-speed differential signal pins, change their center holes to two fan-out holes that are symmetrically distributed vertically with the ground pin as the center.
[0052] in, Figures 3-8 as well as Figure 13The diagram shows how the in-disk holes of all ground pins located in adjacent rows of high-speed differential signal pins are replaced with two fan-out holes that are symmetrically distributed vertically around the ground pins.
[0053] In some examples, high-speed differential signal pins use the gap between two fan-out holes of the corresponding pin in an adjacent row as part of their routing path; specifically:
[0054] High-speed differential signal pins use the gap between two fan-out holes in adjacent rows and near the ground pins of their sensitive signals as part of their wiring path;
[0055] Alternatively, a high-speed differential signal pin may use the gap between two fan-out holes of the ground pin in its adjacent row and near other high-speed differential signal pins as part of its wiring path.
[0056] In some examples, the vias of the corresponding ground pins in the same row as the high-speed differential signal pins are replaced with two fan-out vias that are symmetrically distributed horizontally around the ground pins; specifically, this can be:
[0057] When there is only one ground pin between two sets of high-speed differential signal pins located in the same row and adjacent to each other, the in-panel hole of the ground pin should be changed to two fan-out holes that are symmetrical about the ground pin and horizontally distributed.
[0058] Alternatively, all ground pins located in the same row as the high-speed differential signal pins could have their in-panel holes replaced with two fan-out holes that are symmetrically distributed horizontally with the ground pins as the center. Figures 3-8 as well as Figure 13 The diagram shows how the in-disk holes of all ground pins located in the same row as the high-speed differential signal pins are changed to two fan-out holes that are symmetrically distributed horizontally with the ground pins as the center.
[0059] In some examples, such as Figure 12 , 13 As shown, in the signal pin array, ground pin rows and mixed rows are arranged alternately; among them, the ground pin rows contain only ground pins, while the mixed rows contain both ground pins and high-speed differential signal pins.
[0060] In some examples, signal pin arrays are used for electrical connections to the high-speed chip under test.
[0061] High-speed chips can be BGA packaged chips, or derived packages such as PBGA, CBGA, and TBGA. This signal pin array is part of the chip test carrier board.
[0062] The solutions described in the above embodiments will be explained in detail below, taking into account the pin arrangement of the high-speed chip under test.
[0063] High-speed chips typically have two pin arrangements.
[0064] The first type, such as Figure 1 As shown in (a), this is a standard array arrangement, where the distance between pins is equal, all being X. The spacing between adjacent rows and adjacent columns is also X, which is equal to the pin spacing.
[0065] The second type, such as Figure 1 As shown in (b), this is an interleaved array arrangement, where the pins in the same row are equidistant from each other, both being X. The distance between adjacent rows is also X, equal to the pin spacing. The distance between adjacent columns is less than the pin spacing and greater than 0; or, as shown in... Figure 1 As shown in (c), the pins in the same column are all equal in distance, which is X. The distance between adjacent columns is also X, which is equal to the pin spacing. The distance between adjacent rows is less than the pin spacing and greater than 0.
[0066] like Figure 2 As shown, high-speed chips use differential signals for signal transmission, containing multiple sets of high-speed differential signal pins. These pins are grouped in pairs (located in the same row), and multiple ground pins are distributed around them. The gaps between the pins can serve as routing channels for signal lines. Based on the relative positions of the signal pins on the chip, those closer to the chip center are called inner-ring signals, and those closer to the chip edge are called outer-ring signals.
[0067] The signal pin array in this embodiment is suitable for both pin arrangements of high-speed chips. Therefore, the signal pin array in this embodiment is compatible with high-speed chips and can be configured as follows: Figure 3 and Figure 5 The standard array arrangement shown can also be as follows: Figure 4 and Figure 6 The staggered array arrangement is shown.
[0068] Correspondingly, for the signal pin array connected to the high-speed chip under test, the method of drilling holes for ground pins around the high-speed differential signal pins has been changed from the conventional one-hole in-disk configuration to two fan-out holes. Specifically, for ground pins in the same row as the outer and inner ring signals, the two fan-out holes are symmetrically distributed horizontally with the ground pin as the center point; for ground pins in rows adjacent to the outer and inner ring signals, the two fan-out holes are symmetrically distributed vertically with the ground pin as the center point. Figure 3 and Figure 4 In the diagram, 'a' represents the fan-out hole of the ground pin, 'b' represents the pad of the high-speed differential signal pin, 'A' represents the pad of the ground pin, and 'B' represents the pad of the high-speed differential signal pin.
[0069] like Figure 5 and Figure 6 As shown, when the wiring path of the inner ring signal passes through the outer ring signal, the wiring path passes through the middle of the two fan-out holes of the ground pin above or below the outer ring signal.
[0070] The beneficial effects of the solutions involved in the above embodiments will be described in detail below with specific application examples.
[0071] Application Case 1: For example Figure 7 As shown, the signal pin array is an interleaved array with a pin center distance a=0.9mm and a center distance b=0.6mm between the fan-out hole of the ground pin and the signal hole of the high-speed differential signal pin.
[0072] The high-speed differential signal pin groups diff1 and diff2 are mutually sensitive signals. The winding method described in the above embodiment is employed, specifically as follows: Figure 8 As shown. The traditional winding method is used, specifically as follows... Figure 9 As shown.
[0073] Figure 10 This is a comparison chart of the single-end insertion loss bandwidth results of the winding method and the conventional winding method described in the above embodiments. The solid line represents... Figure 8 The single-ended insertion loss curves of the positive and negative terminals of diff1 for the medium structure (using the winding in the above embodiment), with the dashed line representing... Figure 9 By comparing the single-ended insertion loss curves of the positive and negative terminals of the diff1 in the medium structure (using conventional winding), and the approximate location of the abrupt change in slope frequency, it can be seen that the method in the above embodiment increases the bandwidth frequency by nearly 4 GHz compared to the conventional method.
[0074] Figure 11 This is a comparison diagram of diff1 and diff2 crosstalk between the winding method described in the above embodiments and the conventional winding method. The solid line represents... Figure 8 Crosstalk results of differential vias between adjacent signals; dashed line represents... Figure 9 The crosstalk results of differential apertures between adjacent signals show that the method described in the above embodiments has a significant improvement before 40 GHz.
[0075] Application Case 2: For example Figure 12 As shown, the signal pin array is a standard array with a pin center distance a = 1.0 mm.
[0076] diff2 and diff5 are sensitive signals on the same row, so crosstalk should be avoided; diff2 and diff6 are sensitive signals on different rows, so crosstalk should also be avoided.
[0077] Using the winding method described in the above embodiments, the center distance b between the fan-out hole of the ground pin and the signal hole of the high-speed differential signal pin is 0.65mm. This solves the crosstalk between diff2 and diff5 without increasing the crosstalk between diff2 and diff6. Specifically, as follows... Figure 13 As shown.
[0078] Using the traditional winding method, the ground pins employ a center-hole design, such as... Figure 14 and Figure 15 As shown. In Figure 14 In the structure shown, the signal line of diff2 passes through the channel between diff5 and its adjacent ground pin, causing crosstalk between diff2 and diff5. Figure 15 In the structure shown, if a different wiring path is used to avoid crosstalk between diff2 and diff5, i.e., the signal line of diff2 passes through the gap between diff6 and its adjacent ground pin, crosstalk between diff2 and diff6 will occur.
[0079] Figure 16 This is a graph showing the crosstalk results of diff2 and diff5. The solid line represents... Figure 13 Crosstalk results for the winding method, the dashed line represents... Figure 14 Crosstalk results of the winding method. The comparison results show that by using the method in the above embodiment, moving the diff2 trace away from the diff5 via significantly improves the isolation between the two signal pins diff2 and diff5 before 40GHz, and the crosstalk is reduced.
[0080] Figure 17 This is a graph showing the crosstalk results of diff2 and diff6. The solid line represents... Figure 13 Crosstalk results for the winding method, the dashed line represents... Figure 14 Crosstalk results for the routing method. The comparison results between diff2 and diff6 show that when the diff2 trace passes through the channel between diff5 and its adjacent ground pin, the crosstalk curve is almost unaffected, regardless of whether it is closer to the diff6 signal via. As long as the trace is isolated by ground vias, whether it is one row of isolation or two rows of isolation, the effect can be achieved.
[0081] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A winding method for optimizing crosstalk in high-speed signals, characterized in that, The signal pin array includes multiple sets of high-speed differential signal pins and multiple ground pins surrounding each set of high-speed differential signal pins; the method includes: The in-panel holes of the corresponding ground pins in the adjacent row of the high-speed differential signal pins are changed to two fan-out holes that are symmetrically distributed vertically with the ground pins as the center. High-speed differential signal pins use the gap between the two fan-out holes of the corresponding pins in adjacent rows as part of their wiring path; The vias in the same row as the high-speed differential signal pins are replaced with two horizontally distributed fan-out vias symmetrically centered on the ground pins; among them, High-speed differential signal pins use the gap between the two fan-out holes of the corresponding pins in adjacent rows as part of their routing path; specifically: High-speed differential signal pins use the gap between two fan-out holes in adjacent rows and near the ground pin of their sensitive signal as part of their wiring path.
2. The winding method for optimizing high-speed signal crosstalk according to claim 1, characterized in that, The signal pin array is a standard array.
3. The winding method for optimizing high-speed signal crosstalk according to claim 1, characterized in that, The signal pin array is an interleaved array.
4. The winding method for optimizing high-speed signal crosstalk according to claim 1, characterized in that, In the signal pin array, ground pin rows and mixed rows are arranged alternately; the ground pin rows contain only ground pins, while the mixed rows contain both ground pins and high-speed differential signal pins.
5. The winding method for optimizing crosstalk in high-speed signals according to claim 1, characterized in that, The signal pin array is used for electrical connection to the high-speed chip under test.
6. The winding method for optimizing crosstalk in high-speed signals according to claim 1, characterized in that, The vias in the corresponding ground pins located in the adjacent row of the high-speed differential signal pins are changed to two fan-out vias that are symmetrically distributed vertically with the ground pin as the center; specifically: The in-panel vias located in adjacent rows of high-speed differential signal pins and near other high-speed differential signal ground pins are replaced with two fan-out vias symmetrically distributed vertically around the ground pins.
7. The winding method for optimizing crosstalk in high-speed signals according to claim 1, characterized in that, The vias in the same row as the high-speed differential signal pins are changed to two horizontally distributed fan-out vias symmetrically centered on the ground pins; specifically: When two sets of high-speed differential signal pins located in the same row and adjacent to each other are separated by only one ground pin, the in-disk hole of the ground pin is changed to two fan-out holes that are symmetrical about the ground pin and horizontally distributed.
8. A chip test carrier board, characterized in that, The winding method for optimizing high-speed signal crosstalk as described in any one of claims 1 to 7 is used for winding.