Method and device for improving multiplexing rate of hardened module of digital circuit and optimizing time sequence, power consumption and area
By using minimum bit-width binary encoding in the hardening module, creating a new module block_new and establishing a mapping relationship, the problems of poor timing, power consumption and area in the modular implementation of the hardening module are solved, and the reusability and design efficiency of the module are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINDIE SPACETIME (BEIJING) TECHNOLOGY CO LTD
- Filing Date
- 2025-12-15
- Publication Date
- 2026-04-17
AI Technical Summary
In VLSI design, the modular implementation of hardened modules makes the signals inside the modules unknown to synthesis tools, affecting timing, power consumption and area performance, and also resulting in poor module reusability, increasing design and verification costs.
The input parameters and constants at the boundary of the hardening module are optimized by using the minimum bit-width binary encoding method. By creating a new module block_new, removing the instantiated parameter and constant input ports, adding the encoding input port INST_ID, and establishing a mapping relationship within the new module, the logical equivalence and internal optimization of the hardening module are achieved.
The reuse rate of the hardened module was optimized, significantly improving timing, power consumption and area, and reducing design and verification costs.
Smart Images
Figure CN121881972A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of very large-scale digital integrated circuit design and implementation technology, and in particular to a method and apparatus for improving the reuse rate of hardened modules in digital circuits and optimizing timing, power consumption and area. Background Technology
[0002] In VLSI design, modular and hierarchical design is the mainstream approach. Sub-blocks are typically synthesized, placed, and routed independently to form "hardened blocks," which are then instantiated multiple times in higher-level designs to improve design efficiency and ensure consistency in physical implementation.
[0003] When a hardened module needs to be used in different scenarios, its instantiated parameters or some input ports may need to be connected to different constant values.
[0004] like Figure 1 The diagram shown is a structural diagram of a hardening module in the prior art. The instantiation parameters (param_1, ..., param_m) or constant input ports (input_1, ..., input_n) may not exist, but at least one of them exists, i.e., m≥0, n≥0, and m and n are not both 0 (signal output terminals and possible variable signal input terminals are omitted here).
[0005] The number of instantiated instances of the current block (u_block_inst_0, ..., u_block_inst_(i-1)) is at least 1, i.e., i≥1.
[0006] A constant matrix P with i rows and m+n columns represents the instantiation parameters and / or constant input ports of all instantiated blocks; the i instantiation instances are numbered sequentially from 0, 1, 2, ..., i-1, as follows:
[0007] P(0,1),P(0,2), …,P(0,m+n) represent the values of (m+n) instantiation parameters and / or constant input ports corresponding to the 0th instantiation instance u_block_inst_0;
[0008] P(1,1),P(1,2),…,P(1,m+n) represent the values of (m+n) instantiation parameters and / or constant input ports corresponding to the first instantiation instance u_block_inst_1; ...
[0010] P(i-1,1),P(i-1,2),…,P(i-1,m+n) represent the values of the (m+n) instantiation parameters and / or constant input ports corresponding to the (i-1)th instantiation instance u_block_inst_(i-1);
[0011] The existing hardening module coding method is shown below, using Verilog HDL as an example only, but also including but not limited to other hardware description languages such as VHDL.
[0012] / / u_block_inst_0
[0013] block #(.param_1 (P(0,1)),
[0014] .param_2 (P(0,2)), ... ... ...
[0018] .param_m (P(0,m))
[0019] u_block_inst_0 (
[0020] .input_1 (P(0,m+1)),
[0021] .input_2 (P(0,m+2)), ... ... ...
[0025] .input_n (P(0,m+n)) );
[0027] / / u_block_inst_1
[0028] block #(.param_1 (P(1,1)),
[0029] .param_2 (P(1,2)), ... ... ...
[0033] .param_m (P(1,m))
[0034] u_block_inst_1 (
[0035] .input_1 (P(1,m+1)),
[0036] .input_2 (P(1,m+2)), ... ... ...
[0040] .input_n (P(1,m+n)) );
[0042] / / ... Omitting possible intermediate blocks
[0043] / / u_block_inst_(i-1)
[0044] block #(.param_1 (P(i-1,1)),
[0045] .param_2 (P(i-1,2)), ... ... ...
[0049] .param_m (P(i-1,m))
[0050] u_block_inst_(i-1) (
[0051] .input_1 (P(i-1,m+1)),
[0052] .input_2 (P(i-1,m+2)), ... ... ...
[0056] .input_n (P(i-1,m+n)) );
[0058] In large-scale integrated circuit design, a bottom-up modular implementation approach is commonly used. Taking the aforementioned block as an example, it is typically synthesized, placed, and routed individually, then copied into multiple copies and assembled into a complete circuit and layout at a higher layer. However, the following two types of problems usually exist:
[0059] 1. Different values are passed in from outside the module via parameter instantiation (#(.param(value))) or constant input ports. This makes these signals inside the module "variable" to synthesis tools, preventing them from performing thorough logic optimizations (such as constant propagation, gate-level optimization, register optimization, etc.) based on fixed constant values. This results in poor timing, power, and area performance of the final hardened module.
[0060] 2. For each set of different parameters / constant values, different hardened module versions are generated. While this allows each module to be optimized based on constant values, it completely sacrifices module reusability and increases the cost and complexity of design, verification, backend implementation, and maintenance. Summary of the Invention
[0061] The purpose of this invention is to provide a technical solution for improving the reuse rate of hardening modules in digital circuits and optimizing timing, power consumption, and area, addressing the shortcomings of existing technologies. This optimization method has simple steps and can not only optimize the input parameters and constant values at the boundary of the hardening module by using minimum bit-width binary encoding under the premise of ensuring the logical equivalence of digital circuits, based on the reuse number of the hardening module, but also optimize the timing, power consumption, and area inside the hardening module to the greatest extent.
[0062] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0063] A method for improving the reuse rate of hardened modules in digital circuits and optimizing timing, power consumption, and area is characterized by comprising the following steps:
[0064] S1. Determine the instantiation number i of the hardening module to be optimized. Based on the instantiation number i, calculate and determine the bit width w of the encoded input signal INST_ID used to distinguish different instantiations, where w is the smallest positive integer that satisfies 2^w≥i.
[0065] S2. Create a new module block_new, which removes all instantiation parameters and constant input ports from the module to be optimized and hardened, and adds an encoding input port INST_ID[w-1:0] with a bit width of w;
[0066] S3. Inside the new module block_new, temporary variables are created for the instantiation parameters and constant input ports of the module to be optimized and hardened, respectively, based on the value of the encoding input port INST_ID.
[0067] S4. Inside the new module block_new, the corresponding instantiation parameters and constant values are assigned to temporary variables by encoding the value of the input port INST_ID, thus establishing a mapping relationship between the input port INST_ID and each instantiated instance.
[0068] S5. Instantiate the hardening module to be optimized inside the new module block_new using a temporary variable;
[0069] S6. In the top-level design, all original instances are re-instantiated using the new module block_new, and the encoded values from 0 to i-1 are assigned to the encoded input ports INST_ID of each instantiation.
[0070] This optimization method is simple in steps. It can optimize the input instantiation parameters and constant values at the boundary of the hardening module by using the minimum bit width binary encoding method, based on the number of times the hardening module is reused, while ensuring the logical equivalence of digital circuits. It can also optimize the timing, power consumption and area inside the hardening module to the greatest extent.
[0071] Furthermore, the encoded input signal in step S1 is a binary code, which is obtained by converting the decimal number i using the following formula:
[0072] ;
[0073] Where b k It is 0 or 1, and b w-1 The value is 1.
[0074] Furthermore, the temporary variables in step S3 include param_1_temp to param_m_temp for storing instantiated parameters, and input_1_temp to input_n_temp for storing constant input values.
[0075] Furthermore, the establishment of the mapping relationship between INST_ID and each instantiated instance in step S4 specifically includes the following steps: Inside the new module block_new, a mapping relationship is used to realize the mapping of the encoding input port INST_ID to the specific instantiated parameters and constant values.
[0076] Furthermore, the mapping relationship is implemented through conditional statements, including but not limited to case statements or if-else statements.
[0077] Furthermore, when 2^w > i, the conditional statement includes a default branch, and the default branch is assigned any set of instantiation parameters and constants corresponding to 0 to i-1.
[0078] Furthermore, the number of instantiated parameters of the hardening module to be optimized is m, and the number of constant input ports is n, where m≥0, n≥0, and m and n are not both 0.
[0079] Furthermore, the instantiation parameters and constant input port values of all original instances constitute an i-row (m+n) constant matrix P, where the instantiation parameters and constant values corresponding to the j-th instantiation instance are P(j,1) to P(j,m+n), and the value of j ranges from 0 to i-1.
[0080] An apparatus for performing a method as described above for improving the reuse rate of hardened digital circuit modules and optimizing timing, power consumption, and area, characterized in that it includes:
[0081] The encoding determination unit is used to determine the instantiation number i of the hardening module to be optimized, and calculates and determines the bit width w of the encoding input signal INST_ID used to distinguish different instantiations based on the instantiation number i.
[0082] The new module generation unit is used to generate a new module block_new, which removes all instantiation parameters and constant input ports from the original module block, and adds an encoded input port INST_ID with a bit width of w.
[0083] Internal decoding unit; used within the new module block_new, configured to receive the INST_ID signal and output a set of instantiation parameters and constants corresponding to the INST_ID value for internal instantiation of the original module block;
[0084] The internal instantiation unit is used to instantiate the original module block within the new module block_new, based on the instantiation parameters and constant values output by the internal decoding unit.
[0085] The present invention, by adopting the above-described technical solution, has the following beneficial effects:
[0086] The optimization method of the present invention has simple steps. It can not only optimize the input instantiation parameters and constant values on the boundary of the hardening module by using the minimum bit width binary encoding method according to the number of times the hardening module is reused, while ensuring the logic equivalence of digital circuits, but also optimize the timing, power consumption and area inside the hardening module to the greatest extent. Attached Figure Description
[0087] The present invention will be further described below with reference to the accompanying drawings:
[0088] Figure 1 This is a schematic diagram of the hardening module in the prior art;
[0089] Figure 2 This is a flowchart of the optimization method in the method and apparatus for improving the reuse rate of hardened modules in digital circuits and optimizing timing, power consumption and area according to the present invention.
[0090] Figure 3 This is a schematic diagram of the hardening module encoding structure in this invention;
[0091] Figure 4 This is a schematic diagram of the structure of the hardening module instantiated in this invention;
[0092] Figure 5 This is a schematic diagram of a device for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption and area according to the present invention. Detailed Implementation
[0093] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0094] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0095] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0096] like Figure 2 and Figure 4 As shown, this invention provides a method for improving the reuse rate of hardened modules in digital circuits and optimizing timing, power consumption, and area, comprising the following steps:
[0097] S1. Determine the instantiation number i of the hardening module to be optimized. Based on the instantiation number i, calculate and determine the bit width w of the encoded input signal INST_ID used to distinguish different instantiations, where w is the smallest positive integer that satisfies 2^w≥i.
[0098] The number of instantiation parameters of the hardening module to be optimized is m, and the number of constant input ports is n, where m≥0, n≥0, and m and n are not both 0.
[0099] The instantiation parameters and constant input port values of all original instances constitute an i-row (m+n) constant matrix P, where the instantiation parameters and constant values corresponding to the j-th instantiation instance are P(j,1) to P(j,m+n), and the value of j ranges from 0 to i-1.
[0100] The input signal is encoded in binary. The binary code is obtained by converting the decimal number i using the formula:
[0101] ;
[0102] Where b k It is 0 or 1, and b w-1 The value is 1.
[0103] If i is 1, then no encoding is needed, i.e., w=0; if i=2, then w=1; if i=3, then w=2; if i=4, then w=2; if i=5, then w=3; and so on.
[0104] S2. Create a new module block_new, which removes all instantiation parameters and constant input ports from the module to be optimized and hardened, and adds an encoding input port INST_ID[w-1:0] with a bit width of w.
[0105] As shown below, the original variable signal input and output ports are omitted.
[0106] module block_new(
[0107] input [w-1:0] INST_ID, ... ... ...);
[0111] S3. Inside the new module block_new, temporary variables are created for the instantiation parameters and constant input ports of the module to be optimized and hardened, based on the value of the encoding input port INST_ID.
[0112] Temporary variables include param_1_temp to param_m_temp for storing instantiated parameters, and input_1_temp to input_n_temp for storing constant input values.
[0113] reg [...] param_1_temp;
[0114] reg [...] param_2_temp; ...
[0116] reg [...] param_m_temp;
[0117] reg [...] input_1_temp;
[0118] reg [...] input_2_temp; ...
[0120] reg [...] input_n_temp;
[0121] S4. Inside the new module block_new, the corresponding instantiation parameters and constant values are assigned to temporary variables by encoding the value of the input port INST_ID, thus establishing a mapping relationship between the input port INST_ID and each instantiated instance.
[0122] Establishing the mapping relationship between INST_ID and each instantiated instance includes the following steps: Inside the new module block_new, a mapping relationship is used to realize the mapping from the encoding input port INST_ID to the specific instantiated parameters and constant values.
[0123] The mapping relationship is achieved through conditional statements, including but not limited to case statements or if-else statements.
[0124] When 2^w > i, the conditional statement includes a default branch, and the default branch is assigned any set of instantiation parameters and constants corresponding to 0 to i-1.
[0125] This embodiment uses a case study as an example. It should be noted that the default branch must use any set of values corresponding to 0 to i-1. This not only avoids generating latches but also yields the optimal circuit structure. That is, when 2^w > i, it can be guaranteed that there are still only the minimum required i decision branches.
[0126] always@(*) begin
[0127] case(INST_ID)
[0128] 0: begin
[0129] param_1_temp = P(0,1);
[0130] param_2_temp = P(0,2); ...
[0132] param_m_temp = P(0,m);
[0133] input_1_temp = P(0,m+1);
[0134] input_2_temp = P(0,m+2); ...
[0136] input_n_temp = P(0,m+n);
[0137] end
[0138] 1: begin
[0139] param_1_temp = P(1,1);
[0140] param_2_temp = P(1,2); ...
[0142] param_m_temp = P(1,m);
[0143] input_1_temp = P(1,m+1);
[0144] input_2_temp = P(1,m+2); ...
[0146] input_n_temp = P(1,m+n);
[0147] end ...
[0149] i-1: begin
[0150] param_1_temp = P(i-1,1);
[0151] param_2_temp = P(i-1,2); ...
[0153] param_m_temp = P(i-1,m);
[0154] input_1_temp = P(i-1,m+1);
[0155] input_2_temp = P(i-1,m+2); ...
[0157] input_n_temp = P(i-1,m+n);
[0158] end
[0159] default:
[0160] begin
[0161] param_1_temp = P(i-1,1);
[0162] param_2_temp = P(i-1,2); ...
[0164] param_m_temp = P(i-1,m);
[0165] input_1_temp = P(i-1,m+1);
[0166] input_2_temp = P(i-1,m+2); ...
[0168] input_n_temp = P(i-1,m+n);
[0169] end
[0170] S5. Instantiate the module to be optimized and hardened using a temporary variable inside the new module block_new, as shown below:
[0171] block #(.param_1 (param_1_temp),
[0172] .param_2 (param_2_temp), ... ... ...
[0176] .param_m (param_m_temp)
[0177] u_block_sub_inst (
[0178] .input_1 (input_1_temp),
[0179] .input_2 (input_2_temp), ... ... ...
[0183] .input_n (input_n_temp) );
[0185] S6. In the top-level design, all original instances are re-instantiated using the new module block_new, and the encoded values from 0 to i-1 are assigned to the encoded input ports INST_ID of each instantiation.
[0186] The above u_block_inst_0, u_block_inst_1, ..., u_block_inst_(i-1) are re-instantiated using the new block_new. The INST_ID numbers must correspond one-to-one with u_block_inst_0, u_block_inst_1, ..., u_block_inst_(i-1) according to the mapping relationship in step S4, as shown below:
[0187] / / u_block_inst_0
[0188] block_new u_block_inst_0 (
[0189] .INST_ID (0), ... ... ... );
[0194] / / u_block_inst_1
[0195] block_new u_block_inst_1 (
[0196] .INST_ID (1), ... ... ... );
[0201] / / ... Omit possible intermediate blocks
[0202] / / u_block_inst_(i-1)
[0203] block_new u_block_inst_(i-1) (
[0204] .INST_ID (i-1), ... ... ... );
[0209] This optimization method is simple in steps. It can optimize the input instantiation parameters and constant values at the boundary of the hardening module by using the minimum bit width binary encoding method, while ensuring the logical equivalence of the digital circuit. Logical equivalence means that this method does not change the original circuit function. It can also optimize the timing, power consumption and area inside the hardening module to the greatest extent.
[0210] The existing design is as follows:
[0211] block.v code:
[0212] module block
[0213] input [15:0] x,
[0214] input [15:0] y,
[0215] output [31:0] z );
[0217] assign z = x * y;
[0218] endmodule
[0219] top.v code:
[0220] module top(
[0221] input [15:0] b1,
[0222] input [15:0] b2,
[0223] input [15:0] b3,
[0224] output [31:0] c1,
[0225] output [31:0] c2,
[0226] output [31:0] c3 );
[0228] block u_block_inst_0 (.x(16'd2025),
[0229] .y(b1),
[0230] .z(c1) );
[0232] block u_block_inst_1 (.x(16'd1205),
[0233] .y(b2),
[0234] .z(c2) );
[0236] block u_block_inst_2 (.x(16'd1039),
[0237] .y(b3),
[0238] .z(c3) );
[0240] endmodule
[0241] This invention is designed as follows:
[0242] block_new.v code:
[0243] module block_new (
[0244] input [1:0] INST_ID,
[0245] input [15:0] y,
[0246] output [31:0] z );
[0248] reg [15:0] x_temp;
[0249] always @(*) begin
[0250] case (INST_ID)
[0251] 2’d0: x_temp = 16’d2025;
[0252] 2’d1: x_temp = 16’d1205;
[0253] 2’d2: x_temp = 16’d1039;
[0254] default: x_temp = 16’d2025;
[0255] endcase
[0256] end
[0257] block u_block_sub_inst (.x(x_temp),
[0258] .y(y),
[0259] .z(z) );
[0261] endmodule
[0262] Top - new.v code:
[0263] module top_new(
[0264] input [15:0] b1,
[0265] input [15:0] b2,
[0266] input [15:0] b3,
[0267] output [31:0] c1,
[0268] output [31:0] c2,
[0269] output [31:0] c3 );
[0271] block_new u_block_inst_0 (.INST_ID(2'd0),
[0272] .y(b1),
[0273] .z(c1) );
[0275] block_new u_block_inst_1 (.INST_ID(2'd1),
[0276] .y(b2),
[0277] .z(c2) );
[0279] block_new u_block_inst_2 (.INST_ID(2'd2),
[0280] .y(b3),
[0281] .z(c3) );
[0283] endmodule
[0284] The two designs described above are identical in all aspects except for the RTL (Randomization Technology), such as process, timing constraints, and scripting. A comparison of the logic synthesis results is shown in Table 1, where the right side shows the design using the new RTL encoding. It can be seen that the new RTL encoding method significantly improves timing, power consumption, and area. This patent selects a 16x16 multiplier as a specific embodiment. The specific percentage improvement depends on the circuit design and synthesis environment, but does not affect the overall conclusion.
[0285] block block_new Percentage of improvement WNS(ps) -41.8 -25.5 39.0% TNS(ps) -706.3 -368.5 47.9% cell area (um^2) 153.366 87.225 43.1% Power(nW) 33985.516 19970.821 41.2%
[0286] Table 1 Comparison of overall results before and after optimization
[0287] like Figure 5 As shown, this invention provides an apparatus for improving the reuse rate of hardened digital circuit modules and optimizing timing, power consumption, and area, comprising:
[0288] The encoding determination unit is used to determine the instantiation number i of the hardening module to be optimized, and calculates and determines the bit width w of the encoding input signal INST_ID used to distinguish different instantiations based on the instantiation number i.
[0289] The new module generation unit is used to generate a new module block_new, which removes all instantiation parameters and constant input ports from the original module block, and adds an encoded input port INST_ID with a bit width of w.
[0290] Internal decoding unit; used within the new module block_new, configured to receive the INST_ID signal and output a set of instantiation parameters and constants corresponding to the INST_ID value for internal instantiation of the original module block;
[0291] The internal instantiation unit is used to instantiate the original module block within the new module block_new, based on the instantiation parameters and constant values output by the internal decoding unit.
[0292] A digital integrated circuit includes the apparatus described above, wherein the top-level design of the digital integrated circuit obtains logical functions with different internal configurations by applying different INST_ID values to a new module block_new.
[0293] An electronic device comprising a digital integrated circuit as described above.
[0294] The above are merely specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on the present invention to achieve substantially the same technical effect are all covered within the protection scope of the present invention.
Claims
1. A method for improving the reuse rate of hardened modules in digital circuits and optimizing timing, power consumption, and area, characterized in that... Includes the following steps: S1. Determine the instantiation number i of the hardening module to be optimized. Based on the instantiation number i, calculate and determine the bit width w of the encoded input signal INST_ID used to distinguish different instantiations, where w is the smallest positive integer that satisfies 2^w≥i. S2. Create a new module block_new, which removes all instantiation parameters and constant input ports from the module to be optimized and hardened, and adds an encoding input port INST_ID with a bit width of w. S3. Inside the new module block_new, temporary variables are created for the instantiation parameters and constant input ports of the module to be optimized and hardened, respectively, based on the value of the encoding input port INST_ID. S4. Inside the new module block_new, the corresponding instantiation parameters and constant values are assigned to the temporary variable by encoding the value of the input port INST_ID, and a mapping relationship between the input port INST_ID and each instantiated instance is established. S5. Instantiate the hardening module to be optimized inside the new module block_new using the temporary variable; S6. In the top-level design, all original instances are re-instantiated using the new module block_new, and the encoding values from 0 to i-1 are assigned to the encoding input port INST_ID of each instantiation.
2. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption, and area according to claim 1, characterized in that: The encoded input signal in step S1 is a binary code, which is obtained by converting a decimal number i using a formula: ； Where b k It is 0 or 1, and b w-1 The value is 1.
3. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption, and area according to claim 1, characterized in that: The temporary variables in step S3 include param_1_temp to param_m_temp for storing instantiated parameters, and input_1_temp to input_n_temp for storing constant input values.
4. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption, and area according to claim 1, characterized in that: The specific steps for establishing the mapping relationship between INST_ID and each instantiated instance in step S4 are as follows: Inside the new module block_new, a mapping relationship is used to realize the mapping of the encoding input port INST_ID to the specific instantiated parameters and constant values.
5. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption and area according to claim 4, characterized in that: The mapping relationship is implemented through conditional statements, including but not limited to case statements or if-else statements.
6. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption and area according to claim 4, characterized in that: When 2^w > i, the conditional statement includes a default branch, and the default branch is assigned any set of instantiation parameters and constants corresponding to 0 to i-1.
7. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption, and area according to claim 1, characterized in that: The number of instantiation parameters of the hardening module to be optimized is m, and the number of constant input ports is n, where m≥0, n≥0, and m and n are not both 0.
8. The method for improving the reuse rate of digital circuit hardening modules and optimizing timing, power consumption and area according to claim 7, characterized in that: The instantiation parameters and constant input port values of all original instances constitute an i-row (m+n) constant matrix P, where the instantiation parameters and constant values corresponding to the j-th instantiation instance are P(j,1) to P(j,m+n), and the value of j ranges from 0 to i-1.
9. An apparatus for performing a method for improving the reuse rate of hardened digital circuit modules and optimizing timing, power consumption, and area as described in any one of claims 1 to 8, characterized in that: include The encoding determination unit is used to determine the instantiation number i of the hardening module to be optimized, and to calculate and determine the bit width w of the encoding input signal INST_ID used to distinguish different instantiations based on the instantiation number i. The new module generation unit is used to generate a new module block_new. Based on the module to be optimized and hardened, all instantiation parameters and constant input ports are removed, and an encoding input port INST_ID with a bit width of w is added. Internal decoding unit; Inside the new module block_new, it is configured to receive the INST_ID signal and output a set of instantiation parameters and constants corresponding to the INST_ID value for internally instantiating the hardening module to be optimized; An internal instantiation unit is used to instantiate the hardening module to be optimized within the new module block_new, based on the instantiation parameters and constant values output by the internal decoding unit.