Semiconductor device and operating method and system thereof

Abstract

The embodiment of the invention provides a semiconductor device and an operation method and system thereof. The semiconductor device comprises a memory array; the memory array includes a plurality of memory strings, each of which includes a plurality of memory cells connected in series between a bit line and a source layer; the storage unit is configured to store weight data; the source electrode layer comprises a plurality of first sub-source electrode layers which are spaced along a first direction, M memory strings where M memory units storing the same weight data are located are respectively coupled with different first sub-source electrode layers, and the first direction is parallel to the extending direction of the bit line; m is an integer greater than 1.

Description

Technical Field

[0001] This application relates to, but is not limited to, a semiconductor device and its operating method and system. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent.

[0003] Application content

[0004] According to a first aspect of the present application, a semiconductor device is provided, the semiconductor device comprising: a memory array; the memory array comprising a plurality of memory strings, each memory string comprising a plurality of memory cells connected in series between a bit line and a source layer; the memory cells being configured to store weight data; the source layer comprising a plurality of first sub-source layers spaced apart along a first direction, the M memory strings containing M memory cells storing the same weight data being respectively coupled to different first sub-source layers, the first direction being parallel to the direction in which the bit line extends; M being an integer greater than 1.

[0005] In some embodiments, M storage units storing the same weight data are coupled to the same bit line.

[0006] In some embodiments, two storage units storing the same weight data are coupled to the same bit line.

[0007] In some embodiments, the semiconductor device further includes peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to: write N weighted data into M*N memory cells; N is an integer greater than 0; apply a corresponding input voltage to the bit line coupled to the memory cell where the weighted data is written; and obtain the calculation result based on the output current of the source layer of the semiconductor device.

[0008] In some embodiments, the peripheral circuit includes a sensing circuit, a shift circuit, and an arithmetic circuit; wherein, the sensing circuit is coupled to the first sub-source layer and configured to acquire the output current signals of the M first sub-source layers respectively coupled to the M storage cells storing the same weight data, and perform analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals; the shift circuit is coupled to the sensing circuit and configured to shift at least a portion of the results of the multiple analog-to-digital conversions according to a preset rule; the arithmetic circuit is coupled to the shift circuit and configured to sum the shifted results corresponding to the results of the multiple analog-to-digital conversions to obtain the arithmetic result.

[0009] In some embodiments, the peripheral circuit is configured such that when writing N weight data into M*N memory cells, one weight data is stored in the M memory cells coupled to the first bit line and the M memory cells coupled to the second bit line respectively; the data stored in the 2M memory cells are used to form a differential data pair of weight data.

[0010] In some embodiments, the first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

[0011] In some embodiments, the storage unit has three bits; a weight data is stored in two storage units line-coupled at the first bit and two storage units line-coupled at the second bit; the data type of a weight data includes an eight-bit signed integer.

[0012] In some embodiments, the peripheral circuit is configured to: sequentially apply a first input voltage to the first bit line, apply a second input voltage to the second bit line; and apply a third input voltage to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; wherein the third input voltage is less than the first input voltage and greater than the second input voltage, and the voltage difference between the third input voltage and the first input voltage is equal to the voltage difference between the third input voltage and the second input voltage.

[0013] In some embodiments, the sensing circuit is specifically configured to acquire two opposite current signals output from each of the M first sub-source layers to which the 2M storage cells are respectively coupled, and to perform analog-to-digital conversion on the voltage signals corresponding to the acquired current signals.

[0014] In some embodiments, the peripheral circuit is configured to: sequentially apply a first input voltage to the first bit line, apply a second input voltage to the second bit line; and apply a third input voltage to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; wherein the first input voltage is equal to the second input voltage.

[0015] In some embodiments, the peripheral circuit further includes: a differential circuit; the differential circuit is coupled to the first sub-source layer and configured to perform differential processing on two current signals of the same direction output by each of the M first sub-source layers to which the 2M storage cells storing weight data are respectively coupled; a sensing circuit is coupled to the differential circuit and configured to acquire the differential data pair signal after differential processing, and perform analog-to-digital conversion processing on the voltage signal corresponding to the differential data pair signal.

[0016] In some embodiments, the source layer includes a plurality of second sub-source layers spaced apart along a second direction, and the M memory strings containing the M memory cells storing the same weight data are all coupled to the same second sub-source layer, with the second direction being perpendicular to the direction in which the bit line extends.

[0017] In some embodiments, a second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

[0018] In some embodiments, the semiconductor device includes a first semiconductor structure and a second semiconductor structure; a memory array is located in the first semiconductor structure, and the first semiconductor structure further includes a first bonding layer located on one side of the source layer; a peripheral circuit is located in the second semiconductor structure, and the second semiconductor structure further includes a second bonding layer located on one side of the peripheral circuit; the memory array and the peripheral circuit are connected by a hybrid bonding method of the first bonding layer and the second bonding layer.

[0019] In some embodiments, the semiconductor device includes a three-dimensional NAND-type memory.

[0020] According to a second aspect of the present application, a system is provided, the system comprising: at least one semiconductor device provided in the embodiments of the present application; and a controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive computation results output by the semiconductor device.

[0021] According to a third aspect of the embodiments of this application, an operation method for a semiconductor device is provided, the operation method comprising: writing N weight data into M*N memory cells of the semiconductor device; multiple M memory strings containing M memory cells storing the same weight data being coupled to different first sub-source layers; the semiconductor device comprising multiple memory strings, each memory string comprising multiple memory cells connected in series between a bit line and a source layer; the source layer comprising multiple first sub-source layers spaced apart along a first direction, the first direction being parallel to the direction in which the bit line extends; M being an integer greater than 1, and N being an integer greater than 0; applying a corresponding input voltage to the bit line coupled to the memory cell where the weight data is written; and obtaining a calculation result based on the output current of the source layer.

[0022] In some embodiments, two storage units storing the same weight data are coupled to the same bit line.

[0023] In some embodiments, two storage units storing the same weight data are coupled to the same bit line.

[0024] In some embodiments, obtaining the calculation result based on the output current of the source layer includes: acquiring the output current signals of M first sub-source layers respectively coupled to M storage cells storing the same weight data, and performing analog-to-digital conversion on the voltage signals corresponding to the acquired current signals; shifting at least some of the results of the multiple analog-to-digital conversions according to a preset rule; and summing the shifted results corresponding to the multiple analog-to-digital conversions to obtain the calculation result.

[0025] In some embodiments, the method further includes: when writing N weight data into M*N storage units, one weight data is stored in the first bit-coupled M storage units and the second bit-coupled M storage units respectively; the data stored in the 2M storage units is used to form a differential data pair of weight data.

[0026] In some embodiments, the first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

[0027] In some embodiments, the storage unit has three bits; a weight data is stored in two storage units line-coupled at the first bit and two storage units line-coupled at the second bit; the data type of a weight data includes an eight-bit signed integer.

[0028] In some embodiments, applying a corresponding input voltage to the bit line coupled to the storage cell for writing weight data includes: sequentially applying a first input voltage to the first bit line and applying a second input voltage to the second bit line; the operation method further includes: applying a third input voltage to each of the M first sub-source layers coupled to the 2M storage cells; wherein the third input voltage is less than the first input voltage and greater than the second input voltage, and the voltage difference between the third input voltage and the first input voltage is equal to the voltage difference between the third input voltage and the second input voltage.

[0029] In some embodiments, the process of acquiring the output current signals of M first sub-source layers to which M storage cells storing the same weight data are respectively coupled, and performing analog-to-digital conversion on the voltage signals corresponding to the acquired current signals, includes: acquiring two current signals in opposite directions output by each of the M first sub-source layers to which 2M storage cells are respectively coupled, and performing analog-to-digital conversion on the voltage signals corresponding to the acquired current signals respectively.

[0030] In some embodiments, applying a corresponding input voltage to the bit line coupled to the storage cell for writing weight data includes: sequentially applying a first input voltage to the first bit line and applying a second input voltage to the second bit line; the operation method further includes: applying a third input voltage to each of the M first sub-source layers coupled to the 2M storage cells; wherein the first input voltage is equal to the second input voltage.

[0031] In some embodiments, the operation method further includes: performing differential processing on two current signals of the same direction output from each of the M first sub-source layers to which the 2M storage cells storing weight data are respectively coupled; acquiring the output current signals of the M first sub-source layers to which the M storage cells storing the same weight data are respectively coupled, and performing analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals, including: acquiring differential data pair signals after differential processing, and performing analog-to-digital conversion processing on the voltage signals corresponding to the differential data pair signals respectively.

[0032] In some embodiments, the source layer includes a plurality of second sub-source layers spaced apart along a second direction, and the M memory strings containing the M memory cells storing the same weighted data are all coupled to the same second sub-source layer, with the second direction being perpendicular to the direction in which the bit line extends.

[0033] In some embodiments, a second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

[0034] The semiconductor device provided in this application embodiment includes: a memory array; the memory array includes multiple memory strings, each memory string including multiple memory cells connected in series between a bit line and a source layer; the memory cells are configured to store weight data; the source layer includes multiple first sub-source layers spaced apart along a first direction, and the M memory strings containing M memory cells storing the same weight data are respectively coupled to different first sub-source layers, the first direction being parallel to the direction of extension of the bit line; M is an integer greater than 1. In this application embodiment, the source layer is divided into multiple first sub-source layers spaced apart along the direction of extension of the bit line, that is, the source layer is divided into multiple first sub-source layers. The separation of these multiple first sub-source layers facilitates the execution of different subsequent operations on the output data of different first sub-source layers, such as performing different processing, so that the same weight data can be stored together by multiple memory cells in this application embodiment. Thus, the number of bits of weight data is not limited by the number of bits of storage of the memory cells, thereby providing storage of more bits of weight data in this application embodiment, thereby improving the computational parallelism of in-memory computing. Attached Figure Description

[0035] Figure 1This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of this application;

[0036] Figure 2A This is a schematic cross-sectional view of a memory array including NAND-type memory strings according to an embodiment of this application;

[0037] Figure 2B This is a perspective view of a memory array including NAND-type memory strings according to an embodiment of this application;

[0038] Figure 3A This is a schematic diagram illustrating an exemplary signal twisting method including peripheral circuitry according to an embodiment of this application;

[0039] Figure 3B This is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry according to an embodiment of this application;

[0040] Figure 4 This is a three-dimensional schematic diagram of a memory array as described in an embodiment of this application. Figure 1 ;

[0041] Figure 5 This is a top view schematic diagram of an embodiment of the present application including a memory array. Figure 1 ;

[0042] Figure 6 This is a second perspective view of an embodiment of the present application including a memory array;

[0043] Figure 7A This is a top view of an embodiment of the present application including a memory array;

[0044] Figure 7B This is a top view of an embodiment of the present application, including a memory array (Figure 3).

[0045] Figure 8A This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this application. Figure 1 ;

[0046] Figure 8B This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this application;

[0047] Figure 9 This is a three-dimensional schematic diagram of a memory array, as shown in embodiment three of this application.

[0048] Figure 10 This is a schematic diagram of four TLCs storing the same weight data, as described in an embodiment of this application.

[0049] Figure 11A This is a schematic diagram of the bit line and the method of applying the first sub-source layer voltage in the embodiments of this application. Figure 1 ;

[0050] Figure 11B This is a schematic diagram (2) showing the bit line and the method of applying the first sub-source layer voltage in an embodiment of this application;

[0051] Figure 12A This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this application;

[0052] Figure 12B This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this application. Figure 4 ;

[0053] Figure 12C This is a schematic diagram of the hardware composition including peripheral circuits in an embodiment of this application. Figure 5 ;

[0054] Figure 13 This is a top view schematic diagram of an embodiment of the present application including a memory array. Figure 4 ;

[0055] Figure 14 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0056] Figure 15A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0057] Figure 15B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application;

[0058] Figure 16 This is a schematic diagram illustrating the implementation flow of an operation method for a semiconductor device according to an embodiment of this application. Detailed Implementation

[0059] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0061] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0062] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0063] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0066] As the parameters of large AIGC (Artificial Intelligence Generated Content) models continue to grow, the traditional von Neumann architecture faces the "memory wall" and "power wall" problems. The bandwidth between the central processing unit (CPU) and memory has become a bottleneck restricting the performance of AI chips. Inspired by the working mode of the human brain, in-memory computing architecture has flourished in recent years. By embedding computing functions in memory, it avoids data transfer back and forth, reducing the impact of the memory wall and power wall, and thus has the potential to build high-performance, high-bandwidth, and high-energy-efficiency computing systems. At the same time, the data era places higher demands on storage density, and more bits, such as 4.5 bits, is an effective way to increase storage density. Based on this, semiconductor devices that can simultaneously realize more bits of storage and in-memory computing will be of great significance.

[0067] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random-Access Memory (SRAM), NAND flash memory, and Dynamic Random-Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will first introduce NAND flash memory.

[0068] Figure 1A schematic circuit diagram of an exemplary memory device 300 according to some aspects of this application is shown. The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory array 301 is described, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0069] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0070] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0071] like Figure 1 As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled through the same source layer (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0072] like Figure 1As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source layer 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source layer 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0073] refer to Figure 1 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0074] Figure 2A A schematic cross-sectional view of an exemplary memory array 301, including a memory string 308, exemplified by NAND, is shown according to some aspects of this application. Figure 2A As shown, the NAND memory array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and adjacent gate layers 411 are separated by an insulating layer 412.

[0075] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0076] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0077] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0078] Figure 2B This is a perspective view of a memory array including NAND flash memory strings according to an embodiment of this application. Figure 2B As shown, the memory array 301 sequentially includes multiple bit lines BL (e.g., m lines), multiple up-select transistor TSG lines (e.g., p lines), multiple word lines (e.g., n lines), down-select transistor BSG lines, source layer CSL, and multiple memory cells coupled to the word lines.

[0079] Return to reference Figure 1The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source layer 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source layer 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0080] Figure 3A Some exemplary semiconductor devices are shown, with peripheral circuitry including control logic 512, a digital-to-analog converter 501 connected to the control logic 512, and an analog-to-digital converter 502 connected to the memory array 301. The analog-to-digital converter 502 is connected to the control logic 512.

[0081] During the computation phase using semiconductor devices, the analog-to-digital converter 501 converts digital signals into voltage signals required by the memory array 301 in the in-memory computing chip. The analog-to-digital converter 502 converts the current signals output by the memory array 301 into digital signals. The control logic 512 can be coupled to peripheral circuits and configured to control the operation of the peripheral circuits. The control logic 512 can also be used to receive input data sent by the memory controller and send the calculation results to the memory controller.

[0082] Figure 3B Some exemplary peripheral circuits are shown, except Figure 3A In addition to the structure of the peripheral circuitry shown, the peripheral circuitry includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 3B Additional peripheral circuitry not shown.

[0083] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0084] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source layer voltages to be supplied to memory array 301.

[0085] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 706 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0086] Figure 4 This is a three-dimensional schematic diagram of a memory array as described in an embodiment of this application. Figure 1 ; Figure 5 This is a top view schematic diagram of an embodiment of the present application including a memory array. Figure 1 In some embodiments, during the computation phase using semiconductor devices as in-memory computing chips, before the computation begins, weight data is written into the corresponding storage cells of the memory array according to a certain mapping rule. For example... Figure 4 As shown, a single memory cell, such as a TLC, can store a weight data of 3 bits (INT3). Then, based on the input data, input voltages are applied to the corresponding bit lines, and finally, the output current of the source layer SL is received to obtain the computation result. It is understandable that in the above embodiment, the in-memory computing technology based on 3D NAND uses one memory cell to store one weight data. The number of bits in the weight data is limited by the number of bits in the memory cell, resulting in low parallelism and low precision. While inputting data from the bit line BL can increase input precision, it further reduces parallelism.

[0087] In some embodiments, both the gate line isolation structure (GLS) and the top select gate (or TSG line) isolation structure (TSGCUT) extend in a direction perpendicular to the bit line extension direction. GLS and TSGCUT divide the memory block into multiple memory shards (String), such as 6 shards. Figure 5 The example shows two Strings, String1 and String2, each coupled to a different TSG. For example... Figure 5 As shown, bit lines BL are coupled to channel structures CH, where adjacent memory cells in a row of channel structures along the bit line extension direction are coupled to different bit lines BL. Source layer SL ( Figure 5(Not shown in the diagram) Interconnected in units of storage blocks. It is understandable that regardless of the size of the input data, the entire storage block will be occupied due to the interconnection of the source layer SL, and bit lines BL and storage cells not used for data input will be wasted. In other words, due to the interconnection of the source layer SL, the parallelism is extremely low, especially for small-scale weighted data where significant waste occurs.

[0088] Based on this, this application embodiment provides another semiconductor device, which includes: a memory array; the memory array includes a plurality of memory strings, each memory string including a plurality of memory cells connected in series between a bit line and a source layer; the memory cells are configured to store weight data; the source layer includes a plurality of first sub-source layers spaced along a first direction, and the M memory strings containing M memory cells storing the same weight data are respectively coupled to different first sub-source layers, the first direction being parallel to the direction of extension of the bit line; M is an integer greater than 1.

[0089] Here, the memory array can refer to the aforementioned memory array 301 and... Figure 1 , Figure 3B For understanding; the storage string can be referred to as the aforementioned storage string 308 and... Figure 2A , Figure 2B For understanding; the bit line can be referred to as bit line 316 mentioned above and Figure 2A , Figure 2B For understanding; the source layer can be referred to as the aforementioned source layer 314 and... Figure 1 , Figure 2B For understanding; the storage unit can refer to the aforementioned storage unit 306 and... Figure 1 The details are not elaborated here.

[0090] Here and below, the first direction is the same as the direction of bit line extension; the second direction is perpendicular to the direction of bit line extension and parallel to the direction of word line extension; the third direction is perpendicular to both the first and second directions, and the direction of storage string extension can be parallel to the third direction.

[0091] In this embodiment, the source layer is no longer connected as a single block of memory, but rather comprises multiple first sub-source layers spaced apart along a first direction. In some embodiments, such as... Figure 7A , Figure 7B As shown, the source layer is divided into multiple first sub-source layers by a first source layer isolation structure SLCUT1 extending along the second direction. The first source layer isolation structure G1 can penetrate the source layer along the third direction. It should be noted that... Figure 7A , Figure 7B Other logos can be referenced. Figure 5 The identifier in the text.

[0092] In this embodiment, during the computation stage using a semiconductor device as a memory computing chip, before the computation begins, weight data is written into the corresponding storage cells of the memory array according to a certain mapping rule. Furthermore, the M storage strings containing the M storage cells storing the same weight data are respectively coupled to different first sub-source layers, where M is an integer greater than 1. In other words, this embodiment uses at least two storage cells to store the same weight data together. Figure 6 The illustration shows a case where the same weight data is stored together using two storage units; wherein, at least two different storage units are used to store different data bits of the same weight data, so that the number of bits of weight data is not limited by the number of bits of storage units, thereby providing storage for more bits of weight data in the embodiments of this application, thereby improving parallelism.

[0093] It is understood that in this embodiment, the source layer is divided into multiple first sub-source layers. This separation of the multiple first sub-source layers facilitates the execution of different subsequent operations on the output data of different first sub-source layers, such as performing different shift operations, and then summing the shifted data. The separation of the multiple first sub-source layers also allows different storage units in the M storage units used to store the same weight data to store different data bits of the same weight data.

[0094] In some embodiments, M can be determined based on the data type of the weight data and the number of bits in the storage unit. For example, if the weight data is a six-bit positive integer, then M can be 2 for TLC; if the weight data is a nine-bit positive integer, then M can be 3 for TLC; if the weight data is a sixteen-bit positive integer, then M can be 4 for QLC.

[0095] In some embodiments, the configuration of the first source layer isolation structure SLCUT1 can be determined based on the coupling between the bit line BL and the memory cells in the channel structure, and the number of M. For example, as... Figure 7A , 7B In a row of channel structures extending along the bit line extension direction, adjacent channel structure storage cells are coupled to different bit lines BL. If M=2, then a first source layer isolation structure SLCUT1 can be set every two rows of channels to complete one source layer isolation. This application does not limit the specific setting of the first source layer isolation structure SLCUT1, but regardless of the setting, it must satisfy the requirement that the M storage strings containing the M storage cells storing the same weight data are respectively divided into different first sub-source layers.

[0096] In some embodiments, M memory cells storing the same weight data are coupled to the same bit line. It is understood that, in the embodiments of this application, during the computation stage using a semiconductor device as a memory computing chip, data is input by applying voltage to the bit line. If the M memory cells storing the same weight data can be coupled to the same bit line, the voltage applied to the same bit line can be mapped to the multiple memory cells coupled to it, effectively saving bit lines.

[0097] In some embodiments, two storage units storing the same weight data are coupled to the same bit line. That is, in this case, M=2, such as... Figure 6 As shown.

[0098] In some embodiments, the M storage strings containing the M storage units storing the same weight data are each coupled to the same selection line, such as... Figure 7A As shown, taking M=2 as an example, the two storage cells within the dashed box coupled to the leftmost bit line BL are used to store the same weight data. Here and below, the selection line may include a TSG line and / or a BSG line. In some embodiments, the selection line may be a TSG line.

[0099] In some embodiments, the M storage strings containing the M storage units storing the same weight data are respectively coupled to different selection lines, such as... Figure 7B As shown, taking M=2 as an example, the two storage cells within the dashed box coupled to the leftmost bit line BL are used to store the same weight data. Furthermore, in... Figure 7B In this embodiment, the two storage units used to store the same weight data are located in two adjacent storage slices (String) along the first direction. In some embodiments not shown, the two storage units used to store the same weight data may also be located in two spaced-apart storage slices (String) along the first direction.

[0100] In some embodiments, the semiconductor device further includes peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to: write N weighted data into M*N memory cells; N is an integer greater than 0; apply a corresponding input voltage to the bit line coupled to the memory cell where the weighted data is written; and obtain the calculation result based on the output current of the source layer of the semiconductor device.

[0101] Here, the peripheral circuit can refer to the aforementioned peripheral circuit 302 and... Figure 3A , Figure 3B The details are not elaborated here.

[0102] Here, N can be the number of weight data to be written. N can be one or more. Each weight data is stored using M storage units. Based on this, N weight data are written into M*N storage units.

[0103] As mentioned above, in the embodiments of this application, during the computation stage using semiconductor devices as in-memory computing chips, before the operation begins, weight data is written into the corresponding storage cells of the memory array according to a certain mapping rule; then, according to the input data, the corresponding input voltage is applied to the bit lines coupled to the storage cells where the weight data is written; finally, the output current of each first sub-source layer in the source layer SL is received, and according to the received current signal, the result of multiplying or adding the input data and the data stored in the memory array (corresponding to the weight data) is obtained.

[0104] In some embodiments, the weight data mapping rule may involve multiple memory cells in a memory array coupled to a selected word line. The weight data in this application embodiment can be vector-type or matrix-type weight data. In some embodiments, the weight data is a matrix, and each data in the matrix is ​​written into multiple memory cells in the memory array according to a multiple set of position rules, with M memory cells as a group, extending along a first direction and a second direction respectively. This process is similar to the programming operation process of a semiconductor device.

[0105] In some embodiments, the peripheral circuitry is configured to apply corresponding input voltages to the bit lines coupled to the memory cells where the weighted data is written, based on the input data. That is, the input voltage applied to the bit lines is related to the data value of the input data. The input data can be vector-type or matrix-type. In some embodiments, the input data is a vector. Different input voltages can characterize different data values ​​of the input data; for example, applying a programming enable voltage to the bit line BL, which puts the channel structure in a conducting state, characterizes the input data value "1"; applying a programming disable voltage to the bit line BL, which puts the channel structure in a turning state, characterizes the input data value "0".

[0106] In some embodiments, the peripheral circuit includes a sensing circuit, a shifting circuit, and an arithmetic circuit; wherein, the sensing circuit is coupled to the first sub-source layer and configured to acquire the output current signals of the M first sub-source layers respectively coupled to the M storage cells storing the same weight data, and perform analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals; the shifting circuit is coupled to the sensing circuit and configured to shift at least a portion of the results of the multiple analog-to-digital conversions according to a preset rule; the arithmetic circuit is coupled to the shifting circuit and configured to sum the shifted results corresponding to the results of the multiple analog-to-digital conversions to obtain the arithmetic result.

[0107] For example, let's illustrate this by using two storage units to store the same weight data. Figure 8A , Figure 8BAs shown, the peripheral circuitry includes multiple sensing circuits 801, one or more shift circuits 802, and one or more operational circuits 803. The output terminals of different first sub-source layers ( Figure 8A and Figure 8B Out1 and Out3 can correspond to Figure 6 (Understanding Out1 and Out3 in the original text) can be coupled to the input terminals of different sensing circuits 801, each sensing circuit 801 acquiring and converting the input signal from analog to digital; then the output terminal of the sensing circuit 801 can be selectively coupled to the input terminal of the shift circuit 802. Figure 8A Only one sensing circuit 801 is coupled to the shift circuit 802. Figure 8B Both sensing circuits 801 are coupled to shift circuit 802, which performs shift processing on the input digital signal. Figure 8B The two shift circuits 802 need to satisfy the requirement that the shift difference is the same as the actual high-low bit difference of the weighted data; the output of each shift circuit 802 that has undergone shift processing is coupled to the input of the same arithmetic circuit 803, or the output of the sensing circuit 801 of the branch that has not undergone shift processing and the output of the shift circuit 802 of the branch that has undergone shift processing are coupled to the input of the same arithmetic circuit 803. The arithmetic circuit 803 performs a summation operation on the input data and outputs the operation result.

[0108] In some embodiments, the plurality of sensing circuits 801 may include a plurality of single-channel analog-to-digital converters (ADCs) or one or more multi-channel ADCs. In some embodiments, the shift circuit 802 may include, but is not limited to, a shift register. In some embodiments, the arithmetic circuitry may include an adder.

[0109] The above embodiments of this application improve the parallelism of in-memory computing from the perspective of storing more bit weight data. Embodiments of this application can also improve the accuracy of in-memory computing by using differential data pairs. It is understood that interference signals generally act on both signals of a differential data pair simultaneously. The receiver in a differential data pair is concerned with the difference between the two signals, so the interference signals suffered by both signals will be completely canceled out, thereby improving accuracy through differential data pairs.

[0110] In some embodiments, the peripheral circuit is configured such that when writing N weight data into M*N memory cells, one weight data is stored in the M memory cells coupled to the first bit line and the M memory cells coupled to the second bit line respectively; the data stored in the 2M memory cells are used to form a differential data pair of weight data.

[0111] Here, the same weight data is stored in the first line-coupled M storage units and the first line-coupled M storage units respectively. That is, the same weight data is stored twice in 2M storage units. The data stored in these 2M storage units is used to form the difference data pairs of the weight data.

[0112] In some embodiments, the first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

[0113] In some embodiments, the first bit line and the second bit line adjacent along the second direction are both coupled to the same column of channel structures; wherein, in the same column of channel structures, the memory cells of some channel structures are coupled to the first bit line, and the memory cells of the remaining channel structures are coupled to the second bit line.

[0114] Understandably, using adjacent bit lines for the differential data pairs used to form the weight data can reduce the wiring complexity between the output of the first sub-source layer and the input of the peripheral circuit.

[0115] In some embodiments, the storage unit has three bits; a weight data is stored in two storage units line-coupled at the first bit and two storage units line-coupled at the second bit; the data type of a weight data includes an eight-bit signed integer.

[0116] In some implementations, four storage units used to store the same weight data can reside in the same String. For example... Figure 7A As shown, the four storage units used to store the same weight data can be four storage units coupled to the dashed rectangle and the 5th bit line and the 6th bit line on the left.

[0117] In some implementations, the four storage units used to store the same weight data can be located in different Strings. For example... Figure 7B As shown, the four storage units used to store the same weight data can also be four storage units coupled to the 5th bit line and the 6th bit line on the left, respectively, by two dashed rectangles.

[0118] In some implementations, such as Figure 9 As shown, the storage unit has three bits; a weighted data is stored in the first storage unit (corresponding to Out1) and the third storage unit (corresponding to Out3) coupled to the first bit line, and in the second storage unit (corresponding to Out2) and the fourth storage unit (corresponding to Out4) coupled to the second bit line. The storage strings containing the first and second storage units are coupled to the same first sub-source layer, and the storage strings containing the third and fourth storage units are coupled to the same first sub-source layer.

[0119] In some implementations, the data type of one of the weight data includes an eight-bit signed integer, which includes one sign bit and seven data bits, and its corresponding data range is -128 to +127.

[0120] like Figure 10 As shown, taking TLC as an example, the first storage cell, BL1, is coupled to the first and third storage cells, Cell1 and Cell3, which store the positive part of the weight data. Cell1 and Cell3 have 8 storage states with a data range of 0-7. The second storage cell, BL2, is coupled to the second and fourth storage cells, Cell2 and Cell4, which store the negative part of the weight data. Cell1 and Cell3 have 9 storage states with a data range of 0-8 (the negative sign needs to be reflected in the subsequent differential implementation scheme). Cell1 and Cell2 store the low-order differential data pairs of the weight data; Cell3 and Cell4 store the high-order differential data pairs of the weight data, shifting the high-order differential data pairs 4 bits to the left (similar to shifting 2 bits to the left). 4 The weight range of INT8 can be achieved by multiplying the data and then summing it with the lower-order difference data.

[0121] It should be noted that, in Figure 10 In this embodiment, the first storage unit Cell1 and the second storage unit Cell2 are coupled to TSG0, and the third storage unit Cell3 and the fourth storage unit Cell4 are coupled to TSG1. However, in other embodiments, the first storage unit Cell1, the second storage unit Cell2, the third storage unit Cell3 and the fourth storage unit Cell4 can all be in the same String and coupled to the same TSG.

[0122] It should be noted that the different number of storage states between the first storage unit Cell1 and the second storage unit Cell2, and between the third storage unit Cell3 and the fourth storage unit Cell4, can be achieved through structural differences in the storage units themselves, such as differences in the total threshold width.

[0123] There are several implementation schemes for differential mapping in the embodiments of this application. Two of them are shown below.

[0124] Option 1: Differential current is achieved by applying different voltages to the bit lines. The different voltages applied to the bit lines result in one branch being a positive current and the other branch being a negative current, thus forming a differential current. The result is then fed into the ADC.

[0125] In some embodiments, the peripheral circuit is configured to: sequentially apply a first input voltage V1 to the first bit line, apply a second input voltage V2 to the second bit line; and apply a third input voltage V3 to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; wherein the third input voltage V3 is less than the first input voltage V1 and greater than the second input voltage V2, and the voltage difference between the third input voltage V3 and the first input voltage V1 is equal to the voltage difference between the third input voltage V3 and the second input voltage V2.

[0126] In this embodiment, the voltages on different bit lines BL need to be input in a time-division manner in order to receive data from different memory strings on the same first sub-source layer. Therefore, a first input voltage needs to be applied to the first bit line sequentially, and a second input voltage needs to be applied to the second bit line sequentially.

[0127] In this embodiment, differential current is achieved by setting the voltage applied to the first sub-source layer between the voltage applied to the first bit line and the voltage applied to the second bit line, so that the output current on the first sub-source layer is opposite.

[0128] It should be noted that, Figure 11A The first input voltage of 10V, the second input voltage of 0V, and the third input voltage of 5V shown are merely examples and are not intended to limit the specific voltage values ​​of the first input voltage, the second input voltage, and the third input voltage in the embodiments of this application. It is understood that the specific voltage values ​​of the first input voltage, the second input voltage, and the third input voltage can be adjusted and set according to the characteristics of the semiconductor device.

[0129] In some embodiments, the sensing circuit is specifically configured to acquire two opposite current signals output from each of the M first sub-source layers to which the 2M storage cells are respectively coupled, and to perform analog-to-digital conversion on the voltage signals corresponding to the acquired current signals.

[0130] In this embodiment of the application, reference is made to Figure 12A Taking M=2 as an example, no additional differential circuit is needed. The sensing circuit 801 acquires two current signals in opposite directions output from each of the two first sub-source layers coupled to the four memory cells. Specifically, the current directions of Out1 and Out2 are opposite, and the current directions of Out3 and Out4 are opposite. Out1, Out2, Out3, and Out4 can be referenced... Figure 9 Understand Out1, Out2, Out3, and Out4.

[0131] It should be noted that, Figure 8B The shift circuit example in the previous example can also be applied to the embodiments of this application.

[0132] Option 2: The voltage applied to the bit lines is the same, and the difference is achieved through a differential circuit in the peripheral circuit.

[0133] In some embodiments, the peripheral circuit is configured to: sequentially apply a first input voltage V1 to the first bit line, apply a second input voltage to the second bit line V2; and apply a third input voltage V3 to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; wherein, the first input voltage V1 is equal to the second input voltage V2.

[0134] In this embodiment, the voltages on different bit lines BL need to be input in a time-division manner in order to receive data from different memory strings on the same first sub-source layer. Therefore, a first input voltage needs to be applied to the first bit line sequentially, and a second input voltage needs to be applied to the second bit line sequentially.

[0135] In this embodiment, the voltage applied to the first bit line is the same as the voltage applied to the second bit line, while the differential circuit added in the peripheral circuit is used to achieve the differential.

[0136] It should be noted that, Figure 11B The first input voltage of 10V, the second input voltage of 10V, and the third input voltage of 0V shown are merely examples and are not intended to limit the specific voltage values ​​of the first input voltage, the second input voltage, and the third input voltage in the embodiments of this application. It is understood that the specific voltage values ​​of the first input voltage, the second input voltage, and the third input voltage can be adjusted and set according to the characteristics of the semiconductor device.

[0137] In some embodiments, the peripheral circuit further includes: a differential circuit; the differential circuit is coupled to the first sub-source layer and configured to perform differential processing on two current signals of the same direction output by each of the M first sub-source layers to which the 2M storage cells storing weight data are respectively coupled; a sensing circuit is coupled to the differential circuit and configured to acquire the differential data pair signal after differential processing, and perform analog-to-digital conversion processing on the voltage signal corresponding to the differential data pair signal.

[0138] In some embodiments, the differential circuitry includes, but is not limited to, a differential amplifier.

[0139] In this embodiment of the application, reference is made to Figure 12B Taking M=2 as an example, an additional differential circuit 804 is required. The sensing circuit 801 acquires two current signals of the same direction output from each of the two first sub-source layers coupled to the four storage cells. Among them, the current directions of Out1 and Out2 are the same, and the current directions of Out3 and Out4 are the same. Out1, Out2, Out3, and Out4 can be referenced. Figure 9Let's understand Out1, Out2, Out3, and Out4. The differential circuit 804 forms differential data pairs between Out1 and Out2, and between Out3 and Out4.

[0140] refer to Figure 12C Taking M=3 as an example, an additional differential circuit 804 is required. The sensing circuit 801 acquires two current signals in the same direction output from each of the three first sub-source layers, which are respectively coupled to the six memory cells. Among them, Out1, Out3, and Out5 are coupled to the same bit line, and Out2, Out4, and Out6 are coupled to the same bit line. The current directions of Out1, Out2, Out3, Out4, Out5, and Out6 are all the same. The differential circuit 804 forms differential data pairs for Out1 and Out2, Out3 and Out4, and Out5 and Out6, respectively.

[0141] It should be noted that, Figure 8B The shift circuit example in the previous example can also be applied to the embodiments of this application.

[0142] In some embodiments, before differential processing of the two signals output from the source layer, the two current signals output from the source layer (the two current signals have the same direction) are converted into voltage signals through sampling resistors, etc., and differential processing is performed on the two voltage signals. Then, the differentially processed voltage signals are converted into digital signals.

[0143] In some embodiments, the source layer includes a plurality of second sub-source layers spaced apart along a second direction, and the M memory strings containing the M memory cells storing the same weight data are all coupled to the same second sub-source layer, with the second direction being perpendicular to the direction in which the bit line extends.

[0144] In this embodiment, the source layer may further include a plurality of second sub-source layers spaced apart along the second direction. In some embodiments, such as Figure 13 As shown, the source layer is divided into multiple second sub-source layers by a second source layer isolation structure SLCUT2 extending along the first direction. The second source layer isolation structure G1 can penetrate the source layer along the third direction. It should be noted that... Figure 13 Other logos can be referenced. Figure 5 The identifier in the diagram. The M storage strings containing the M storage units storing the same weight data are all coupled to the same second sub-source layer. It should be noted that each second sub-source layer is also divided into multiple parts by the first source layer isolation structure SLCUT1.

[0145] In some embodiments, the first bit line and the second bit line of the aforementioned memory cell coupling for differential processing are both coupled to the same second sub-source layer.

[0146] In some embodiments, a second sub-source layer is coupled to several memory strings, and the number of bit lines coupled to the several memory strings is related to the amount of input data.

[0147] In this embodiment, the segmentation of the source layer SL along the extension direction of bit line BL is related to the amount of input data, i.e., related to the computational cost of each calculation. For example, if the size of the input data is 32, for a scheme without differential processing, the source layer SL is segmented every 32 bit lines; for a scheme with differential processing, the source layer SL is segmented every 64 bit lines.

[0148] It is understood that, in the embodiments of this application, the source layer SL can be adaptively divided along the extension direction of the bit line BL according to the specifications of the input data, thereby avoiding the waste of bit lines BL and storage units that are not used for data input, and thus improving the parallelism of the source layer output.

[0149] In some embodiments, the semiconductor device includes a three-dimensional NAND-type memory.

[0150] In some embodiments, the memory array is located in a first semiconductor structure, which further includes a first bonding layer located on one side of the source layer; the peripheral circuit is located in a second semiconductor structure, which further includes a second bonding layer located on one side of the peripheral circuit; the memory array and the peripheral circuit are connected by a hybrid bonding method of the first bonding layer and the second bonding layer.

[0151] In some embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on the first wafer, the second semiconductor structure can be formed on the second wafer, and then the two wafers can be bonded together. The first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. In some embodiments, the first semiconductor structure further includes a first bonding layer located on one side of the source layer; the peripheral circuit is located in the second semiconductor structure, and the second semiconductor structure further includes a second bonding layer located on one side of the peripheral circuit. Both the first bonding layer and the second bonding layer include a dielectric layer and a conductive structure (such as a conductive pillar) located between the dielectric layers. The first bonding layer and the second bonding layer are bonded using a hybrid bonding process.

[0152] In this embodiment of the application, the source layer SL can be isolated in a direction perpendicular to the bit line extension direction on the first wafer, i.e., the wafer where the memory array is located, or the source layer SL can be isolated in a direction along the bit line extension direction on the wafer where the memory array is located.

[0153] In this embodiment of the application, additional differential circuits, shift circuits, arithmetic circuits, etc., can be added on the second wafer, i.e., the wafer where the peripheral circuits are located.

[0154] In other embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device may also be formed on the same wafer, but the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. The architecture in which the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device can save more area of ​​the semiconductor device.

[0155] In this embodiment, the BL input stores a single INT8 weight data through four TLC memory cells connected by adjacent bit lines BL, along with differential and shift processing. Isolating the source layer SL along a direction perpendicular to the bit line extension direction ensures the implementation of shift and differential processing; isolating the source layer SL along a direction perpendicular to the bit line extension direction improves the parallelism of the source layer output, thereby enhancing the computational parallelism and accuracy of the in-memory computing chip.

[0156] A second aspect of this application provides a system comprising: at least one semiconductor device as provided in this application; and a controller coupled to the at least one semiconductor device and configured to control the execution of data access operations on the semiconductor device or to send input data to the semiconductor device and to receive computation results output by the semiconductor device.

[0157] In some embodiments, the system described above may be as follows: Figure 14 The memory system 102 shown includes a memory controller 106 and a memory device 104 coupled to the memory controller 106. The controller in the above embodiment can be, for example,... Figure 14 , Figure 15A as well as Figure 15B The memory controller 106 shown is an example. In other embodiments, the system described above may be as follows: Figure 14 The system 100 shown includes a host device 108 and a memory system 102 coupled to the host device 108. The controller in the above embodiment may be a control unit independent of the memory controller 106, such as the CPU in the host device. The input data here includes vectors or matrices. According to some implementations, such as... Figure 14As shown, memory controller 106 is coupled to memory device 104 and host device 108 and is configured to control the operation of memory device 104, such as read, erase, program, and compute operations. Memory controller 106 can manage data stored in memory device 104 and communicate with host device 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, Universal Serial Bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise memory arrays.

[0158] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 15A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash memory card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host device (e.g., Figure 14 The host device 108 in the memory card connector 204 is coupled to it. In such a way... Figure 15B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include interfaces for connecting the SSD 206 to host devices (e.g., Figure 14 The SSD connector 208 is coupled to the host device 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0159] The third aspect of this application provides a method for operating a semiconductor device, such as... Figure 16 As shown, the operation method includes:

[0160] Step S1601: Write N weight data into the M*N memory cells of the semiconductor device; M memory strings containing the M memory cells storing the same weight data are respectively coupled to different first sub-source layers; the semiconductor device includes multiple memory strings, each memory string including multiple memory cells connected in series between the bit line and the source layer; the source layer includes multiple first sub-source layers spaced along a first direction, the first direction being parallel to the direction of the bit line extension; M is an integer greater than 1, and N is an integer greater than 0.

[0161] Step S1602: Apply the corresponding input voltage to the bit line coupled to the storage cell where the weight data is written.

[0162] Step S1603: Obtain the calculation result based on the output current of the source layer.

[0163] In some embodiments, two storage units storing the same weight data are coupled to the same bit line.

[0164] In some embodiments, two storage units storing the same weight data are coupled to the same bit line.

[0165] In some embodiments, obtaining the calculation result based on the output current of the source layer includes: acquiring the output current signals of M first sub-source layers respectively coupled to M storage cells storing the same weight data, and performing analog-to-digital conversion on the voltage signals corresponding to the acquired current signals; shifting at least some of the results of the multiple analog-to-digital conversions according to a preset rule; and summing the shifted results corresponding to the multiple analog-to-digital conversions to obtain the calculation result.

[0166] In some embodiments, the method further includes: when writing N weight data into M*N storage units, one weight data is stored in the first bit-coupled M storage units and the second bit-coupled M storage units respectively; the data stored in the 2M storage units is used to form a differential data pair of weight data.

[0167] In some embodiments, the first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

[0168] In some embodiments, the storage unit has three bits; a weight data is stored in two storage units line-coupled at the first bit and two storage units line-coupled at the second bit; the data type of a weight data includes an eight-bit signed integer.

[0169] In some embodiments, applying a corresponding input voltage to the bit line coupled to the storage cell for writing weight data includes: sequentially applying a first input voltage to the first bit line and applying a second input voltage to the second bit line; the operation method further includes: applying a third input voltage to each of the M first sub-source layers coupled to the 2M storage cells; wherein the third input voltage is less than the first input voltage and greater than the second input voltage, and the voltage difference between the third input voltage and the first input voltage is equal to the voltage difference between the third input voltage and the second input voltage.

[0170] In some embodiments, the output currents of M first sub-source layers, which are respectively coupled to M storage cells storing the same weight data, are collected, and the voltage signals corresponding to the collected current signals are processed by analog-to-digital conversion. This includes: collecting the currents in two opposite directions output by each of the M first sub-source layers, which are respectively coupled to M storage cells, and processing the voltage signals corresponding to the collected current signals by analog-to-digital conversion.

[0171] In some embodiments, applying a corresponding input voltage to the bit line coupled to the storage cell for writing weight data includes: sequentially applying a first input voltage to the first bit line and applying a second input voltage to the second bit line; the operation method further includes: applying a third input voltage to each of the M first sub-source layers coupled to the 2M storage cells; wherein the first input voltage is equal to the second input voltage.

[0172] In some embodiments, the operation method further includes: performing differential processing on two current signals of the same direction output from each of the M first sub-source layers to which the 2M storage cells storing weight data are respectively coupled; acquiring the output current signals of the M first sub-source layers to which the M storage cells storing the same weight data are respectively coupled, and performing analog-to-digital conversion processing on the voltage signals corresponding to the acquired current signals, including: acquiring differential data pair signals after differential processing, and performing analog-to-digital conversion processing on the voltage signals corresponding to the differential data pair signals respectively.

[0173] In some embodiments, the source layer includes a plurality of second sub-source layers spaced apart along a second direction, and the M memory strings containing the M memory cells storing the same weighted data are all coupled to the same second sub-source layer, with the second direction being perpendicular to the direction in which the bit line extends.

[0174] In some embodiments, a second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

[0175] For details regarding the implementation of the operation method of semiconductor devices, please refer to the examples mentioned above. For the sake of brevity, these details will not be repeated here.

[0176] Based on the above-described operation method of the semiconductor device, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method described in any of the above embodiments.

[0177] Here, implementing all or part of the processes in the operation methods of the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0178] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0179] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A memory array; the memory array includes multiple memory strings, each memory string including multiple memory cells connected in series between a bit line and a source layer; the memory cells are configured to store weight data; The source layer includes multiple first sub-source layers spaced apart along a first direction. M storage strings containing M storage cells storing the same weight data are respectively coupled to different first sub-source layers. The first direction is parallel to the direction in which the bit line extends. M is an integer greater than 1.

2. The semiconductor device according to claim 1, characterized in that, The M storage units storing the same weight data are coupled to the same bit line.

3. The semiconductor device according to claim 2, characterized in that, Two storage units storing the same weight data are coupled to the same bit line.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor device also includes peripheral circuitry coupled to the memory array; The peripheral circuit is configured as follows: Write N weight data into M*N storage units; where N is an integer greater than 0. ； A corresponding input voltage is applied to the bit line coupled to the storage cell where the weight data is written; The calculation result is obtained based on the output current of the source layer of the semiconductor device.

5. The semiconductor device according to claim 4, characterized in that, The peripheral circuitry includes a sensing circuit, a shifting circuit, and a processing circuit; wherein... The sensing circuit is coupled to the first sub-source layer and configured to acquire the output current signals of the M first sub-source layers respectively coupled to the M storage units storing the same weight data, and perform analog-to-digital conversion on the voltage signals corresponding to the acquired current signals. The shifting circuit is coupled to the sensing circuit and configured to shift at least a portion of the results of multiple analog-to-digital conversions according to a preset rule. The arithmetic circuit is coupled to the shift circuit and configured to sum the shifted results corresponding to the results of the plurality of analog-to-digital conversions to obtain the arithmetic result.

6. The semiconductor device according to claim 5, characterized in that, The peripheral circuit is configured as follows: When writing N weight data into the M*N storage units, each weight data is stored in the first bit-coupled M storage units and the second bit-coupled M storage units respectively; the data stored in the 2M storage units are used to form the differential data pairs of the weight data.

7. The semiconductor device according to claim 6, characterized in that, The first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

8. The semiconductor device according to claim 6, characterized in that, The storage unit has three bits; one of the weighted data is stored in the two storage units that are line-coupled to the first bit and in the two storage units that are line-coupled to the second bit. The data type of one of the weight data includes an eight-bit signed integer.

9. The semiconductor device according to claim 6, characterized in that, The peripheral circuit is configured as follows: A first input voltage is applied to the first bit line, and a second input voltage is applied to the second bit line; A third input voltage is applied to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; Wherein, the third input voltage is less than the first input voltage and greater than the second input voltage, and the voltage difference between the third input voltage and the first input voltage is equal to the voltage difference between the third input voltage and the second input voltage.

10. The semiconductor device according to claim 9, characterized in that, The sensing circuit is specifically configured to acquire two opposite current signals output from each of the M first sub-source layers to which the 2M storage cells are respectively coupled, and to perform analog-to-digital conversion on the voltage signals corresponding to the acquired current signals.

11. The semiconductor device according to claim 6, characterized in that, The peripheral circuit is configured as follows: A first input voltage is applied to the first bit line, and a second input voltage is applied to the second bit line; A third input voltage is applied to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; Wherein, the first input voltage is equal to the second input voltage.

12. The semiconductor device according to claim 10, characterized in that, The peripheral circuit also includes: a differential circuit; The differential circuit is coupled to the first sub-source layer and configured to perform differential processing on the two currents of the same direction output by each of the M first sub-source layers to which the 2M storage cells storing weight data are respectively coupled. The sensing circuit is coupled to the differential circuit and configured to acquire differential data pairs after differential processing, and to perform analog-to-digital conversion processing on the voltage signals corresponding to the differential data pairs.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The source layer includes multiple second sub-source layers spaced along a second direction. The M storage strings containing the M storage cells storing the same weight data are all coupled to the same second sub-source layer. The second direction is perpendicular to the direction in which the bit line extends.

14. The semiconductor device according to claim 13, characterized in that, A second sub-source layer is coupled to a plurality of memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

15. The semiconductor device according to any one of claims 4 to 12, characterized in that, The semiconductor device includes a first semiconductor structure and a second semiconductor structure; The memory array is located in the first semiconductor structure, and the first semiconductor structure further includes a first bonding layer located on one side of the source layer; The peripheral circuit is located in the second semiconductor structure, and the second semiconductor structure further includes a second bonding layer located on one side of the peripheral circuit; The memory array is connected to the peripheral circuit via a hybrid bonding method using the first bonding layer and the second bonding layer.

16. The semiconductor device according to any one of claims 1 to 12, characterized in that, The semiconductor device includes a three-dimensional NAND flash memory.

17. A system, characterized in that, include: At least one semiconductor device as claimed in any one of claims 1 to 16; A controller, coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive computation results output by the semiconductor device.

18. A method of operating a semiconductor device, characterized in that, include: N weighted data are written into the M*N memory cells of the semiconductor device; M memory strings containing M memory cells storing the same weight data are respectively coupled to different first sub-source layers; the semiconductor device includes multiple memory strings, each memory string including multiple memory cells connected in series between the bit line and the source layer; the source layer includes multiple first sub-source layers spaced along a first direction, the first direction being parallel to the direction in which the bit line extends; M is an integer greater than 1, and N is an integer greater than 0; A corresponding input voltage is applied to the bit line coupled to the storage cell where the weight data is written; The calculation result is obtained based on the output current of the source layer.

19. The operating method according to claim 18, characterized in that, The M storage units storing the same weight data are coupled to the same bit line.

20. The operating method according to claim 19, characterized in that, Two storage units storing the same weight data are coupled to the same bit line.

21. The operating method according to claim 19, characterized in that, Based on the output current of the source layer, the calculation results are obtained, including: The output current signals of the M first sub-source layers, which are respectively coupled to the M storage units storing the same weighted data, are collected, and the voltage signals corresponding to the collected current signals are processed by analog-to-digital conversion. According to preset rules, at least some of the results of multiple analog-to-digital conversions are shifted. The results of the multiple analog-to-digital conversions are summed after shifting to obtain the calculation result.

22. The operating method according to claim 21, characterized in that, The method further includes: When writing N weight data into M*N storage units, each weight data is stored in the first bit-coupled M storage units and the second bit-coupled M storage units respectively; the data stored in the 2M storage units are used to form the differential data pairs of the weight data.

23. The operating method according to claim 22, characterized in that, The first bit line and the second bit line are two adjacent bit lines along a second direction, which is perpendicular to the direction in which the bit lines extend.

24. The operating method according to claim 22, characterized in that, The storage unit has three bits; one of the weighted data is stored in the two storage units that are line-coupled to the first bit and in the two storage units that are line-coupled to the second bit. The data type of one of the weight data includes an eight-bit signed integer.

25. The operating method according to claim 22, characterized in that, Applying a corresponding input voltage to the bit line coupled to the storage cell where the weighted data is written includes: A first input voltage is applied to the first bit line in sequence, and a second input voltage is applied to the second bit line in sequence; The method further includes: A third input voltage is applied to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; Wherein, the third input voltage is less than the first input voltage and greater than the second input voltage, and the voltage difference between the third input voltage and the first input voltage is equal to the voltage difference between the third input voltage and the second input voltage.

26. The operating method according to claim 25, characterized in that, The process of collecting the output current signals of the M storage units storing the same weight data, which are respectively coupled to the M first sub-source layers, and performing analog-to-digital conversion on the voltage signals corresponding to the collected current signals, includes: The system collects two current signals in opposite directions from each of the M first sub-source layers to which the 2M storage cells are respectively coupled, and performs analog-to-digital conversion on the voltage signals corresponding to the collected current signals.

27. The operating method according to claim 22, characterized in that, Applying a corresponding input voltage to the bit line coupled to the storage cell where the weighted data is written includes: A first input voltage is applied to the first bit line in sequence, and a second input voltage is applied to the second bit line in sequence; The method further includes: A third input voltage is applied to each of the M first sub-source layers to which the 2M memory cells are respectively coupled; Wherein, the first input voltage is equal to the second input voltage.

28. The operating method according to claim 27, characterized in that, The method further includes: The two signals output from each of the M first sub-source layers, to which the 2M storage units storing the weight data are respectively coupled, are processed differentially. The process of acquiring and storing the output current signals of the M first sub-source layers, which are respectively coupled to the M storage units storing the same weighted data, and performing analog-to-digital conversion on the voltage signals corresponding to the acquired current signals includes: The differential data pairs are acquired after differential processing, and the corresponding voltage signals are converted from analog to digital.

29. The operating method according to any one of claims 18 to 28, characterized in that, The source layer includes multiple second sub-source layers spaced along a second direction. The M memory strings containing the M memory cells storing the same weighted data are all coupled to the same second sub-source layer. The second direction is perpendicular to the direction in which the bit line extends.

30. The operating method according to claim 29, characterized in that, A second sub-source layer is coupled to a plurality of the memory strings, the number of bit lines coupled to the plurality of memory strings being related to the amount of input data; the input voltage applied to the bit lines is related to the data value of the input data.

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