Semiconductor device and operating method thereof, storage device, structure and electronic

Abstract

The embodiment of the invention provides a semiconductor device and an operation method thereof, a storage and calculation device, a structure and electronic equipment. The semiconductor device comprises a first semiconductor structure and a second semiconductor structure, the first semiconductor structure and the second semiconductor structure are in bonding connection; wherein the first semiconductor structure comprises an analog-to-digital conversion circuit and a data processing circuit; the second semiconductor structure includes a memory array for performing a first operation and at least a portion of a peripheral circuit coupled to the memory array. The analog-to-digital conversion circuit is configured to convert analog calculation information obtained by executing the first operation by the storage array into digital information; the data processing circuitry is configured to perform a second operation on the digital information.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor device and its operation method, a memory computing device, a structure, and an electronic device. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and its operation method, a memory computing device, a structure, and an electronic device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including: a first semiconductor structure and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are bonded together; wherein the first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; the second semiconductor structure includes a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array; the analog-to-digital conversion circuit is configured to convert analog computation information obtained by the memory array performing the first operation into digital information; and the data processing circuit is configured to perform a second operation on the digital information.

[0005] In some embodiments, the second semiconductor structure includes a first sub-semiconductor structure having a memory array and a second sub-semiconductor structure having at least some peripheral circuitry; the first sub-semiconductor structure includes a first bonding layer and a second bonding layer, the memory array is bonded to the second sub-semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

[0006] In some embodiments, the memory array is located between the first bonding layer and the second bonding layer; the second sub-semiconductor structure includes a third bonding layer, which is bonded to the first bonding layer; the first semiconductor structure includes a fourth bonding layer, which is bonded to the second bonding layer.

[0007] In some embodiments, the first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact, and the third bonding layer includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded, and the first dielectric layer and the third dielectric layer are bonded.

[0008] In some embodiments, the second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the fourth bonding layer includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

[0009] In some implementations, the analog-to-digital conversion circuit is connected to the memory array via a fourth bonding layer and a second bonding layer, and receives analog calculation information output by the memory array after performing a first operation via the fourth bonding layer and the second bonding layer.

[0010] In some embodiments, the first sub-semiconductor structure further includes a bit line; the second semiconductor structure further includes a first connection structure that extends through the memory array and is connected to the bit line and the second bonding layer; wherein the memory array is connected to the analog-to-digital converter circuit through the bit line, the first connection structure, the second bonding layer and the fourth bonding layer.

[0011] In some implementations, the memory array includes multiple memory strings, each containing a drain terminal and a source terminal; wherein the source terminal is connected to the analog-to-digital converter circuit via a second bonding layer and a fourth bonding layer.

[0012] In some embodiments, the first sub-semiconductor structure further includes a source layer with source terminals connected to the source layer; the source layer is located on the side of the memory array near the second bonding layer; the source layer includes a first isolation structure extending along the word line direction and a second isolation structure extending along the bit line direction, the first isolation structure and the second isolation structure dividing the source layer into multiple sub-source layers.

[0013] In some implementations, each of the multiple sub-source layers is connected to the analog-to-digital converter circuit via a second bonding layer and a fourth bonding layer.

[0014] In some embodiments, the second semiconductor structure further includes a second connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through a third bonding layer, a first bonding layer, and a second connection structure.

[0015] In some embodiments, the first semiconductor structure further includes: a switch control circuit, the switch control circuit including switch groups connected to each sub-source layer through a fourth bonding layer and a second bonding layer; each switch group includes a first switch and a second switch, one end of the first switch being connected to the sub-source layer and the other end being connected to the analog-to-digital conversion circuit; one end of the second switch being connected to the sub-source layer and the other end being connected to the second sub-semiconductor structure through the fourth bonding layer and the second bonding layer.

[0016] In some embodiments, the second semiconductor structure further includes a third connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through the third bonding layer, the first bonding layer, the third connection structure, the second bonding layer, the fourth bonding layer, and the second switch.

[0017] In some implementations, when the first switch is closed and the second switch is open, the sub-source layer, the second bonding layer, the fourth bonding layer, and the first switch constitute a signal transmission path between the source terminal and the analog-to-digital conversion circuit; when the first switch is open and the second switch is closed, the third connection structure, the second bonding layer, the fourth bonding layer, the second switch, and the sub-source layer constitute a signal transmission path between the second sub-semiconductor structure and the source terminal.

[0018] In some embodiments, the first semiconductor structure further includes a first interface circuit and a controller; the first interface circuit is configured to output the result of the second operation performed by the digital processing circuit to an external device, and the controller is used to control the second semiconductor structure to perform the first operation.

[0019] In some embodiments, the second semiconductor structure further includes a fourth connection structure that extends through the memory array; one end of the fourth connection structure is connected to the second sub-semiconductor structure, and the other end is connected to the first interface circuit through a fourth bonding layer and a second bonding layer.

[0020] In some embodiments, the second semiconductor structure further includes a second interface circuit; the second semiconductor structure is also connected to the first semiconductor structure via the second interface circuit.

[0021] In some implementations, when there are multiple second semiconductor structures, the memory array of each second semiconductor structure is located between the corresponding peripheral circuit and the first semiconductor structure.

[0022] In some implementations, the first operation includes a multiplication-accumulation operation.

[0023] In some implementations, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0024] In some implementations, the second semiconductor structure includes a three-dimensional NAND-type memory.

[0025] In a second aspect, embodiments of this disclosure provide a memory computing device, comprising: a first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit; and a second semiconductor structure including a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array; wherein the first semiconductor structure and the second semiconductor structure are bonded together, and the memory array is located between the at least a portion of the peripheral circuitry and the second semiconductor structure.

[0026] Thirdly, embodiments of this disclosure provide a semiconductor structure, including: a first sub-semiconductor structure and a second sub-semiconductor structure; the first sub-semiconductor structure includes a memory array for performing a first operation, and the second sub-semiconductor structure includes at least a portion of peripheral circuitry; the first sub-semiconductor structure includes a first bonding layer and a second bonding layer, the memory array is bonded to the second sub-semiconductor structure through the first bonding layer, the second bonding layer is located on the side of the memory array away from the second sub-semiconductor structure, and is used for the memory array to output analog calculation information after performing the first operation.

[0027] Fourthly, embodiments of this disclosure provide an operation method for a semiconductor device, the method comprising: performing a first operation through a memory array in a second semiconductor structure to obtain analog computation information, wherein the second semiconductor structure further includes at least a portion of peripheral circuitry coupled to the memory array; converting the analog computation information obtained by performing the first operation through an analog-to-digital converter circuit in a first semiconductor structure into digital information, wherein the first semiconductor structure and the second semiconductor structure are bonded together; and performing a second operation on the digital information through a data processing circuit in the first semiconductor structure.

[0028] In some implementations, the first operation includes a multiplication-accumulation operation.

[0029] In some implementations, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0030] In some embodiments, the second semiconductor structure further includes a source layer coupled to the source end of the memory array, the source layer being divided into multiple sub-source layers, and the first semiconductor structure further includes: a switch control circuit, the switch control circuit including a switch group connected to each sub-source layer; each switch group includes a first switch and a second switch, the first switch electrically controlling signal transmission between the sub-source layer and the analog-to-digital conversion circuit, and the second switch electrically controlling signal transmission between the sub-source layer and at least a portion of the peripheral circuitry; the method further includes: in response to an execution command of a first operation, controlling the first switch to close to output analog calculation information to the analog-to-digital conversion circuit.

[0031] In some implementations, the method further includes: controlling a second switch to close in response to an erase command, a programming command, or a read command to output a control voltage to the sub-source layer.

[0032] Fifthly, embodiments of this disclosure provide a packaging structure, including: a packaging substrate, a semiconductor device of any one of the first aspects or a memory computing device of the second aspect, and a molding compound; the semiconductor device or memory computing device is disposed on the packaging substrate; and the molding compound encapsulates the semiconductor device or memory computing device.

[0033] In a sixth aspect, embodiments of this disclosure provide an electronic device, including: a semiconductor device according to any one of the first aspects or a memory computing device according to the second aspect.

[0034] This disclosure provides a semiconductor device and its operating method, in-memory computing device, structure, and electronic device. The semiconductor device includes a first semiconductor structure and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are bonded together; wherein the first semiconductor structure includes an analog-to-digital converter circuit and a data processing circuit; the second semiconductor structure includes a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array; the analog-to-digital converter circuit is configured to convert analog computation information obtained by the memory array performing the first operation into digital information; the data processing circuit is configured to perform a second operation on the digital information. In this disclosure, the first semiconductor structure and the second semiconductor structure are in different planes and stacked on top of each other. This reduces the planar size of the semiconductor device. Attached Figure Description

[0035] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 1 .

[0036] Figure 2 This is a schematic diagram of the structure of a second semiconductor structure provided in an embodiment of the present disclosure.

[0037] Figure 3 This is a schematic diagram showing the distribution of memory cells in a second semiconductor structure provided in an embodiment of the present disclosure.

[0038] Figure 4 A schematic diagram of an exemplary second semiconductor structure including peripheral circuitry provided for embodiments of this disclosure.

[0039] Figure 5 This is a cross-sectional schematic diagram of a storage array including storage strings, provided as an embodiment of the present disclosure.

[0040] Figure 6 A schematic diagram of a second semiconductor structure including peripheral circuitry and a memory array provided in an embodiment of this disclosure. Figure 1 .

[0041] Figure 7 A schematic diagram of a second semiconductor structure including peripheral circuitry and a memory array provided in an embodiment of this disclosure. Figure 2 .

[0042] Figure 8 This is a schematic diagram of input voltage being input to the memory block via a top selection line, provided as an embodiment of this disclosure.

[0043] Figure 9This is a schematic diagram of a string of multiple memory cells coupled to a bit line, provided in an embodiment of this disclosure.

[0044] Figure 10 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 .

[0045] Figure 11 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 3 .

[0046] Figure 12A A top view of a first sub-semiconductor structure including a memory array provided in an embodiment of this disclosure. Figure 1 .

[0047] Figure 12B A top view of a first sub-semiconductor structure including a memory array provided in an embodiment of this disclosure. Figure 2 .

[0048] Figure 13A A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 4 .

[0049] Figure 13B A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 5 .

[0050] Figure 14A A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 6 .

[0051] Figure 14B A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 7 .

[0052] Figure 14C A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 8 .

[0053] Figure 15 This is a schematic flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0054] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0061] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0062] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will provide a detailed introduction to NAND flash memory.

[0063] This disclosure provides a semiconductor device, Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 1 , refer to Figure 1 The semiconductor device includes a first semiconductor structure 200 and a second semiconductor structure 300; the first semiconductor structure 200 and the second semiconductor structure 300 are bonded together; wherein, the first semiconductor structure 200 includes an analog-to-digital converter circuit and a data processing circuit; the second semiconductor structure 300 includes a memory array 301 for performing a first operation and at least a portion of peripheral circuitry 302 coupled to the memory array 301; the analog-to-digital converter circuit is configured to convert analog computation information obtained by the memory array 301 performing the first operation into digital information; the data processing circuit is configured to perform a second operation on the digital information.

[0064] In some embodiments, the first semiconductor structure 200 and the second semiconductor structure 300 are in different planes and stacked on top of each other. Furthermore, the memory array 301 and the peripheral circuitry 302 in the second semiconductor structure 300 can be in different planes and stacked on top of each other, thereby reducing the planar size of the semiconductor device.

[0065] In some embodiments, a first semiconductor structure 200 and a second semiconductor structure 300 may be formed in parallel on different substrates. For example, the first semiconductor structure 200 may be formed on a first substrate, a memory array 301 may be formed on a second substrate, and a peripheral circuit 302 may be formed on a third substrate. They may then be stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0066] In this embodiment of the disclosure, by vertically integrating the first semiconductor structure 200 and the second semiconductor structure 300, and vertically separating the first semiconductor structure 200, the memory array 301 and the peripheral circuit 302 into different planes, the chip size can be reduced and the storage density can be increased.

[0067] In embodiments of this disclosure, the second semiconductor structure 300 includes a first sub-semiconductor structure on which a memory array 301 is formed and a second sub-semiconductor structure on which at least a portion of peripheral circuitry 302 is formed. In some embodiments, a portion of the peripheral circuitry is formed in the second sub-semiconductor structure, and another portion is formed in the first sub-semiconductor structure. In other words, the peripheral circuitry of the memory array can be divided into two parts, one part of which is formed together with the memory array in the first sub-semiconductor structure, and the other part of which is formed in the second sub-semiconductor structure. In other embodiments, the peripheral circuitry can be entirely formed in the second sub-semiconductor structure.

[0068] Figure 2 A schematic diagram of a second semiconductor structure is provided as an example. Here, a three-dimensional NAND flash memory is used as an example for illustration. Figure 2 As shown, the memory array may include multiple memory planes, such as Plane 0, Plane 1, Plane 2, and Plane 3 (four memory planes in total). Each memory plane includes multiple memory banks, and each memory bank includes multiple memory blocks. In some embodiments, a portion of the peripheral circuitry is formed in a second sub-semiconductor structure, while another portion is formed in a first sub-semiconductor structure. In other words, the first sub-semiconductor structure may include the memory array and a portion of the peripheral circuitry. Exemplarily, in embodiments of this disclosure, a page buffer, for example, in the peripheral circuitry may be formed in the first sub-semiconductor structure.

[0069] In other embodiments, the peripheral circuitry may be entirely formed within the second sub-semiconductor structure. It should be noted that this disclosure uses the example of the peripheral circuitry being entirely formed within the second sub-semiconductor structure for illustration.

[0070] Figure 3 An exemplary schematic diagram of the distribution of memory cells in a second semiconductor structure is provided. For example... Figure 3As shown, the memory array consists of several rows of parallel, staggered memory cells parallel to the gate isolation structure (GLS). Every four rows of memory cells are separated by a gate isolation structure and a select gate isolation structure. Each memory cell row includes multiple memory strings arranged along the X-direction. The figure shows one memory cell in each memory string, with the remaining memory cells stacked with that cell along the Z-direction. The select gate isolation structure can be a top select gate isolation structure (TSG CUT), which divides the top select gate (TSG) into multiple top select lines. Alternatively, it can be a bottom select gate isolation structure (BSG CUT), which divides the bottom select gate (BSG) into multiple bottom select lines. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks, and multiple second gate isolation structures can divide the memory blocks into multiple finger regions. A select gate isolation structure placed in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two memory chips. Figure 3 The storage block shown contains 6 storage pieces. In practical applications, the number of storage pieces in a storage block is not limited to this. Figure 3 Only one storage block of the memory is shown as an example, but the memory includes multiple such blocks. Figure 3 The memory blocks shown are separated by a first gate isolation structure, and multiple memory blocks can be arranged along the Y direction.

[0071] It should be noted that, Figure 3 The number of cell rows between the gate isolation structure and the selected gate isolation structure given is merely an example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0072] Figure 4This is a schematic diagram of an exemplary second semiconductor structure including peripheral circuitry provided for embodiments of the present disclosure. The second semiconductor structure 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 306 are NAND memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically. In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0073] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0074] like Figure 4As shown, each memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The bottom select gate 310 and top select gate 312 can be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the source ends of memory strings 308 within the same memory block 304 can be coupled via a common source line (CSL) 314. In other words, all memory strings 308 within the same memory block 304 have a common source (ACS). According to some embodiments, the top select gate 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 312 via one or more top select lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 310 via one or more bottom select lines (BSL) 315.

[0075] like Figure 4 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0076] Figure 5 A schematic cross-sectional view of an exemplary storage array including storage string 308 is shown, according to some aspects of this disclosure. Figure 5As shown, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0077] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select line, and the gate layer 411 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0078] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0079] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0080] Return to reference Figure 4 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSL315, and TSL313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSL315, and TSL313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0081] Figure 6 A schematic diagram of a second semiconductor structure including peripheral circuitry and a memory array provided for embodiments of this disclosure. Figure 1 Combined with reference Figure 4 and Figure 6 The peripheral circuitry 302 may include control logic 512, a digital-to-analog converter 501 coupled to the control logic 512 and the memory array 301, and an analog-to-digital converter 502 coupled to the memory array 301 and the control logic 512. When performing the first operation using the second semiconductor structure, the digital-to-analog converter 501 can convert the digital signal into a voltage signal required by the memory array 301 in the second semiconductor structure. The analog-to-digital converter 502 can convert the current signal output by the memory array 301 into a digital signal. The control logic 512 may be coupled to the peripheral circuitry and configured to control the operation of the peripheral circuitry. The control logic 512 can also be used to receive input data sent by external devices. Here, the digital-to-analog converter 501 is a one-bit digital-to-analog converter (DAC), and the analog-to-digital converter 502 is a one-bit digital-to-analog converter (DAC).

[0082] Figure 7 A schematic diagram of the composition of an exemplary second semiconductor structure including a memory array and peripheral circuitry provided for embodiments of this disclosure. Figure 2 ,remove Figure 6 In addition to the circuit structure shown, the peripheral circuitry 302 may also include a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a register 514, and a data bus 518. It should be understood that in some examples, it may also include... Figure 6 as well as Figure 7 Additional peripheral circuitry not shown.

[0083] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0084] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cell 306 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0085] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc., input voltage), bit line voltages, and source line voltages to be supplied to memory array 301.

[0086] Return to reference Figure 1 In this embodiment of the disclosure, the first sub-semiconductor structure includes a first bonding layer 101 and a second bonding layer 102. The memory array 301 is bonded to the second sub-semiconductor structure through the first bonding layer 101, and the memory array 301 is bonded to the first semiconductor structure 200 through the second bonding layer 102.

[0087] In some embodiments, the first semiconductor structure 200 and the second semiconductor structure 300 can be vertically connected by bonding. This bonding connection includes hybrid bonding connections (also known as "metal / dielectric hybrid bonding connections"), a direct bonding technique, such as forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive, and simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding. It should be noted that the term "bonding" as used in this disclosure can refer to any suitable bonding technique, such as the hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding mentioned above.

[0088] In this embodiment of the present disclosure, the memory array 301 is located between the first bonding layer 101 and the second bonding layer 102; the second sub-semiconductor structure includes a third bonding layer 103, which is bonded to the first bonding layer 101; the first semiconductor structure 200 includes a fourth bonding layer 104, which is bonded to the second bonding layer 102.

[0089] In some embodiments, the first semiconductor structure 200 and the peripheral circuit 302 are located on opposite sides of the memory array 301. That is, the memory array 301 is vertically located between the first semiconductor structure 200 and the peripheral circuit 302.

[0090] In some embodiments, the semiconductor device may further include a first bonding interface between the third bonding layer 103 and the first bonding layer 101, and a second bonding interface between the fourth bonding layer 104 and the second bonding layer 102. Data transfer between the first sub-semiconductor structure and the second sub-semiconductor structure can be achieved through interconnects (e.g., bonding contacts) across the first bonding interface. Data transfer between the first semiconductor structure and the second semiconductor structure can be achieved through interconnects (e.g., bonding contacts) across the second bonding interface.

[0091] In some embodiments, a first interconnect layer (not shown) may be further included between the memory array 301 and the first bonding layer 101, and a second interconnect layer (not shown) may be further included between the peripheral circuitry 302 and the third bonding layer 103. The first and second interconnect layers may include multiple interconnect structures, such as lateral lines and vias, which may be formed in one or more interlayer dielectric (ILD) layers. The interconnect structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0092] In this embodiment of the present disclosure, the first bonding layer 101 includes a first bonding contact and a first dielectric layer that isolates the first bonding contact, and the third bonding layer 103 includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded, and the first dielectric layer and the third dielectric layer are bonded.

[0093] In this embodiment of the present disclosure, the second bonding layer 102 includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the fourth bonding layer 104 includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

[0094] In some embodiments, the bonding contacts may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In a specific example, the bonding contacts of the bonding layer include Cu. The remaining area of ​​the bonding layer may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts in the bonding layer and the surrounding dielectric can be used for hybrid bonding, simultaneously achieving metal-to-metal bonding and dielectric-to-dielectric bonding.

[0095] In this embodiment of the present disclosure, the analog-to-digital conversion circuit is connected to the memory array 301 through the fourth bonding layer 104 and the second bonding layer 102, and receives the analog calculation information output by the memory array 301 after performing the first operation via the fourth bonding layer 104 and the second bonding layer 102.

[0096] Combination Figure 1 , Figure 6 and Figure 7 When performing the first operation using the second semiconductor structure, control logic 512 can receive input data sent by an external device (e.g., a host). The digital-to-analog converter 501 in peripheral circuit 302 converts the input data into a voltage signal to be applied to the word line or bit line. Voltage generator 510 generates the corresponding voltage to be applied to the word line or bit line. Row decoder / word line driver 508 is configured to drive the selected word line using the word line voltage generated by voltage generator 510, or column decoder / bit line driver 506 is configured to drive the selected bit line using the bit line voltage generated by voltage generator 510. The analog calculation information obtained after performing the first operation is transmitted to the analog-to-digital converter circuit through the fourth bonding layer 104 and the second bonding layer 102. The analog-to-digital converter circuit converts the analog calculation information into digital information and transmits the final digital information to the data processing circuit, which then performs the second operation on the digital information.

[0097] In some embodiments, for in-memory computing chips, it is necessary to perform the first operation between input data and weight matrix. The input data can be an input vector or input matrix composed of multiple elements, and the weight matrix is ​​composed of multiple weights. Each element in the input data needs to be multiplied and added with the multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0098] To achieve the aforementioned computational functions, the storage array 301 can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the storage array 301 according to a certain mapping rule, and each storage cell 306 in the storage array 301 can be configured to store one weight. During the computation phase, the second semiconductor structure can receive input data from an external device. The input data can be an input vector or an input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by the digital-to-analog converter circuit 501 and input to the storage array 301 via the bit line 316 or the word line 318.

[0099] In this embodiment of the disclosure, analog computation information can be output via bit lines or via the source terminal. That is, the bit lines in the second semiconductor structure are analog information output terminals, or the source terminal is an analog information output terminal.

[0100] In this embodiment, by placing the analog-to-digital conversion circuit in the first semiconductor structure, when the source terminal is the analog information output terminal, the voltage / current signal output from the source terminal enters the analog-to-digital conversion circuit through the hybrid bonding channel (the second bonding layer and the fourth bonding layer) for analog-to-digital conversion. Thus, there is no need for the analog calculation information to be digitized (analog-to-digital conversion) in the peripheral circuit, and therefore no need for the compression module to compress the digitized result. This greatly reduces the frequency requirement for interface data transmission.

[0101] The following example, using the bit line as the analog signal output terminal, illustrates the specific process of the first operation.

[0102] In some specific examples, Figure 8 This is a schematic diagram illustrating the input voltage to the memory block via the top selection line, as provided in an embodiment of this disclosure. Figure 9 This is a schematic diagram of a string of multiple memory cells coupled to a bit line, provided in an embodiment of this disclosure. It should be noted that... Figure 8 and Figure 9 The number of bit lines, the number of memory cell strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this disclosure does not limit the specific number of each structure.

[0103] like Figure 8As shown, the input voltage corresponding to an element in the input data can be input via multiple top select lines. During the first operation phase using the memory array, the peripheral circuitry is configured to apply a first read voltage V to the target word line WLn coupled to the target memory block. rd Appropriate input voltages are applied to the multiple top select lines coupled to the target memory block. For example, input voltages V can be applied to the top select lines TSL0, TSL1, and TSL2 coupled to the target memory block. in0 V in1 V in2 A first on-state voltage is applied to a non-target word line coupled to the target memory block. For example, a first on-state voltage V can be applied to word line WLn+1. pass1 A second on-state voltage is applied to the bottom select line coupled to the target memory block; for example, a second on-state voltage V can be applied to the bottom select line BSL. pass2 Analog calculation information can be obtained by sensing the current on the bit line coupled to the target memory block. For example, by sensing the current I0 on bit line BL0 and converting the current I0, information related to the input voltage V can be obtained. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of these three products. In some embodiments, the first operation includes a multiplication-accumulation operation.

[0104] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to a target word line coupled to a target memory block to program the memory cell coupled to the target word line before performing a first operation using the memory array.

[0105] In a specific example, a memory cell in the target memory block is configured to store one bit of data. Multiple memory cells in the target memory block have a first memory state and a second memory state. The threshold voltage of a memory cell having the first memory state is less than the threshold voltage of a memory cell having the second memory state. The first read voltage V... rdThe threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the first operation, writing weights to the memory cell according to a certain mapping rule. For a single-level cell, the weight writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the memory cells coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0106] In some embodiments, such as Figure 9 As shown, taking a target memory block comprising a string of eight memory cells coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five "1"s and three "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage to be applied to the top select line by a voltage generator. The input voltage is then transmitted to the top select line by a driver coupled to the top select line. Specifically, the eight input voltages can be applied to the eight top select lines simultaneously. Among them, the input voltage corresponding to "1" includes V in0 V in1 V in4 V in5 and V in6 This allows the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. in2 V in3 V in7 This can turn off the top select transistors TSG2, TSG3, and TSG7, which are coupled to the top select lines TSL2, TSL3, and TSL7, respectively.

[0107] In a specific example, such as Figure 9As shown, the current I0 on bit line BL0 is the sum of the output currents of the eight memory cell strings coupled to bit line BL0. The input voltage on the top select line coupled to memory cell strings Str0, Str4, and Str5 causes the top select transistors TSG0, TSG4, and TSG5 to be in the on state. The memory cells in memory cell strings Str0, Str4, and Str5 coupled to the target word line WLn have a first memory state (erasure state E). Therefore, memory cell strings Str0, Str4, and Str5 are turned on and can generate a current greater than or equal to a preset current. The current I0 on bit line BL0 is approximately equal to the sum of the output currents of memory cell strings Str0, Str4, and Str5. The multiple of current I0 relative to the current generated by any memory cell string in memory cell strings Str0, Str4, and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory cell strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0108] Based on the specific example above, when the number of memory cell strings coupled to bit line BLx in the target memory block is Y+1, the Y+1 elements corresponding to the input voltage input by the Y+1 first selection lines are α0, α1...α... Y The Y+1 memory cells coupled to the target word line WLn store weights w0, w1, ..., w1, respectively. Y Then, the analog calculation information equivalent to the current on bit line BLx relative to the multiple of the output current greater than or equal to the preset current can be α. 0* w0+α 1* w1+……+α Y* w Y .

[0109] In this embodiment of the present disclosure, when multiple memory banks are required to perform a first operation, a first conduction voltage can be applied to the non-target word lines in the multiple memory banks simultaneously. As a result, the voltage establishment phases of the first conduction voltage applied to the non-selection word lines coupled to different memory banks can overlap. Compared with the method of applying the first conduction voltage to the non-selection word lines coupled to different memory banks separately in different operation phases, the overall operation time can be shortened and the operation efficiency of performing the first operation using multiple memory banks can be improved.

[0110] Furthermore, for each memory bank, multiple memory blocks within that bank can be used simultaneously for the first operation. The peripheral circuitry can be configured to: apply a first read voltage to the target word lines coupled to each of the multiple memory blocks in the bank; apply corresponding input voltages to the multiple first select lines coupled to each of the multiple memory blocks in the bank; and sense the current on the bit lines coupled to the multiple memory blocks in the bank. Specifically, a first read voltage Vrd can be applied simultaneously to the target word lines coupled to each of the multiple memory blocks Block0 to BlockN in Bank0, and corresponding input voltages Vin can be applied to the multiple first select lines coupled to each of the multiple memory blocks Block0 to BlockN. The current on the bit lines is the analog calculation information after all memory cell strings coupled to that bit line have performed the first operation. Thus, multiple memory blocks can perform the first operation in parallel, thereby further improving the computational efficiency and power of the semiconductor device.

[0111] Figure 10 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 2 , refer to Figure 10 The first semiconductor structure 200 includes an analog-to-digital converter circuit 210 and a data processing circuit 220. It should be noted that... Figure 10 The following explanation uses the bit line as an analog signal output terminal as an example.

[0112] In this embodiment, the second semiconductor structure 300 further includes a first connection structure 320 that penetrates the memory array 301 and connects to the bit line and the second bonding layer; wherein the memory array 301 is connected to the analog-to-digital converter circuit 210 through the bit line, the first connection structure 320, the second bonding layer, and the fourth bonding layer. In a specific example, the first connection structure 320 is a through array contact (TAC). In some embodiments, one end of the first connection structure 320 is connected to the bit line, and the other end is connected to the second bonding layer. Thus, the bit line can be connected to the analog-to-digital converter circuit 210 through the first connection structure 320, the second bonding layer, and the fourth bonding layer, thereby transmitting analog computation information to the analog-to-digital converter circuit 210.

[0113] In this embodiment, the first semiconductor structure 200 further includes a first interface circuit 230 and a controller 240. The first interface circuit 230 is configured to receive and transmit data between the semiconductor device and other external devices. Specifically, the first interface circuit 230 is configured to output the result of a second operation performed by the digital processing circuit 220 to the external device. The controller 240 can be configured to control the operation of the first semiconductor structure 200 and the second semiconductor structure 300. That is, the controller 240 can act as a memory controller managing data storage and transmission in the second semiconductor structure 300 and an operation controller managing data processing and transmission in the first semiconductor structure 200. In some embodiments, the controller 240 is also configured to control data transmission between the first semiconductor structure 200 and the second semiconductor structure 300. In some embodiments, the controller 240 is also configured to receive input data sent by an external device and send the input data to the second semiconductor structure 300.

[0114] In some embodiments, the controller 240 is coupled to the second semiconductor structure 300 and an external device (e.g., a host device). It is configured to control the second semiconductor structure 300. The controller 240 can manage data stored in the second semiconductor structure 300 and communicate with the external device.

[0115] In some embodiments, the controller 240 may also be configured to manage various functions relating to data stored or to be stored in the second semiconductor structure 300, wherein these functions include, but are not limited to, bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the controller 240 is also configured to process error correction codes (ECCs) relating to data read from or written to the second semiconductor structure. In some embodiments, the controller 240 may also perform any other suitable functions, such as formatting the second semiconductor structure.

[0116] In some embodiments, the first interface circuit 230 may be configured in the controller 240, and an interface protocol may be used as the first interface circuit between the controller 240 and an external device. Thus, the controller 240 can communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc. The first interface circuit 230 here may also be referred to as a front-end interface. In some embodiments, the controller 240 interacts with the second semiconductor structure 300 via multiple configured channels for command / data exchange. These channels are also referred to as back-end interfaces.

[0117] In this embodiment, the second semiconductor structure 300 further includes a fourth connection structure 330 penetrating the memory array 301; one end of the fourth connection structure 330 is connected to the second sub-semiconductor structure, and the other end is connected to the first interface circuit 230 through the fourth bonding layer 104 and the second bonding layer 102. Thus, the peripheral circuit 302 in the second semiconductor structure can be connected to the first interface circuit 230 through the fourth connection structure 330, and can transmit data with other external devices through the first interface circuit 230.

[0118] It should be noted that, Figure 10 The dashed arrows in the diagram represent the fourth connection structure 330, and the number of such dashed arrows is merely an example and not intended to limit this disclosure. It should also be noted that the bonding layers (second bonding layer 102 and fourth bonding layer 104) between the first semiconductor structure 200 and the memory array 301 further include interconnect structures coupled to the fourth connection structure 330, thereby allowing the fourth connection structure 330 to be connected to the first interface circuit 230 via the second bonding layer 102 and the fourth bonding layer 104.

[0119] In this embodiment of the disclosure, combined with Figure 7 and Figure 10The second semiconductor structure also includes a second interface circuit 516. Specifically, the second sub-semiconductor structure further includes the second interface circuit 516; the second semiconductor structure is also connected to the first semiconductor structure via the second interface circuit. That is, the second interface circuit 516 here is the interface coupled to the back-end interface of the aforementioned controller, that is, the second interface circuit 516 can also be the interface for communication between the second semiconductor structure and the first semiconductor structure. The second interface circuit 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay it to the host. The second interface circuit 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 301.

[0120] In some embodiments, the data processing circuit 220 in the first semiconductor structure 200 includes a processor, which may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), visual processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the data processing circuit is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations.

[0121] In embodiments of this disclosure, the second operation includes multiple or one of compensation, activation, shift, or pooling operations. In a specific example, a second semiconductor structure in the semiconductor device is configured to store a weight matrix to perform multiplication-accumulation operations and output analog computation information; a first semiconductor structure in the semiconductor device is configured to convert the analog computation information output by the second semiconductor structure into digital information, and to perform activation operations on the digital information to generate an output result. In some embodiments, the activation operation can be implemented using activation functions stored in the NPU, which may include, but are not limited to, step functions, correction functions, sigmoid functions, hyperbolic tangent (tanh) functions, and softplus functions (also known as smoothing correction).

[0122] Figure 11 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 3 It should be noted that, Figure 11 The explanation will be based on the example of the source terminal being the analog signal output terminal.

[0123] Reference Figure 11The source terminal is connected to the analog-to-digital converter circuit 210 through the second bonding layer and the fourth bonding layer. Thus, when the source terminal is the analog information output terminal of the storage array 301, the analog calculation information can be transmitted to the analog-to-digital converter circuit 210 through the second bonding layer 102 and the fourth bonding layer 104.

[0124] Figure 12A A top view of a first sub-semiconductor structure including a memory array provided in an embodiment of this disclosure. Figure 1 , refer to Figure 12A GLS and TSGCUT divide storage blocks into multiple storage slices (e.g., 6 slices). Figure 12A The diagram shows two strings, String1 and String2, each coupled to a different TSG. As shown in Figure 12, bit lines BL are coupled to channel structures CH, where adjacent storage cells in a row of channel structures along the bit line extension direction are coupled to different bit lines BL. Source layer ( Figure 12A (Not shown in the image) Interconnected in units of memory blocks. It is understandable that without partitioning the source layer (common source), regardless of the size of the input data, the entire memory block will be occupied due to the interconnection of the source layer, and bit lines BL and memory cells not used for data input will be wasted. In other words, due to the interconnection of the source layer, parallelism is extremely low, especially with significant waste of small-scale weighted data.

[0125] In this embodiment, the first sub-semiconductor structure further includes a source layer 340, with source terminals connected to the source layer 340. The source layer 340 is located on the side of the memory array 301 near the second bonding layer 102. The source layer 340 includes a first isolation structure extending along the word line direction and a second isolation structure extending along the bit line direction, the first and second isolation structures dividing the source layer into multiple sub-source layers. The source layer may include one or more layers. For example, the source layer includes a conductive layer and a semiconductor layer. In some examples, the material of the source layer is a semiconductor material, including but not limited to intrinsic polysilicon, doped polysilicon (e.g., N-type doped silicon, P-type doped silicon), etc. In some embodiments, the source layer can be used to form a common source. That is, multiple memory strings in the same memory block are coupled together.

[0126] Here and below, the first direction is the same as the direction of bit line extension; the second direction is perpendicular to the direction of bit line extension and parallel to the direction of word line extension; the third direction is perpendicular to both the first and second directions, and the direction of storage string extension can be parallel to the third direction.

[0127] Figure 12B A top view of a first sub-semiconductor structure including a memory array provided in an embodiment of this disclosure. Figure 2 , refer to Figure 12B The source layer includes multiple first sub-source layers spaced along a first direction and multiple second sub-source layers spaced along a second direction. The source layer is divided into multiple first sub-source layers by a first isolation structure SLCUT1 extending along the second direction. The first isolation structure may penetrate the source layer along a third direction. The source layer is divided into multiple second sub-source layers by a second isolation structure SLCUT2 extending along the first direction. The second isolation structure may penetrate the source layer along a third direction.

[0128] In some embodiments, during the first operation phase, before the first operation begins, weight data is written into the corresponding storage cells of the storage array according to a certain mapping rule, and the M storage strings containing the M storage cells storing the same weight data are respectively coupled to different first sub-source layers, where M is an integer greater than 1. In other words, in this embodiment of the present disclosure, the same weight data is stored together using at least two storage cells; wherein, different storage cells in the at least two storage cells are used to store different data bits of the same weight data, so the number of bits of weight data is not limited by the number of bits of storage cells, thereby this embodiment of the present disclosure can provide storage of more bits of weight data, thereby improving parallelism.

[0129] Understandably, in some embodiments, the source layer is divided into multiple first sub-source layers. This separation of multiple first sub-source layers facilitates the execution of different subsequent operations on the output data of different first sub-source layers, such as performing different shift operations, followed by summing the shifted data. The separation of multiple first sub-source layers also allows different storage units among the M storage units used to store the same weight data to store different data bits of the same weight data.

[0130] In some embodiments, M can be determined based on the data type of the weight data and the number of bits in the storage unit. For example, if the weight data is a six-bit positive integer, then M can be 2 for TLC; if the weight data is a nine-bit positive integer, then M can be 3 for TLC; if the weight data is a sixteen-bit positive integer, then M can be 4 for QLC.

[0131] In some embodiments, the M storage strings containing the M storage units storing the same weight data are all coupled to the same second sub-source layer. It should be noted that each second sub-source layer is also divided into multiple parts by the first isolation structure SLCUT1.

[0132] In some embodiments, the segmentation of the source layer along the first direction is related to the amount of input data, i.e., related to the amount of computation performed each time. For example, if the size of the input data is 32, the source layer can be segmented every 32 bit lines; if the size of the input data is 64, the source layer can be segmented every 64 bit lines.

[0133] It is understood that in some embodiments, the source layer can be adaptively divided along the first direction according to the specifications of the input data, thereby avoiding the waste of bit lines and storage units that are not used for data input, and thus improving the parallelism of the source layer output.

[0134] In this embodiment of the present disclosure, each of the plurality of sub-source layers is connected to the analog-to-digital converter circuit 210 through the second bonding layer 102 and the fourth bonding layer 104.

[0135] In some embodiments, when the source layer (common source) is not divided, all memory strings in the same memory block are coupled through the source layer, and the analog computation information output by the source layer is the analog computation information corresponding to that memory block. Dividing the source layer into multiple sub-source layers is equivalent to dividing the common source of the memory block into smaller blocks. Then, when the source end is the analog information output end of the memory array, the analog computation information can be output in partitions through each sub-source layer. That is, each sub-source layer of the same memory block outputs one piece of analog computation information, and the multiple pieces of analog computation information output by multiple sub-source layers of the same memory block together constitute the analog computation information of that memory block.

[0136] In this embodiment, the second semiconductor structure 300 further includes a second connection structure 350 that penetrates the memory array 301 and connects to the sub-source layer 340; at least a portion of the peripheral circuitry 302 is connected to the sub-source layer via the third bonding layer 103, the first bonding layer 101, and the second connection structure 350. In a specific example, the second connection structure 350 is a TAC (Transient Acoustic Coupling). In some embodiments, one end of the second connection structure 350 is connected to the source terminal via the sub-source layer, and the other end is connected to the first bonding layer 101. Thus, the peripheral circuitry 302 can be connected to the source terminal via the third bonding layer 103, the first bonding layer 101, the second connection structure 350, and the sub-source layer.

[0137] In some embodiments, each sub-source layer is connected to a second connection structure, which connects the corresponding sub-source layer to peripheral circuitry. Thus, when the peripheral circuitry receives an erase command, a programming command, or a read command, it can output the corresponding control voltage to the sub-source layer via the second connection structure. In a specific example, the peripheral circuitry receives a programming command from the controller via a second interface circuit, and in response, sends control signals to at least the row decoder / word line driver, the column decoder / bit line driver, and the voltage generator to initiate a programming operation on the selected memory cell.

[0138] Figure 13A A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 4 , Figure 13BA schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 5 It should be noted that, Figure 13A and Figure 13B The explanation will be based on the example of the source terminal being the analog signal output terminal.

[0139] Reference Figure 13A The first semiconductor structure 200 further includes a switch control circuit, which includes a switch group 250 connected to the sub-source layer through a fourth bonding layer and a second bonding layer; the switch group 250 includes a first switch 251 and a second switch 252, one end of the first switch 251 is connected to the sub-source layer and the other end is connected to the analog-to-digital conversion circuit 210; one end of the second switch 252 is connected to the sub-source layer and the other end is connected to the second sub-semiconductor structure through the fourth bonding layer and the second bonding layer.

[0140] In this embodiment of the disclosure, the second semiconductor structure 300 further includes a third connection structure 360 ​​that penetrates the memory array 301 and is connected to the sub-source layer; at least a portion of the peripheral circuitry 302 is connected to the sub-source layer through the third bonding layer, the first bonding layer, the third connection structure 360, the second bonding layer, the fourth bonding layer, and the second switch 252.

[0141] In some embodiments, under an in-memory computing architecture, since the semiconductor device simultaneously possesses storage and computing functions, when the source terminal is the analog information output terminal of the storage array, the source layer must be connected to both the peripheral circuit to achieve the storage function and the analog-to-digital converter circuit to achieve the computing function. Furthermore, since the source layer is located on the side of the storage array furthest from the peripheral circuit, a large number of connection structures (e.g., TACs) are required to connect multiple sub-source layers to the peripheral circuits respectively. Based on this, embodiments of this disclosure provide a switch group connected to each sub-source layer in the first semiconductor structure. The switch group controls whether the corresponding sub-source layer is connected to the analog-to-digital converter circuit or to the peripheral circuit, thereby reducing the number of connection structures.

[0142] In some embodiments, the second switch 252 is connected to the peripheral circuit 302 by providing a third connection structure 360. In some embodiments, the third connection structure 360 ​​is a TAC (Transmitter Across the Memory Array) that runs through the memory array, and one end of the third connection structure 360 ​​is connected to the second bonding layer, thereby connecting to the second switch 252 through the second and fourth bonding layers. The other end of the third connection structure 360 ​​is connected to the first bonding layer, thereby connecting to the peripheral circuit 302 through the first and third bonding layers. Thus, the peripheral circuit 302 can be connected to the second switch 252 through the third bonding layer, the first bonding layer, the third connection structure 360, the second bonding layer, and the fourth bonding layer.

[0143] In this embodiment, when the first switch is closed and the second switch is open, the sub-source layer, the second bonding layer, the fourth bonding layer, and the first switch constitute a signal transmission path between the source terminal and the analog-to-digital conversion circuit; when the first switch is open and the second switch is closed, the third connection structure, the second bonding layer, the fourth bonding layer, the second switch, and the sub-source layer constitute a signal transmission path between the second sub-semiconductor structure and the source terminal.

[0144] In some embodiments, when a calculation function is required, the first switch 251 is closed and the second switch 252 is open, thereby transmitting analog calculation information to the analog-to-digital converter circuit 210 through the signal transmission path formed by the sub-source layer, the second bonding layer, the fourth bonding layer, and the first switch 251 at the source terminal; when a storage function is required, the first switch 251 is open and the second switch 252 is closed, thereby transmitting control voltage to the source terminal through the signal transmission path formed by the third bonding layer, the first bonding layer, the third connection structure 360, the second bonding layer, the fourth bonding layer, the second switch 252, and the sub-source layer.

[0145] In some embodiments, each sub-source layer is connected to a corresponding analog-to-digital converter circuit via a switch group, and the second switch of each switch group is connected to a peripheral circuit via a third connection structure. In other words, the number of switch groups in the first semiconductor structure, the number of sub-source layers, and the number of third connection structures in the second semiconductor structure are all equal.

[0146] In other embodiments, the number of third connection structures 360 may be less than the number of switch groups (or the number of sub-source layers). Several switch groups may share one third connection structure 360. For example, sub-source layers connected to the same bit line may share one third connection structure 360. This can reduce the number of third connection structures to some extent.

[0147] In some other embodiments, there may be only one third connection structure 360, meaning that all switch groups corresponding to the same memory block share one third connection structure 360. (Refer to...) Figure 13B The second switches 352 of multiple switch groups are connected together and connected to the peripheral circuit 302 through a third connection structure 360. Thus, when all the second switches are closed, the peripheral circuit 302 is connected to all the sub-source layers (common source) through the third bonding layer, the first bonding layer, the third connection structure 360, the second bonding layer, the fourth bonding layer, and all the second switches 252, thereby transmitting the control voltage to the common source. This significantly reduces the number of third connection structures.

[0148] In some embodiments, the analog-to-digital conversion circuit in the first semiconductor structure can specifically be a multi-bit analog-to-digital converter (ADC). The digital information output by the ADC can include multiple bits (e.g., 4 bits, 8 bits, 12 bits, etc.). After converting analog calculation information into digital information, the ADC outputs it to the data processing circuit.

[0149] It should be noted that each sub-source layer is connected to a corresponding analog-to-digital converter (ADC) circuit via a switch group. In other words, the number of ADC circuits and the number of switch groups in the first semiconductor structure are equal to the number of sub-source layers in the second semiconductor structure. The multiple ADC circuits corresponding to the multiple sub-source layers together constitute the ADC circuit 210 of the first semiconductor structure 200.

[0150] In this embodiment of the disclosure, when there are multiple second semiconductor structures, the memory array of each second semiconductor structure is located between the corresponding peripheral circuit and the first semiconductor structure.

[0151] Figure 14A A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 6 . Reference Figure 14A When there are two second semiconductor structures, the two second semiconductor structures 300-1 and 300-2 are located on opposite sides of the first semiconductor structure 200, and the memory arrays of the two second semiconductor structures 300-1 and 300-2 are located between the corresponding peripheral circuits and the first semiconductor structure 200. That is, the first semiconductor structure 200, the second semiconductor structures 300-1 and 300-2 are stacked on top of each other in different planes. When the planar dimensions of the first semiconductor structure and the second semiconductor structure are similar, a method is used... Figure 14A The stacking method shown can reduce the planar size of semiconductor devices.

[0152] Figure 14B A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 7 . Reference Figure 14B When there are two second semiconductor structures, the two second semiconductor structures 300-1 and 300-2 are located on the same side of the first semiconductor structure 200, and the memory arrays of the two second semiconductor structures 300-1 and 300-2 are located between the corresponding peripheral circuits and the first semiconductor structure 200. When the planar dimension of the first semiconductor structure is larger than the planar dimension of the second semiconductor structure, a method is adopted. Figure 14B The stacking method shown can reduce the stack size of semiconductor devices.

[0153] Figure 14C A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure. Figure 8 . Reference Figure 14CWhen there are four second semiconductor structures 300, the four second semiconductor structures 300-1, 300-2, 300-3, and 300-4 are all located on the same side of the first semiconductor structure 200, and the memory arrays of the four second semiconductor structures 300-1, 300-2, 300-3, and 300-4 are located between the corresponding peripheral circuits and the first semiconductor structure 200. When the planar dimension of the first semiconductor structure is much larger than the planar dimension of the second semiconductor structure, a method is adopted... Figure 14C The stacking method shown can reduce the stack size of semiconductor devices.

[0154] In the embodiments disclosed herein, the semiconductor device may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc. Specifically, the above-mentioned semiconductor device can be used in terminal products such as computers, televisions, set-top boxes, and automotive devices.

[0155] This disclosure also provides a memory computing device, including: a first semiconductor structure including an analog-to-digital conversion circuit and a data processing circuit; and a second semiconductor structure including a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array; wherein the first semiconductor structure and the second semiconductor structure are bonded together, and the memory array is located between the at least a portion of the peripheral circuitry and the second semiconductor structure.

[0156] In some implementations, the storage array is used to perform the first operation.

[0157] In some implementations, the analog-to-digital converter circuit is configured to convert the analog computation information obtained by the first operation of the storage array into digital information; the data processing circuit is configured to perform a second operation on the digital information.

[0158] In some embodiments, the second semiconductor structure includes a first sub-semiconductor structure having a memory array and a second sub-semiconductor structure having at least some peripheral circuitry; the first sub-semiconductor structure includes a first bonding layer and a second bonding layer, the memory array is bonded to the second sub-semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

[0159] In some embodiments, the memory array is located between the first bonding layer and the second bonding layer; the second sub-semiconductor structure includes a third bonding layer, which is bonded to the first bonding layer; the first semiconductor structure includes a fourth bonding layer, which is bonded to the second bonding layer.

[0160] In some embodiments, the first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact, and the third bonding layer includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded, and the first dielectric layer and the third dielectric layer are bonded.

[0161] In some embodiments, the second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the fourth bonding layer includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

[0162] In some implementations, the analog-to-digital conversion circuit is connected to the memory array via a fourth bonding layer and a second bonding layer, and receives analog calculation information output by the memory array after performing a first operation via the fourth bonding layer and the second bonding layer.

[0163] In some embodiments, the first sub-semiconductor structure further includes a bit line; the second semiconductor structure further includes a first connection structure that extends through the memory array and is connected to the bit line and the second bonding layer; wherein the memory array is connected to the analog-to-digital converter circuit through the bit line, the first connection structure, the second bonding layer and the fourth bonding layer.

[0164] In some implementations, the memory array includes multiple memory strings, each containing a drain terminal and a source terminal; wherein the source terminal is connected to the analog-to-digital converter circuit via a second bonding layer and a fourth bonding layer.

[0165] In some embodiments, the first sub-semiconductor structure further includes a source layer with source terminals connected to the source layer; the source layer is located on the side of the memory array near the second bonding layer; the source layer includes a first isolation structure extending along the word line direction and a second isolation structure extending along the bit line direction, the first isolation structure and the second isolation structure dividing the source layer into multiple sub-source layers.

[0166] In some implementations, each of the multiple sub-source layers is connected to the analog-to-digital converter circuit via a second bonding layer and a fourth bonding layer.

[0167] In some embodiments, the second semiconductor structure further includes a second connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through a third bonding layer, a first bonding layer, and a second connection structure.

[0168] In some embodiments, the first semiconductor structure further includes: a switch control circuit, the switch control circuit including switch groups connected to each sub-source layer through a fourth bonding layer and a second bonding layer; each switch group includes a first switch and a second switch, one end of the first switch being connected to the sub-source layer and the other end being connected to the analog-to-digital conversion circuit; one end of the second switch being connected to the sub-source layer and the other end being connected to the second sub-semiconductor structure through the fourth bonding layer and the second bonding layer.

[0169] In some embodiments, the second semiconductor structure further includes a third connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through the third bonding layer, the first bonding layer, the third connection structure, the second bonding layer, the fourth bonding layer, and the second switch.

[0170] In some implementations, when the first switch is closed and the second switch is open, the sub-source layer, the second bonding layer, the fourth bonding layer, and the first switch constitute a signal transmission path between the source terminal and the analog-to-digital conversion circuit; when the first switch is open and the second switch is closed, the third connection structure, the second bonding layer, the fourth bonding layer, the second switch, and the sub-source layer constitute a signal transmission path between the second sub-semiconductor structure and the source terminal.

[0171] In some embodiments, the first semiconductor structure further includes a first interface circuit and a controller; the first interface circuit is configured to output the result of the second operation performed by the digital processing circuit to an external device, and the controller is used to control the second semiconductor structure to perform the first operation.

[0172] In some embodiments, the second semiconductor structure further includes a fourth connection structure that extends through the memory array; one end of the fourth connection structure is connected to the second sub-semiconductor structure, and the other end is connected to the first interface circuit through a fourth bonding layer and a second bonding layer.

[0173] In some embodiments, the second sub-semiconductor structure further includes a second interface circuit; the second semiconductor structure is also connected to the first semiconductor structure via the second interface circuit.

[0174] In some implementations, when there are multiple second semiconductor structures, the memory array of each second semiconductor structure is located between the corresponding peripheral circuit and the first semiconductor structure.

[0175] In some implementations, the first operation includes a multiplication-accumulation operation.

[0176] In some implementations, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0177] In some implementations, the second semiconductor structure includes a three-dimensional NAND-type memory.

[0178] The specific structures and other details of the first and second semiconductor structures are similar to those in the aforementioned semiconductor devices, and will not be repeated here for the sake of brevity.

[0179] This disclosure also provides a semiconductor structure, including: a first sub-semiconductor structure and a second sub-semiconductor structure; the first sub-semiconductor structure includes a memory array for performing a first operation, and the second sub-semiconductor structure includes at least a portion of peripheral circuitry; the first sub-semiconductor structure includes a first bonding layer and a second bonding layer, the memory array is bonded to the second sub-semiconductor structure through the first bonding layer, the second bonding layer is located on the side of the memory array away from the second sub-semiconductor structure, and is used for the memory array to output analog calculation information after performing the first operation.

[0180] Here, the specific structures and other details of the first and second sub-semiconductor structures in the semiconductor structure are similar to those in the aforementioned semiconductor devices, and will not be repeated here for the sake of brevity.

[0181] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device. Figure 15 This is a schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 15 As shown, the operation method of a semiconductor device includes the following steps.

[0182] Step S10: Perform a first operation through the memory array in the second semiconductor structure of the semiconductor device to obtain analog calculation information, wherein the second semiconductor structure further includes at least a portion of the peripheral circuitry coupled to the memory array.

[0183] Step S20: The analog calculation information obtained by the storage array performing the first operation is converted into digital information through the analog-to-digital conversion circuit in the first semiconductor structure of the semiconductor device, wherein the first semiconductor structure and the second semiconductor structure are bonded together.

[0184] Step S30: Perform a second operation on the digital information through the data processing circuit in the first semiconductor structure.

[0185] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0186] In some embodiments, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0187] In some embodiments, the second semiconductor structure further includes a source layer coupled to the source end of the memory array, the source layer being divided into a plurality of sub-source layers; the first semiconductor structure further includes a switch control circuit, the switch control circuit including a switch group connected to each sub-source layer; each switch group includes a first switch and a second switch, the first switch electrically controlling signal transmission between the sub-source layer and the analog-to-digital conversion circuit, and the second switch electrically controlling signal transmission between the sub-source layer and at least a portion of the peripheral circuitry; the method further includes: in response to an execution command of a first operation, controlling the first switch to close to output analog calculation information to the analog-to-digital conversion circuit.

[0188] In some embodiments, the method further includes: controlling a second switch to close in response to an erase command, a programming command, or a read command to output a control voltage to the sub-source layer.

[0189] Based on the above-described semiconductor device, this disclosure also provides a packaging structure, including: a packaging substrate, a semiconductor device or a memory computing device described in any of the above embodiments, and a molding compound; the semiconductor device or memory computing device is disposed on the packaging substrate; and the molding compound encapsulates the semiconductor device or memory computing device.

[0190] In some embodiments, the packaging substrate includes a substrate and an interposer formed on the substrate, wherein interconnection circuits are formed in the interposer, and semiconductor devices or memory computing devices are disposed on the side of the interposer away from the substrate.

[0191] Based on the above-described semiconductor device, this disclosure also provides an electronic device, including: the semiconductor device described in any of the above embodiments or the memory computing device described in the above embodiments.

[0192] Here, the specific structure of the semiconductor device is described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0193] In some embodiments, the electronic device may further include a host, wherein the host may be a processor of the electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), wherein the SoC may be, for example, an application processor (AP).

[0194] In some embodiments, the aforementioned electronic device may be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, or power bank.

[0195] It should be understood that the phrases "some embodiments" or "embodiments of this disclosure" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "embodiments of this disclosure" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0196] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized by, include: A first semiconductor structure and a second semiconductor structure; the first semiconductor structure and the second semiconductor structure are bonded together; The first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; the second semiconductor structure includes a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array. The analog-to-digital converter circuit is configured to convert the analog computation information obtained by the storage array performing the first operation into digital information. The data processing circuit is configured to perform a second operation on the digital information.

2. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure includes a first sub-semiconductor structure having the memory array and a second sub-semiconductor structure having at least a portion of the peripheral circuitry; the first sub-semiconductor structure includes a first bonding layer and a second bonding layer, the memory array is bonded to the second sub-semiconductor structure through the first bonding layer, and the memory array is bonded to the first semiconductor structure through the second bonding layer.

3. The semiconductor device according to claim 2, The memory array is located between the first bonding layer and the second bonding layer; the second sub-semiconductor structure includes a third bonding layer, which is bonded to the first bonding layer; the first semiconductor structure includes a fourth bonding layer, which is bonded to the second bonding layer.

4. The semiconductor device according to claim 3, wherein The first bonding layer includes a first bonding contact and a first dielectric layer that isolates the first bonding contact; the third bonding layer includes a third bonding contact and a third dielectric layer that isolates the third bonding contact; the first bonding contact and the third bonding contact are bonded together, and the first dielectric layer and the third dielectric layer are bonded together.

5. The semiconductor device of claim 3, wherein The second bonding layer includes a second bonding contact and a second dielectric layer that isolates the second bonding contact; the fourth bonding layer includes a fourth bonding contact and a fourth dielectric layer that isolates the fourth bonding contact; the second bonding contact and the fourth bonding contact are bonded, and the second dielectric layer and the fourth dielectric layer are bonded.

6. The semiconductor device according to claim 3, characterized in that, The analog-to-digital conversion circuit is connected to the memory array through the fourth bonding layer and the second bonding layer, and receives the analog calculation information output by the memory array after performing the first operation through the fourth bonding layer and the second bonding layer.

7. The semiconductor device according to claim 3, characterized in that, The first sub-semiconductor structure further includes a bit line; the second semiconductor structure further includes a first connection structure that extends through the memory array and is connected to the bit line and the second bonding layer; The storage array is connected to the analog-to-digital converter circuit via the bit line, the first connection structure, the second bonding layer, and the fourth bonding layer.

8. The semiconductor device according to claim 3, characterized in that, The storage array includes multiple storage strings, each storage string having a drain terminal and a source terminal; wherein the source terminal is connected to the analog-to-digital converter circuit via the second bonding layer and the fourth bonding layer.

9. The semiconductor device according to claim 8, characterized in that, The first sub-semiconductor structure further includes a source layer, wherein the source terminal is connected to the source layer; the source layer is located on the side of the memory array near the second bonding layer; The source layer includes a first isolation structure extending along the word line direction and a second isolation structure extending along the bit line direction, wherein the first isolation structure and the second isolation structure divide the source layer into multiple sub-source layers.

10. The semiconductor device according to claim 9, characterized in that, Each of the plurality of sub-source layers is connected to the analog-to-digital converter circuit through the second bonding layer and the fourth bonding layer.

11. The semiconductor device according to claim 9, characterized in that, The second semiconductor structure further includes a second connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through the third bonding layer, the first bonding layer, and the second connection structure.

12. The semiconductor device according to claim 9, characterized in that, The first semiconductor structure further includes a switch control circuit, the switch control circuit including a switch group connected to each of the sub-source layers through the fourth bonding layer and the second bonding layer; each switch group includes a first switch and a second switch, one end of the first switch is connected to the sub-source layer and the other end is connected to the analog-to-digital conversion circuit; one end of the second switch is connected to the sub-source layer and the other end is connected to the second sub-semiconductor structure through the fourth bonding layer and the second bonding layer.

13. The semiconductor device according to claim 12, characterized in that, The second semiconductor structure further includes a third connection structure that extends through the memory array and is connected to the sub-source layer; at least a portion of the peripheral circuitry is connected to the sub-source layer through the third bonding layer, the first bonding layer, the third connection structure, the second bonding layer, the fourth bonding layer, and the second switch.

14. The semiconductor device according to claim 13, characterized in that, When the first switch is closed and the second switch is open, the sub-source layer, the second bonding layer, the fourth bonding layer, and the first switch constitute a signal transmission path between the source terminal and the analog-to-digital conversion circuit; When the first switch is open and the second switch is closed, the third connection structure, the second bonding layer, the fourth bonding layer, the second switch, and the sub-source layer constitute a signal transmission path between the second sub-semiconductor structure and the source terminal.

15. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a first interface circuit and a controller; the first interface circuit is configured to output the calculation result of the second operation performed by the digital processing circuit to an external device, and the controller is used to control the second semiconductor structure to perform the first operation.

16. The semiconductor device according to claim 15, characterized in that, The second semiconductor structure further includes a fourth connection structure that runs through the memory array; one end of the fourth connection structure is connected to the second sub-semiconductor structure, and the other end is connected to the first interface circuit through the fourth bonding layer and the second bonding layer.

17. The semiconductor device of claim 1, wherein The second semiconductor structure also includes a second interface circuit; The second semiconductor structure is also connected to the first semiconductor structure via the second interface circuit.

18. The semiconductor device of claim 1, wherein, When there are multiple second semiconductor structures, the memory array of each second semiconductor structure is located between the corresponding peripheral circuit and the first semiconductor structure.

19. The semiconductor device according to claim 1, characterized in that, The first operation includes multiplication and addition operations.

20. The semiconductor device according to claim 1, characterized in that, The second operation includes one or more of the following operations: compensation, activation, shift, or pooling.

21. The semiconductor device according to claim 1, characterized in that, The second semiconductor structure includes a three-dimensional NAND-type memory.

22. A compute-in-memory device comprising: include: The first semiconductor structure includes an analog-to-digital conversion circuit and a data processing circuit; as well as The second semiconductor structure includes a memory array for performing a first operation and at least a portion of peripheral circuitry coupled to the memory array; The first semiconductor structure and the second semiconductor structure are bonded together, and the memory array is located between the at least part of the peripheral circuit and the second semiconductor structure.

23. A semiconductor structure, characterized in that, include: A first sub-semiconductor structure and a second sub-semiconductor structure; the first sub-semiconductor structure includes a memory array for performing a first operation, and the second sub-semiconductor structure includes at least a portion of peripheral circuitry; The first sub-semiconductor structure includes a first bonding layer and a second bonding layer. The memory array is bonded to the second sub-semiconductor structure through the first bonding layer. The second bonding layer is located on the side of the memory array away from the second sub-semiconductor structure and is used by the memory array to output analog calculation information after performing the first operation.

24. A method of operating a semiconductor device, characterized by, The method includes: The first operation is performed by a memory array in a second semiconductor structure to obtain analog computing information, wherein the second semiconductor structure further includes at least a portion of peripheral circuitry coupled to the memory array; the analog computing information obtained by the memory array performing the first operation is converted into digital information by an analog-to-digital converter circuit in a first semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure are bonded together. The digital information is subjected to a second operation through the data processing circuit in the first semiconductor structure.

25. The operating method according to claim 24, characterized in that, The first operation includes multiplication and addition operations.

26. The operating method according to claim 24, characterized in that, The second operation includes one or more of the following operations: compensation, activation, shift, or pooling.

27. The method of claim 24, wherein, The second semiconductor structure further includes a source layer coupled to the source terminal of the memory array, the source layer being divided into a plurality of sub-source layers; the first semiconductor structure further includes a switch control circuit, the switch control circuit including switch groups connected to each of the sub-source layers; each switch group includes a first switch and a second switch, the first switch electrically controlling signal transmission between the sub-source layer and the analog-to-digital conversion circuit, and the second switch electrically controlling signal transmission between the sub-source layer and the at least part of the peripheral circuitry; the method further includes: In response to the execution command of the first operation, the first switch is controlled to close so as to output the analog calculation information to the analog-to-digital conversion circuit.

28. The operating method according to claim 27, characterized in that, The method further includes: In response to an erase command, a programming command, or a read command, the second switch is controlled to close to output a control voltage to the sub-source layer.

29. A packaging structure, characterized in that, include: The encapsulation substrate, the semiconductor device according to any one of claims 1-21 or the memory computing device according to claim 22, and the molding layer; The semiconductor device or the memory computing device is disposed on the packaging substrate; the molding layer encapsulates the semiconductor device or the memory computing device.

30. An electronic device, characterized in that, include: The semiconductor device according to any one of claims 1-21 or the memory computing device according to claim 22.

Images