Automatic configuration programming writing system for three-dimensional phase change random access memory
By adaptively adjusting the programming current using bitline data mode and row/column address awareness modules, the problem of uneven current distribution in 3D PCRAM is solved, thereby improving the reliability and lifespan of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI XINCHU INTEGRATED CIRCUIT
- Filing Date
- 2025-12-05
- Publication Date
- 2026-04-17
AI Technical Summary
Traditional fixed-current programming schemes cannot adapt to the non-uniform current distribution caused by changes in position and data mode in three-dimensional PCRAM structures, resulting in insufficient current in far cells or overprogramming in near cells, affecting the reliability and lifespan of the memory.
The system employs a bitline data mode sensing module and a row and column address sensing module. By detecting the number of low-resistance storage cells and the row and column addresses on the selected bitline, it generates corresponding address index signals. Combined with the lookup table address synthesis module, it reads the optimal RESET programming current configuration signal from the preset current configuration table, and the write drive control circuit generates and applies the matching programming current.
It effectively overcomes the problem of uneven current distribution caused by parasitic effects and voltage drop in three-dimensional arrays, significantly avoids insufficient current in far-end cells and overprogramming in near-end cells, and improves the write reliability and lifespan of memory.
Smart Images
Figure CN121884901A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor memory technology, and more specifically to an automatic configuration programming and writing system. Background Technology
[0002] Phase-change random access memory (PCRAM), as a promising new type of non-volatile memory, has become an important candidate for next-generation storage technology due to its high-speed read / write, low power consumption, high density, and good scalability, especially showing significant advantages in embedded storage and large-scale data storage. Traditional fixed-current programming schemes typically use a specific current amplitude to perform RESET or SET operations on selected memory cells. This scheme is simple to design, has clear control logic, and has achieved good application results in planar arrays.
[0003] However, with the continuous increase in storage density requirements, three-dimensional cross-stacked PCRAM structures have gradually become a key technical path for achieving high-density integration. In a three-dimensional array, due to the multi-layer stacking of memory cells in the vertical direction, physical effects such as interconnect resistance, parasitic capacitance, and wire voltage drop are significantly enhanced, resulting in a noticeable non-uniform distribution of the effective current actually received by memory cells at different locations during write operations. Traditional fixed-current programming schemes cannot adapt to the differences in current demand caused by the dynamic changes in cell location and data mode. This can easily lead to memory cells far from the drive circuit failing to fully reset due to insufficient current, or near-end cells experiencing "overprogramming" due to excessive current, seriously affecting the reliability and lifespan of the three-dimensional PCRAM.
[0004] Therefore, designing a write operation scheme that can adaptively adjust the programming current based on the structural characteristics of three-dimensional PCRAM has become a pressing technical challenge. Summary of the Invention
[0005] To address the above technical problems, this invention provides a technical solution for an automatic configuration programming and writing system for a three-dimensional phase-change random access memory.
[0006] The technical problem solved by this invention can be achieved by the following technical solutions: An automatic configuration programming and writing system for a three-dimensional phase-change random access memory, comprising: The bit line data pattern sensing module is used to detect the number of low-resistivity memory cells on the selected bit line and obtain the data pattern encoding signal on the selected bit line. The row and column address sensing module is used to generate the corresponding address index signal based on the row and column address of the selected memory cell; The RESET current configuration table module is used to store the RESET programming current configuration lookup table. The lookup table address synthesis module is connected to the bit line data mode sensing module, the row and column address sensing module, and the RESET current configuration table module. It is used to read the corresponding RESET programming current configuration signal from the RESET current configuration table module according to the data mode encoding signal on the selected bit line and the address index signal. The write drive control circuit is connected to the lookup table address synthesis module and is used to generate a programming current of a corresponding amplitude according to the RESET programming current configuration signal, and apply the programming current to the selected memory unit.
[0007] Preferably, in the bit line data pattern sensing module, the number of low-resistivity memory cells on the selected bit line is detected by simulating matrix-vector multiplication using a 3D PCRAM cross array.
[0008] Preferably, the bitline data pattern sensing module specifically performs the following operations: The selected bit line is biased to a detection voltage by a detection circuit, while the unselected bit lines and word lines are biased to zero. The detection current flowing through the selected bit line is compared with multiple preset reference currents by a current comparator to determine the data mode on the selected bit line. The data pattern is converted into a 3-bit binary encoded signal, and the encoded signal is written into a register.
[0009] Preferably, the criteria for dividing the data patterns are as follows: like If so, the data mode on the selected bit line is determined to be Mode1; like If so, the data mode on the selected bit line is determined to be Mode2; like If so, the data mode on the selected bit line is determined to be Mode3; like If so, the data mode on the selected bit line is determined to be Mode4; like If so, the data mode on the selected bit line is determined to be Mode5; in, To detect current, As the first reference current, As the second reference current, As the third reference current, This is the fourth reference current.
[0010] Preferably, the reference current has a non-linear relationship with the number of low-resistivity memory cells on the selected bit line.
[0011] Preferably, the row and column address sensing module adopts a block addressing mechanism to divide the storage array into multiple address blocks, and the storage cells in each address block use the same RESET programming current amplitude.
[0012] Preferably, the address index signal is formed by mapping the high-order bits of the row address and column address of the selected memory cell, and is used to identify the address block to which the selected memory cell belongs.
[0013] Preferably, the multi-level RESET programming current configuration lookup table stores RESET programming current configuration signals based on different data modes and different row and column address block indices.
[0014] Preferably, the lookup table address aggregation module performs the following operations: The data pattern encoding signal is combined with the address index signal to form a lookup table query address; Access the multi-level RESET programming current configuration table based on the lookup table index address to obtain the RESET programming current configuration signal.
[0015] It also includes an automatic configuration programming method for three-dimensional phase-change random access memory, applied to an automatic configuration programming system for three-dimensional phase-change random access memory as described above, comprising: Step S1: Detect the number of low-resistivity memory cells on the selected bit line using the bit line data pattern sensing module, and obtain the data pattern encoding signal on the selected bit line. Step S2: The row and column address sensing module generates the corresponding address index signal based on the row and column address of the selected storage unit. Step S3: The lookup table address synthesis module reads the corresponding RESET programming current configuration signal from the multi-level RESET programming current configuration table according to the data mode encoding signal on the selected bit line and the address index signal. Step S4: The write drive control circuit generates a programming current of a corresponding amplitude according to the RESET programming current configuration signal, and applies the programming current to the selected memory cell to perform a write operation.
[0016] Beneficial effects: This invention dynamically detects the number of low-resistivity cells on the selected bit line using a bit line data pattern sensing module, and identifies the specific location of the memory cell in the three-dimensional array using a row and column address sensing module. A lookup table address synthesis module integrates both information to accurately index the optimal RESET programming current amplitude from a preset current configuration table. Finally, the write drive control circuit generates and applies a programming current that matches the actual needs of the memory cell. This effectively overcomes the problem of uneven current distribution caused by parasitic effects and voltage drops in the three-dimensional array, significantly avoids insufficient current in far-end cells and overprogramming in near-end cells, and extends the lifespan of the memory while ensuring write reliability. Attached Figure Description
[0017] Figure 1 This is a block diagram of the automatic configuration programming writing system of the present invention; Figure 2 This is a schematic diagram of the cross array of the present invention; Figure 3 This is a circuit diagram of the selected bit line data mode detection circuit of the present invention; Figure 4 This is a circuit diagram of the current comparator of the present invention; Figure 5 This invention provides a RESET programming current configuration table for selecting memory cell row and column addresses under different selected bit line data modes. Figure 6 This is a flowchart of the method of the present invention. Detailed Implementation
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0021] Reference Figure 1 This invention provides an automatic configuration programming and writing system for a three-dimensional phase-change random access memory, comprising: The bit line data pattern sensing module 1 is used to detect the number of low-resistivity memory cells on the selected bit line and to acquire the data pattern encoding signal on the selected bit line. The row and column address sensing module 2 is used to generate the corresponding address index signal based on the row and column address of the selected storage unit; RESET current configuration table module 3 is used to store the RESET programming current configuration lookup table; The lookup table address synthesis module is connected to the bit line data mode sensing module 1, the row and column address sensing module 2, and the RESET current configuration table module 3. It is used to read the corresponding RESET programming current configuration signal from the RESET current configuration table module 3 according to the data mode encoding signal on the selected bit line and the address index signal. The write drive control circuit 5 is connected to the lookup table address synthesis module 4, and is used to generate a programming current of a corresponding amplitude according to the RESET programming current configuration signal, and apply the programming current to the selected memory unit.
[0022] Specifically, addressing the issue of non-uniform distribution of effective current during write operations in three-dimensional cross-stacked PCRAM arrays due to interconnect resistance, parasitic capacitance, and wire voltage drop, this solution integrates an adaptive current configuration mechanism that is aware of bit line (BL) data patterns and cell addresses. This avoids the reliability risks of "insufficient current at the far end and overprogramming at the near end" in traditional fixed-current schemes, enabling precise current programming of storage cells at different locations and under different data loads in the three-dimensional array. This significantly improves the overall array's write reliability and lifespan.
[0023] Specifically, the system comprehensively quantifies two core dynamic variables that affect the effective programming current (the data pattern on the selection line and the physical position of the selected memory cell in the three-dimensional array). By using a lookup table method, the system uses the combination of codes for these two types of variables as an index to query the preset optimal current amplitude value in real time, thereby controlling the write drive circuit to output a programming current that precisely matches the current write operation condition.
[0024] In a preferred embodiment of the present invention, the number of low-resistivity memory cells on the selected bit line is detected by using a 3D PCRAM cross array to simulate matrix-vector multiplication.
[0025] Specifically, the total leakage current on the selected bit line is mainly contributed by all the low-resistivity (SET) memory cells connected to it, and this current value has a monotonically non-linear relationship with the number of low-resistivity cells S. This relationship is mainly due to two factors: first, the non-linear IV characteristics of the OTS / PCM memory cell itself; and second, when multiple low-resistivity cells are connected in parallel on BL, the significant voltage drop caused by the parasitic resistance of BL leads to a gradual decrease in the actual voltage drop across each cell as the number of cells S increases, causing the growth of the total current to show a saturation trend, that is, the growth rate slows down as S increases.
[0026] Based on this, refer to Figure 2 In this embodiment of the invention, during the detection period, the selected BL is biased to a fixed detection voltage. Meanwhile, all unselected BLs and all WLs (Word Lines) are biased to 0V (i.e., ground). At this time, the detection voltage is measured by the detection circuit. The detection current flowing into the selected BL Since only the low-resistivity cells constitute an effective conductive path, and the current contributed by the high-resistivity cells is negligible, the detection current... The size of S directly and non-linearly reflects the total number S of memory cells in a low-resistance state on the selected BL; that is, the more S there are, the higher the resistance. The larger the number of low-resistivity memory cells selected on the BL, the more non-linear the growth becomes. The BL detection current changes monotonically but non-linearly with the number of low-resistivity memory cells selected on the BL.
[0027] In a preferred embodiment of the present invention, the bitline data pattern sensing module 1 specifically performs the following operations: The selected bit line is biased to a detection voltage by the detection circuit 11, while the unselected bit lines and word lines are biased to zero. The current comparator 12 compares the detected current flowing through the selected bit line with multiple preset reference currents to determine the data mode on the selected bit line. The data pattern is converted into a 3-bit binary encoded signal, and the encoded signal is written into register 13.
[0028] Specifically, considering the balance between the accuracy of current detection, comparison speed, and array access power consumption, this embodiment of the invention achieves fast and reliable sensing of data patterns with limited additional overhead by reusing part of the read circuit and integrating a high-precision, multi-threshold parallel current comparator 12.
[0029] Specifically, the bitline data pattern sensing module 1 performs the following operations: First, refer to Figure 3 During the detection process, the detection circuit 11 utilizes a low-dropout linear regulator (LDO) in the 3D PCRAM read path to generate a stable, low-noise detection voltage. This is then applied to the selected BL. Simultaneously, a unity-gain buffered operational amplifier (AMP) is configured as a voltage follower, with its non-inverting input connected to a precise bias voltage. Its output is connected to the common bias node of current comparator 12, providing a stable and matched bias voltage to current comparator 12 to ensure the accuracy and consistency of the current mirror. The core of the detection circuit 11 consists of an LDO, a buffer operational amplifier AMP, and an additional integrated multi-channel current comparator 12. The detection current flowing through the selected BL... It is led out and fed to the input node of the current comparator 12.
[0030] Next, refer to Figure 4 The current comparator 12 employs a high-precision cascode current mirror structure, specifically: the input transistor NM0 accurately replicates the detected current. The transistors are mirrored into four parallel comparator branches by four sets of mirror transistor pairs (NM0 and NM1, NM0 and NM2, NM0 and NM3, NM0 and NM4).
[0031] In each branch, the mirrored With a preset reference current (first reference current) Second reference current Third reference current Fourth reference current The comparison is performed using the output nodes R of each branch. <0> R <1> R <2> The high and low voltage levels directly generate characterization in parallel. The original logic signals relating to the magnitudes of each reference current.
[0032] Then, an adjacent digital logic encoding unit receives this set of original logic signals. This unit, according to a preset truth table or priority encoding rule, combines the four comparison results and converts them into a unified 3-bit binary encoded signal. This 3-bit encoded signal uniquely identifies... The specific current range in which it is located corresponds to the BL data mode (e.g., multiple modes from light load to heavy load).
[0033] Finally, this encoded signal is latched into a dedicated 3-bit detection result register 13, and its output is used as a static signal for the subsequent lookup table address synthesis module 4 to read directly, thereby completing the entire sensing process.
[0034] In a preferred embodiment of the present invention, the reference current has a non-linear relationship with the number of low-resistivity memory cells on the selected bit line.
[0035] More specifically, in order to accurately divide continuous current values into discrete, meaningful "data patterns," this embodiment of the invention employs a series of non-uniformly set reference current thresholds, as shown in Table 1 below: Table 1 Reference Current and Corresponding Number of Low-Impedance Memory Cells
[0036] These reference currents (first reference current) Second reference current Third reference current Fourth reference current It is not set at equal intervals, but precisely matched to the detection current. The nonlinear saturation trend with the increase of the number of low-resistivity units S.
[0037] Specifically, as S increases, the increment in the number of cells required to reach the next current threshold increases significantly (e.g., from...). arrive Approximately 107 additional units are needed, and from... arrive (Approximately 152 additional cells are required). This nonlinear partitioning aims to keep the variation in the optimal RESET programming current requirement within a minimum and relatively uniform range, despite the varying range of low-resistivity cells within each divided data mode interval.
[0038] In this way, the pattern encoding output by the bitline data pattern sensing module 1 can more accurately characterize the actual impact of the current BL load state on the programming current, providing a key and reliable input for the subsequent address synthesis module to perform accurate current configuration, thereby optimizing the uniformity of current distribution at the system level and effectively suppressing overprogramming and underprogramming phenomena.
[0039] In a preferred embodiment of the present invention, the data pattern division criterion is as follows: like If so, the data mode on the selected bit line is determined to be Mode1; like If so, the data mode on the selected bit line is determined to be Mode2; like If so, the data mode on the selected bit line is determined to be Mode3; like If so, the data mode on the selected bit line is determined to be Mode4; like If so, the data mode on the selected bit line is determined to be Mode5; in, To detect current, As the first reference current, As the second reference current, As the third reference current, Fourth reference current.
[0040] Specifically, in this embodiment of the invention, based on the nonlinear reference current thresholds listed in Table 1, the detailed data mode division criteria and their corresponding 3-bit binary codes are determined as shown in Table 2. There are a total of 5 types of BL data modes, and these 5 different data modes are represented by 3-bit binary codes.
[0041] Table 2 BL Data Pattern
[0042] The original logic signal (R) output in parallel by current comparator 12 <0> , R <1> , R <2> After passing through the preset decoding logic, it can be directly mapped to the 3-bit binary code R<2:0> defined in Table 2. This code is then latched into register 13 as a static mode signal representing the current BL load state.
[0043] This division method ensures that each mode interval not only corresponds to a specific detection current range, but also is essentially associated with a BL load state interval with a relatively uniform demand for the optimal programming current, thus laying a precise sensing foundation for subsequent adaptive current configuration.
[0044] In a preferred embodiment of the present invention, the row and column address sensing module 2 adopts a block addressing mechanism to divide the storage array into multiple address blocks, and the storage cells in each address block use the same RESET programming current amplitude.
[0045] Specifically, in a three-dimensional cross-stacked array, the optimal RESET programming current requirement of a memory cell is closely related to its physical location in the array (i.e., row and column address), exhibiting an increasing profile from the peripheral circuitry towards the center of the array. To achieve a balance between hardware overhead and programming accuracy, and to avoid the enormous area and complexity costs associated with configuring current individually for each cell, this embodiment of the invention proposes a block-sharing RESET current scheme.
[0046] This block-based shared RESET current scheme divides a single-layer 1024×1024 memory array into 8 rows × 8 columns, totaling 64 address blocks, based on row and column addresses. Each block has a capacity of 128×128 memory cells. Because the array structure is symmetrical, the upper and lower layers of memory cells share the same RESET current configuration.
[0047] By modeling and simulating all position cells of the array, the optimal programming current range required to complete the RESET operation was determined (Best case approximately 90.14 μA, Worst case approximately 119.69 μA). Based on this, the row and column address sensing module 2 is configured to provide a set of multi-level RESET programming currents with fixed amplitude ranges and step sizes, ranging from 95 μA to 120 μA with a step size of 5 μA, for a total of 6 different current amplitudes. These 6 current amplitudes are represented by a 3-bit binary code, as shown in Table 3 below: Table 3 Multi-stage RESET programming current
[0048] In this scheme, all memory cells within the same block will use the same RESET programming current amplitude, the value of which is determined by the optimal programming current required by the memory cell in the worst case within the block (usually the cell furthest from the drive circuit and with the most severe parasitic effects).
[0049] This method, while ignoring the minute current differences between cells within the same block, accurately compensates for the main current demand differences caused by location between different blocks, thus achieving effective perception and response to cell location factors at an acceptable hardware cost.
[0050] In a preferred embodiment of the present invention, the address index signal is composed of the high-order bits of the row address and column address of the selected memory cell, and is used to identify the address block to which the selected memory cell belongs.
[0051] Specifically, considering the need to efficiently and unambiguously map continuous physical address spaces to discrete address block indices and minimize the complexity of address decoding logic, in this embodiment of the invention, the high-order bits inherent in the row and column addresses of storage units are used to directly implement block mapping.
[0052] Accordingly, for 1024 (2 10 The array is 1024×8, with each row and column address represented by 10 binary address lines (e.g., row address R<9:0>, column address C<9:0>). The address index signal is composed of the highest three bits of the row address (R<9:7>) and the highest three bits of the column address (C<9:7>). The eight possible values of these three high-order address bits (binary 000 to 111, corresponding to decimal 0 to 7) naturally correspond to eight block indices. Therefore, the value of R<9:7> is directly mapped to the row block index (0~7) in the 8×8 block structure, and the value of C<9:7> is directly mapped to the column block index (0~7).
[0053] This mapping method eliminates the need for additional complex decoding circuits. Based on the 10-bit complete row and column address of any given memory cell, its 128×128 address block can be quickly and uniquely determined from its highest three bits.
[0054] For example, when the row address R<9:0> is in the range of 0 to 127, its R<9:7> is "000", which indicates that the cell belongs to row block 0; when the column address C<9:0> is in the range of 512 to 639, its C<9:7> is "100" (decimal 4), which indicates that the cell belongs to column block 4; the address index signal generated in this way serves as one of the key inputs for subsequent lookup table (LUT) addressing, ensuring that memory cells in different physical locations can be indexed to the optimized RESET programming current configuration corresponding to their respective blocks.
[0055] In a preferred embodiment of the present invention, the multi-level RESET programming current configuration lookup table stores RESET programming current configuration signals based on different data modes and different row and column address block indices.
[0056] Specifically, in order to fuse the results of BL data pattern sensing and row / column address sensing, and ultimately output a precise programmable current control signal, refer to Figure 5 In this embodiment of the invention, a multi-level RESET programming current configuration lookup table (LUT) is constructed. This lookup table uses a 3-bit binary code representing five different BL data modes and a 3-bit row index and a 3-bit column index representing the address block to which the memory cell belongs (i.e., the high three bits of the row address R<9:7> and the high three bits of the column address C<9:7>) as the combined input address. For each BL data mode (Mode1 to Mode5), the lookup table pre-stores a corresponding 8x8 current configuration matrix. Each element in the matrix is a 3-bit encoded value pointing to one of the six RESET programming current amplitudes defined in Table 3.
[0057] like Figure 5 As shown, taking the configuration tables of Mode1 (light load mode) and Mode5 (heavy load mode) as examples, a clear mapping pattern can be observed. Under the same BL data mode, the current configuration code value shows a "diagonal trend" that increases from the array edge (row and column index 0,0) towards the array center or diagonally.
[0058] For example, in Mode 1, the configuration code for peripheral blocks is mostly "000" (corresponding to 95μA), while the code for blocks closer to the center gradually increases to "001" (100μA) or higher. In Mode 5, the starting code for peripheral blocks is already higher, increasing towards the center to "101" (120μA). This trend precisely matches the physical characteristics of the three-dimensional array. The farther the memory cell is from the peripheral drive circuit, the more severe the influence of interconnect resistance and voltage drop, and the greater the effective current required to complete a reliable RESET operation. Therefore, this lookup table, through address indexing, essentially maps each physical location of a block to a globally optimized RESET programming current amplitude that matches its electrical environment (the load environment characterized by the BL data mode and the location environment characterized by the row and column addresses).
[0059] Using this lookup table, the system combines dynamically sensed BL load status (mode code) with static cell physical location (address block index) to query and output an optimal 3-bit current configuration code in real time. This code directly controls the write drive circuit to generate a programming current of the corresponding magnitude.
[0060] In this way, the system not only responds to the dynamic current demand changes caused by the data pattern, but also compensates for the systematic current deviation caused by the fixed position of the unit. Thus, it achieves accurate and adaptive configuration of the programming current in the entire space of the three-dimensional array and under all operating conditions, effectively suppressing overprogramming or programming failure caused by current overshoot or undershoot, and significantly improving the reliability and service life of the memory.
[0061] In a preferred embodiment of the present invention, the RESET programming current configuration lookup table is a volatile memory. When the circuit is powered on, the multi-level RESET programming current configuration table is loaded from the reserved PCRAM space into the RESET programming current configuration lookup table.
[0062] Specifically, considering that Static Random-Access Memory (SRAM) has advantages such as fast access speed, ease of integration, and read / write, making it suitable as a lookup table (LUT) requiring frequent and fast access, but its data is easily lost after power failure, the stored current configuration table cannot be saved after system power failure. Therefore, in this embodiment of the invention, SRAM is used to implement the multi-level RESET programmable current configuration lookup table.
[0063] To ensure that the LUT can obtain the correct configuration data each time the system is powered on to support the normal operation of the automatic configuration write operation, a dedicated non-volatile storage space is reserved in the PCRAM array during circuit design for persistently storing all the data of the multi-level RESET programming current configuration table.
[0064] During the system power-on initialization phase, the built-in loading logic completely writes the configuration data (a total of 960 bits, corresponding to 64 3-bit configuration files in 5 data modes) stored in the reserved PCRAM space into the SRAM-type LUT. This process will result in approximately 77.57 μm of... 2 Area cost.
[0065] In this way, the system utilizes the high-speed access characteristics of SRAM (index latency of approximately 5 ns) to meet the requirements for configuration read speed in the write operation timing, while leveraging the non-volatility of PCRAM to ensure the reliable preservation of critical configuration data after power failure and reliable recovery after system power-on, thus achieving an effective balance between performance and reliability.
[0066] In a preferred embodiment of the present invention, the lookup table address synthesis module 4 specifically performs the following operations: The data pattern encoding signal is combined with the address index signal to form a lookup table query address; Access the multi-level RESET programming current configuration table based on the lookup table index address to obtain the RESET programming current configuration signal.
[0067] Specifically, in this embodiment of the invention, the lookup table address synthesis module 4 concatenates the 3-bit data pattern encoded signal (R<2:0>) output by the bit line data pattern sensing module 1 with the 6-bit address index signal provided by the row and column address sensing module 2, which is composed of the three high bits of the row address (R<9:7>) and the three high bits of the column address (C<9:7>), to form a unified LUT lookup address; this LUT lookup address directly points to a specific entry pre-stored in the multi-level RESET programming current configuration table.
[0068] Before the programming operation (RESET) begins, the module quickly indexes the LUT through the query address and reads the corresponding 3-bit RESET programming current configuration signal. This configuration signal is then sent to the write drive control circuit 5, which guides it to generate a programming current with a specific amplitude (e.g., 95μA to 120μA, a total of 6 levels). This process ensures that the optimal programming current is dynamically matched for each write operation.
[0069] This design enables awareness of the row and column addresses of selected memory cells. Its physical essence is to compensate for the effective voltage drop that varies with cell location due to interconnect resistance and parasitic effects. By jointly looking up two key variables—data pattern (affecting total BL leakage current and voltage drop) and physical location (determining the specific node of the cell in the resistor network)—the lookup table address synthesis module 4 achieves a high degree of adaptability to the three-dimensional array write operation environment, providing core configuration decisions for reliable and uniform programming operations.
[0070] Reference Figure 6 The present invention also includes an automatic configuration programming and writing method for a three-dimensional phase-change random access memory, applied to an automatic configuration programming and writing system for a three-dimensional phase-change random access memory as described above, comprising: Step S1: The number of low-resistivity memory cells on the selected bit line is detected by the bit line data pattern sensing module 1, and the data pattern encoding signal on the selected bit line is obtained. Step S2: The row and column address sensing module 2 generates the corresponding address index signal based on the row and column address of the selected storage unit; Step S3: The lookup table address synthesis module 4 reads the corresponding RESET programming current configuration signal from the multi-level RESET programming current configuration table according to the data mode encoding signal on the selected bit line and the address index signal. Step S4: The write drive control circuit 5 generates a programming current of a corresponding amplitude according to the RESET programming current configuration signal, and applies the programming current to the selected memory cell to perform a write operation.
[0071] In summary, this invention overcomes the challenge of non-uniform current distribution in three-dimensional PCRAM arrays faced by traditional fixed current schemes through an adaptive current configuration mechanism that integrates BL data pattern awareness and cell position awareness.
[0072] Compared with the prior art, the present invention has the following significant progress and advantages: Precise adaptive control: It overcomes the problem that traditional fixed current schemes cannot adapt to the non-uniform current distribution caused by differences in position and data mode in three-dimensional arrays. It can dynamically sense and compensate for these effects, and fundamentally avoid the phenomena of "underprogramming at the far end" and "overprogramming at the near end".
[0073] Significantly improved reliability: By providing the optimal programming current to memory cells in different locations and under different load conditions to match their actual needs, the programming success rate and data retention capability of the 3D PCRAM array are greatly improved, thereby significantly enhancing the overall reliability and lifespan of the memory.
[0074] Optimizing performance overhead: While introducing adaptive functionality, strategies such as block-based current sharing, multiplexing read circuits, optimizing LUT design, and employing high-speed SRAM were used to control the additional area overhead to only 183.17 μm² per bank, and the additional latency of the critical path (RESET operation) was controlled to 55 ns. Since this latency is much smaller than the inherent SET operation latency of PCRAM (approximately 300 ns), it did not significantly affect the overall write speed, achieving an excellent balance between performance and functionality.
[0075] The system is highly robust: key parameters in the scheme (such as nonlinear reference current and block current configuration table) are based on accurate modeling and simulation of the electrical characteristics of the three-dimensional array, ensuring the robustness of the adaptive logic under different process angles and operating conditions.
[0076] Excellent scalability: The proposed sensing and configuration architecture is clear and modular, and can flexibly adjust parameters such as block granularity and current level to adapt to the design requirements of three-dimensional PCRAM arrays of different scales and layers, thus possessing good technical extensibility.
[0077] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.
Claims
1. An auto-configuration programming write system for a three-dimensional phase change random access memory, characterized by, include: The bit line data pattern sensing module (1) is used to detect the number of low-resistivity memory cells on the selected bit line and to obtain the data pattern encoding signal on the selected bit line. The row and column address sensing module (2) is used to generate the corresponding address index signal according to the row and column address of the selected storage unit; The RESET current configuration table module (3) is used to store the RESET programming current configuration lookup table; The lookup table address synthesis module (4) is connected to the bit line data mode sensing module (1), the row and column address sensing module (2), and the RESET current configuration table module (3). It is used to read the corresponding RESET programming current configuration signal from the RESET current configuration table module (3) according to the data mode encoding signal on the selected bit line and the address index signal. The write drive control circuit (5) is connected to the lookup table address synthesis module (4) and is used to generate a programming current of a corresponding amplitude according to the RESET programming current configuration signal and apply the programming current to the selected memory unit.
2. An auto-programmed write system for a three-dimensional phase change random access memory according to any one of claims 1, wherein, In the bitline data pattern sensing module (1), the number of low-resistivity memory cells on the selected bitline is detected by 3D PCRAM cross array analog matrix vector multiplication.
3. The auto-programmed write system for 3D phase change RAM of claim 1, wherein, The bitline data pattern sensing module (1) performs the following operations: The selected bit line is biased to a detection voltage by the detection circuit (11), and the unselected bit line and word line are biased to zero. The detection current flowing through the selected bit line is compared with multiple preset reference currents by a current comparator (12) to determine the data mode on the selected bit line. The data pattern is converted into a 3-bit binary encoded signal and the encoded signal is written into register (13).
4. The auto-programmed write system for 3D phase change RAM of claim 3, wherein, The criteria for classifying the data patterns are as follows: like If so, the data mode on the selected bit line is determined to be Mode1; If then determine that the data pattern on the selected bit line is Mode2; If then the data pattern on the selected bit line is determined to be Mode 3; If then the data pattern on the selected bit line is determined to be Mode 4; If then the data pattern on the selected bit line is determined to be Mode 5; wherein, is a detection current, is a first reference current, is a second reference current, is a third reference current, is a fourth reference current.
5. The auto-programmed write system for 3D phase change RAM of claim 3, wherein, The reference current has a non-linear relationship with the number of low-resistivity memory cells on the selected bit line.
6. The auto-programmed write system for 3D phase change RAM of claim 1, wherein, The row and column address sensing module (2) adopts a block addressing mechanism to divide the storage array into multiple address blocks, and the storage units in each address block use the same RESET programming current amplitude.
7. The auto-programmed write system for 3D phase change RAM of claim 6, wherein, The address index signal is formed by mapping the high-order bits of the row address and column address of the selected memory cell, and is used to identify the address block to which the selected memory cell belongs.
8. The auto-programmed write system for 3D phase change RAM of claim 1, wherein, The multi-level RESET programming current configuration lookup table stores RESET programming current configuration signals based on different data modes and different row and column address block indices.
9. An automatic configuration programming and writing system for a three-dimensional phase-change random access memory according to claim 1, characterized in that, The lookup table address synthesis module (4) performs the following operations: The data pattern encoding signal is combined with the address index signal to form a lookup table query address; Access the multi-level RESET programming current configuration table based on the lookup table index address to obtain the RESET programming current configuration signal.
10. An automatic configuration programming and writing method for a three-dimensional phase-change random access memory, characterized in that, An application implemented in an automatic configuration programming and writing system for a three-dimensional phase-change random access memory as described in any one of claims 1-9 includes: Step S1: The number of low-resistivity memory cells on the selected bit line is detected by the bit line data pattern sensing module (1), and the data pattern encoding signal on the selected bit line is obtained. Step S2: The row and column address sensing module (2) generates the corresponding address index signal based on the row and column address of the selected storage unit; Step S3: The lookup table address synthesis module (4) reads the corresponding RESET programming current configuration signal from the multi-level RESET programming current configuration table according to the data mode encoding signal on the selected bit line and the address index signal. Step S4: The write drive control circuit (5) generates a programming current of a corresponding amplitude according to the RESET programming current configuration signal, and applies the programming current to the selected memory cell to perform a write operation.