Overvoltage protection circuit for intelligent fusion terminal switching power supply and switching power supply

Abstract

The invention discloses an overvoltage protection circuit for an intelligent fusion terminal switching power supply and the switching power supply. The overvoltage protection circuit comprises an input voltage acquisition circuit and an overvoltage signal conversion output circuit, the input voltage acquisition circuit is connected in parallel between a direct current bus voltage end and a grounding end, and is used for carrying out voltage division sampling on the first voltage and outputting a sampling voltage; the input end of the overvoltage signal conversion output circuit is electrically connected with the input voltage acquisition circuit, the output end of the overvoltage signal conversion output circuit is electrically connected with the current detection end of the switching power supply control chip, the overvoltage signal conversion output circuit comprises a power supply reference chip and a first triode, and the input end of the power supply reference chip is connected with sampling voltage; when the sampling voltage exceeds the reference voltage of the power supply reference chip, the power supply reference chip drives the first triode to be switched on, so that the voltage of the current detection end is raised to trigger an overcurrent comparison threshold of the switching power supply control chip; therefore, under the condition that a special overvoltage detection interface is not added, input overvoltage protection is realized, and occupation of peripheral circuits and interfaces is reduced.

Description

Technical Field

[0001] This application relates to the field of input overvoltage protection technology for switching power supplies, and in particular to an overvoltage protection circuit and switching power supply for a smart fusion terminal. Background Technology

[0002] In power distribution systems and various electronic devices, AC-DC switching power supplies are widely used to convert AC mains power into DC bus voltage, providing a stable DC power supply for subsequent power conversion and control circuits. As the application scenarios of switching power supplies become increasingly complex, the input side may be affected by factors such as grid fluctuations, load switching, lightning surges, and rectifier / filter transients, leading to abnormal increases in the input DC bus voltage. Therefore, monitoring and protecting against input overvoltage has become an important aspect of switching power supply reliability design.

[0003] In existing technologies, input overvoltage protection in switching power supplies is typically achieved by implementing overvoltage detection and shutdown / power limiting measures on the input bus side. For example, this can be achieved using a resistor divider in conjunction with a comparator or reference device to determine the overvoltage threshold, followed by a control chip to stop the switching transistor from driving and enter a protection state. Alternatively, dedicated overvoltage protection devices or clamping / discharging devices can be used to suppress input overvoltage. However, these solutions often suffer from problems in engineering applications, such as increased component count, complex peripheral circuitry, limited compatibility with different control chips, the need for dedicated detection pins / interfaces, and significant impact of component variability on the consistency of protection thresholds and actions. Furthermore, when the power control chip itself integrates overcurrent detection / protection functions, achieving input overvoltage protection without significantly increasing cost and complexity has become a common design requirement.

[0004] Therefore, in the input protection of AC-DC switching power supplies, the detection and protection of input bus overvoltage is complex, the system integration is limited due to the occupation of devices and interfaces, and the reliability and consistency of protection actions are difficult to balance, which have become technical problems that urgently need to be solved. Summary of the Invention

[0005] This application provides an overvoltage protection circuit and a switching power supply for a smart fusion terminal, aiming to solve the problems in the input protection of AC-DC switching power supplies, such as the complexity of input bus overvoltage detection and protection, the limited system integration due to the occupation of devices and interfaces, and the difficulty in balancing the reliability and consistency of protection actions.

[0006] In a first aspect, an overvoltage protection circuit for a switching power supply of an intelligent fusion terminal is provided, the circuit comprising an input voltage acquisition circuit and an overvoltage signal conversion and output circuit.

[0007] The input voltage acquisition circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The input voltage acquisition circuit is used to perform voltage division sampling on the first voltage output from the DC bus voltage terminal and output the sampled voltage.

[0008] The input terminal of the overvoltage signal conversion output circuit is electrically connected to the input voltage acquisition circuit, and the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal of the switching power supply control chip.

[0009] The overvoltage signal conversion output circuit includes a power reference chip and a first transistor, and the input terminal of the power reference chip is connected to the sampling voltage.

[0010] When the sampling voltage exceeds the reference voltage of the power reference chip, the power reference chip drives the first transistor to conduct, causing the voltage at the current detection terminal to rise, thereby triggering the overcurrent comparison threshold of the switching power supply control chip.

[0011] Optionally, in the above scheme, the input voltage acquisition circuit includes a voltage divider branch formed by connecting a first resistor, a second resistor, a fifth resistor, a sixth resistor, and a twelfth resistor in series. The two ends of the voltage divider branch are respectively connected to the DC bus voltage terminal and the ground terminal.

[0012] The connection point between the sixth resistor and the twelfth resistor is the sampling voltage output terminal, which is used to output the sampling voltage.

[0013] Optionally, in the above scheme, the input voltage acquisition circuit further includes a first capacitor, the first end of which is electrically connected to the sampling voltage output terminal, and the second end of which is electrically connected to the ground terminal.

[0014] Optionally, in the above scheme, the overvoltage signal conversion output circuit further includes a base bias and current limiting network, which includes a third resistor, a fourth resistor, a seventh resistor, and an eighth resistor.

[0015] The input terminal of the power reference chip is connected to the sampling voltage, the ground terminal of the power reference chip is electrically connected to the ground terminal, the output terminal of the power reference chip is electrically connected to the first terminal of the seventh resistor and the first terminal of the eighth resistor respectively; the second terminal of the seventh resistor is electrically connected to the base of the first transistor, and the second terminal of the eighth resistor is connected to the supply voltage.

[0016] The emitter of the first transistor is connected to the power supply voltage through the fourth resistor;

[0017] The collector of the first transistor is electrically connected to the first end of the third resistor.

[0018] Optionally, in the above scheme, the overvoltage signal conversion output circuit further includes a protection diode, the positive terminal of which is electrically connected to the second terminal of the third resistor, and the negative terminal of which is electrically connected to the current detection terminal.

[0019] Optionally, in the above scheme, the power reference chip is a TL431 power reference chip, and the reference voltage of the power reference chip is 2.5V.

[0020] Optionally, in the above scheme, the first transistor is a PNP transistor.

[0021] In the above scheme, optionally, the voltage division ratio of the input voltage acquisition circuit is configured such that when the first voltage reaches a preset overvoltage threshold, the sampling voltage reaches or exceeds the reference voltage of the power reference chip.

[0022] In a second aspect, a switching power supply includes a rectifier and filter unit, a switching power supply control chip, and an input overvoltage protection circuit as described in the first aspect.

[0023] The input terminal of the rectifier and filter unit is used to connect to AC mains power, and the output terminal of the rectifier and filter unit is the output DC bus voltage terminal, which outputs a first voltage.

[0024] The switching power supply control chip has a current detection terminal;

[0025] The input voltage acquisition circuit of the input overvoltage protection circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, and the output terminal of the overvoltage signal conversion output circuit of the input overvoltage protection circuit is electrically connected to the current detection terminal of the switching power supply control chip.

[0026] Compared with the prior art, this application has at least the following beneficial effects:

[0027] Based on further analysis and research of existing technical problems, this application recognizes that existing technologies for input protection of AC-DC switching power supplies suffer from complex implementation of input bus overvoltage detection and protection, limited system integration due to component and interface requirements, and difficulty in simultaneously ensuring the reliability and consistency of protection actions. This application addresses these issues by connecting an input voltage acquisition circuit in parallel between the DC bus voltage terminal and the ground terminal. The first voltage UDC output from the DC bus voltage terminal is sampled by voltage division to obtain a sampling voltage VREF. Therefore, when the first voltage UDC increases, the sampling voltage VREF will increase accordingly according to the voltage division relationship. Simultaneously, the input terminal of the overvoltage signal conversion output circuit is electrically connected to the input voltage acquisition circuit, and the input terminal of its internal power reference chip U2 is connected to the sampling voltage VREF. This means that the power reference chip U2 controls the sampling voltage VREF. The relationship between REF and the reference voltage of the power reference chip U2 is determined. When the sampling voltage VREF does not exceed the reference voltage, the power reference chip U2 does not drive the first transistor Q1 to conduct. When the sampling voltage VREF exceeds the reference voltage, the power reference chip U2 drives the first transistor Q1 to conduct. Since the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal CS of the switching power supply control chip, once the first transistor Q1 conducts under the drive of the power reference chip U2, it will create a boost effect on the voltage of the current detection terminal CS at the output terminal of the overvoltage signal conversion output circuit. This will cause the voltage of the current detection terminal CS to cross and trigger the overcurrent comparison threshold of the switching power supply control chip, thereby forcing the switching power supply control chip to enter its existing overcurrent protection logic to limit or stop the power switch drive. This application enables input overvoltage protection by utilizing the existing current detection terminal and overcurrent comparison mechanism of the switching power supply control chip without introducing an additional dedicated overvoltage detection interface. This reduces the complexity of external detection and control circuits and interface occupation, improves compatibility and integration convenience with different switching power supply control chips, and solves the problems of complex implementation of input overvoltage detection and protection and limited system integration caused by interface occupation in the prior art. Attached Figure Description

[0028] Figure 1 This is a block diagram of an overvoltage protection circuit for a smart fusion terminal switching power supply provided in one embodiment of this application;

[0029] Figure 2 A schematic diagram of an overvoltage protection circuit for a smart fusion terminal switching power supply provided in one embodiment of this application;

[0030] Figure 3 This is a block diagram illustrating the working principle of an AC-DC switching power supply according to an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] In one embodiment, such as Figure 1 As shown, an overvoltage protection circuit for a switching power supply of a smart fusion terminal is provided. The circuit includes an input voltage acquisition circuit and an overvoltage signal conversion and output circuit.

[0033] The input voltage acquisition circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The input voltage acquisition circuit is used to perform voltage division sampling on the first voltage output from the DC bus voltage terminal and output the sampled voltage.

[0034] The input terminal of the overvoltage signal conversion output circuit is electrically connected to the input voltage acquisition circuit, and the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal CS of the switching power supply control chip.

[0035] The overvoltage signal conversion output circuit includes a power reference chip U2 and a first transistor Q1, with the input terminal of the power reference chip U2 connected to the sampling voltage;

[0036] When the sampling voltage exceeds the reference voltage of the power reference chip U2, the power reference chip U2 drives the first transistor Q1 to turn on, causing the voltage at the current detection terminal CS to rise, thereby triggering the overcurrent comparison threshold of the switching power supply control chip.

[0037] In one embodiment, the overvoltage protection circuit for the switching power supply of the intelligent fusion terminal includes an input voltage acquisition circuit and an overvoltage signal conversion output circuit. The input voltage acquisition circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, and is used to perform voltage division sampling on the first voltage UDC output from the DC bus voltage terminal and output the sampled voltage VREF; the input terminal of the overvoltage signal conversion output circuit is electrically connected to the input voltage acquisition circuit, and the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal CS of the switching power supply control chip.

[0038] In this embodiment, the overvoltage signal conversion output circuit includes a power reference chip U2 and a first transistor Q1. The input terminal of the power reference chip U2 is connected to the sampling voltage VREF. The power reference chip U2 is used to determine the relationship between the sampling voltage VREF and its reference voltage: when the sampling voltage VREF does not exceed the reference voltage, the power reference chip U2 does not apply a conduction drive to the first transistor Q1; when the sampling voltage VREF exceeds the reference voltage, the power reference chip U2 drives the first transistor Q1 to conduct.

[0039] Since the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal CS of the switching power supply control chip, after the first transistor Q1 is turned on under the drive of the power reference chip U2, the voltage of the current detection terminal CS will rise, thereby causing the voltage of the current detection terminal CS to reach and trigger the overcurrent comparison threshold of the switching power supply control chip, and thus causing the switching power supply control chip to enter its corresponding protection control state.

[0040] In this embodiment, the first voltage UDC is converted into a sampling voltage VREF through an input voltage acquisition circuit. The power reference chip U2 uses the comparison result between the sampling voltage VREF and the reference voltage to drive the first transistor Q1, thereby raising the voltage at the current detection terminal CS and triggering the overcurrent comparison threshold of the switching power supply control chip. This achieves a protective response to the input overvoltage state, reduces the reliance on an additional dedicated overvoltage detection interface, and lowers the complexity and interface occupancy of the external protection implementation.

[0041] In this embodiment, the input voltage acquisition circuit includes a voltage divider branch formed by connecting a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, and a twelfth resistor R12 in series. The two ends of the voltage divider branch are respectively connected to the DC bus voltage terminal and the ground terminal.

[0042] The connection point between the sixth resistor R6 and the twelfth resistor R12 is the sampling voltage output terminal, which is used to output the sampling voltage.

[0043] In one embodiment, the input voltage acquisition circuit includes a voltage divider branch formed by connecting a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, and a twelfth resistor R12 in series. The two ends of this voltage divider branch are connected to the DC bus voltage terminal and the ground terminal, respectively, so that the first voltage UDC is applied across the two ends of the voltage divider branch.

[0044] In this embodiment, the connection point of the sixth resistor R6 and the twelfth resistor R12 is defined as the sampling voltage output terminal. The sampling voltage output terminal is used to output the sampling voltage VREF and serves as the input-side electrical connection node of the subsequent overvoltage signal conversion output circuit.

[0045] This embodiment uses a series voltage divider branch consisting of a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, and a twelfth resistor R12. The connection between the sixth resistor R6 and the twelfth resistor R12 is used as the sampling voltage output terminal to output the sampling voltage VREF. This enables stable voltage division sampling of the first voltage UDC, providing a clear voltage input for subsequent reference discrimination and overvoltage signal conversion.

[0046] In this embodiment, the input voltage acquisition circuit further includes a first capacitor C1, the first end of the first capacitor C1 being electrically connected to the sampling voltage output terminal, and the second end of the first capacitor C1 being electrically connected to the ground terminal.

[0047] In one embodiment, the input voltage acquisition circuit further includes a first capacitor C1, with a first end of the first capacitor C1 electrically connected to the sampling voltage output terminal and a second end of the first capacitor C1 electrically connected to the ground terminal, so that the first capacitor C1 is connected in parallel between the sampling voltage output terminal and the ground terminal.

[0048] By connecting the first capacitor C1 to the sampling voltage output terminal, the sampling voltage VREF can be smoothed to a certain extent before being output to the overvoltage signal conversion output circuit, which is suitable for application scenarios where the input voltage UDC has ripple or transient disturbances.

[0049] In this embodiment, the first capacitor C1 is connected in parallel between the sampling voltage output terminal and the ground terminal. This can filter out or attenuate the high-frequency components in the sampling voltage VREF, making the sampling voltage VREF more stably reflect the changes in the first voltage UDC. This is beneficial for the subsequent power reference chip U2 to perform threshold discrimination and drive control.

[0050] In this embodiment, the overvoltage signal conversion output circuit further includes a base bias and current limiting network, which includes a third resistor R3, a fourth resistor R4, a seventh resistor R7, and an eighth resistor R8.

[0051] The input terminal of the power reference chip U2 is connected to the sampling voltage, the ground terminal of the power reference chip U2 is electrically connected to the ground terminal, the output terminal of the power reference chip U2 is electrically connected to the first terminal of the seventh resistor R7 and the first terminal of the eighth resistor R8 respectively; the second terminal of the seventh resistor R7 is electrically connected to the base of the first transistor Q1, and the second terminal of the eighth resistor R8 is connected to the power supply voltage.

[0052] The emitter of the first transistor Q1 is connected to the power supply voltage through the fourth resistor R4;

[0053] The collector of the first transistor Q1 is electrically connected to the first end of the third resistor R3.

[0054] In one embodiment, the overvoltage signal conversion output circuit further includes a base bias and current limiting network, which includes a third resistor R3, a fourth resistor R4, a seventh resistor R7, and an eighth resistor R8. The input terminal of the power reference chip U2 is connected to the sampling voltage VREF, and the ground terminal of the power reference chip U2 is electrically connected to the ground terminal; the output terminal of the power reference chip U2 is electrically connected to the first terminal of the seventh resistor R7 and the first terminal of the eighth resistor R8, respectively.

[0055] In this embodiment, the second end of the seventh resistor R7 is electrically connected to the base of the first transistor Q1, so that the output of the power reference chip U2 can drive or bias the base of the first transistor Q1 through the seventh resistor R7; the second end of the eighth resistor R8 is connected to the supply voltage VDD, so that the output side of the power reference chip U2 and the supply voltage VDD are biased, thereby cooperating to set the driving conditions for the base of the first transistor Q1.

[0056] In this embodiment, the emitter of the first transistor Q1 is connected to the supply voltage VDD through the fourth resistor R4, so that the emitter side of the first transistor Q1 has a power supply source and forms a corresponding current limiting condition through the fourth resistor R4; the collector of the first transistor Q1 is electrically connected to the first end of the third resistor R3, so that when the first transistor Q1 is turned on, it can provide a voltage boosting path to the output side through the third resistor R3.

[0057] In this embodiment, a base bias and current limiting network composed of the third resistor R3, the fourth resistor R4, the seventh resistor R7, and the eighth resistor R8 establishes a clear connection between the output terminal of the power reference chip U2 and the base, emitter, and collector nodes of the first transistor Q1. This allows for the constraint of the conduction drive conditions and current path of the first transistor Q1, enabling the overvoltage signal conversion output circuit to convert the threshold discrimination result of the sampled voltage VREF into a controllable effect on the output voltage rise.

[0058] In this embodiment, the overvoltage signal conversion output circuit further includes a protection diode D2. The positive terminal of the protection diode D2 is electrically connected to the second terminal of the third resistor R3, and the negative terminal of the protection diode D2 is electrically connected to the current detection terminal CS.

[0059] In one embodiment, the overvoltage signal conversion output circuit further includes a protection diode D2. The positive terminal of the protection diode D2 is electrically connected to the second terminal of the third resistor R3, and the negative terminal of the protection diode D2 is electrically connected to the current detection terminal CS, so that the protection diode D2 is connected in series between the third resistor R3 and the current detection terminal CS.

[0060] Through the above polarity connection of the protection diode D2, when the overvoltage signal conversion output circuit applies a boosting effect to the current detection terminal CS, the protection diode D2 provides a corresponding unidirectional conduction path; when the current detection terminal CS experiences a reverse potential change or transient disturbance, the protection diode D2 blocks the reverse coupling path, so that the third resistor R3 and its upstream node present a controlled unidirectional connection relationship with the current detection terminal CS.

[0061] In this embodiment, the protection diode D2 is connected in series between the third resistor R3 and the current detection terminal CS and connected in the positive and negative directions. This enables unidirectional coupling between the overvoltage signal conversion output circuit and the current detection terminal CS, reducing the reverse influence of the signal on the current detection terminal CS side on the front-end bias network and the power reference chip U2 side, thereby making the overvoltage triggering and recovery process more stable.

[0062] In this embodiment, the power reference chip U2 is a power reference chip TL431, and the reference voltage of the power reference chip U2 is 2.5V.

[0063] In one embodiment, the power reference chip U2 is a TL431 power reference chip, and the reference voltage of the power reference chip U2 is 2.5V. After the sampling voltage VREF is connected to the input terminal of the power reference chip U2, the power reference chip U2 uses its reference voltage as a threshold to distinguish the sampling voltage VREF.

[0064] When the sampling voltage VREF does not exceed 2.5V, the power reference chip U2 remains in a state where it does not drive the first transistor Q1 to conduct; when the sampling voltage VREF exceeds 2.5V, the power reference chip U2 enters the corresponding conduction / output state to drive the first transistor Q1 to conduct, and then acts on the current detection terminal CS through the subsequent stage connection.

[0065] In this embodiment, the power reference chip TL431 is used as the power reference chip U2 and 2.5V is used as the reference voltage. This provides a clear threshold discrimination benchmark for the sampling voltage VREF, so that the input overvoltage discrimination condition has an achievable device basis and a definite threshold reference.

[0066] In this embodiment, the first transistor Q1 is a PNP transistor.

[0067] In one embodiment, the first transistor Q1 is a PNP transistor. Based on the conduction characteristics of a PNP transistor, the first transistor Q1 enters the conduction state when its base potential satisfies the corresponding bias condition relative to the emitter, thereby forming a voltage / current path related to the output terminal on its collector side.

[0068] In the above embodiment, the emitter of the first transistor Q1 is connected to the supply voltage VDD through the fourth resistor R4, and the collector is connected to the third resistor R3. When the first transistor Q1 is turned on, it can use the supply voltage VDD to generate the driving source required for the current detection terminal CS to be raised, and establish an output coupling path with the current detection terminal CS through the third resistor R3 and subsequent devices.

[0069] By limiting the first transistor Q1 to a PNP transistor, it is beneficial to provide the conduction path required for the voltage rise of the current detection terminal CS on the supply voltage VDD side, so that the driving relationship of the overvoltage signal conversion output circuit is matched with the conduction direction of the device, which facilitates the control of the rise of the current detection terminal CS.

[0070] In this embodiment, the voltage division ratio of the input voltage acquisition circuit is configured such that when the first voltage reaches a preset overvoltage threshold, the sampling voltage reaches or exceeds the reference voltage of the power reference chip U2.

[0071] In one embodiment, the voltage division ratio of the input voltage acquisition circuit is configured such that when the first voltage UDC reaches a preset overvoltage threshold, the sampling voltage VREF reaches or exceeds the reference voltage of the power reference chip U2. Specifically, the sampling voltage VREF and the first voltage UDC can satisfy a preset correspondence by selecting the resistance ratio of the first resistor R1, the second resistor R2, the fifth resistor R5, the sixth resistor R6, and the twelfth resistor R12.

[0072] When the first voltage UDC rises to the preset overvoltage threshold range, and the sampling voltage VREF reaches or exceeds the reference voltage of the power reference chip U2, the power reference chip U2 applies a conduction drive to the first transistor Q1, which in turn raises the voltage at the current detection terminal CS and triggers the overcurrent comparison threshold of the switching power supply control chip, thereby realizing the closed loop of the overvoltage triggering link.

[0073] This embodiment configures the voltage division ratio so that when the first voltage UDC reaches the preset overvoltage threshold, the sampling voltage VREF can reach or exceed the reference voltage of the power reference chip U2. The input overvoltage threshold can be clearly mapped to the threshold discrimination condition of the power reference chip U2, thereby realizing a protection trigger design with a settable and adjustable input overvoltage threshold.

[0074] The circuit in this embodiment mainly includes an input voltage acquisition circuit and an overvoltage signal conversion and output circuit. The input voltage acquisition circuit includes a first resistor R1, a second resistor R2, a fifth resistor R5, a sixth resistor R6, a twelfth resistor R12, and a first capacitor C1.

[0075] The overvoltage signal conversion and output circuit includes a power reference chip U2, a third resistor R3, a fourth resistor R4, a seventh resistor R7, an eighth resistor R8, a protection diode D2, and a first transistor Q1 (PNP transistor).

[0076] The selection of components in the circuit of this embodiment can be made according to actual needs. The selection parameters in this scheme are as follows: Figure 2As shown: the first resistor R1, the second resistor R2, the fifth resistor R5, and the sixth resistor R6 are all 1MΩ, the twelfth resistor R12 is 27kΩ, the first capacitor C1 is 100nF, the power reference chip U2 is a TL431 with a reference voltage of 2.5V, the third resistor R3 is 1kΩ, the fourth resistor R4 and the eighth resistor R8 are both 4.7kΩ, the seventh resistor R7 is 20kΩ, the protection diode D2 is a 1N4148, the first transistor Q1 (PNP transistor) is an LMBT3906LT1G, and the switching power supply control chip is an ME8204B.

[0077] The network labels of the circuit are as follows: the first voltage UDC is the input voltage after rectification and filtering, the ground terminal GND is the reference ground, the supply voltage VDD is the power supply of the switching power supply control chip, the sampling voltage VREF is the feedback input of the power reference chip U2 (TL431), and the current detection terminal CS is the overcurrent detection terminal of the switching power supply control chip, and also serves as the output terminal of the overvoltage signal.

[0078] The key working principle of this application is as follows: The power supply voltage VDD of the switching power supply control chip is generally DC 10V~30V, and in this scheme, the power supply voltage VDD is 15V; and in this scheme, the overcurrent protection action voltage triggered by the current detection terminal CS pin of the switching power supply control chip is >0.875V. First, the first voltage UDC is divided by the first resistor R1, the second resistor R2, the fifth resistor R5, the sixth resistor R6, and the twelfth resistor R12 to obtain the sampling voltage VREF, and the sampling voltage VREF is connected to the feedback pin of the power reference chip U2 (TL431), while the first capacitor C1 filters out high-frequency noise. When the sampling voltage VREF is less than or equal to the reference voltage 2.5V of the power reference chip U2, no current flows into the power reference chip U2, there is no voltage drop between the emitter and base of the first transistor Q1, the first transistor Q1 is in an open circuit state, and the voltage at the current detection terminal CS is dominated by the overcurrent detection voltage. When the sampling voltage VREF is greater than 2.5V, current flows through the power reference chip U2, a voltage drop is formed between the emitter and base of the first transistor Q1, the first transistor Q1 is turned on, and the voltage at the current detection terminal CS will increase with the increase of the first voltage UDC. When the voltage at the current detection terminal CS is higher than 0.875V, the overcurrent protection function of the switching power supply control chip is triggered, thereby protecting the power switching devices.

[0079] Combination Figure 2Case study: In the example, the nominal input voltage UDC of the switching power supply has an upper limit of 700V and a limit input voltage of 900V. The supply voltage VDD is a stable 15V. Therefore, it is designed to enter overvoltage protection when the first voltage UDC is higher than 800V. In this example, since the first transistor Q1 is an analog device, current can flow through it even when the base current is very weak. Combining this with the current-limiting resistors R10 and R13 at the current detection terminal CS of the switching power supply control chip, a rough calculation can be performed: When the first voltage UDC = 800V, VREF = UDC / (R1+R2+R5+R6+R12)*R12 = 800V / (4000k+13k)*13k = 2.59V; the theoretically calculated voltage at the current detection terminal CS is VCS = (VDD-D2-Q1) / (R3+R4+R10+R13)*(R10+R13) = (15V-0.7V-0.3V) / (1000+4700+1000+2)*(R10+R13) = 2.09V, which is much higher than the detection voltage of 0.875V, thus triggering the protection action.

[0080] like Figure 3 As shown, the AC input is rectified by a full-bridge converter to obtain a pulsating DC voltage. This voltage is then filtered and stored by a filter and energy storage capacitor, forming a first voltage UDC at the DC bus voltage terminal, with the ground terminal GND used as a reference ground. This first voltage UDC provides DC bus power to the main power converter. Energy from the DC bus side is transferred to the secondary side via an isolation transformer. The secondary side obtains a stable DC output through output rectification and filtering circuits. On the primary side, MOSFETs act as power switching devices to control the high-frequency switching of the isolation transformer's primary side. The power chip outputs drive control signals to the MOSFETs and manages their operating status. The power chip also acquires switching current information through a current sensing module. Its current sensing signal is typically connected to the power chip's current sensing terminal CS for overcurrent comparison and protection control.

[0081] The input overvoltage protection circuit provided in this application corresponds to Figure 3 The input overvoltage protection circuit in the power supply chip samples the first voltage UDC of the DC bus voltage terminal in parallel and outputs a sampling voltage VREF. Its output terminal is connected to the current detection terminal CS of the power supply chip. When the first voltage UDC is overvoltaged and the sampling voltage VREF exceeds the reference condition, the voltage of the current detection terminal CS is boosted through the overvoltage signal conversion output path, thereby triggering the overcurrent comparison threshold of the power supply chip to enter the corresponding protection state.

[0082] In one embodiment, an AC-DC switching power supply is provided, including a rectifier and filter unit, a switching power supply control chip, and the input overvoltage protection circuit described in the above embodiment.

[0083] The input terminal of the rectifier and filter unit is used to connect to AC mains power, and the output terminal of the rectifier and filter unit is the output DC bus voltage terminal, which outputs a first voltage.

[0084] The switching power supply control chip has a current detection terminal;

[0085] The input voltage acquisition circuit of the input overvoltage protection circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, and the output terminal of the overvoltage signal conversion output circuit of the input overvoltage protection circuit is electrically connected to the current detection terminal of the switching power supply control chip.

[0086] In one embodiment, the AC-DC switching power supply includes a rectifier and filter unit, a switching power supply control chip, and the input overvoltage protection circuit described in the above embodiment. The input terminal of the rectifier and filter unit is used to connect to AC mains power, and its output terminal is used to output a DC bus voltage terminal, and outputs a first voltage UDC at the DC bus voltage terminal.

[0087] In this embodiment, the input voltage acquisition circuit of the input overvoltage protection circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, so as to perform voltage division sampling on the first voltage UDC and output the sampling voltage VREF; the output terminal of the overvoltage signal conversion output circuit of the input overvoltage protection circuit is electrically connected to the current detection terminal CS of the switching power supply control chip, so as to apply the voltage rise effect when overvoltage is triggered to the current detection terminal CS.

[0088] When the first voltage UDC is within the normal range, the sampling voltage VREF does not exceed the reference voltage of the power supply reference chip U2, and the overvoltage signal conversion output circuit does not raise the current detection terminal CS. When the first voltage UDC exceeds the preset overvoltage threshold and the sampling voltage VREF exceeds the reference voltage of the power supply reference chip U2, the overvoltage signal conversion output circuit raises the current detection terminal CS, thereby triggering the overcurrent comparison threshold of the switching power supply control chip, and the switching power supply control chip enters the corresponding protection control state accordingly.

[0089] This embodiment integrates the input overvoltage protection circuit into the AC-DC switching power supply, and makes the output terminal of the overvoltage signal conversion output circuit directly act on the current detection terminal CS of the switching power supply control chip. When an overvoltage occurs in the first voltage UDC formed by rectification and filtering, the existing overcurrent comparison threshold triggering mechanism of the control chip can be used to realize the input overvoltage protection response, thereby reducing the need for additional overvoltage detection interfaces at the system level and simplifying the implementation path of input overvoltage protection.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. An overvoltage protection circuit for a switching power supply in a smart converged terminal, characterized in that, The circuit includes an input voltage acquisition circuit and an overvoltage signal conversion and output circuit; The input voltage acquisition circuit is connected in parallel between the DC bus voltage terminal and the ground terminal. The input voltage acquisition circuit is used to perform voltage division sampling on the first voltage output from the DC bus voltage terminal and output the sampled voltage. The input terminal of the overvoltage signal conversion output circuit is electrically connected to the input voltage acquisition circuit, and the output terminal of the overvoltage signal conversion output circuit is electrically connected to the current detection terminal (CS) of the switching power supply control chip. The overvoltage signal conversion output circuit includes a power reference chip (U2) and a first transistor (Q1), and the input terminal of the power reference chip (U2) is connected to the sampling voltage; When the sampling voltage exceeds the reference voltage of the power reference chip (U2), the power reference chip (U2) drives the first transistor (Q1) to turn on, causing the voltage of the current detection terminal (CS) to rise, thereby triggering the overcurrent comparison threshold of the switching power supply control chip.

2. The circuit according to claim 1, characterized in that, The input voltage acquisition circuit includes a voltage divider branch formed by connecting the first resistor (R1), the second resistor (R2), the fifth resistor (R5), the sixth resistor (R6), and the twelfth resistor (R12) in series. The two ends of the voltage divider branch are respectively connected to the DC bus voltage terminal and the ground terminal. The connection point between the sixth resistor (R6) and the twelfth resistor (R12) is the sampling voltage output terminal, which is used to output the sampling voltage.

3. The circuit according to claim 2, characterized in that, The input voltage acquisition circuit also includes a first capacitor (C1), the first end of which is electrically connected to the sampling voltage output terminal, and the second end of which is electrically connected to the ground terminal.

4. The circuit according to claim 1, characterized in that, The overvoltage signal conversion output circuit also includes a base bias and current limiting network, which includes a third resistor (R3), a fourth resistor (R4), a seventh resistor (R7), and an eighth resistor (R8). The input terminal of the power reference chip (U2) is connected to the sampling voltage, the ground terminal of the power reference chip (U2) is electrically connected to the ground terminal, the output terminal of the power reference chip (U2) is electrically connected to the first terminal of the seventh resistor (R7) and the first terminal of the eighth resistor (R8); the second terminal of the seventh resistor (R7) is electrically connected to the base of the first transistor (Q1), and the second terminal of the eighth resistor (R8) is connected to the supply voltage. The emitter of the first transistor (Q1) is connected to the power supply voltage through the fourth resistor (R4); The collector of the first transistor (Q1) is electrically connected to the first terminal of the third resistor (R3).

5. The circuit according to claim 4, characterized in that, The overvoltage signal conversion output circuit also includes a protection diode (D2), the positive terminal of which is electrically connected to the second terminal of the third resistor (R3), and the negative terminal of which is electrically connected to the current detection terminal (CS).

6. The circuit according to claim 1, characterized in that, The power reference chip (U2) is a TL431 power reference chip, and the reference voltage of the power reference chip (U2) is 2.5V.

7. The circuit according to claim 1, characterized in that, The first transistor (Q1) is a PNP transistor.

8. The circuit according to claim 1, characterized in that, The voltage division ratio of the input voltage acquisition circuit is configured such that when the first voltage reaches a preset overvoltage threshold, the sampled voltage reaches or exceeds the reference voltage of the power reference chip (U2).

9. A switching power supply, characterized in that, Includes a rectifier and filter unit, a switching power supply control chip, and an input overvoltage protection circuit as described in any one of claims 1 to 8; The input terminal of the rectifier and filter unit is used to connect to AC mains power, and the output terminal of the rectifier and filter unit is the output DC bus voltage terminal, which outputs a first voltage. The switching power supply control chip has a current detection terminal; The input voltage acquisition circuit of the input overvoltage protection circuit is connected in parallel between the DC bus voltage terminal and the ground terminal, and the output terminal of the overvoltage signal conversion output circuit of the input overvoltage protection circuit is electrically connected to the current detection terminal of the switching power supply control chip.

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