CRM boost pfc conversion circuit, switching power supply chip and electronic device

Abstract

This application belongs to the field of electronic circuits and provides a CRM boost PFC converter circuit, a switching power supply chip, and an electronic device. The circuit includes a first control module, a second control module, a drive module, and a conversion module. The drive terminal of the conversion module is connected to both the drive module and the first control module. The zero-crossing detection terminal of the conversion module is connected to the first control module. The current sampling terminal of the conversion module is connected to both the first and second control modules. The second control module is connected to the compensation terminal, feedback terminal, and voltage sampling terminal of the conversion module. The first control module is connected to both the second control module and the drive module. The second control module is also connected to the drive module. The CRM boost PFC converter circuit provided in this application solves the problem that traditional CRM boost PFC converters cannot suppress entry into deep CCM mode, reduces the current stress on the switching transistors in the conversion module, and avoids drive oscillation.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a CRM boost PFC converter circuit, a switching power supply chip, and an electronic device. Background Technology

[0002] With the development of smart electronic products, the power and efficiency requirements of power supplies are constantly increasing, and high-frequency switching power supplies are being used more and more widely in daily life. Under the current concept of "green power," power supplies must be free from "pollution" to the power grid. This "pollution" mainly includes harmonic content, power factor, and waveform distortion. This "pollution" can affect the safe and economical operation of other electrical equipment along transmission lines, such as causing additional power losses to generators and transformers, and interfering with relays and automatic protection devices, leading to malfunctions. Therefore, preventing and reducing "pollution" to the power grid has become an issue that cannot be ignored. The most direct way to solve these problems is to adopt power factor correction technology.

[0003] A Power Factor Correction (PFC) converter is a power conversion device used to improve the power factor of a power system. A CRM boost PFC converter combines a CRM (Critical Conduction Mode) boost converter with power factor correction technology. CRM refers to the inductor of this boost converter operating in a critical current mode. This is in contrast to CCM (Continuous Current Mode) and DCM (Discontinuous Current Mode). PFC technology aims to eliminate the problem of power factor degradation in power systems caused by nonlinear loads, thereby improving the efficiency and stability of the power system.

[0004] Traditional CRM boost PFC converters achieve inductor current CRM by adding an auxiliary winding to the inductor. Changes in the voltage across this auxiliary winding (i.e., a zero-crossing detection signal) determine whether the inductor current has crossed zero, thus determining the turn-on time of the switching transistor. However, this method has limitations: the zero-crossing detection signal disappears when the potentials across the inductor are equal; if the controller does not detect a zero-crossing detection signal within a certain time, it will force the switching transistor to turn on, causing the converter to be unable to maintain CRM mode at all times, and potentially even entering deep CCM mode. In deep CCM mode, the switching transistor operates in a hard-switching state. At the moment of turn-on, a very large current flows rapidly from the drain to the source of the switching transistor, resulting in a large current change rate. If parasitic inductance exists in the circuit, it can cause severe oscillations and spikes in the voltage between the drain and source and between the gate and source of the switching transistor, potentially damaging the switching transistor and affecting the safe operation of the chip. Summary of the Invention

[0005] This application provides a CRM boost PFC converter circuit, a switching power supply chip, and an electronic device, which can solve the problem that traditional CRM boost PFC converters cannot suppress entering deep CCM mode.

[0006] In a first aspect, embodiments of this application provide a CRM boost-type PFC converter circuit, including a first control module, a second control module, a drive module, and a conversion module. The drive terminal of the conversion module is connected to the drive module and the first control module, respectively. The zero-crossing detection terminal of the conversion module is connected to the first control module. The current sampling terminal of the conversion module is connected to the first control module and the second control module, respectively. The second control module is connected to the compensation terminal, feedback terminal, and voltage sampling terminal of the conversion module, respectively. The first control module is connected to the second control module and the drive module, respectively. The second control module is connected to the drive module.

[0007] The conversion module is used to convert the power supply voltage according to the drive signal to obtain the output voltage, and output a zero-crossing detection signal, a current sampling signal, a voltage sampling signal, a feedback voltage signal, and an error voltage compensation signal; the first control module is used to generate a time window according to the drive signal; and simultaneously output a start signal according to the drive signal, the start signal becoming high at a first preset time interval, and outputting a start detection signal when the start signal becomes high; it is also used to compare the current sampling signal with a first threshold according to the drive signal, and output a protection signal when the current sampling signal is detected to be greater than the first threshold within the time window and lasts for a second preset time; it is also used to... The zero-crossing detection signal is processed to obtain a first signal, and the first signal is shielded according to the start signal and the protection signal; it is also used to output a conduction signal according to the start signal and the first signal; it is also used to switch the current sampling protection threshold from a second threshold to a third threshold according to the start detection signal, and output a comparison signal according to the current sampling signal and the third threshold; the second control module is used to output a shutdown signal according to the current sampling signal, the voltage sampling signal, the feedback voltage signal, the error voltage compensation signal and the comparison signal; the drive module is used to output a drive signal according to the conduction signal and the shutdown signal; wherein, the third threshold is less than the second threshold.

[0008] In one possible implementation of the first aspect, the first control module includes a signal processing module, a signal generation module, a time window generation module, a first comparison module, a second comparison module, a signal shielding module, and a logic module; the input terminal of the signal processing module is connected to the zero-crossing detection terminal of the transformation module, the output terminal of the signal processing module is connected to the first input terminals of the signal shielding module and the logic module respectively, the input terminal of the signal generation module is connected to the input terminal of the time window generation module, the first input terminal of the first comparison module, and the driving terminal of the transformation module respectively, the first output terminal of the signal generation module is connected to the second input terminals of the signal shielding module and the logic module respectively, the second output terminal of the signal generation module is connected to the first input terminal of the second comparison module, the output terminal of the time window generation module is connected to the second input terminal of the first comparison module, the third input terminal of the first comparison module is connected to the second input terminal of the second comparison module and the current sampling terminal of the transformation module respectively, the output terminal of the first comparison module is connected to the signal shielding module, the output terminal of the second comparison module is connected to the second control module, and the output terminal of the logic module is connected to the driving module;

[0009] The signal processing module processes the zero-crossing detection signal to obtain a first signal; the signal generation module outputs a start signal according to the drive signal, the start signal going high every first preset time interval, and outputs a start detection signal when the start signal goes high; the time window generation module generates a time window according to the drive signal; the first comparison module compares the current sampling signal and the first threshold according to the drive signal, and outputs a protection signal when the current sampling signal is detected to be greater than the first threshold and lasts for a second preset time within the time window; the signal shielding module shields the first signal according to the start signal and the protection signal; the logic module outputs a conduction signal according to the start signal and the first signal; the second comparison module switches the current sampling protection threshold from a second threshold to a third threshold according to the start detection signal, and outputs a comparison signal according to the current sampling signal and the third threshold.

[0010] In one possible implementation of the first aspect, the signal generation module includes a first current source, a first switch, a first capacitor, a first power supply, and a first comparator. The input terminal of the first current source receives the power supply voltage. The output terminal of the first current source is connected to the first terminal of the first switch, the positive terminal of the first capacitor, and the first input terminal of the first comparator. The negative terminal of the first capacitor, the second terminal of the first switch, and the third terminal of the first switch are all grounded. The fourth terminal of the first switch is connected to the input terminal of the time window generation module, the first input terminal of the first comparison module, and the driving terminal of the conversion module. The second input terminal of the first comparator is connected to the positive terminal of the first power supply, the negative terminal of the first power supply is grounded, and the output terminal of the first comparator is connected to the second input terminal of the signal shielding module and the logic module.

[0011] The signal generation module further includes a signal generation unit, which is connected to the output terminal of the first comparator and the first input terminal of the second comparison module, respectively.

[0012] The signal generation unit is used to generate a start detection signal based on the start signal.

[0013] In one possible implementation of the first aspect, the time window generation module includes a first NOT gate, a first AND gate, a first RS flip-flop, a first diode, a second switch, a second capacitor, a second current source, a second power supply, and a second comparator. The input terminal of the first NOT gate is connected to the first input terminal of the first AND gate, the input terminal of the signal generation module, the first input terminal of the first comparison module, and the driving terminal of the conversion module, respectively. The output terminal of the first NOT gate is connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is connected to the S terminal of the first RS flip-flop. The Q terminal of the first RS flip-flop is connected to the second input terminal of the first comparison module. The R terminal of the first RS flip-flop is connected to the output terminal of the second comparator. The QN terminal of the first RS flip-flop is connected to the fourth terminal of the second switch. The first terminal of the second switch is connected to the positive terminal of the second capacitor, the cathode of the first diode, the first input terminal of the second comparator, and the output terminal of the second current source, respectively. The input terminal of the second current source receives the power supply voltage. The anode of the first diode, the cathode of the second capacitor, the second terminal of the second switch, and the third terminal of the second switch are all grounded. The second input terminal of the second comparator is connected to the positive terminal of the second power supply, and the negative terminal of the second power supply is grounded.

[0014] In one possible implementation of the first aspect, the first comparison module includes a third switch, a third power supply, a third comparator, a fourth switch, a third capacitor, a second diode, a fourth power supply, a third current source, a fourth comparator, a second AND gate, a second NOT gate, a third AND gate, and a fourth AND gate. The first terminal of the third switch serves as the third input terminal of the first comparison module, and the fourth terminal of the third switch serves as the first input terminal of the first comparison module. The second terminal of the third switch is connected to the second input terminal of the third comparator, and the third terminal of the third switch is grounded. The first input terminal of the third comparator is connected to the positive terminal of the third power supply, and the negative terminal of the third power supply is grounded. The voltage provided by the third power supply is a first threshold value. The first output terminal of the third comparator is connected to the fourth terminal of the fourth switch, and the second output terminal of the third comparator is connected to the first input terminal of the second AND gate. The first terminal of the fourth switch is connected to the third diode, a third power supply, a third current source, a fourth current source, a second AND gate, a second NOT gate, a third AND gate, and a fourth AND gate. The positive terminal of the three capacitors, the cathode of the second diode, the first input terminal of the fourth comparator, and the output terminal of the third current source are connected. The input terminal of the third current source receives the power supply voltage. The second input terminal of the fourth comparator is connected to the positive terminal of the fourth power supply. The negative terminal of the fourth power supply, the anode of the second diode, the negative terminal of the third capacitor, the second terminal of the fourth switch, and the third terminal of the fourth switch are all grounded. The output terminal of the fourth comparator is connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is connected to the input terminal of the second NOT gate and the first input terminal of the third AND gate. The output terminal of the second NOT gate is connected to the second input terminal of the third AND gate. The output terminal of the third AND gate is connected to the first input terminal of the fourth AND gate. The second input terminal of the fourth AND gate serves as the second input terminal of the first comparison module, and the output terminal of the fourth AND gate serves as the output terminal of the first comparison module.

[0015] In one possible implementation of the first aspect, the second comparison module includes a fifth switch, a fifth comparator, a first resistor, and a fifth power supply. The positive terminal of the fifth power supply is connected to the first terminal of the fifth switch and the second input terminal of the fifth comparator, respectively. The negative terminal of the fifth power supply is grounded. The voltage provided by the fifth power supply is a second threshold. The second terminal of the fifth switch is connected to the first terminal of the first resistor. The fourth terminal of the fifth switch serves as the first input terminal of the second comparison module. The third terminal of the fifth switch and the second terminal of the first resistor are both grounded. The first input terminal of the fifth comparator serves as the second input terminal of the second comparison module. The output terminal of the fifth comparator serves as the output terminal of the second comparison module.

[0016] In one possible implementation of the first aspect, the signal shielding module includes a second RS flip-flop, a third NOT gate, a fifth AND gate, and a sixth switch. The S terminal of the second RS flip-flop is connected to the output terminal of the first comparison module, the R terminal of the second RS flip-flop is connected to the output terminal of the fifth AND gate, the input terminal of the third NOT gate is connected to the first input terminal of the fifth AND gate and the first output terminal of the signal generation module, the output terminal of the third NOT gate is connected to the second input terminal of the fifth AND gate, the Q terminal of the second RS flip-flop is connected to the fourth terminal of the sixth switch, the first terminal of the sixth switch is connected to the output terminal of the signal processing module, and both the second and third terminals of the sixth switch are grounded.

[0017] In one possible implementation of the first aspect, the logic module includes an OR gate, the first input of which is connected to the output of the signal processing module and the signal shielding module, the second input of which is connected to the output of the signal generation module and the signal shielding module, and the output of which is connected to the driving module.

[0018] Secondly, embodiments of this application provide a switching power supply chip, including the CRM boost PFC converter circuit described in any one of the first aspects.

[0019] Thirdly, embodiments of this application provide an electronic device including the switching power supply chip described in any one of the second aspects.

[0020] The beneficial effects of the embodiments in this application compared with the prior art are:

[0021] This application provides a CRM boost-type PFC converter circuit, including a first control module, a second control module, a drive module, and a conversion module. The drive terminal of the conversion module is connected to the drive module and the first control module, respectively. The zero-crossing detection terminal of the conversion module is connected to the first control module, and the current sampling terminal of the conversion module is connected to the first control module and the second control module, respectively. The second control module is connected to the compensation terminal, feedback terminal, and voltage sampling terminal of the conversion module, respectively. The first control module is connected to the second control module and the drive module, respectively. The second control module is connected to the drive module.

[0022] The conversion module is used to convert the power supply voltage according to the drive signal to obtain the output voltage, and output zero-crossing detection signal, current sampling signal, voltage sampling signal, feedback voltage signal and error voltage compensation signal.

[0023] The first control module is used to generate a time window based on the drive signal; at the same time, it outputs a start signal based on the drive time. The start signal goes high every first preset time, and a start detection signal is output when the start signal goes high.

[0024] The first control module is also used to compare the current sampling signal and the first threshold according to the drive signal. When the current sampling signal is detected to be greater than the first threshold within the time window and lasts for a second preset time, a protection signal is output. The protection signal is used to characterize the circuit entering the deep CCM mode.

[0025] The first control module is also used to process the zero-crossing detection signal to obtain a first signal, and to shield the first signal according to the start signal and the protection signal;

[0026] The first control module is also used to output a conduction signal based on the start signal and the first signal;

[0027] The first control module is also used to switch the current sampling protection threshold from the second threshold to the third threshold according to the start detection signal, and output a comparison signal according to the current sampling signal and the third threshold. The second threshold is the current sampling protection threshold when the circuit is operating normally, and the third threshold is the current sampling protection threshold when the circuit enters deep CCM mode and outputs a conduction signal from the start signal, and the third threshold is less than the second threshold.

[0028] The second control module outputs a shutdown signal based on the current sampling signal, voltage sampling signal, feedback voltage signal, error voltage compensation signal, and comparison signal. The drive module outputs a drive signal based on the turn-on and shutdown signals.

[0029] When the circuit is turned on and the zero-crossing detection signal is 0, the first signal is also 0 after processing because the zero-crossing detection signal is 0. At this time, the conduction signal output by the first control module is the start signal, and the current sampling protection threshold is switched to the third threshold. This reduces the current sampling protection threshold when the conduction signal is the start signal, minimizes the conduction time of the switching transistor in the conversion module, reduces the turn-on current, and thus suppresses the depth of CCM mode.

[0030] When the circuit is turned on and the output voltage is not zero, the zero-crossing detection signal will gradually decrease and become zero. The first control module will first identify the deep CCM mode: it compares the current sampling signal with the first threshold based on the drive signal. When the current sampling signal is detected to be greater than the first threshold within the time window and lasts for a second preset time, a protection signal is output, indicating that the deep CCM mode has been identified. When the deep CCM mode is identified, the first signal is shielded according to the start signal and the protection signal. At this time, the conduction signal is the start signal. By extending the demagnetization time of the inductor in the conversion module, the CCM mode is prevented from deepening further. At the same time, the current sampling protection threshold is switched to the third threshold, reducing the current sampling protection threshold when the conduction signal is the start signal, reducing the turn-on current, and thus suppressing the depth of the CCM mode.

[0031] In summary, the CRM boost PFC converter circuit provided in this application solves the problem that traditional CRM boost PFC converters cannot suppress entry into deep CCM mode.

[0032] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a traditional CRM boost PFC converter;

[0035] Figure 2 This is a schematic diagram of key waveforms in a traditional CRM boost PFC converter;

[0036] Figure 3 This is a schematic diagram of the key waveforms when a traditional CRM boost PFC converter enters deep CCM mode during simulation. Figure 1 ;

[0037] Figure 4 This is a schematic diagram of the key waveforms when a traditional CRM boost PFC converter enters deep CCM mode during simulation. Figure 2 ;

[0038] Figure 5 This is a schematic diagram of a CRM boost PFC converter circuit provided in an embodiment of this application;

[0039] Figure 6 This is a schematic diagram of a CRM boost PFC converter circuit provided in another embodiment of this application;

[0040] Figure 7 This is a circuit connection diagram of the signal generation module in this application;

[0041] Figure 8 This is a circuit connection diagram of the time window generation module in this application;

[0042] Figure 9 This is a circuit connection diagram of the first comparison module in this application;

[0043] Figure 10 This is a circuit connection diagram of the second comparison module in this application;

[0044] Figure 11 This is a circuit connection diagram of the signal shielding module in this application;

[0045] Figure 12 This is a circuit connection diagram of the logic module in this application;

[0046] Figure 13 This is a simulation waveform diagram of this application. Figure 1 ;

[0047] Figure 14 This is a simulation waveform diagram of this application. Figure 2 .

[0048] In the diagram: 10, First control module; 11, Signal processing module; 12, Signal generation module; 121, Signal generation unit; 13, Time window generation module; 14, First comparison module; 15, Second comparison module; 16, Signal shielding module; 17, Logic module; 20, Second control module; 30, Drive module; 40, Transformation module. Detailed Implementation

[0049] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0050] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0051] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0052] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0053] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0054] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0055] The traditional CRM boost PFC converter achieves inductor current CRM by adding an auxiliary winding to the inductor. Changes in the voltage across this auxiliary winding (i.e., a zero-crossing detection signal) determine whether the inductor current has crossed zero, thus determining the turn-on time of the switching transistor. The structure of a traditional CRM boost PFC converter is as follows: Figure 1 As shown, it mainly consists of a controller and a conversion module 40. Here, VRec represents the output voltage of the rectifier bridge, Vmult represents the voltage sampling signal (i.e., the voltage signal after voltage division and sampling of VRec), Vaux represents the voltage on the auxiliary winding Aw, VOUT represents the output voltage, VDD represents the power supply voltage of the controller, VDS represents the drain-source voltage of the switching transistor M1, VZCD represents the zero-crossing detection signal, VCS represents the current sampling signal, VFB represents the feedback voltage signal, Vcomp represents the error voltage compensation signal, and VG... The following parameters represent the driving signal: the common terminal of resistors R01 and R02 serves as the voltage sampling terminal of the conversion module 40; the common terminal of resistor R03 and capacitor C02 serves as the zero-crossing detection terminal of the conversion module 40; the common terminal of resistor R08 and capacitor C05 serves as the current sampling terminal of the conversion module 40; the gate of switch M1 serves as the driving terminal of the conversion module 40; the common terminal of resistors R05, R06, capacitors C06 and C07 serves as the feedback terminal of the conversion module 40; and the common terminal of resistor R09 and capacitor C07 serves as the compensation terminal of the conversion module 40. The working principle of the conversion module 40 can be found in the description of relevant prior art, and will not be repeated here.

[0056] Key waveforms of traditional CRM boost PFC converters are as follows: Figure 2 As shown, from Figure 2It can be seen that the controller determines the timing of the drive signal VG going high by using the zero-crossing detection signal VZCD. For example, when the zero-crossing detection signal VZCD first rises to 2.1V and then falls to 1.4V, it determines that the inductor current IL has crossed zero and turns on the switch M1. However, this method has limitations: when the potentials across the inductor L are equal, the zero-crossing detection signal VZCD will disappear; if the controller does not detect the zero-crossing detection signal VZCD within a certain time, such as 160us, it will force the switch M1 to turn on, causing the converter to be unable to maintain CRM mode at any time, and may even enter deep CCM mode.

[0057] There are two cases where the potentials across inductor L are equal. The first case is as follows: Figure 3 As shown, when the converter is turned on, the output voltage VOUT is not 0, from Figure 3 The simulation waveforms show that the zero-crossing detection signal VZCD exists after the converter is turned on. As the output voltage VOUT gradually rises to near the input voltage, the zero-crossing detection signal VZCD decreases until it becomes 0, at which point the converter enters deep CCM mode. The second type... Figure 4 As shown, when the converter is turned on, the zero-crossing detection signal VZCD is 0, and the converter enters deep CCM mode.

[0058] In deep CCM mode, the switching transistor M1 will be in a hard-switching state. At the moment of turn-on, a very large current flows rapidly from the drain to the source of the switching transistor M1, resulting in a large current change rate. If parasitic inductance exists in the circuit, it will cause severe oscillations and spikes in the voltage between the drain and source and between the gate and source of the switching transistor, which may damage the switching transistor and affect the safe use of the chip.

[0059] To address the aforementioned issues, this application provides a CRM boost-type PFC converter circuit. When the circuit is turned on and the zero-crossing detection signal VZCD is 0, the turn-on signal output by the first control module is the start signal, and the current sampling protection threshold is switched to the third threshold. This reduces the current sampling protection threshold when the turn-on signal is the start signal, thereby minimizing the conduction time of the switching transistor M1 in the converter module 40, reducing the turn-on current, and thus suppressing the depth of the CCM mode.

[0060] When the circuit is turned on and the output voltage is not zero, the zero-crossing detection signal VZCD gradually decreases and becomes 0. The first control module first identifies the deep CCM mode: it compares the current sampling signal VCS with the first threshold based on the drive signal VG. When the current sampling signal VCS is detected to be greater than the first threshold within the time window and lasts for a second preset time, a protection signal is output, indicating that the deep CCM mode has been identified. When the deep CCM mode is identified, the zero-crossing detection signal VZCD is shielded. At this time, the conduction signal is the start signal. By extending the demagnetization time of the inductor L in the conversion module 40, the CCM mode is prevented from deepening further. At the same time, the current sampling protection threshold is switched to the third threshold, reducing the current sampling protection threshold when the conduction signal is the start signal, reducing the turn-on current, and thus suppressing the depth of the CCM mode.

[0061] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0062] Figure 5 A schematic diagram of the CRM boost-type PFC converter circuit provided in an embodiment of this application is shown. Figure 5 As shown, a CRM boost-type PFC converter circuit includes a first control module 10, a second control module 20, a drive module 30, and a conversion module 40. The drive terminal of the conversion module 40 is connected to the drive module 30 and the first control module 10, respectively. The zero-crossing detection terminal of the conversion module 40 is connected to the first control module 10, and the current sampling terminal of the conversion module 40 is connected to the first control module 10 and the second control module 20, respectively. The second control module 20 is connected to the compensation terminal, feedback terminal, and voltage sampling terminal of the conversion module 40, respectively. The first control module 10 is connected to the second control module 20 and the drive module 30, respectively. The second control module 20 is connected to the drive module 30.

[0063] Specifically, the conversion module 40 is used to convert the power supply voltage AC according to the drive signal VG to obtain the output voltage VOUT, and output the zero-crossing detection signal VZCD, the current sampling signal VCS, the voltage sampling signal Vmult, the feedback voltage signal VFB, and the error voltage compensation signal Vcomp. In this embodiment, the power supply voltage AC is an alternating current voltage.

[0064] The first control module 10 generates a time window_time based on the drive signal VG; simultaneously, it outputs a start signal Starter based on the drive time VG. The start signal Starter goes high every first preset time interval, and outputs a start detection signal Starter_check when the start signal Starter goes high. In this embodiment, the time window_time is 300ns to ensure that the switching transistor M1 in the conversion module 40 is fully turned on; the first preset time is 400us. The start detection signal Starter_check is a high-level signal.

[0065] The first control module 10 is further configured to compare the current sampling signal VCS with the first threshold Vth1 based on the drive signal VG. When the current sampling signal VCS is detected to be greater than the first threshold within the time window window_time and continues for a second preset time, a protection signal CCM_protection is output. The protection signal CCM_protection is used to characterize the circuit entering deep CCM mode. In this embodiment, the first threshold Vth1 is 0.2V; the second preset time is 30ns. The protection signal CCM_protection is a high-level signal.

[0066] The first control module 10 is also used to process the zero-crossing detection signal VZCD to obtain the first signal Vally, and to shield the first signal Vally according to the start signal Starter and the protection signal CCM_protection.

[0067] The first control module 10 is also used to output a conduction signal on based on the start signal Starter and the first signal Valley.

[0068] The first control module 10 is further configured to switch the current sampling protection threshold from the second threshold Vth2 to the third threshold Vth3 based on the start detection signal Starter_check, and output a comparison signal Vcmp based on the current sampling signal VCS and the third threshold. The second threshold Vth2 is the current sampling protection threshold when the circuit is operating normally, and the third threshold Vth3 is the current sampling protection threshold when the circuit enters deep CCM mode and outputs a conduction signal from the start signal, and the third threshold Vth3 is less than the second threshold Vth2. In this embodiment, the second threshold Vth2 is 1.1V, and the third threshold Vth3 is 0.2V.

[0069] The second control module 20 is used to output a turn-off signal (off) based on the current sampling signal VCS, the voltage sampling signal Vmult, the feedback voltage signal VFB, the error voltage compensation signal Vcomp, and the comparison signal Vcmp. The drive module 30 is used to output a drive signal VG based on the turn-on signal (on) and the turn-off signal (off).

[0070] When the circuit is turned on and the zero-crossing detection signal VZCD is 0, the first signal Vally is also 0 after processing because the zero-crossing detection signal VZCD is 0. At this time, the on signal output by the first control module 10 is the start signal Starter, and the current sampling protection threshold is switched to the third threshold Vth3. This reduces the current sampling protection threshold when the on signal is the start signal Starter, thereby minimizing the conduction time of the switching transistor M1 in the conversion module 40 and reducing the turn-on current, thus suppressing the depth of the CCM mode.

[0071] When the circuit is turned on and the output voltage VOUT is not 0, the zero-crossing detection signal VZCD will gradually decrease and become 0. The first control module 10 will first identify the deep CCM mode: it compares the current sampling signal VCS with the first threshold Vth1 according to the drive signal VG. When the current sampling signal VCS is detected to be greater than the first threshold Vth1 within the time window window_time and lasts for a second preset time, the protection signal CCM_protection is output, that is, the deep CCM mode is identified. When the deep CCM mode is identified, the first signal Vally is shielded according to the start signal Starter and the protection signal CCM_protection. At this time, the on signal is the start signal Starter. In this application, the 160us in the traditional solution is modified to 400us to extend the demagnetization time of the inductor L in the conversion module 40 and prevent the CCM mode from deepening. At the same time, the current sampling protection threshold is switched to the third threshold Vth3, reducing the current sampling protection threshold when the on signal is the start signal Starter, reducing the turn-on current, thereby suppressing the depth of the CCM mode.

[0072] In summary, the CRM boost PFC converter circuit provided in this application solves the problem that traditional CRM boost PFC converters cannot suppress entering deep CCM mode. It can not only reduce the current stress of the switching transistor M1 in the converter module 40 and avoid drive oscillation, but also eliminate the need for a high reverse recovery time rectifier diode D04. At the same time, it improves the reliability of the circuit without increasing the power consumption.

[0073] In one embodiment of this application, such as Figure 6As shown, the first control module 10 includes a signal processing module 11, a signal generation module 12, a time window generation module 13, a first comparison module 14, a second comparison module 15, a signal shielding module 16, and a logic module 17. The input terminal of the signal processing module 11 is connected to the zero-crossing detection terminal of the transformation module 40, and the output terminal of the signal processing module 11 is connected to the first input terminals of the signal shielding module 16 and the logic module 17, respectively. The input terminals of the signal generation module 12 are connected to the input terminals of the time window generation module 13, the first input terminal of the first comparison module 14, and the driving terminal of the transformation module 40, respectively. The first output terminal is connected to the second input terminal of the signal shielding module 16 and the logic module 17 respectively. The second output terminal of the signal generation module 12 is connected to the first input terminal of the second comparison module 15. The output terminal of the time window generation module 13 is connected to the second input terminal of the first comparison module 14. The third input terminal of the first comparison module 14 is connected to the second input terminal of the second comparison module 15 and the current sampling terminal of the conversion module 40 respectively. The output terminal of the first comparison module 14 is connected to the signal shielding module 16. The output terminal of the second comparison module 15 is connected to the second control module 20. The output terminal of the logic module 17 is connected to the drive module 30.

[0074] Specifically, signal processing module 11 processes the zero-crossing detection signal VZCD to obtain the first signal Vally. Signal generation module 12 outputs a start signal Starter based on the drive signal VG. The start signal Starter goes high every first preset time interval, and a start detection signal Starter_check is output when the start signal Starter goes high. Time window generation module 13 generates a time window window_time based on the drive signal VG. First comparison module 14 compares the current sampling signal VCS with a first threshold Vth1 based on the drive signal VG. When the current sampling signal VCS is detected to be greater than the first threshold Vth1 within the time window window_time and lasts for a second preset time, a protection signal CCM_protection is output. The protection signal CCM_protection indicates that the circuit has entered deep CCM mode. Signal shielding module 16 shields the first signal Vally based on the start signal Starter and the protection signal CCM_protection. Logic module 17 outputs an on signal based on the start signal Starter and the first signal Vally. The second comparison module 15 is used to switch the current sampling protection threshold from the second threshold Vth2 to the third threshold Vth3 according to the start detection signal Starter_check, and output the comparison signal Vcmp according to the current sampling signal VCS and the third threshold.

[0075] In one embodiment of this application, such as Figure 7 As shown, the signal generation module 12 includes a first current source I1, a first switch S1, a first capacitor C1, a first power supply P1, and a first comparator U1. The input terminal of the first current source I1 receives the power supply voltage VCC. The output terminal of the first current source I1 is connected to the first terminal of the first switch S1, the positive terminal of the first capacitor C1, and the first input terminal of the first comparator U1. The negative terminal of the first capacitor C1, the second terminal and the third terminal of the first switch S1 are all grounded. The fourth terminal of the first switch S1 is connected to the input terminal of the time window generation module 13, the first input terminal of the first comparison module 14, and the driving terminal of the conversion module 40. The second input terminal of the first comparator U1 is connected to the positive terminal of the first power supply P1, and the negative terminal of the first power supply P1 is grounded. The output terminal of the first comparator U1 is connected to the second input terminals of the signal shielding module 16 and the logic module 17.

[0076] The signal generation module 12 further includes a signal generation unit 121, which is connected to the output of the first comparator U1 and the first input of the second comparison module 15. The signal generation unit 121 is used to generate a start detection signal Starter_check based on the start signal Starter. In this embodiment, the first input of the first comparator U1 is a non-inverting input, and the second input of the first comparator U1 is an inverting input.

[0077] Specifically, when the drive signal VG is low, the first switch S1 is open, and the power supply voltage VCC charges the first capacitor C1 through the first current source I1. When the voltage on the first capacitor C1 is greater than the voltage provided by the first power supply P1, the start signal Starter output by the first comparator U1 becomes high. The charging process of the first capacitor C1 is the timing process, which lasts for 400us, that is, the start signal Starter becomes high every 400us.

[0078] In one embodiment of this application, such as Figure 8As shown, the time window generation module 13 includes a first NOT gate (NOT1), a first AND gate (AND1), a first RS flip-flop (FF1), a first diode (D1), a second switch (S2), a second capacitor (C2), a second current source (I2), a second power supply (P2), and a second comparator (U2). The input terminal of the first NOT gate (NOT1) is connected to the first input terminal of the first AND gate (AND1), the input terminal of the signal generation module 12, the first input terminal of the first comparison module 14, and the driving terminal of the conversion module 40, respectively. The output terminal of the first NOT gate (NOT1) is connected to the second input terminal of the first AND gate (AND1), the output terminal of the first AND gate (AND1) is connected to the S terminal of the first RS flip-flop (FF1), and the Q terminal of the first RS flip-flop (FF1) is connected to the second input terminal of the first comparison module 14. The circuit is connected to the output of the time window `window_time`. The R terminal of the first RS flip-flop FF1 is connected to the output of the second comparator U2. The QN terminal of the first RS flip-flop FF1 is connected to the fourth terminal of the second switch S2. The first terminal of the second switch S2 is connected to the positive terminal of the second capacitor C2, the cathode of the first diode D1, the first input terminal of the second comparator U2, and the output terminal of the second current source I2. The input terminal of the second current source I2 receives the power supply voltage VCC. The anode of the first diode D1, the negative terminal of the second capacitor C2, the second terminal of the second switch S2, and the third terminal of the second switch S2 are all grounded. The second input terminal of the second comparator U2 is connected to the positive terminal of the second power supply P2, and the negative terminal of the second power supply P2 is grounded. In this embodiment, the first input terminal of the second comparator U2 is the non-inverting input terminal, and the second input terminal of the second comparator U2 is the inverting input terminal.

[0079] Specifically, the first NOT gate (NOT1) and the first AND gate (AND1) form an edge-triggered circuit. When the drive signal VG goes high, a narrow pulse of 20ns is generated after passing through the first NOT gate (NOT1) and the first AND gate (AND1). This narrow pulse triggers the S terminal of the first RS flip-flop FF1, causing the Q terminal of the first RS flip-flop FF1 to go high and QN to go low. After QN goes low, the second switch S2 opens, and the power supply voltage VCC charges the second capacitor C2 through the second current source I2. When the voltage on the second capacitor C2 is greater than the voltage provided by the second power supply P2, the second comparator U2 outputs a high-level signal. This high-level signal resets the first RS flip-flop FF1, causing the Q terminal of the first RS flip-flop FF1 to go low and QN to go high. After QN goes high, the second switch S2 turns on, short-circuiting the second capacitor C2, and the second comparator U2 outputs a low-level signal. Once the Q terminal is set low, a time window window_time is generated. The charging process of the second capacitor C2 is the timing process, which lasts for 300ns, thus generating a 300ns time window window_time.

[0080] In one embodiment of this application, such as Figure 9As shown, the first comparison module 14 includes a third switch S3, a third power supply P3, a third comparator U3, a fourth switch S4, a third capacitor C3, a second diode D2, a fourth power supply P4, a third current source I3, a fourth comparator U4, a second AND gate AND2, a second NOT gate NOT2, a third AND gate AND3, and a fourth AND gate AND4. The first terminal of the third switch S3 serves as the third input terminal of the first comparison module 14, and the fourth terminal of the third switch S3 serves as the first input terminal of the first comparison module 14. The second terminal of the third switch S3 is connected to the second input terminal of the third comparator U3, and the third terminal of the third switch S3 is grounded. The first input terminal of the third comparator U3 is connected to the positive terminal of the third power supply P3, and the negative terminal of the third power supply P3 is grounded. The voltage provided by the third power supply P3 is a first threshold voltage. The first output terminal of the third comparator U3 is connected to the fourth terminal of the fourth switch S4, and the second output terminal of the third comparator U3 is connected to the first input terminal of the second AND gate AND2. The first terminal of the fourth switch S4 is connected to the third capacitor... The positive terminal of C3, the cathode of the second diode D2, the first input terminal of the fourth comparator U4, and the output terminal of the third current source I3 are connected. The input terminal of the third current source I3 receives the power supply voltage VCC. The second input terminal of the fourth comparator U4 is connected to the positive terminal of the fourth power supply P4. The negative terminal of the fourth power supply P4, the anode of the second diode D2, the negative terminal of the third capacitor C3, the second terminal of the fourth switch S4, and the third terminal of the fourth switch S4 are all grounded. The output terminal of the fourth comparator U4 is connected to the second input terminal of the second AND gate AND2. The output terminal of the second AND gate AND2 is connected to the input terminal of the second NOT gate NOT2 and the first input terminal of the third AND gate AND3. The output terminal of the second NOT gate NOT2 is connected to the second input terminal of the third AND gate AND3. The output terminal of the third AND gate AND3 is connected to the first input terminal of the fourth AND gate AND4. The second input terminal of the fourth AND gate AND4 serves as the second input terminal of the first comparison module 14, and the output terminal of the fourth AND gate AND4 serves as the output terminal of the first comparison module 14. In this embodiment, the first input terminal of the third comparator U3 is the non-inverting input terminal, the second input terminal of the third comparator U3 is the inverting input terminal, the first output terminal of the third comparator U3 is the non-inverting output terminal, and the second output terminal of the third comparator U3 is the inverting output terminal; the first input terminal of the fourth comparator U4 is the non-inverting input terminal, and the second input terminal of the fourth comparator U4 is the inverting input terminal.

[0081] Specifically, when the drive signal VG goes high, the third switch S3 is turned on, and the third comparator U3 compares the current sampling signal VCS with the first threshold Vth1. When the current sampling signal VCS is greater than the first threshold Vth1, the second output of the third comparator U3 outputs a high-level signal, and the first output of the third comparator U3 outputs a low-level signal. This low-level signal controls the fourth switch S4 to open, and the power supply voltage VCC charges the third capacitor C3 through the third current source I3. When the voltage on the third capacitor C3 is greater than the voltage provided by the fourth power supply P4, the fourth comparator U4 outputs a high-level signal. Since the signals at both inputs of the second AND gate AND2 are both high-level signals, the second AND gate AND2 outputs a high-level signal. After passing through the second NOT gate NOT2 and the third AND gate AND3, a narrow pulse of 20ns is generated. This narrow pulse is logically ANDed with the time window window_time. When it is high, the protection signal CCM_protection is output. The charging process of the third capacitor C3 is the timing process, which lasts for 30 ns, which is also the second preset time. The charging process of the third capacitor C3 is used to ensure that the current sampling signal VCS is greater than the first threshold Vth1 for 30 ns.

[0082] In one embodiment of this application, such as Figure 10 As shown, the second comparison module 15 includes a fifth switch S5, a fifth comparator U5, a first resistor R1, and a fifth power supply P5. The positive terminal of the fifth power supply P5 is connected to the first terminal of the fifth switch S5 and the second input terminal of the fifth comparator U5, respectively. The negative terminal of the fifth power supply P5 is grounded. The voltage provided by the fifth power supply P5 is the second threshold voltage. The second terminal of the fifth switch S5 is connected to the first terminal of the first resistor R1. The fourth terminal of the fifth switch S5 serves as the first input terminal of the second comparison module 15. The third terminal of the fifth switch S5 and the second terminal of the first resistor R1 are both grounded. The first input terminal of the fifth comparator U5 serves as the second input terminal of the second comparison module 15, and the output terminal of the fifth comparator U5 serves as the output terminal of the second comparison module 15. In this embodiment, the first input terminal of the fifth comparator U5 is the non-inverting input terminal, and the second input terminal of the fifth comparator U5 is the inverting input terminal.

[0083] Specifically, whenever the start signal Starter goes high, a start detection signal Starter_check is output. Since the start detection signal Starter_check is high, it controls the fifth switch S5 to turn on. After the fifth switch S5 turns on, the first resistor R1 is connected to the positive terminal of the fifth power supply P5, and the first resistor R1 performs voltage division, thereby switching the second threshold Vth2 to the third threshold Vth3. The fifth comparator U5 is used to compare the current sampling signal VCS and the third threshold Vth3, and outputs a comparison signal Vcmp. The second comparison module 15 is mainly used to switch the current sampling protection threshold to the third threshold Vth3 in deep CCM mode, reducing the current sampling protection threshold when the on signal is the start signal Starter, reducing the turn-on current, and thus suppressing the depth of CCM mode.

[0084] In one embodiment of this application, such as Figure 11 As shown, the signal shielding module 16 includes a second RS flip-flop FF2, a third NOT gate NOT3, a fifth AND gate AND5, and a sixth switch S6. The S terminal of the second RS flip-flop FF2 is connected to the output terminal of the first comparison module 14, the R terminal of the second RS flip-flop FF2 is connected to the output terminal of the fifth AND gate AND5, the input terminal of the third NOT gate NOT3 is connected to the first input terminal of the fifth AND gate AND5 and the first output terminal of the signal generation module 12, the output terminal of the third NOT gate NOT3 is connected to the second input terminal of the fifth AND gate AND5, the Q terminal of the second RS flip-flop FF2 is connected to the fourth terminal of the sixth switch S6, the first terminal of the sixth switch S6 is connected to the output terminal of the signal processing module 11, and the second and third terminals of the sixth switch S6 are both grounded.

[0085] Specifically, when the protection signal CCM_protection is high, it triggers the S-terminal of the second RS flip-flop FF2, causing the Q-terminal of the first RS flip-flop FF1 to go high. Once Q is high, it controls the sixth switch S6 to turn on, thereby pulling the first signal Valy low, effectively shielding it. When the start signal Starter goes high, a narrow 20ns pulse is generated after passing through the third NOT gate (NOT3) and the fifth AND gate (AND5). This narrow pulse resets the second RS flip-flop FF2, causing its Q-terminal to go low. Once Q is low, the sixth switch S6 turns off, preventing the first signal Valy from going low, thus no longer shielding it.

[0086] In one embodiment of this application, such as Figure 12As shown, the logic module 17 includes an OR gate NOR. The first input terminal of the OR gate NOR is connected to the output terminal of the signal processing module 11 and the signal shielding module 16, respectively. The second input terminal of the OR gate NOR is connected to the output terminal of the signal generation module 12 and the signal shielding module 16, respectively. The output terminal of the OR gate NOR is connected to the driving module 30.

[0087] Specifically, the NOR gate is used to OR the first signal Value and the start signal Starter. When the converter is turned on, the zero-crossing detection signal VZCD is 0, so the first signal Value is also 0, and the start signal Starter is the on signal.

[0088] The following is a simulation verification of this application:

[0089] When the converter is turned on, the output voltage VOUT is not 0. The zero-crossing detection signal VZCD is present after the converter is turned on. As the output voltage VOUT gradually rises to near the input voltage, the zero-crossing detection signal VZCD decreases until it becomes 0, at which point the converter enters deep CCM mode. The proposed scheme is used in this scenario, and simulations are performed. Key simulation waveforms are shown below. Figure 13 As shown, from Figure 13 It can be seen that the depth of the CCM mode is significantly suppressed.

[0090] When the converter is turned on, the zero-crossing detection signal VZCD is 0, and the converter enters deep CCM mode. The proposed scheme is used in this case, and simulations are performed. Key simulation waveforms are as follows: Figure 14 As shown, from Figure 14 It can be seen that the depth of the CCM mode is significantly suppressed.

[0091] In summary, the CRM boost PFC converter circuit provided in this application effectively suppresses the circuit from entering deep CCM mode. This not only reduces the current stress on the switching transistor M1 in the converter module 40 and avoids drive oscillation, but also eliminates the need for a high reverse recovery time rectifier diode D04, thereby improving the reliability of the circuit without increasing the power consumption.

[0092] This application also provides a switching power supply chip, including the CRM boost PFC converter circuit described above. Since the switching power supply chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0093] This application also provides an electronic device including the aforementioned switching power supply chip. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0095] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A CRM boost PFC conversion circuit, characterized by, The system includes a first control module, a second control module, a drive module, and a conversion module. The drive terminal of the conversion module is connected to both the drive module and the first control module. The zero-crossing detection terminal of the conversion module is connected to the first control module. The current sampling terminal of the conversion module is connected to both the first control module and the second control module. The second control module is connected to the compensation terminal, feedback terminal, and voltage sampling terminal of the conversion module. The first control module is connected to both the second control module and the drive module. The second control module is connected to the drive module. The conversion module is used to convert the power supply voltage according to the drive signal to obtain the output voltage, and output a zero-crossing detection signal, a current sampling signal, a voltage sampling signal, a feedback voltage signal, and an error voltage compensation signal; the first control module is used to generate a time window according to the drive signal; simultaneously output a start signal according to the drive signal, the start signal becoming high every first preset time, and outputting a start detection signal when the start signal becomes high; it is also used to compare the current sampling signal with a first threshold according to the drive signal, and output a protection signal when the current sampling signal is detected to be greater than the first threshold within the time window and lasts for a second preset time; it is also used to process the zero-crossing detection signal to obtain a first signal, and shield the first signal according to the start signal and the protection signal; it is also used to output a conduction signal according to the start signal and the first signal; It is also used to switch the current sampling protection threshold from the second threshold to the third threshold according to the start detection signal, and to output a comparison signal according to the current sampling signal and the third threshold; The second control module is used to output a shutdown signal based on the current sampling signal, the voltage sampling signal, the feedback voltage signal, the error voltage compensation signal, and the comparison signal; the drive module is used to output a drive signal based on the turn-on signal and the shutdown signal; wherein, the third threshold is less than the second threshold.

2. The CRM boost PFC conversion circuit according to claim 1, characterized by, The first control module includes a signal processing module, a signal generation module, a time window generation module, a first comparison module, a second comparison module, a signal shielding module, and a logic module. The input terminal of the signal processing module is connected to the zero-crossing detection terminal of the transformation module. The output terminal of the signal processing module is connected to the first input terminals of the signal shielding module and the logic module, respectively. The input terminal of the signal generation module is connected to the input terminal of the time window generation module, the first input terminal of the first comparison module, and the driving terminal of the transformation module, respectively. The first output terminal of the signal generation module is connected to the second input terminals of the signal shielding module and the logic module, respectively. The second output terminal of the signal generation module is connected to the first input terminal of the second comparison module. The output terminal of the time window generation module is connected to the second input terminal of the first comparison module. The third input terminal of the first comparison module is connected to the second input terminal of the second comparison module and the current sampling terminal of the transformation module, respectively. The output terminal of the first comparison module is connected to the signal shielding module. The output terminal of the second comparison module is connected to the second control module. The output terminal of the logic module is connected to the driving module. The signal processing module processes the zero-crossing detection signal to obtain a first signal; the signal generation module outputs a start signal according to the drive signal, the start signal going high every first preset time interval, and outputs a start detection signal when the start signal goes high; the time window generation module generates a time window according to the drive signal; the first comparison module compares the current sampling signal and the first threshold according to the drive signal, and outputs a protection signal when the current sampling signal is detected to be greater than the first threshold and lasts for a second preset time within the time window; the signal shielding module shields the first signal according to the start signal and the protection signal; the logic module outputs a conduction signal according to the start signal and the first signal; the second comparison module switches the current sampling protection threshold from a second threshold to a third threshold according to the start detection signal, and outputs a comparison signal according to the current sampling signal and the third threshold.

3. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The signal generation module includes a first current source, a first switch, a first capacitor, a first power supply, and a first comparator. The input terminal of the first current source receives the power supply voltage. The output terminal of the first current source is connected to the first controlled terminal of the first switch, the positive terminal of the first capacitor, and the first input terminal of the first comparator. The negative terminal of the first capacitor, the second controlled terminal of the first switch, and the reference ground corresponding to the control terminal of the first switch are all grounded. The control terminal of the first switch is connected to the input terminal of the time window generation module, the first input terminal of the first comparison module, and the driving terminal of the conversion module. The second input terminal of the first comparator is connected to the positive terminal of the first power supply, and the negative terminal of the first power supply is grounded. The output terminal of the first comparator is connected to the second input terminal of the signal shielding module and the logic module. The signal generation module further includes a signal generation unit, which is connected to the output terminal of the first comparator and the first input terminal of the second comparison module, respectively. The signal generation unit is used to generate a start detection signal based on the start signal.

4. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The time window generation module includes a first NOT gate, a first AND gate, a first RS flip-flop, a first diode, a second switch, a second capacitor, a second current source, a second power supply, and a second comparator. The input terminal of the first NOT gate is connected to the first input terminal of the first AND gate, the input terminal of the signal generation module, the first input terminal of the first comparison module, and the driving terminal of the conversion module. The output terminal of the first NOT gate is connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is connected to the S terminal of the first RS flip-flop. The Q terminal of the first RS flip-flop is connected to the second input terminal of the first comparison module. The R terminal of the first RS flip-flop is connected to the output terminal of the second comparator. The QN terminal of the first RS flip-flop is connected to the control terminal of the second switch. The first controlled terminal of the second switch is connected to the positive terminal of the second capacitor, the cathode of the first diode, the first input terminal of the second comparator, and the output terminal of the second current source. The input terminal of the second current source receives the power supply voltage. The reference ground terminals corresponding to the anode of the first diode, the cathode of the second capacitor, the second controlled terminal of the second switch, and the control terminal of the second switch are all grounded. The second input terminal of the second comparator is connected to the positive terminal of the second power supply, and the negative terminal of the second power supply is grounded.

5. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The first comparison module includes a third switch, a third power supply, a third comparator, a fourth switch, a third capacitor, a second diode, a fourth power supply, a third current source, a fourth comparator, a second AND gate, a second NOT gate, a third AND gate, and a fourth AND gate. The first controlled terminal of the third switch serves as the third input terminal of the first comparison module, and the control terminal of the third switch serves as the first input terminal of the first comparison module. The second controlled terminal of the third switch is connected to the second input terminal of the third comparator. The reference ground terminal corresponding to the control terminal of the third switch is grounded. The first input terminal of the third comparator is connected to the positive terminal of the third power supply, and the negative terminal of the third power supply is grounded. The voltage provided by the third power supply is a first threshold voltage. The first output terminal of the third comparator is connected to the control terminal of the fourth switch, and the second output terminal of the third comparator is connected to the first input terminal of the second AND gate. The first controlled terminal of the fourth switch is connected to the positive terminal of the third capacitor, and the second input terminal of the third diode is connected to the first input terminal of the second AND gate. The cathode of the second diode, the first input terminal of the fourth comparator, and the output terminal of the third current source are connected. The input terminal of the third current source receives the power supply voltage. The second input terminal of the fourth comparator is connected to the positive terminal of the fourth power supply. The negative terminal of the fourth power supply, the anode of the second diode, the negative terminal of the third capacitor, the second controlled terminal of the fourth switch, and the reference ground corresponding to the control terminal of the fourth switch are all grounded. The output terminal of the fourth comparator is connected to the second input terminal of the second AND gate. The output terminal of the second AND gate is connected to the input terminal of the second NOT gate and the first input terminal of the third AND gate. The output terminal of the second NOT gate is connected to the second input terminal of the third AND gate. The output terminal of the third AND gate is connected to the first input terminal of the fourth AND gate. The second input terminal of the fourth AND gate serves as the second input terminal of the first comparison module, and the output terminal of the fourth AND gate serves as the output terminal of the first comparison module.

6. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The second comparison module includes a fifth switch, a fifth comparator, a first resistor, and a fifth power supply. The positive terminal of the fifth power supply is connected to the first controlled terminal of the fifth switch and the second input terminal of the fifth comparator, respectively. The negative terminal of the fifth power supply is grounded. The voltage provided by the fifth power supply is a second threshold. The second controlled terminal of the fifth switch is connected to the first terminal of the first resistor. The control terminal of the fifth switch serves as the first input terminal of the second comparison module. The reference ground terminal corresponding to the control terminal of the fifth switch and the second terminal of the first resistor are both grounded. The first input terminal of the fifth comparator serves as the second input terminal of the second comparison module, and the output terminal of the fifth comparator serves as the output terminal of the second comparison module.

7. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The signal shielding module includes a second RS flip-flop, a third NOT gate, a fifth AND gate, and a sixth switch. The S terminal of the second RS flip-flop is connected to the output terminal of the first comparison module, the R terminal of the second RS flip-flop is connected to the output terminal of the fifth AND gate, the input terminal of the third NOT gate is connected to the first input terminal of the fifth AND gate and the first output terminal of the signal generation module, the output terminal of the third NOT gate is connected to the second input terminal of the fifth AND gate, the Q terminal of the second RS flip-flop is connected to the control terminal of the sixth switch, the first controlled terminal of the sixth switch is connected to the output terminal of the signal processing module, and the reference ground terminals corresponding to the second controlled terminal and the control terminal of the sixth switch are both grounded.

8. The CRM boost-type PFC converter circuit according to claim 2, characterized in that, The logic module includes an OR gate, the first input of which is connected to the output of the signal processing module and the signal shielding module, the second input of which is connected to the output of the signal generation module and the signal shielding module, and the output of which is connected to the driving module.

9. A switching power supply chip, characterized in that, Includes the CRM boost PFC converter circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the switching power supply chip as described in claim 9.

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