Stackable switched mode converter

Abstract

The invention relates to a stackable switched mode converter. A circuit includes a first transistor (106), a second transistor (108), a PWM circuit (114), a minimum turn-off timer (116), and a trigger circuit (112). The first transistor (106) has a first control terminal and the second transistor (108) has a second control terminal. The PWM circuit (114) has a first output coupled to the first control terminal, a second output coupled to the second control terminal, a first input, and a second input. The minimum turn-off timer (116) has a timer output coupled to a first input of the PWM circuit (114). The trigger circuit (112) has a trigger signal output, a trigger signal input, and a trigger signal receiving output coupled to the PWM circuit (114). The trigger circuit (112) includes a latch circuit.

Description

Technical Field

[0001] This application relates to a stackable switch-mode converter. Background Technology

[0002] A switch-mode converter is an electronic circuit that converts an input direct current (DC) voltage into one or more DC output voltages with a magnitude higher or lower than the input DC voltage. A switch-mode converter that generates an output voltage lower than the input voltage is called a buck or step-down converter. A switch-mode converter that generates an output voltage higher than the input voltage is called a boost or step-up converter. Stackable switch-mode converters are a type of converter that can be connected to other converters of the same type to increase the output current. Summary of the Invention

[0003] In one example, a circuit includes a first transistor, a second transistor, a PWM circuit, a minimum shutdown timer, and a trigger circuit. The first transistor has a first control terminal, and the second transistor has a second control terminal. The PWM circuit has a first output coupled to the first control terminal, a second output coupled to the second control terminal, a first input, and a second input. The minimum shutdown timer has a timer output coupled to the first input of the PWM circuit. The trigger circuit has a trigger signal output, a trigger signal input, and a trigger signal receive output coupled to the PWM circuit. The trigger circuit includes a latch circuit. The latch circuit has a first latch input coupled to the trigger signal input, a second latch input coupled to the timer output, and a latch output coupled to the second input of the PWM circuit.

[0004] In another example, a power supply circuit includes a first switch-mode converter and a second switch-mode converter. The first switch-mode converter has a trigger output and a first current output. The first switch-mode converter is configured to provide a trigger signal at the trigger output having a first sequence pulse and a second sequence pulse. The first pulse indicates that the first switch-mode converter is providing current at the first current output. The second switch-mode converter has a trigger input coupled to the trigger output and a second current output coupled to the first current output, and the second switch-mode converter includes a trigger circuit, a minimum shutdown timer, a latch circuit, and a pulse width modulation (PWM) circuit. The trigger circuit is configured to receive the trigger signal and identify the second sequence pulse. The minimum shutdown timer is configured to define a minimum shutdown time during which current flow to the second current output is interrupted. The latch circuit is configured to set the trigger receive signal to a first state in response to the second sequence pulse; and to set the trigger receive signal to a second state in response to the minimum shutdown time expiring. The PWM circuit is coupled to the latch circuit. The PWM circuit is configured to allow current flow to the second current output in response to the trigger receive signal having the first state and the minimum shutdown time expiring.

[0005] In another example, a system includes a processor and a power supply circuit. The processor has a voltage input. The power supply circuit has a voltage output coupled to the voltage input of the processor. The power supply circuit includes an inductor and a switch-mode converter circuit. The inductor has a first terminal coupled to the voltage input of the processor and a second terminal. The switch-mode converter circuit has a current output coupled to the second terminal of the inductor and a trigger input configured to receive a trigger signal having a first sequence pulse and a second sequence pulse. The switch-mode converter includes a trigger circuit, a minimum shutdown timer, a latch circuit, and a PWM circuit. The trigger circuit is configured to receive a trigger signal and identify the second sequence pulse. The minimum shutdown timer is configured to define a minimum shutdown time during which current flow to the current output is interrupted. The latch circuit is configured to set the trigger receive signal to a first state in response to the second sequence pulse; and to set the trigger receive signal to a second state in response to the minimum shutdown time expiring. The PWM circuit is coupled to the latch circuit. The PWM circuit is configured to allow current flow to the second current output in response to the trigger receive signal having the first state and the minimum shutdown time expiring. Attached Figure Description

[0006] Figure 1 This is a block diagram of a stackable switch-mode converter circuit that uses a single trigger signal to control activation.

[0007] Figure 2 It is applicable Figure 1 A block diagram of an example trigger circuit for a stackable switch-mode converter circuit.

[0008] Figure 3 yes Figure 2 The flowchart illustrates an example method for trigger control in the state machine of a trigger circuit.

[0009] Figure 4 It can be included Figure 2 A schematic diagram of an example circuit in a trigger circuit to enable secondary operations.

[0010] Figure 5A and 5B It is shown Figure 4 Timing diagrams of example signals in the circuit.

[0011] Figure 6 It includes Figure 1 A graph of an example signal in the power supply of a stackable switch-mode converter circuit.

[0012] Figure 7 It is existence or non-existence. Figure 2 The curves show the power supply operation of an example circuit under the trigger circuit condition.

[0013] Figure 8 It includes the use Figure 1 A block diagram of an example system of power supplies for a stackable switch-mode converter circuit. Detailed Implementation

[0014] In stackable switch-mode converters, the primary converter controls one or more secondary converters to regulate the output voltage. The primary and secondary converters can communicate via one or more control signals. For example, bidirectional signaling can be implemented between the primary and secondary converters to achieve a handshake for transmitting control and status information. Some stackable converters implement unidirectional control, where the primary converter triggers one or more secondary controllers via a single signal. This type of implementation reduces the pin count of the converter's integrated circuit, allowing for a smaller package size, which is advantageous. However, in the absence of secondary-to-primary communication, the primary converter can trigger the secondary converters if the secondary controllers fail to respond. Failure to respond to a trigger signal received from the primary controller can cause a drop in the converter's output voltage.

[0015] The stackable switch-mode converter circuit described herein uses a single signal for unidirectional communication between the primary and secondary converters. The secondary converter includes circuitry that records the reception of a trigger signal from the primary converter and ensures that even if the secondary device fails to respond to the trigger signal, it will still respond by switching current to a current output.

[0016] Figure 1 This is a block diagram of a stackable switch-mode converter circuit 100, an example of using a single trigger signal to control the activation of a secondary converter. The stackable switch-mode converter circuit 100 includes a half-bridge circuit 102 and a control circuit 104. The half-bridge circuit 102 includes a high-side transistor 106 and a low-side transistor 108. The high-side transistor 106 and the low-side transistor 108 may be n-channel field-effect transistors (NFETs). The high-side transistor 106 has a first terminal (e.g., drain) coupled to a voltage input terminal (VIN), a second terminal (e.g., source) coupled to a switch terminal (SW), and a control terminal (e.g., gate) coupled to the control circuit 104. The low-side transistor 108 has a first terminal (e.g., drain) coupled to the second terminal of the high-side transistor 106, a second terminal (e.g., source) coupled to a reference voltage terminal (e.g., ground), and a control terminal coupled to the control circuit 104. The high-side transistor 106 and the low-side transistor 108 are controlled by the control circuit 104 to supply current from VIN to SW and couple SW to the reference voltage terminal.

[0017] Control circuit 104 includes comparator 110, trigger circuit 112, pulse width modulation (PWM) circuit 114, minimum shutdown timer 116, and drivers 118 and 120. Drivers 118 and 120 provide control signals with voltages and currents suitable for turning on and off high-side transistor 106 and low-side transistor 108. Driver 118 has an output coupled to a control terminal of high-side transistor 106, an input coupled to PWM circuit 114, and a reference terminal coupled to a second terminal of high-side transistor 106. Driver 120 has an output coupled to a control terminal of low-side transistor 108, an input coupled to PWM circuit 114, and a reference terminal coupled to a second terminal of driver 120.

[0018] PWM circuit 114 generates transistor control signals HON and LON that control high-side transistor 106 and low-side transistor 108 via drivers 118 and 120. HON controls high-side transistor 106 and LON controls low-side transistor 108. PWM circuit 114 has a first output coupled to the input of driver 118 and a second output coupled to the input of driver 120, providing HON at the first output and LON at the second output. PWM circuit 114 has inputs coupled to low-side current sensor 132, trigger circuit 112, and minimum shutdown timer 116. PWM circuit 114 receives a current sensing signal from low-side current sensor 132, a trigger receive signal (TRIG RCVD) from trigger circuit 112, and a minimum shutdown time signal (MINOFF) from minimum shutdown timer 116. PWM circuit 114 can initiate the switching on of high-side transistor 106 by setting HON to an on state (e.g., logic high state) based on the sensed current, TRIG RCVD, and MINOFF. For example, the PWM circuit 114 can set HON to the on state based on the sensed current being below a threshold, TRIG RCVD having a state indicating that a trigger signal has been received, and MINOFF having a state indicating that HON is in the off state (e.g., logic low state), for a minimum selected duration.

[0019] The minimum shutdown timer 116 includes a timer circuitry that generates MINOFF. MINOFF defines a minimum time that begins from the shutdown of the high-side transistor 106 (e.g., HON transitioning to a logic low state) and expires after a predetermined interval (e.g., a minimum shutdown time). For example, MINOFF has a first state (e.g., a logic high state) indicating the shutdown time interval following the shutdown of the high-side transistor 106 (when current flow through the high-side transistor 106 has been interrupted), and a second state (e.g., a logic low state) indicating the time during which the high-side transistor 106 can be turned on.

[0020] Comparator 110 compares an error signal (e.g., the difference between the converter output voltage and a reference voltage) with a ramp voltage to generate an internal trigger signal (INTTRIG). The circuitry used to generate the error signal, ramp signal, and reference voltage is not shown. The output of comparator 110 is coupled to trigger circuitry 112. The stackable switch-mode converter circuitry 100 may include other circuitry, such as error amplifiers, compensation circuitry, and, for clarity, elements omitted from the original text. Figure 1 Other circuits omitted.

[0021] Trigger circuit 112 allows stackable switch-mode converter circuit 100 to function as either a primary or secondary converter by providing a trigger signal to PWM circuit 114, the trigger signal being based on INTTRIG received from comparator 110 or on trigger signal TRIG received at input / output (I / O) terminals of stackable switch-mode converter circuit 100 (e.g., where TRIG is provided by the primary converter). Trigger circuit 112 has a trigger signal output for providing TRIG to the secondary converter and a trigger signal input for receiving TRIG provided by the primary converter. Trigger circuit 112 also has inputs for receiving MINOFF and HON for use as follows: If stackable switch-mode converter circuit 100 is used as a primary converter, trigger circuit 112 generates TRIG to control the operation of the secondary converter and provides TRIG at trigger signal output of trigger circuit 112. Signal 124 is a TRIG instance for three parallel coupled instances of stackable switch-mode converter circuit 100 (e.g., one primary converter and two secondary converters). Signal 124 comprises a series of sequential pulses, each pulse representing the activation (or requested activation) of the high-side transistor in the converter. The amplitude of the visible pulses distinguishes between primary converter control and secondary converter control. The amplitude of pulse 126 is higher than that of pulses 128 and 130. For example, the amplitude of pulse 126 may be approximately twice the amplitude of pulses 128 and 130 (e.g., 4.5 volts versus 2.25 volts). Pulse 126 represents the activation of the high-side transistor in the primary converter. Pulse 128 represents a request from the primary converter to activate its high-side transistor in the secondary converter to provide current. Pulse 130 represents a request from the primary converter to activate its high-side transistor in the secondary converter to provide current.

[0022] If the stackable switch-mode converter circuit 100 is used as a secondary converter, the trigger circuit 112 receives the TRIG provided by the primary converter at its trigger signal input. The trigger circuit 112 identifies pulse 126 and pulse 128 or 130 corresponding to the stackable switch-mode converter circuit 100 (depending on whether the stackable switch-mode converter circuit 100 is used as a first-stage converter or a second-stage converter). For example, the trigger circuit 112 may include a comparator for identifying different pulses based on amplitude, and a counter circuit system for counting lower amplitude pulses following higher amplitude pulses. In response to the identification of the pulse corresponding to the stackable switch-mode converter circuit 100, the trigger circuit 112 may set the TRIG RCVD to an ON state (e.g., logic high state), indicating that the PWM circuit 114 should set HON to turn on the high-side transistor 106. However, if a pulse corresponding to the stackable switch-mode converter circuit 100 is received when HON is set to turn on the high-side transistor 106 or when MINOFF is set to turn off the high-side transistor 106, the PWM circuit 114 may fail to respond to the TRIG RCVD, and the stackable switch-mode converter circuit 100 may skip the conversion cycle.

[0023] Trigger circuit 112 includes a state machine 122 that latches pulses corresponding to the stackable switch-mode converter circuit 100. State machine 122 sets and holds TRIG RCVD in the ON state until, for the immediately preceding conversion cycle, HON is reset to turn off the high-side transistor 106 and the minimum off-time has expired (MINOFF is in the OFF state), and HON can be set to the ON state for the current conversion cycle. Therefore, state machine 122 ensures that the stackable switch-mode converter circuit 100 provides current via the high-side transistor 106 in each conversion cycle, which improves the transient response and output regulation of the stackable converter. Without state machine 122, the stackable switch-mode converter circuit 100 may fail to respond to trigger pulses, and the performance of the stackable converter may be adversely affected. State machine 122 can be implemented using various circuits. Figure 2 and 4 An example circuit for implementing state machine 122 is illustrated. State machine 122 can also be implemented as a synchronous circuit system that provides the functionality described herein.

[0024] Figure 2 This is a block diagram of the example trigger circuit 112. The trigger circuit 112 includes a pulse flag circuit 202 and a state machine 122. Figure 2The example of state machine 122 shown includes trigger sensing circuitry 204 and trigger receiving circuitry 206. If stackable switch-mode converter circuitry 100 is used as a primary converter, pulse marking circuitry 202 receives TRIG provided by the primary converter and marks pulses 126 and 128, and provides signal 208 indicating marking of pulse 126 and signal 210 indicating marking of pulse 128.

[0025] The trigger sensing circuit 204 generates a trigger sensing signal (SNS) based on signals 208 and 210. For example, the trigger sensing circuit 204 may set the SNS to a first state (e.g., logic high) in response to signal 208 and set the SNS to a second state (e.g., logic low) in response to signal 210.

[0026] Trigger receiver circuit 206 generates TRIG RCVD based on SNS, HON, and MINOFF. For example, trigger receiver circuit 206 may include a latch circuit set in response to a transition of SNS from a first state to a second state (in response to an SNS transition of pulse 128). Setting the latch circuit sets the TRIG RCVD to the ON state. After setting the latch circuit (e.g., after a predetermined time after setting the latch), if HON is in the OFF state (indicating that the high-side transistor 106 is off) and MINOFF is in the OFF state (indicating that the minimum off time has expired), the latch circuit can be reset. Resetting the latch circuit sets the TRIG RCVD to the OFF state. Therefore, state machine 122 keeps the TRIG RCVD in the ON state until PWM circuit 114 can set HON to turn on the high-side transistor 106, thereby ensuring that the stackable switch-mode converter circuit 100 does not skip conversion cycles.

[0027] Figure 3 This is a flowchart of an example method 300 for trigger control in a secondary converter. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Additionally, some embodiments may only perform some of the actions shown. The operation of method 300 may be performed by an example of trigger circuit 112.

[0028] In block 302, trigger circuit 112 is receiving TRIG. Trigger circuit 112 can compare TRIG with a first threshold to identify pulse 126. Pulse 126 is a primary trigger pulse that indicates that the high-side transistor 106 of the primary converter is turned on.

[0029] In block 304, trigger circuit 112 is receiving a TRIG. Trigger circuit 112 can compare the TRIG with a second threshold to identify pulse 128. For example, a pulse with an amplitude greater than the second threshold and less than the first threshold (e.g., pulse 128) can be identified as a secondary trigger pulse.

[0030] In block 306, trigger circuit 112 sets TRIG RCVD to the ON state in response to an indication of pulse 128. Setting TRIG RCVD to the ON state may include setting the latch to a first state.

[0031] In block 308, trigger circuit 112 determines whether HON is in an on state (e.g., logic high) to turn on high-side transistor 106, or whether MINOFF is in an on state (e.g., logic high), indicating that the minimum off time after HON transitions to the off state has not yet expired. If HON or MINOFF is in an on state, method 300 continues in block 306. That is, TRIGRCVD remains set until HON and MINOFF change to the off state.

[0032] If HON and MINOFF are in the off state, then in block 310, trigger circuit 112 resets TRIG RCVD to the off state. Resetting TRIG RCVD to the off state may include setting the latch to a second state. PWM circuit 114 detects that TRIG RCVD is in the on state while HON and MINOFF are in the off state, and in response, can set HON to the on state.

[0033] Figure 4This is a schematic diagram of circuit 400, which may be part of state machine 122 for generating TRIG RCVD for secondary operations. Circuit 400 includes flip-flops 402, 404, and 406, logic gate 408, inverters 410 and 424, and delay circuits 412, 414, 416, 418, 420, and 422. Flip-flops 402 and delay circuits 412, 414, 416, and 418 are connected as a pulse generator that provides a pulse with the width of the delay provided by delay circuits 412, 414, 416, and 418 at the rising edge of the signal MIN_TOFF_DONE. In various embodiments of circuit 400, any number of delay circuits can be used to generate the desired pulse width. Flip-flops 402 have a data input coupled to a voltage terminal and a clock input coupled to logic gate 426 that provides the output of MIN_TOFF_DONE. If HON and MINOFF are logic low (high-side transistor 106 is off and the minimum off time has expired), then logic gate 426 sets MIN_TOFF_DONE to the logic high state. Delay circuits 412, 414, 416, and 418 are coupled in series between the output of flip-flop 402 and the reset input of flip-flop 402. The pulse signal (MINOFFP) provided at the output of flip-flop 402 changes state (to logic low) at the rising edge of MIN_TOFF_DONE. The logic low propagates through delay circuits 412, 414, 416, and 418 and resets flip-flop 402, causing the pulse signal to transition to the logic high state.

[0034] Flip-flop 404 has a data input that receives MIN_TOFF_DONE via inverter 424, a clock input coupled to trigger sensing circuit 204 for receiving the output of SNS, and a reset input coupled to the reset input of flip-flop 402. If MIN_TOFF_DONE is logic low at the rising edge of SNS, the output signal provided at the output of flip-flop 404 transitions to logic low and remains logic low until flip-flop 404 is reset by a pulse generated by flip-flop 402. Therefore, the output signal provided at the output of flip-flop 404 can have a logic low state from the rising edge of SNS to the rising edge of MIN_TOFF_DONE.

[0035] Flip-flop 406 has a data input coupled to a voltage terminal, a clock input coupled to the clock input of flip-flop 404, and a reset input coupled to the output of flip-flop 406 via delay circuits 420 and 422. The output signal provided at the output of flip-flop 406 transitions to logic low at the rising edge of SNS and transitions back to logic high when the logic low propagates through delay circuits 420 and 422 to the reset input of flip-flop 406. Therefore, flip-flop 406 generates a relatively short pulse at the rising edge of SNS. In various embodiments of circuit 400, any number of delay circuits can be used to generate the desired pulse width.

[0036] Logic gate 408 has an input coupled to the output of flip-flop 404 and an input coupled to the output of flip-flop 406. The output of logic gate 408 is coupled to the input of inverter 410, and provides a TRIG RCVD at the output of inverter 410. Therefore, if MIN_TOFF_DONE is logic high at the rising edge of SNS, the TRIG RCVD can be a short pulse provided by flip-flop 406, or if MIN_TOFF_DONE is logic low at the rising edge of SNS, the TRIG RCVD can extend from the rising edge of SNS to the rising edge of MIN_TOFF_DONE.

[0037] The function of circuit 400 can also be used with Figure 4 The circuit shown can be implemented using different circuits. For example, a synchronization circuit can be implemented to provide the same or similar function as circuit 400.

[0038] Figure 5A This is a timing diagram showing the signals in circuit 400 when MIN_TOFF_DONE is logic high at the rising edge of SNS and TRIG RCVD is a short pulse generated by flip-flop 406.

[0039] Figure 5B This is a timing diagram showing the signals in circuit 400 when MIN_TOFF_DONE is logic low at the rising edge of SNS and TRIG RCVD is logic high between the rising edge of SNS and the rising edge of MIN_TOFF_DONE.

[0040] Figure 6 It is a graph of the instance signals in the power supply of two instances (e.g., a primary converter and a secondary converter) of the stackable switch-mode converter circuit 100. Figure 6 Examples of the trigger signal TRIG received by the secondary converter and the signals SNS, TRIG RCVD, and HON generated by the secondary converter are shown. Figure 6The diagram also shows the inductor current 614 of the primary converter, the inductor current 616 of the secondary converter, and the signal MINOFFP generated by the secondary converter. MINOFFP is a pulse at the trailing edge of MINOFF, indicating that the minimum off-time has expired. The TRIG signal contains a primary trigger pulse and a secondary trigger pulse. The primary trigger pulse has a larger amplitude (higher voltage) than the secondary trigger pulse. SNS is set to logic low by each primary trigger pulse and to logic high by each secondary trigger pulse. TRIG RCVD is set to logic high each time SNS transitions from low to high.

[0041] At time 610, corresponding to secondary pulse 604 (after primary pulse 602), HON is in the off state and MINOFFP has been generated (indicating that MINOFF is in the off state). Therefore, in response to TRIG RCVD, HON is set to the on state without delay, and TRIG RCVD is reset to the logic low state.

[0042] At time 612, corresponding to secondary pulse 608 (following primary pulse 606), HON is in the off state, but MINOFFP has not yet been generated (indicating MINOFF is in the on state). Therefore, HON cannot be immediately set to the on state in response to TRIG RCVD. State machine 122 holds TRIG RCVD in a logic high state until the minimum off time expires and MINOFFP has been generated. Afterward, HON is set to the on state. TRIG RCVD is reset to a logic low state as MINOFFP is generated and / or HON is set to the on state. By extending TRIG RCVD until the minimum off time expires and / or HON is set to the on state, state machine 122 ensures that the secondary converter does not skip conversion cycles, and the transient performance of the stacked converter is improved.

[0043] Figure 7 This is a graph showing the operation of an example power supply with and without a stackable switch-mode converter circuit 100 in a power supply with a primary converter and a secondary converter. Figure 7 The diagram shows the signal TRIG received by the secondary converter, the inductor current 706 in the primary converter, the inductor current 708 in the secondary converter without the stackable switch-mode converter circuit 100, and the inductor current 710 in the secondary converter with the stackable switch-mode converter circuit 100. Figure 5 also shows the output voltage (VOUT) 702 of the stacked converter with the stackable switch-mode converter circuit 100 and the VOUT 704 of the stacked converter without the stackable switch-mode converter circuit 100.

[0044] TRIG contains a primary trigger pulse and a secondary trigger pulse, with the primary pulse having a higher amplitude than the secondary pulse. At time 712, due to the increase in load current, the secondary trigger pulse is provided closer to the primary pulse than in the previous cycle. Inductor current 708 indicates that without the stackable switch-mode converter circuit 100, the secondary converter cannot respond, and the secondary converter does not provide current (the secondary converter skips a cycle). Inductor current 710 indicates that with the stackable switch-mode converter circuit 100, the secondary converter's response is delayed until the minimum off time from the previous cycle has expired, but the secondary converter does provide current (the secondary converter does not skip a cycle).

[0045] VOUT 702 and 704 show that, with the stackable switch-mode converter circuit 100, the transient response of the stackable converter is significantly improved compared to the case without the stackable switch-mode converter circuit 100.

[0046] Figure 8 This is a block diagram of an example system 800 including a power supply using a stackable switch-mode converter circuit 100. System 800 includes a power supply circuit 801 and a processor 812. The processor 812 may be a general-purpose microprocessor, a digital signal processor, a graphics processor, or any other type of processor used in a computer or computing application. The power supply circuit 801 includes a primary converter 802, a secondary converter 804, an inductor 806, an inductor 808, and a capacitor 810. Some embodiments of the power supply circuit 801 may include more than one secondary converter. The power supply circuit 801 generates a voltage to power the processor 812. The primary converter 802 and the secondary converter 804 are examples of the stackable switch-mode converter circuit 100. The primary converter 802 has a TRIG output coupled to the TRIG input of the secondary converter 804. The primary converter 802 provides a TRIG at the TRIG output to control the operation of the secondary converter 804. The switching terminal of the primary converter 802 is coupled to the first terminal of the inductor 806, and the second terminal of the inductor 806 is coupled to the first terminal of the capacitor 810. The switching terminal of the secondary converter 804 is coupled to the first terminal of the inductor 808, and the second terminal of the inductor 808 is coupled to the second terminal of the inductor 806. The first terminal of the capacitor 810 is coupled to the voltage input terminal of the processor 812, and the second terminal of the capacitor 810 is coupled to a reference terminal (e.g., ground).

[0047] The primary converter 802 and secondary converter 804 enable the power supply circuit 801 to provide significantly better transient response than other stacked converters using a single-signal control interface, while also reducing the integrated circuit package size compared to converters using multi-signal control interfaces. Examples of the power supply circuit 801 can be used in a wide variety of applications, including computing, communications, industrial, and other fields.

[0048] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0049] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends of device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0050] The circuits or devices described herein as containing certain components may be practically adaptable to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may practically contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0051] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used in practice with minimal alteration to the rest of the circuitry. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0052] The control input and current terminals of a transistor may be referenced in the claims. In the context of a FET, the control input (or transistor control terminal) is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0053] In this article, "FET on" means that there is a conductive channel in the FET and drain current can flow through it. "FET off" means that there is no conductive channel and therefore drain current does not flow through the FET. However, a "off" FET allows current to flow through the body diode of the transistor.

[0054] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0055] While some elements of the described examples are contained within the integrated circuit, while others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0056] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0057] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A circuit comprising: A first transistor and a second transistor, wherein the first transistor has a first control terminal and the second transistor has a second control terminal; A pulse width modulation (PWM) circuit having a first output coupled to the first control terminal, a second output coupled to the second control terminal, a first input, and a second input; A minimum shutdown timer having a timer output coupled to a first input of the PWM circuit; as well as A trigger circuit has a trigger signal output, a trigger signal input, and a trigger signal receiving output coupled to the PWM circuit. The trigger circuit includes a latch circuit having a first latch input coupled to the trigger signal input, a second latch input coupled to the timer output, and a latch output coupled to the second input of the PWM circuit.

2. The circuit of claim 1, wherein the trigger circuit is configured to: A trigger signal with a first sequence pulse and a second sequence pulse is generated, wherein the first sequence pulse indicates that the first transistor is turned on; and The trigger signal is provided at the trigger signal output.

3. The circuit of claim 1, wherein the trigger circuit is configured to receive a trigger signal at the trigger signal input, the trigger signal having a first sequential pulse and a second sequential pulse, the second sequential pulse indicating that the first transistor will be turned on.

4. The circuit according to claim 3, wherein the amplitude of the first sequential pulse is greater than the amplitude of the second sequential pulse.

5. The circuit of claim 3, wherein the latching circuit is configured to: A trigger receive signal is provided at the latch output; In response to the second sequential pulse, the trigger receiving signal is set to a first state; and In response to the expiration of the minimum shutdown time generated by the minimum shutdown timer, the trigger receive signal is set to the second state.

6. The circuit of claim 5, wherein the PWM circuit is configured to: A transistor control signal is provided at the first output of the PWM circuit; and In response to the trigger receiving signal having the first state and the minimum shutdown time expiring, the transistor control signal is set to the first state.

7. The circuit of claim 6, wherein the latch circuit is configured to set the trigger receive signal to the second state in response to the transistor control signal having the second state.

8. A power supply circuit, comprising: A first switch-mode converter has a trigger output and a first current output. The first switch-mode converter is configured to provide a trigger signal at the trigger output having a first sequential pulse and a second sequential pulse, the first sequential pulse indicating that the first switch-mode converter is providing current at the first current output. A second switch-mode converter has a trigger input coupled to the trigger output and a second current output coupled to the first current output. The second switch-mode converter includes: A trigger circuit configured to receive the trigger signal and identify the second sequential pulse; A minimum shutdown timer, configured to define the minimum shutdown time during which current flow to the second current output is prohibited; A latching circuit configured to set a trigger receiving signal to a first state in response to the second sequential pulse; And in response to the expiration of the minimum shutdown time, the trigger receiving signal is set to the second state; as well as A pulse width modulation (PWM) circuit coupled to the latch circuit, the PWM circuit being configured to allow current flow to the second current output in response to the trigger receive signal having the first state and the minimum off time expiring.

9. The power supply circuit of claim 8, wherein the latching circuit is configured to set the trigger receiving signal to the second state based on the prohibition of current flow to the second current output.

10. The power supply circuit of claim 8, wherein the latching circuit is configured to set the trigger receiving signal to the first state based on the current flow to the second current output being permitted or the minimum shutdown time not having expired.

11. The power supply circuit of claim 8, wherein the first sequential pulse has a first amplitude and the second sequential pulse has a second amplitude.

12. The power supply circuit of claim 11, wherein the first amplitude is greater than the second amplitude.

13. The power supply circuit according to claim 8, wherein the trigger circuit comprises: A sensing circuit configured to set the sensing signal to a first state in response to the second sequential pulse. And in response to the first sequential pulse, the sensing signal is set to a second state; and A latching circuit configured to set the trigger receiving signal to the first state in response to the sensing signal changing from the second state to the first state.

14. The power supply circuit of claim 8, wherein the minimum shutdown timer is configured to begin the minimum shutdown time in response to the PWM circuit prohibiting current flow to the second current output.

15. A system comprising: A processor that has a voltage input; as well as A power supply circuit having a voltage output coupled to the voltage input of the processor, the power supply circuit comprising: An inductor having a first terminal coupled to the voltage input of the processor, and a second terminal; A switch-mode converter circuit having a current output coupled to a second terminal of the inductor and a trigger input configured to receive trigger signals having a first sequence pulse and a second sequence pulse, the switch-mode converter circuit comprising: A trigger circuit configured to receive the trigger signal and identify the second sequential pulse; A minimum shutdown timer, configured to define the minimum shutdown time during which current flow to the current output is prohibited; A latching circuit configured to set a trigger receiving signal to a first state in response to the second sequential pulse; And in response to the expiration of the minimum shutdown time, the trigger receiving signal is set to the second state; as well as A pulse width modulation (PWM) circuit coupled to the latch circuit, the PWM circuit being configured to allow current flow to the current output in response to the trigger receive signal having the first state and the minimum off time expiring.

16. The system of claim 15, wherein the amplitude of the first sequential pulse is greater than the amplitude of the second sequential pulse.

17. The system of claim 15, wherein the latching circuit is configured to set the trigger receiving signal to the second state based on the prohibition of current flow to the current output.

18. The system of claim 15, wherein the latching circuit is configured to set the trigger receiving signal to the first state based on whether current flow to the current output is permitted or the minimum shutdown time has not expired.

19. The system of claim 15, wherein the trigger circuit comprises: A sensing circuit configured to set the sensing signal to a first state in response to the second sequential pulse. And in response to the first sequential pulse, the sensing signal is set to a second state; and A latching circuit configured to set the trigger receiving signal to the first state in response to the sensing signal changing from the second state to the first state.

20. The system of claim 15, wherein the minimum shutdown timer is configured to begin the minimum shutdown time in response to the PWM circuit prohibiting current flow to the current output.

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