Spread spectrum clock circuit

Abstract

The invention discloses a spread spectrum clock circuit. The spread spectrum clock circuit is characterized in that a first phase frequency detector forms a first phase difference signal; the first charge pump forms a first current according to the first phase difference signal; the first loop filter forms a first voltage according to the first current; the first voltage-controlled oscillator forms a first output clock signal according to the first voltage; the first frequency divider forms a first feedback clock signal; the second phase frequency detector forms a second phase difference signal; the second charge pump forms a second current according to the second phase difference signal; the second loop filter forms a second voltage according to the second current; the spread spectrum voltage generation module generates a voltage-controlled voltage waveform for controlling the second voltage-controlled oscillator according to the first voltage and the second voltage, and the voltage-controlled voltage waveform is used for changing the frequency of a second output clock signal generated by the second voltage-controlled oscillator; the second frequency divider forms a second feedback clock signal. According to the invention, the spread spectrum range of the clock signal finally output by the spread spectrum clock circuit is determined.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a spread spectrum clock circuit. Background Technology

[0002] Spread spectrum clocking is a process of jittering the system clock in a controlled manner to reduce the peak energy of the clock output spectrum. Spread spectrum clocking is widely used in various circuit systems, mainly to reduce the electromagnetic interference of the clock on the system.

[0003] In the prior art, spread spectrum clock circuits can be implemented by phase-locked loops, and the spread spectrum capability of spread spectrum clock circuits can be implemented by modulation circuits. However, modulation circuits do not have feedback signals to control the spread spectrum depth, resulting in low accuracy of the spread spectrum range of spread spectrum clock circuits under temperature and process variations. Summary of the Invention

[0004] This invention provides a spread spectrum clock circuit to solve the problem of low spread spectrum range accuracy in existing spread spectrum clock circuits.

[0005] In a first aspect, the present invention provides a spread spectrum clock circuit, the circuit comprising: a first frequency and phase detector, a first charge pump, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, a second frequency and phase detector, a second charge pump, a second loop filter, a spread spectrum voltage generation module, a second voltage-controlled oscillator, and a second frequency divider.

[0006] The first input terminal of the first frequency and phase detector is used to input a first reference clock signal. The second input terminal of the first frequency and phase detector is connected to the output terminal of the first frequency divider. The output terminal of the first frequency and phase detector is connected to the input terminal of the first charge pump. The output terminal of the first charge pump is connected to the input terminal of the first loop filter. The output terminal of the first loop filter is connected to the input terminal of the first voltage-controlled oscillator and the first input terminal of the spread spectrum voltage generation module. The output terminal of the first voltage-controlled oscillator is connected to the input terminal of the first frequency divider. The first frequency and phase detector is used to generate a first phase difference signal based on the first reference clock signal and the first feedback clock signal. The first charge pump is used to generate a first current based on the first phase difference signal. The first loop filter is used to generate a first voltage based on the first current. The first voltage-controlled oscillator is used to generate a first output clock signal based on the first voltage. The first frequency divider is used to divide the first output clock signal by a first division ratio to generate a first feedback clock signal.

[0007] The first input terminal of the second frequency and phase detector is used to input a second reference clock signal. The second input terminal of the second frequency and phase detector is connected to the output terminal of the second frequency divider. The output terminal of the second frequency and phase detector is connected to the input terminal of the second charge pump. The output terminal of the second charge pump is connected to the input terminal of the second loop filter. The output terminal of the second loop filter is connected to the second input terminal of the spread spectrum voltage generation module. The output terminal of the spread spectrum voltage generation module is connected to the input terminal of the second voltage-controlled oscillator. The output terminal of the second voltage-controlled oscillator is connected to the input terminal of the second frequency divider. The second frequency and phase detector is used to generate a second phase difference signal based on the second reference clock signal and the second feedback clock signal. The second charge pump is used to generate a second current based on the second phase difference signal. The second loop filter is used to generate a second voltage based on the second current. The spread spectrum voltage generation module is used to generate a voltage-controlled voltage waveform to control the second voltage-controlled oscillator based on the first voltage and the second voltage. The second voltage-controlled oscillator is used to generate a first output clock signal based on the voltage-controlled voltage waveform. The voltage-controlled voltage waveform is used to change the frequency of the second output clock signal generated by the second voltage-controlled oscillator. The second frequency divider is used to divide the second output clock signal by a second division ratio to form a second feedback clock signal.

[0008] Optionally, the spread spectrum voltage generation module includes a level generator and a waveform generator;

[0009] The first input terminal of the level generator is connected to the output terminal of the first loop filter, and the second input terminal of the level generator is connected to the output terminal of the second loop filter. The first input terminal of the waveform generator is connected to the first output terminal of the level generator, and the second input terminal of the waveform generator is connected to the second output terminal of the level generator. The output terminal of the waveform generator is connected to the input terminal of the second voltage-controlled oscillator. The level generator is used to generate the maximum and minimum values ​​of the voltage-controlled voltage waveform based on the first voltage and the second voltage, and the waveform generator is used to generate the voltage-controlled voltage waveform based on the maximum and minimum values ​​of the voltage-controlled voltage waveform.

[0010] Optionally, the level generator includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a sixth PMOS transistor, a first operational amplifier, and a first resistor;

[0011] The gate of the first NMOS transistor is connected to the output of the second loop filter, the source of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the first PMOS transistor, and the source of the first PMOS transistor is connected to the power supply.

[0012] The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source of the second PMOS transistor is connected to the power supply, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor; the source of the second NMOS transistor is grounded.

[0013] The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate and drain of the second NMOS transistor, and the drain of the fourth NMOS transistor is connected to the drain and gate of the third PMOS transistor. The gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, the source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply.

[0014] The gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor, the drain of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor is connected to the power supply; the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the fifth PMOS transistor is connected to the output terminal of the first operational amplifier.

[0015] The output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier, and the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first loop filter.

[0016] The first end of the first resistor is connected to the output of the first operational amplifier, and the second end of the first resistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the fifth NMOS transistor is grounded.

[0017] The present invention provides a spread spectrum clock circuit, comprising a first phase-locked loop (PLL) consisting of a first phase detector, a first charge pump, a first loop filter, a first voltage-controlled oscillator (VCO), and a first frequency divider; and a second phase-locked loop consisting of a second phase detector, a second charge pump, a second loop filter, a spread spectrum voltage generation module, a second VCO, and a second frequency divider. The spread spectrum voltage generation module generates a voltage-controlled voltage waveform based on the outputs of the first and second loop filters and outputs it to the second VCO. The frequency of the second output clock signal from the second VCO varies with the voltage-controlled voltage waveform, thereby ensuring that the spread spectrum range of the final clock signal output by the spread spectrum clock circuit is determined. This avoids the problem of low spread spectrum range accuracy in the prior art when temperature and process variations occur.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a spread spectrum clock circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of another spread spectrum clock circuit provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the connection between a first loop filter, a second loop filter, and a level generator provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 1 This is a schematic diagram of a spread spectrum clock circuit provided in an embodiment of the present invention. Figure 1 As shown, the circuit includes: a first frequency and phase detector 8, a first charge pump 9, a first loop filter 1, a first voltage-controlled oscillator 2, a first frequency divider 7, a second frequency and phase detector 10, a second charge pump 11, a second loop filter 3, a spread spectrum voltage generation module 4, a second voltage-controlled oscillator 5, and a second frequency divider 6.

[0026] The first input terminal of the first frequency and phase detector 8 is used to input the first reference clock signal CLK1. The second input terminal of the first frequency and phase detector 8 is connected to the output terminal of the first frequency divider 7. The output terminal of the first frequency and phase detector 8 is connected to the input terminal of the first charge pump 9. The output terminal of the first charge pump 9 is connected to the input terminal of the first loop filter 1. The output terminal of the first loop filter 1 is connected to the input terminal of the first voltage-controlled oscillator 2 and the first input terminal of the spread spectrum voltage generation module 4. The output terminal of the first voltage-controlled oscillator 2 is connected to the input terminal of the first frequency divider 7. The first frequency and phase detector 8 is used to generate a first phase difference signal based on the first reference clock signal CLK1 and the first feedback clock signal. The first charge pump 9 is used to generate a first current based on the first phase difference signal. The first loop filter 1 is used to generate a first voltage based on the first current. The first voltage-controlled oscillator 2 is used to generate a first output clock signal based on the first voltage. The first frequency divider 7 is used to divide the first output clock signal by a first division ratio to generate a first feedback clock signal.

[0027] The first input terminal of the second frequency and phase detector 10 is used to input the second reference clock signal CLK2. The second input terminal of the second frequency and phase detector 10 is connected to the output terminal of the second frequency divider 6. The output terminal of the second frequency and phase detector 10 is connected to the input terminal of the second charge pump 11. The output terminal of the second charge pump 11 is connected to the input terminal of the second loop filter 3. The output terminal of the second loop filter 3 is connected to the second input terminal of the spread spectrum voltage generation module 4. The output terminal of the spread spectrum voltage generation module 4 is connected to the input terminal of the second voltage-controlled oscillator 5. The output terminal of the second voltage-controlled oscillator 5 is connected to the input terminal of the second frequency divider 6. The second frequency and phase detector 10 is used to generate a second phase difference signal based on the second reference clock signal CLK2 and the second feedback clock signal. The second charge pump 11 is used to generate a second current based on the second phase difference signal. The second loop filter 3 is used to generate a second voltage based on the second current. The spread spectrum voltage generation module 4 is used to generate a voltage-controlled voltage waveform that controls the second voltage-controlled oscillator 5 based on the first voltage and the second voltage. The second voltage-controlled oscillator 5 is used to generate a first output clock signal based on the voltage-controlled voltage waveform. The voltage-controlled voltage waveform is used to change the frequency of the second output clock signal generated by the second voltage-controlled oscillator 5. The second frequency divider 6 is used to divide the second output clock signal by a second division ratio to generate a second feedback clock signal.

[0028] Specifically, the first phase-frequency discriminator 8, the first charge pump 9, the first loop filter 1, the first voltage-controlled oscillator 2, and the first frequency divider 7 constitute the first phase-locked loop (PLL), and the second phase-frequency discriminator 10, the second charge pump 11, the second loop filter 3, the spread spectrum voltage generation module 4, the second voltage-controlled oscillator 5, and the second frequency divider 6 constitute the second PLL. The technical solution of this embodiment includes three cases: the first reference clock signal CLK1 and the second reference clock signal CLK2 have the same frequency, and the first frequency divider 7 and the second frequency divider 6 are set with different division ratios; the first reference clock signal CLK1 and the second reference clock signal CLK2 have different frequencies, and the first frequency divider 7 and the second frequency divider 6 are set with the same division ratio; or the first reference clock signal CLK1 and the second reference clock signal CLK2 have different frequencies, and the first frequency divider 7 and the second frequency divider 6 are set with different division ratios.

[0029] For example, the frequencies of the first reference clock signal CLK1 and the second reference clock signal CLK2 are set to be the same. The first voltage-controlled oscillator 2 and the second voltage-controlled oscillator 5 are set to be identical. The first frequency divider 7 and the second frequency divider 6 are set to different division ratios, so that the first phase-locked loop is locked to the highest frequency of the spread spectrum clock signal. The frequency of the first output clock signal output by the first voltage-controlled oscillator 2 is the highest frequency of the spread spectrum clock signal. The maximum value of the voltage waveform output by the spread spectrum voltage generation module 4 is the output voltage of the first loop filter 1. The second phase-locked loop is locked to the average frequency of the spread spectrum clock signal. The average frequency of the second output clock signal output by the second voltage-controlled oscillator 5 is the average frequency of the spread spectrum clock signal. The spread spectrum clock signal is the second output clock signal.

[0030] The first reference clock signal CLK1 and the second reference clock signal CLK2 are set to have different frequencies. The first voltage-controlled oscillator 2 and the second voltage-controlled oscillator 5 are set to be identical. The first frequency divider 7 and the second frequency divider 6 are set to the same division ratio, so that the first phase-locked loop is locked to the highest frequency of the spread spectrum clock signal. The frequency of the first output clock signal output by the first voltage-controlled oscillator 2 is the highest frequency of the spread spectrum clock signal. The maximum value of the voltage waveform output by the spread spectrum voltage generation module 4 is the output voltage of the first loop filter 1. The second phase-locked loop is locked to the average frequency of the spread spectrum clock signal. The average frequency of the second output clock signal output by the second voltage-controlled oscillator 5 is the average frequency of the spread spectrum clock signal. The spread spectrum clock signal is the second output clock signal.

[0031] The first reference clock signal CLK1 and the second reference clock signal CLK2 are set to have different frequencies. The first voltage-controlled oscillator 2 and the second voltage-controlled oscillator 5 are set to be identical. The first frequency divider 7 and the second frequency divider 6 are set to different division ratios, so that the first phase-locked loop is locked to the highest frequency of the spread spectrum clock signal. The frequency of the first output clock signal output by the first voltage-controlled oscillator 2 is the highest frequency of the spread spectrum clock signal. The maximum value of the voltage waveform output by the spread spectrum voltage generation module 4 is the output voltage of the first loop filter 1. The second phase-locked loop is locked to the average frequency of the spread spectrum clock signal. The average frequency of the second output clock signal output by the second voltage-controlled oscillator 5 is the average frequency of the spread spectrum clock signal. The spread spectrum clock signal is the second output clock signal.

[0032] The technical solution of this invention provides a spread spectrum clock circuit, including a first phase-locked loop (PLL) composed of a first phase detector, a first charge pump, a first loop filter, a first voltage-controlled oscillator (VCO), and a first frequency divider; and a second phase-locked loop composed of a second phase detector, a second charge pump, a second loop filter, a spread spectrum voltage generation module, a second VCO, and a second frequency divider. The spread spectrum voltage generation module generates a voltage-controlled voltage waveform based on the outputs of the first and second loop filters and outputs it to the second VCO. The frequency of the second output clock signal from the second VCO varies with the voltage-controlled voltage waveform, thereby ensuring that the spread spectrum range of the final clock signal output by the spread spectrum clock circuit is determined. This avoids the problem of low spread spectrum range accuracy in the prior art when temperature and process variations occur.

[0033] Figure 2 This is a schematic diagram of another spread spectrum clock circuit provided in an embodiment of the present invention, as shown below. Figure 2 As shown, the spread spectrum voltage generation module 4 includes a level generator 41 and a waveform generator 42. The first input terminal of the level generator 41 is connected to the output terminal of the first loop filter 1, the second input terminal of the level generator 41 is connected to the output terminal of the second loop filter 3, the first output terminal of the level generator 41 is connected to the first input terminal of the waveform generator 42, and the second output terminal of the level generator 41 is connected to the second input terminal of the waveform generator 42. The output terminal of the waveform generator 42 is connected to the input terminal of the second voltage-controlled oscillator 5. The level generator 41 is used to generate the maximum value VH and minimum value VL of the voltage-controlled voltage waveform based on the voltage output of the first loop filter 1 and the voltage output of the second loop filter 3. The waveform generator 42 is used to generate the voltage-controlled voltage waveform based on the maximum value VH and minimum value VL of the voltage-controlled voltage waveform.

[0034] Specifically, waveform generator 42 generates a voltage-controlled voltage waveform based on the maximum value VH and the minimum value VL of the voltage-controlled voltage waveform, where the minimum value is VL and the maximum value is VH. For example, the voltage-controlled voltage waveform can be a triangular wave or other preset waveform. The voltage-controlled voltage waveform generated by waveform generator 42 is output to the second voltage-controlled oscillator 5, serving as the voltage-controlled voltage signal for the second voltage-controlled oscillator 5. The output frequency of the second voltage-controlled oscillator 5 changes according to the voltage value of the voltage-controlled voltage signal. The second phase-locked loop (PLL) locks the average frequency of the second output clock signal from the second voltage-controlled oscillator (VCO) 5. Since the maximum value of the voltage-controlled voltage waveform is VH, which is the voltage-controlled voltage of the first VCO 2, and the output frequency of the first PLL is the maximum frequency of the spread spectrum clock signal, and since the first VCO 2 is the same as the second VCO 5, the maximum value of the output frequency of the second PLL is the maximum frequency of the spread spectrum clock signal. The average value of the output frequency of the second PLL is locked by the frequency of the second reference clock signal CLK2 and the division ratio of the second frequency divider 6. In this way, the maximum and minimum values ​​of the signal frequency output by the second PLL are determined, that is, the maximum and minimum values ​​of the frequency of the second output clock signal from the second VCO 5 are determined. This avoids the problem of low spread spectrum accuracy of the spread spectrum clock circuit under temperature and process changes in the prior art.

[0035] Figure 3 This is a schematic diagram of the connection structure of a first loop filter, a second loop filter, and a level generator provided in an embodiment of the present invention, as shown below. Figure 3As shown, the level generator 41 includes a first NMOS transistor Q1, a first PMOS transistor Q2, a second NMOS transistor Q4, a second PMOS transistor Q3, a third NMOS transistor Q5, a third PMOS transistor Q7, a fourth NMOS transistor Q6, a fourth PMOS transistor Q8, a fifth NMOS transistor Q12, a fifth PMOS transistor Q10, a sixth NMOS transistor Q11, a sixth PMOS transistor Q9, a first operational amplifier U1, and a first resistor R1. The gate of the first NMOS transistor Q1 is connected to the output terminal of the second loop filter 3, the source of the first NMOS transistor Q1 is grounded to GND, and the drain of the first NMOS transistor Q1 is connected to the drain and gate of the first PMOS transistor Q2. The source of the first PMOS transistor Q2 is connected to the power supply VDD; the gate of the second PMOS transistor Q3 is connected to the gate of the first PMOS transistor Q2, the source of the second PMOS transistor Q3 is connected to the power supply VDD, the drain of the second PMOS transistor Q3 is connected to the drain and gate of the second NMOS transistor Q4, and the source of the second NMOS transistor Q4 is grounded to GND. The gate of the third NMOS transistor Q5 is connected to the gate of the first NMOS transistor Q1, the source of the third NMOS transistor Q5 is grounded to GND, and the drain of the third NMOS transistor Q5 is connected to the source of the fourth NMOS transistor Q6. The gate of the fourth NMOS transistor Q6 is connected to the gate and drain of the second NMOS transistor Q4. The drain of the fourth NMOS transistor Q6 is connected to the drain of the third PMOS transistor Q7 and the gate of the fourth PMOS transistor Q8. The gate of the third PMOS transistor Q7 is connected to the gate of the first PMOS transistor Q2. The source of the third PMOS transistor Q7 is connected to the drain of the fourth PMOS transistor Q8. The source of the fourth PMOS transistor Q8 is connected to the power supply VDD. The gate of the sixth PMOS transistor Q9 is connected to the gate of the fourth PMOS transistor Q8. The drain of the sixth PMOS transistor Q9 is connected to the source of the fifth PMOS transistor Q10. The source of the sixth PMOS transistor Q9 is connected to the power supply VDD. The gate of the fifth PMOS transistor Q10 is connected to the gate of the first PMOS transistor Q2. The drain of the fifth PMOS transistor Q10 is connected to the output terminal of the first operational amplifier U1. The output terminal of the first operational amplifier U1 is connected to its inverting input terminal, and the non-inverting input terminal is connected to the output terminal of the first loop filter 1. The first terminal of the first resistor R1 is connected to the output terminal of the first operational amplifier U1, and the second terminal of the first resistor R1 is connected to the drain of the sixth NMOS transistor Q11. The gate of the sixth NMOS transistor Q11 is connected to the gate of the fourth NMOS transistor Q6, and the source of the sixth NMOS transistor Q11 is connected to the drain of the fifth NMOS transistor Q12. The gate of the fifth NMOS transistor Q12 is connected to the gate of the first NMOS transistor Q1, and the source of the fifth NMOS transistor Q12 is grounded (GND).

[0036] The output of operational amplifier U1 serves as the first output of level generator 41, and the drain of the sixth NMOS transistor Q11 serves as the second output of level generator 41. The output of the first loop filter 1 serves as the first input of level generator 41, and the output of the second loop filter 3 serves as the second input of level generator 41.

[0037] In this embodiment of the invention, the first NMOS transistor Q1, the first PMOS transistor Q2, the second NMOS transistor Q4, the second PMOS transistor Q3, the third NMOS transistor Q5, the third PMOS transistor Q7, the fourth NMOS transistor Q6, and the fourth PMOS transistor Q8 together convert the output voltage of the second loop filter 3 of the second phase-locked loop into current. The magnitude of this current is determined by the output voltage of the second loop filter 3 and the size of the third NMOS transistor Q5. Because the gate of the fourth PMOS transistor Q8 is connected to the gate of the sixth PMOS transistor Q9, and the gate of the third PMOS transistor Q7 is connected to the gate of the fifth PMOS transistor Q10; the gate of the fourth NMOS transistor Q6 is connected to the gate of the sixth NMOS transistor Q11, and the gate of the third NMOS transistor Q5 is connected to the gate of the fifth NMOS transistor Q12, the current flowing through the fourth PMOS transistor Q8 and the third PMOS transistor Q7 is mirrored as the current flowing through the sixth PMOS transistor Q9 and the fifth PMOS transistor Q10, and the current flowing through the fourth NMOS transistor Q6 and the third NMOS transistor Q5 is mirrored as the current flowing through the sixth NMOS transistor Q11 and the fifth NMOS transistor Q12. The aspect ratio of the fourth NMOS transistor Q6 is... The aspect ratio of the third NMOS transistor Q5 is... The aspect ratio of the sixth NMOS transistor Q11 Let the width-to-length ratio of the fifth NMOS transistor Q12 be denoted as... The aspect ratio of the fourth PMOS transistor Q8 is... The aspect ratio of the third PMOS transistor Q7 is... The aspect ratio of the sixth PMOS transistor Q9 is... The width-to-length ratio of the fifth PMOS transistor Q10 should be designed such that:

[0038]

[0039] In this embodiment of the invention, based on the working principle of operational amplifier U1, when operational amplifier U1 is working normally, the maximum value VH of the voltage-controlled voltage waveform is equal to the output voltage of the first loop filter 1. The minimum value VL of the voltage-controlled voltage waveform is determined by the maximum value VH of the voltage-controlled voltage waveform, the first resistor R1, and the current flowing through the sixth NMOS transistor Q11 and the fifth NMOS transistor Q12. The current flowing through the sixth NMOS transistor Q11 and the fifth NMOS transistor Q12 is jointly determined by the output voltage of the second loop filter 3 and the third NMOS transistor Q5.

[0040] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0041] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A spread spectrum clock circuit, characterized by, include: First frequency and phase detector, first charge pump, first loop filter, first voltage-controlled oscillator, first frequency divider, second frequency and phase detector, second charge pump, second loop filter, spread spectrum voltage generation module, second voltage-controlled oscillator and second frequency divider; The first input terminal of the first frequency and phase detector is used to input a first reference clock signal; the second input terminal of the first frequency and phase detector is connected to the output terminal of the first frequency divider; the output terminal of the first frequency and phase detector is connected to the input terminal of the first charge pump; the output terminal of the first charge pump is connected to the input terminal of the first loop filter; the output terminal of the first loop filter is connected to the input terminal of the first voltage-controlled oscillator and the first input terminal of the spread spectrum voltage generation module; the output terminal of the first voltage-controlled oscillator is connected to the input terminal of the first frequency divider. The first frequency and phase detector is used to form a first phase difference signal based on the first reference clock signal and the first feedback clock signal; The first charge pump is used to generate a first current based on the first phase difference signal; the first loop filter is used to generate a first voltage based on the first current; the first voltage-controlled oscillator is used to generate a first output clock signal based on the first voltage; the first frequency divider is used to divide the first output clock signal by a first frequency division ratio to generate the first feedback clock signal. The first input terminal of the second frequency and phase detector is used to input a second reference clock signal. The second input terminal of the second frequency and phase detector is connected to the output terminal of the second frequency divider. The output terminal of the second frequency and phase detector is connected to the input terminal of the second charge pump. The output terminal of the second charge pump is connected to the input terminal of the second loop filter. The output terminal of the second loop filter is connected to the second input terminal of the spread spectrum voltage generation module. The output terminal of the spread spectrum voltage generation module is connected to the input terminal of the second voltage-controlled oscillator. The output terminal of the second voltage-controlled oscillator is connected to the input terminal of the second frequency divider. The second frequency and phase detector is used to generate a second phase difference signal based on the second reference clock signal and the second feedback clock signal; the second charge pump is used to generate a second current based on the second phase difference signal; the second loop filter is used to generate a second voltage based on the second current; the spread spectrum voltage generation module is used to generate a voltage-controlled voltage waveform that controls the second voltage-controlled oscillator based on the first voltage and the second voltage, and the second voltage-controlled oscillator is used to generate a first output clock signal based on the voltage-controlled voltage waveform; the voltage-controlled voltage waveform is used to change the frequency of the second output clock signal generated by the second voltage-controlled oscillator; the second frequency divider is used to divide the second output clock signal by a second division ratio to generate the second feedback clock signal.

2. The spread spectrum clock circuit of claim 1, wherein, The spread spectrum voltage generation module includes a level generator and a waveform generator; The first input terminal of the level generator is connected to the output terminal of the first loop filter, the second input terminal of the level generator is connected to the output terminal of the second loop filter, the first input terminal of the waveform generator is connected to the first output terminal of the level generator, the second input terminal of the waveform generator is connected to the second output terminal of the level generator, and the output terminal of the waveform generator is connected to the input terminal of the second voltage-controlled oscillator. The level generator is used to generate the maximum and minimum values ​​of the voltage-controlled voltage waveform based on the first voltage and the second voltage, and the waveform generator is used to generate the voltage-controlled voltage waveform based on the maximum and minimum values ​​of the voltage-controlled voltage waveform.

3. The spread spectrum clock circuit according to claim 2, characterized in that, The level generator includes a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a sixth PMOS transistor, a first operational amplifier, and a first resistor; The gate of the first NMOS transistor is connected to the output terminal of the second loop filter, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gate of the first PMOS transistor; the source of the first PMOS transistor is connected to the power supply. The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source of the second PMOS transistor is connected to the power supply, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor; the source of the second NMOS transistor is grounded. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate and drain of the second NMOS transistor, and the drain of the fourth NMOS transistor is connected to the drain and gate of the third PMOS transistor. The gate of the third PMOS transistor is connected to the gate of the first PMOS transistor, the source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply. The gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor, the drain of the sixth PMOS transistor is connected to the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor is connected to the power supply; the gate of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the fifth PMOS transistor is connected to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier, and the non-inverting input terminal of the first operational amplifier is connected to the output terminal of the first loop filter. The first end of the first resistor is connected to the output terminal of the first operational amplifier, and the second end of the first resistor is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the sixth NMOS transistor is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the fifth NMOS transistor is grounded.

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