Circuit with clock and data recovery circuit

Abstract

This invention provides a circuit including a phase-locked loop (PLL) and a clock-redirecting circuit (CDR). The CDR circuit includes a phase detector, a loop filter, an SSC demodulator, a control code generator, and a phase interpolator. The PLL is configured to generate a clock signal and an SSC direction signal with SSC modulation. The phase detector compares the phase of the input signal with that of the output clock signal to generate a detection result, wherein the input signal has SSC modulation. The loop filter filters the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator generates a control code based on the filtered signal and the control signal to control the phase interpolator to adjust the phase of the clock signal to generate an output clock signal. Using this scheme, the static phase error between the input signal and the output clock signal can be reduced.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a clock and data recovery circuit with a spread spectrum clock synthesizer. Background Technology

[0002] In digital clock and data recovery (CDR) circuits of serializer / deserializer (SerDes) with spread spectrum clocking (SSC), the CDR circuit receives the input signal from the previous stage and a reference clock signal to generate the output clock signal. The reference clock signal typically originates from the phase-locked loop (PLL) of the SerDes transmitter. However, because the near-end SSC used in the reference clock signal differs from the far-end SSC used in the input signal, a residual static phase error exists between the input and output clock signals, thus degrading receiver performance. Summary of the Invention

[0003] Therefore, the purpose of this invention is to provide a CDR circuit with a small static phase error between the input signal and the output clock signal, so as to solve the above-mentioned problems.

[0004] According to one embodiment of the present invention, a circuit including a PLL and a CDR circuit is disclosed, wherein the CDR circuit includes a phase detector, a digital loop filter, an SSC demodulator, a control code generator, and a phase interpolator. The PLL is configured to generate a first clock signal with SSC modulation and an SSC direction signal. The phase detector is configured to compare the phase of an input signal with the phase of an output clock signal to generate a detection result, wherein the input signal has SSC modulation. The digital loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code based on the filtered signal and the control signal. The phase interpolator is configured to use the control code to adjust the phase of the first clock signal to generate an output clock signal.

[0005] According to one embodiment of the present invention, a circuit including a PLL and a CDR circuit is disclosed, wherein the CDR circuit includes a phase detector, a digital loop filter, a first phase interpolator, and a second phase interpolator. The PLL is configured to generate a first clock signal with SSC modulation and a control signal. The phase detector is configured to generate a detection result based on an input signal and an output clock signal, wherein the input signal has SSC modulation. The digital loop filter is coupled to the phase detector for filtering the detection result to generate a filtered signal. The first phase interpolator is used to generate an output clock signal based on the filtered signal and the first clock signal. The second phase interpolator is used to eliminate the SSC of the first clock signal or eliminate the SSC component contributed by the first clock signal in the output clock signal according to the control signal.

[0006] In this configuration, the second phase interpolator is located between the phase detector and the first phase interpolator. The second phase interpolator adjusts the phase of the output clock signal to generate an adjusted output clock signal, and the phase detector compares the phase of the input signal with the phase of the adjusted output clock signal to generate a detection result. Alternatively, the second phase interpolator is located between the PLL and the first phase interpolator. The second phase interpolator adjusts the phase of the first clock signal to generate a second clock signal, and the first phase interpolator adjusts the phase of the second clock signal according to the filtered signal to generate the output clock signal.

[0007] The circuit provided in this application can reduce the static phase error between the input signal and the output clock signal.

[0008] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a CDR circuit according to an embodiment of the present invention.

[0010] Figure 2 A timing diagram of the SSC direction signal, TXSSC and related signals according to an embodiment of the present invention is shown.

[0011] Figure 3 This shows that the static phase error has been halved.

[0012] Figure 4 This is a schematic diagram of a CDR circuit according to an embodiment of the present invention.

[0013] Figure 5 This is a schematic diagram of a CDR circuit according to an embodiment of the present invention. Detailed Implementation

[0014] Certain terms are used throughout the following description and claims to refer to specific system components. As those skilled in the art will understand, manufacturers may use different names to refer to components. This application is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including but not limited to...". The term "coupled" is intended to indicate either an indirect electrical connection or a direct electrical connection. Thus, if a first device is coupled to a second device, the connection can be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0015] Figure 1 This is a schematic diagram of a CDR circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the CDR circuit 100 is a phase interpolator (PI) based CDR circuit, including a phase detector (in this embodiment, a bang-bang phase detector (BBPD) 110), a frequency converter 120, a digital loop filter 130, an SSC demodulator 140, a control code generator 150, and a phase interpolator 160. In this embodiment, the CDR circuit 100 is used in a SerDes with SSC for high-speed communication.

[0016] In the operation of CDR circuit 100, BBPD 110 receives the input signal (digital input signal) Din from the previous stage and compares the phase of the input signal Din with the phase of the output clock signal CKout to generate a detection result. The input signal Din has SSC modulation, and the detection result can indicate the phase information between the input signal Din and the output clock signal CKout (e.g., the phase of the input signal Din leads the phase of the output clock signal CKout, or the phase of the input signal Din lags the phase of the output clock signal CKout). Frequency converter 120 is optional and converts the frequency of the detection result to another frequency. Then, digital loop filter 130 filters the detection result to generate a filtered signal for control code generator 150, which generates control codes. Phase interpolator 160 then uses the control codes generated by control code generator 150 to adjust the phase of clock signal CK1 to generate the output clock signal CKout. Furthermore, each of the clock signal CK1 and the output clock signal CKout can be a single-phase clock signal or a clock signal with multiple phases.

[0017] It should be noted that the operation of BBPD 110, frequency converter 120, digital loop filter 130 and phase interpolator 160 is known to those skilled in the art, and this embodiment focuses on SSC demodulator 140 and control code generator 150. Therefore, the following description focuses on SSC demodulator 140, and details of other components are omitted here.

[0018] In this embodiment, the PLL 102 of the transmitter generates a clock signal CK1 using a reference clock signal CKREF, where the clock signal CK1 is SSC modulated. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK1. However, due to frequency drift and differential design methods, the frequency and SSC amplitude of the input signal Din are not the same as those of the clock signal CK1, and a residual static phase error exists between the input signal Din and the output clock signal CKout. Specifically, assuming that the CDR circuit 100 uses a second-order loop to track the SSC, the static phase error between the input signal Din and the output clock signal CKout can be expressed as:

[0019]

[0020] Where “s” is the complex frequency parameter of the Laplace transform, G(s) is the loop gain, and “A” is a constant related to the SSC amplitude. In order to suppress static phase error, the CDR circuit 100 includes an SSC demodulator 140 to reduce the value “A” in the above formula.

[0021] SSC demodulator 140 receives the SSC direction signal ssc_dir from PLL 102, where the SSC direction signal ssc_dir indicates the direction of frequency change. Figure 2 For example, "TXSSC" represents the frequency of clock signal CK1, where the frequency of clock signal CK1 varies between a specific frequency (e.g., 5 GHz) and (1 ppm - 10000 ppm) * a specific frequency. It is worth noting that the SSC amplitude provided here is for illustrative purposes; in other embodiments, the SSC amplitude can be any other suitable value, such as 5000 ppm. The SSC direction signal ssc_dir can be a square wave, where a high level indicates that the frequency of clock signal CK1 is decreasing, and a low level indicates that the frequency of clock signal CK1 is increasing. After receiving the SSC direction signal ssc_dir, the SSC synthesizer within the SSC demodulator 140 can generate a control signal Vc, which has information about the SSC amplitude and frequency information opposite to the frequency of TXSSC, wherein... Figure 2The synthesized SSC waveform shows a frequency opposite to that of TXSSC. For example, in the first time period T1, the frequency of the clock signal CK1 changes from 5 GHz to (1 ppm - 10000 ppm) * 5 GHz, and the SSC demodulator 140 can generate a control signal with information indicating the opposite direction (e.g., the opposite direction of the frequency or phase change); in the second time period T2, the frequency of the clock signal CK1 changes from (1 ppm - 10000 ppm) * 5 GHz to 5 GHz, and the SSC demodulator 140 can generate a control signal with information indicating the opposite direction.

[0022] In one embodiment, the SSC demodulator 140 can analyze the SSC direction signal ssc_dir to generate frequency information of the clock signal CK1, and convert the frequency information to generate phase information of the clock signal CK1, wherein the phase information of the clock signal CK1 indicates that the phase of the clock signal CK1 will shift forward or backward. The SSC demodulator 140 can then use this phase information to generate a control signal, or the control code generator 150 can use the phase information to generate a control code.

[0023] Control code generator 150 receives the filtered signal from digital loop filter 130 and the control signal from SSC demodulator 140 to generate control codes for phase interpolator 160, adjusting the phase of clock signal CK1 to generate output clock signal CKout. In this embodiment, since the control code contains information about the opposite direction of the frequency / phase change of clock signal CK1, the SSC component of clock signal CK1 can be eliminated by phase interpolator 160, and the effect of clock signal CK1 on output clock signal CKout is close to that of a clock signal without spread spectrum. For example, in Figure 2 In the first time period T1 shown, the frequency of the clock signal CK1 is decreasing, so the SSC demodulator 140 can generate a control signal, and the control code component contributed by the control signal is used by the phase interpolator 160 to advance the phase of the clock signal CK1. Similarly, in Figure 2 During the second time period T2 shown, the frequency of the clock signal CK1 is increasing, so the SSC demodulator 140 can generate a control signal, and the control code component contributed by the control signal is used by the phase interpolator 160 to delay the phase of the clock signal CK1.

[0024] refer to Figure 3 By using the SSC demodulator 140 and the control code generator 150 to eliminate the SSC component of the clock signal CK1 to generate the output clock signal CKout, the SSC amplitude is halved, and the value "A" in the above formula is also reduced, resulting in a 50% reduction in the static phase error. Figure 3As shown, prior to using this application, the frequency difference between the input signal Din and the output clock signal CKout was 20000ppm. With the use of the SSC demodulator 140, the frequency difference between the input signal Din and the output clock signal CKout is 10000ppm or (-10000)ppm, and the CDR circuit 100 only needs to track the far-end SSC (i.e., the SSC of the input signal Din).

[0025] Figure 4 This is a schematic diagram of a CDR circuit 400 according to an embodiment of the present invention. Figure 4 As shown, the CDR circuit 400 is a PI-based CDR circuit, including a phase detector (BBPD 410 in this embodiment), a frequency converter 420, a digital loop filter 430, and two phase interpolators 440 and 450. In this embodiment, the CDR circuit 400 is used in a SerDes with an SSC for high-speed communication.

[0026] In the operation of CDR circuit 400, BBPD 410 receives the input signal (digital input signal) Din from the previous stage and compares the phase of the input signal Din with the phase of the output clock signal CKout to generate a detection result. The input signal Din has SSC modulation, and the detection result can indicate the phase information between the input signal Din and the output clock signal CKout (e.g., the phase of the input signal Din leads the phase of the output clock signal CKout, or the phase of the input signal Din lags the phase of the output clock signal CKout). Frequency converter 420 is optional and converts the frequency of the detection result to another frequency. Then, digital loop filter 430 filters the detection result to generate a filtered signal. Then, phase interpolator 440 uses the filtered signal to adjust the phase of clock signal CK1 to generate clock signal CK2, which is used by phase interpolator 450 to generate the output clock signal CKout. Furthermore, each of clock signal CK1, clock signal CK2, and output clock signal CKout can be a single-phase clock signal or a clock signal with multiple phases.

[0027] It should be noted that the operation of BBPD 410, frequency converter 420, digital loop filter 430 and phase interpolator 460 is known to those skilled in the art, and this embodiment focuses on phase interpolator 450, so the following description focuses on phase interpolator 450, and details of other components are omitted here.

[0028] In this embodiment, the PLL 402 of the transmitter uses the reference clock signal CKREF to generate the clock signal CK1, where the clock signal CK1 is SSC modulated. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK1. However, due to frequency drift and differential design methods, the frequency and SSC amplitude of the input signal Din are not the same as the frequency and SSC amplitude of the clock signal CK1, and there will be a residual static phase error between the input signal Din and the output clock signal CKout, where the static phase error can be referred to in Equation (1) above.

[0029] In this embodiment, since the clock signal CK1 has SSC modulation, the clock signal CK2 generated by the phase interpolator 440 (also referred to as the output clock signal before adjustment) also has SSC modulation. To eliminate the SSC contributed by CK1 in the clock signal CK2, the PLL 402 generates a control signal Vc to the phase interpolator 450 to adjust the phase of the clock signal CK2 to generate the output clock signal. The control signal Vc contains information about the opposite direction of the frequency / phase change of the clock signal CK1. For example, in... Figure 2 In the first time period T1 shown, the frequency of clock signal CK1 is decreasing, therefore PLL 402 can generate a control signal Vc to control phase interpolator 450 to advance the phase of clock signal CK2. Similarly, in Figure 2 In the second time period T2 shown, the frequency of the clock signal CK1 is increasing, so PLL 402 can generate a control signal Vc to control the phase interpolator 450 to delay the phase of the clock signal CK2.

[0030] In summary, by using interpolator 450 to eliminate the SSC component contributed by CK1 in the clock signal CK2 to generate the output clock signal CKout, the influence of CK1 on the clock signal CKout is close to that of a clock signal without spread spectrum. The SSC amplitude is halved, and the value "A" in equation (1) is also reduced, resulting in a 50% reduction in static phase error. Furthermore, by using interpolator 450, the CDR circuit 400 only needs to track the far-end SSC (i.e., the SSC of the input signal Din).

[0031] Figure 5 This is a schematic diagram of a CDR circuit 500 according to an embodiment of the present invention. Figure 5 As shown, the CDR circuit 500 is a PI-based CDR circuit, including a phase detector (BBPD 510 in this embodiment), a frequency converter 520, a digital loop filter 530, and a phase interpolator 540. In this embodiment, the CDR circuit 500 is used in a SerDes with an SSC for high-speed communication.

[0032] In the operation of CDR circuit 500, BBPD 510 receives the input signal (digital input signal) Din from the previous stage and compares the phase of the input signal Din with the phase of the output clock signal CKout to generate a detection result. The input signal Din has SSC modulation, and the detection result can indicate the phase information between the input signal Din and the output clock signal CKout (e.g., the phase of the input signal Din leads the phase of the output clock signal CKout, or the phase of the input signal Din lags the phase of the output clock signal CKout). Frequency converter 520 is optional and converts the frequency of the detection result to another frequency. Then, digital loop filter 530 filters the detection result to generate a filtered signal. Then, phase interpolator 540 uses the filtered signal to adjust the phase of clock signal CK2 to generate the output clock signal CKout. Furthermore, each of clock signals CK1, CK2, and the output clock signal CKout can be a single-phase clock signal or a clock signal with multiple phases.

[0033] It should be noted that the operation of BBPD 510, frequency converter 520, digital loop filter 530 and phase interpolator 540 is well known to those skilled in the art. This embodiment focuses on the generation of clock signal CK2, so the following description focuses on phase interpolator 504, and details of other components are omitted here.

[0034] In this embodiment, the PLL 502 of the transmitter uses the reference clock signal CKREF to generate the clock signal CK1, where the clock signal CK1 has SSC modulation. Ideally, the SSC amplitude of the input signal Din is the same as the SSC amplitude of the clock signal CK1. However, due to frequency drift and differential design methods, the frequency and SSC amplitude of the input signal Din are not the same as the frequency and SSC amplitude of the clock signal CK1, and there will be a residual static phase error between the input signal Din and the output clock signal CKout, where the static phase error can be referred to in Equation (1) above.

[0035] In this embodiment, to eliminate the SSC of clock signal CK1, PLL 502 generates a control signal Vc to phase interpolator 504 to adjust the phase of clock signal CK1 to generate clock signal CK2, wherein the control signal Vc includes information about the opposite direction of the frequency / phase change of clock signal CK1. For example, in Figure 2 In the first time period T1 shown, the frequency of the clock signal CK1 is decreasing, therefore PLL 502 can generate a control signal Vc to control the phase interpolator 504 to advance the phase of the clock signal CK1. Similarly, in Figure 2In the second time period T2 shown, the frequency of the clock signal CK1 is increasing, so PLL 502 can generate a control signal Vc to control the phase interpolator 504 to delay the phase of the clock signal CK1.

[0036] In summary, by using interpolator 504 to eliminate the SSC of clock signal CK1 to generate clock signal CK2, which is close to a clock signal without spread spectrum, the SSC amplitude is halved, and the value "A" in equation (1) above is also reduced, resulting in a 50% reduction in static phase error. Furthermore, by using interpolator 504, the SSC that CDR circuit 500 needs to track is only the far-end SSC (i.e., the SSC of input signal Din).

[0037] While the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments and can be practiced with modifications and variations within the spirit and scope of the appended claims. This description is therefore to be considered illustrative rather than restrictive.

[0038] Those skilled in the art will readily observe that modifications and alterations can be made to the apparatus and methods while retaining the teachings of the present invention. Therefore, the foregoing disclosure should be construed as being limited only by the scope and limits of the appended claims.

Claims

1. A circuit, characterized in that, include: A phase-locked loop is used to generate a first clock signal and an SSC direction signal with spread spectrum clock (SSC) modulation. as well as Clock and data recovery (CDR) circuitry, including: A phase detector is used to compare the phase of an input signal with the phase of an output clock signal to generate a detection result, wherein the input signal is SSC modulated; A digital loop filter, coupled to the phase detector, is used to filter the detection result to generate a filtered signal; An SSC demodulator is used to receive the SSC direction signal and generate a control signal based on the SSC direction signal. A control code generator, used to generate control codes based on the filtered signal and the control signal; and A phase interpolator is used to receive the first clock signal and adjust the phase of the first clock signal using the control code to generate the output clock signal. Wherein, in response to the SSC direction signal indicating that the frequency of the first clock signal is decreasing, the component of the control code contributed by the control signal is used by the phase interpolator to advance the phase of the first clock signal to generate the output clock signal, and / or, in response to the SSC direction signal indicating that the frequency of the first clock signal is increasing, the component of the control code contributed by the control signal is used by the phase interpolator to delay the phase of the first clock signal to generate the output clock signal.

2. The circuit according to claim 1, characterized in that, The SSC direction signal indicates the direction of frequency change of the first clock signal, and the control signal includes information about the opposite direction of frequency change of the first clock signal.

3. The circuit according to claim 2, characterized in that, The SSC direction signal being at a first voltage level indicates that the frequency of the first clock signal is increasing; and the SSC direction signal being at a second voltage level indicates that the frequency of the first clock signal is decreasing.

4. The circuit according to claim 1, characterized in that, The phase interpolator uses the control code to eliminate the SSC component of the first clock signal to generate the output clock signal.

5. The circuit according to claim 1, characterized in that, The SSC demodulator analyzes the SSC direction signal to obtain phase information of the first clock signal, wherein the phase information is used by the SSC demodulator to generate the control signal, or the phase information is used by the control code generator to generate the control code.

6. A circuit, characterized in that, include: A phase-locked loop is used to generate a first clock signal and control signals with spread spectrum clock (SSC) modulation. as well as Clock and data recovery (CDR) circuitry, including: A phase detector is used to generate a detection result based on an input signal and an output clock signal, wherein the input signal has SSC modulation; A digital loop filter, coupled to the phase detector, is used to filter the detection result to generate a filtered signal; A first phase interpolator is configured to generate an output clock signal based on the filtered signal and the first clock signal; and A second phase interpolator is used to eliminate the SSC component of the first clock signal or eliminate the SSC component contributed by the first clock signal in the output clock signal according to the control signal.

7. The circuit according to claim 6, characterized in that, The second phase interpolator is located between the phase detector and the first phase interpolator. The second phase interpolator is used to receive the output clock signal, adjust the phase of the output clock signal according to the control signal to generate an adjusted output clock signal, and the phase detector is used to compare the phase of the input signal and the phase of the adjusted output clock signal to generate the detection result.

8. The circuit according to claim 6, characterized in that, The second phase interpolator is located between the phase-locked loop and the first phase interpolator, and the second phase interpolator is used to receive the first clock signal, adjust the phase of the first clock signal according to the control signal to generate a second clock signal, and the first phase interpolator is used to adjust the phase of the second clock signal according to the filtered signal to generate the output clock signal.

9. The circuit according to claim 7 or 8, characterized in that, The control signal includes information about the opposite direction of the frequency change of the first clock signal.

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