Low-temperature drift receiver for high-speed CAN transceiver

Abstract

A low-temperature drift receiver for a high-speed CAN transceiver comprises a resistance voltage dividing module used for dividing voltages on an input port CANH port and an input port CANL port according to a resistance value proportion and transmitting the divided voltages CANH0 and CANL0 to a hysteresis comparator module; the hysteresis comparator module is used for receiving the voltage CANH0 and the voltage CANL0 after voltage division of the input port CANH port and the input port CANL port, and converting the voltage CANH0 and the voltage CANL0 after voltage division into single-ended analog signals; the shaping module is used for receiving the single-ended analog signal output by the hysteresis comparator module and converting the output single-ended analog signal into a digital signal with the same phase as the port; the output stage module is used for converting a signal of an output end in the shaping module into a signal opposite to a port signal, and improving the load capacity of the circuit by adopting a mode of increasing the width-to-length ratio of a device step by step in the output stage module; according to the invention, the technical effects of wide common-mode input, low temperature drift and low delay are realized, and the circuit has the advantages of strong adaptability, high stability and rapid response.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a low-temperature drift receiver for a high-speed CAN transceiver. Background Technology

[0002] Controller Area Network (CAN) bus technology was proposed by Bosch in the 1980s, with the core purpose of solving the wiring complexity problem caused by the increasing number of Electronic Control Units (ECUs) in automotive electronic systems. This technology achieves highly reliable, low-power multi-node communication through a differential signal transmission mechanism and has become a standard bus protocol in automotive, industrial control, and other fields. The CAN transceiver, as the physical layer interface of the bus system, undertakes the data conversion function between the protocol controller and the physical CAN bus, and its performance directly affects communication quality. However, with the accelerated development of automotive intelligence and connectivity, the number of ECUs in vehicles has increased significantly. The traditional CAN bus's 1 Mb / s communication rate and ±12V common-mode input range can no longer meet the real-time requirements of the 5Mb / s high-speed CAN FD protocol, nor can it cope with the challenges of ±30V common-mode voltage fluctuations and electromagnetic interference under complex operating conditions in a 24V power supply system. Therefore, there is an urgent need to develop a new transceiver architecture with a wide common-mode input range (±30V) and low transmission latency (<100ns) to support highly reliable data interaction.

[0003] In CAN transceivers, the receiver module converts the bus differential signals (CANH / CANL) into digital signals conforming to the ISO 11898 protocol using a hysteresis comparator. The threshold voltage is typically set to Vdiff ≥ 0.9V in the dominant state and Vdiff ≤ 0.5V in the recessive state. Traditional hysteresis comparators use a positive feedback network to generate the hysteresis window, but their common-mode input range is limited by the power supply voltage rail (typically ±12V). The threshold voltage is susceptible to power supply and temperature fluctuations, and the transmission delay is generally as high as 100~200 ns, with temperature drift typically between 1mV / ℃ and 5mV / ℃, making it difficult to meet the timing accuracy requirements of high-speed CAN FD. Furthermore, conventional designs lack protection against ±58V fault voltages, failing to meet the industrial-grade extended requirements of the ISO 11898-2:2016 standard.

[0004] The patent with publication number CN119070790A discloses a CAN bus receiver circuit with a wide common-mode range. It reduces the voltage of the CANH and CANL terminals through a voltage conversion circuit and connects the stepped-down signal to the input of a hysteresis comparator. However, due to the structural limitations of the hysteresis comparator, it cannot adapt to common-mode voltage scenarios exceeding ±12V, resulting in an insufficient common-mode range. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide a low-temperature drift receiver for high-speed CAN transceivers. By optimizing the resistor divider module and the hysteresis comparator module, a semi-floating input structure is introduced into the hysteresis comparator module, extending the common-mode input range to ±30V and the fault protection capability to ±58V. Furthermore, a device with temperature compensation characteristics is introduced into the comparator structure of the hysteresis comparator module, forming a complementary compensation mechanism with other structures, controlling the temperature drift of the threshold voltage within 0.14mV / ℃. At the same time, a compensation current is embedded in the shaping module to compress the transmission delay to within 60ns, thereby significantly improving the communication stability and real-time performance of the high-speed CAN bus in harsh environments.

[0006] A cryogenic drift receiver for a high-speed CAN transceiver includes: The resistor voltage divider module adopts a resistor series voltage divider structure. The input ports of the resistor voltage divider module are CANH port and CANL port. The output terminal of the resistor voltage divider module is connected to the hysteresis comparator module. It is used to divide the voltage on the input ports CANH port and CANL port according to the resistance value ratio, and transmit the divided voltages CANH_0 and CANL_0 to the hysteresis comparator module. The hysteresis comparator module adopts a two-stage differential operational amplifier structure with positive feedback. The input terminal of the hysteresis comparator module is connected to the output terminal of the resistor voltage divider module, and the output terminal of the hysteresis comparator module is connected to the shaping module. It is used to receive the voltages CANH_0 and CANL_0 after voltage division at the input ports CANH and CANL, convert the voltages CANH_0 and CANL_0 into single-ended analog signals, and output them to the shaping module. The shaping module uses a biased inverter as a comparison structure. The input of the shaping module is connected to the output of the hysteresis comparator module, and the output of the shaping module is connected to the input of the output stage module. It is used to receive the single-ended analog signal output by the hysteresis comparator module, convert the output single-ended analog signal into a digital signal in phase with the port, and output it to the output stage module. The output stage module adopts an inverter cascade structure. The input terminal of the output stage module is connected to the output terminal of the shaping module. The output terminal of the output stage module is the final output terminal of the low temperature drift receiver. It converts the signal at the output terminal of the shaping module into a signal that is inverted with the signal at this port. In the output stage module, the width-to-length ratio of the devices is increased step by step to improve the load capacity of the circuit.

[0007] The resistor voltage divider module includes: power supply VCC, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, and CANH port and CANL port. One end of the power supply VCC is connected to the first end of the fifth resistor R5 and the first end of the tenth resistor R10. The second end of the fifth resistor R5 is connected to the first end of the fourth resistor R4 and the first end of the second capacitor C2. The second end of the second capacitor C2 is grounded. The second end of the tenth resistor R10 is connected to the first end of the ninth resistor R9 and the first end of the fourth capacitor C4. The second end of the fourth capacitor C4 is grounded. The second end of the fourth resistor R4 is connected to the first end of the third resistor R3 and the CANH port. The second end of the ninth resistor R9 is connected to the first end of the eighth resistor R8 and the CANL port. The second end of the third resistor R3 is connected to the first end of the second resistor R2 and the first end of the first capacitor C1. The second end of the first capacitor C1 is grounded. The second end of the eighth resistor R8 is connected to the first end of the seventh resistor R7 and the first end of the third capacitor C3. The second end of the third capacitor C3 is grounded. The second end of the second resistor R2 is connected to the first end of the first resistor R1. The CANH_0 terminal is led out from the connection point of the second resistor R2 and the first resistor R1. The second end of the seventh resistor R7 is connected to the sixth resistor R6. The first end, the connection point of the seventh resistor R7 and the sixth resistor R6, leads to the CANL_0 terminal. The CANL_0 terminal and the CANL_0 terminal simultaneously output signals to the hysteresis comparator module. The second end of the first resistor R1 and the second end of the sixth resistor R6 are connected to each other and then grounded together.

[0008] The hysteresis comparator module includes: power supply VCC, first current source I1, second current source I2, third current source I3, fourth current source I4 and fifth current source I5, first BJT transistor Q1, second BJT transistor Q2, third BJT transistor Q3, fourth BJT transistor Q4, fifth BJT transistor Q5, sixth BJT transistor Q6, seventh BJT transistor Q7, eighth BJT transistor Q8, ninth BJT transistor Q9, tenth BJT transistor Q10, eleventh BJT transistor Q11 and twelfth BJT transistor Q12, thirteenth BJT transistor Q13, first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3, fourth PMOS transistor PM4, fifth PMOS transistor PM5, sixth PMOS transistor PM6, seventh PMOS transistor PM7, eighth PMOS transistor PM8 and ninth PMOS transistor PM9, and first NMOS transistor. NM1, NM2, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, nineteenth resistor R19, twentieth resistor R20, twenty-first resistor R21, twenty-second resistor R22 and twenty-third resistor R23, first switch S1, second switch S2; One end of the power supply VCC is connected to the first end of the first current source I1, the first end of the second current source I2, the first end of the third current source I3, the first end of the fourth current source I4, the first end of the fifth current source I5, the source ends of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, and the eighth PMOS transistor PM8, the collector of the first BJT transistor Q1, and the base and collector of the thirteenth BJT transistor Q13; the second end of the first current source I1 is connected to the base of the first BJT transistor Q1 and the collector of the third BJT transistor Q3, and the emitter of the first BJT transistor Q1 is connected to the base and collector of the second BJT transistor Q2 and the third BJT transistor Q3. The bases of the first PMOS transistor PM1, the fourth PMOS transistor Q4, the ninth PMOS transistor Q9, and the tenth PMOS transistor Q10 are connected; the emitters of the second PMOS transistor Q2, the third PMOS transistor Q3, the fourth PMOS transistor Q4, the ninth PMOS transistor Q9, and the tenth PMOS transistor Q10 are grounded via the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the twentieth resistor R20, and the twenty-first resistor R21, respectively; the gate and drain of the first PMOS transistor PM1 are shorted and connected to the gate of the second PMOS transistor PM2 and the third PMOS transistor PM3. The gate terminal of the first BJT transistor is connected to the collector of the fourth BJT transistor Q4. The drain terminal of the second PMOS transistor PM2 is connected to the base and collector of the fifth BJT transistor Q5 and the base of the sixth BJT transistor Q6. The emitter of the fifth BJT transistor Q5 is connected to the first terminal of the fourteenth resistor R14, the second terminal of the first switch S1, and the second terminal of the second current source I2. The first terminal of the first switch S1 is connected to the second terminal of the third current source I3. The second terminal of the fourteenth resistor R14 is connected to the second terminal of the fifteenth resistor R15. The connection between the fourteenth resistor R14 and the fifteenth resistor R15 leads to the CANL_0 terminal, which is used to receive the signal from the CANL_0 terminal of the resistor divider module. The drain of the third PMOS transistor PM3 is connected to the base and collector of the eighth BJT transistor Q8 and the base of the seventh BJT transistor Q7. The emitter of the eighth BJT transistor Q8 is connected to the first terminal of the seventeenth resistor R17. The second terminal of the seventeenth resistor R17 is connected to the second terminal of the fourth current source I4, the second terminal of the second switch S2, and the second terminal of the sixteenth resistor R16. The connection point between the seventeenth resistor R17 and the fourth current source I4, the second switch S2, and the sixteenth resistor R16 leads to the CANH_0 terminal, which is used to receive the signal from the CANH_0 terminal of the resistor divider module. The first terminal of the second switch S2 is connected to the second terminal of the fifth current source I5.The emitter of the thirteenth BJT transistor Q13 is connected to the first terminal of the eighteenth resistor R18 and the first terminal of the nineteenth resistor R19. The second terminal of the eighteenth resistor R18 is connected to the collector of the sixth BJT transistor Q6 and the base of the eleventh transistor Q11. The second terminal of the nineteenth resistor R19 is connected to the collector of the seventh BJT transistor Q7 and the base of the twelfth BJT transistor Q12. The emitter of the sixth BJT transistor Q6 is connected to the emitter of the seventh BJT transistor Q7, the first terminal of the fifteenth resistor R15, and the first terminal of the sixteenth resistor R16. The gate of the fourth PMOS transistor PM4 is connected to the gate of the sixth PMOS transistor PM6, the gate of the eighth PMOS transistor PM8, the drain of the fifth PMOS transistor PM5, and the collector of the ninth BJT transistor Q9. The drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5. The sixth PMOS transistor PM6... The drain of the 11th BJT transistor Q11 is connected to the collector of the 12th BJT transistor Q12 and the source of the 7th PMOS transistor Q7; the drain of the 8th PMOS transistor PM8 is connected to the collector of the 12th BJT transistor Q12 and the source of the 9th PMOS transistor Q9; the gate of the 5th PMOS transistor PM5 is connected to the gate of the 7th PMOS transistor PM7 and the gate of the 9th PMOS transistor PM9, and is connected to the bias voltage Vbias1; the drain of the 7th PMOS transistor PM7 is connected to the first terminal of the 22nd resistor R22. The second terminal of resistor 2 is connected to the gate and drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2. The source of the first NMOS transistor NM1 is grounded. The drain of the ninth PMOS transistor PM9 is connected to the first terminal of the twenty-third resistor R23. The Vo terminal is led out from the connection between the drain of the ninth PMOS transistor PM9 and the twenty-third resistor R23. The Vo terminal simultaneously outputs a signal to the shaping module. The second terminal of the twenty-third resistor R23 is connected to the drain of the second NMOS transistor NM2, and the source of the second NMOS transistor NM2 is grounded.

[0009] The shaping module includes: power supply VCC, third NMOS transistor NM3, fourth NMOS transistor NM4, tenth PMOS transistor PM10, fourteenth BJT transistor Q14, sixth current source I6, third switch S3, first inverter INV1, second inverter INV2, and third inverter INV3. The power supply VCC is connected to the drain of the third NMOS transistor NM3 and the source of the tenth PMOS transistor PM10. The gate of the third NMOS transistor NM3 is connected to the bias voltage Vbias2. A Vo terminal is led out from the connection point between the source of the third NMOS transistor NM3, the gate of the tenth PMOS transistor PM10, and the gate of the fourth NMOS transistor NM4, to receive the Vo signal from the hysteresis comparator module. The source of the third NMOS transistor NM3 is connected to the Vo terminal, the gate of the tenth PMOS transistor PM10, and the gate of the fourth NMOS transistor NM4. The drain of the tenth PMOS transistor PM10 is connected to the drain of the fourth NMOS transistor NM4 and the input of the first inverter INV1. The source of the fourth NMOS transistor NM4 is connected to the collector and base of the thirteenth BJT transistor Q13 and the first terminal of the third switch S3. The emitter of the thirteenth BJT transistor Q13 is grounded. The sixth current source I6... The first terminal is connected to the second terminal of the third switch S3, and the second terminal of the sixth current source I6 is grounded; the output terminal of the first inverter INV is connected to the input terminal of the second inverter INV2, the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, the output terminal of the third inverter INV3 is led out to the OUT terminal, and the OUT terminal simultaneously outputs a signal to the output stage module.

[0010] The output stage module includes the following inverters: INV4 (fourth inverter), INV5 (fifth inverter), INV6 (sixth inverter), INV7 (seventh inverter), INV8 (eighth inverter), INV9 (ninth inverter), INV10 (tenth inverter), INV11 (eleventh inverter), PM11 (eleventh PMOS transistor), PM12 (twelfth PMOS transistor), PM13 (thirteenth PMOS transistor), PM14 (fourteenth PMOS transistor), PM15 (fifth PMOS transistor), PM16 (sixteenth PMOS transistor), PM17 (seventh PMOS transistor), PM18 (eighth PMOS transistor), PM19 (nineteenth PMOS transistor), PM20 (twentieth PMOS transistor), NM5 (fifth NMOS transistor), NM6 (sixth NMOS transistor), NM7 (seventh NMOS transistor), and NM8 (eighth PMOS transistor). NMOS transistors NM8, NM9, NM10, NM11, NM12, NM13, and NM14; resistors R24, R25, R26, R27, R28, R29, R30, R31, R32, and R33; and power supply ports VIO and RXD; the input terminal of the fourth inverter INV4 leads to the OUT terminal, used to receive the OUT terminal signal from the shaping module; the output terminal of the fourth inverter INV4 is connected to the fifth inverter INV5. The input terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6, and the output terminal of the sixth inverter INV6 is connected to the input terminals of the seventh inverter INV7 and the eighth inverter INV8. The output terminal of the ninth inverter INV9 is connected to the input terminal of the tenth inverter INV10, and the output terminal of the tenth inverter INV10 is connected to the input terminal of the eleventh inverter IN11. The output terminal of the seventh inverter INV7 is connected to the eleventh PMOS transistor. The gate terminals of PMOS transistors PM11, PM12, PM13, PM14, and PM15 are connected; the output terminal of the eighth inverter INV8 is connected to the gate terminals of PMOS transistors PM16, PM17, PM18, PM19, and PM20; the output terminal of the eleventh inverter INV11 is connected to the gate terminals of NMOS transistors NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12, NM13, and NM14.The power supply VIO is connected to the sources of the eleventh PMOS transistor PM11, twelfth PMOS transistor PM12, thirteenth PMOS transistor PM13, fourteenth PMOS transistor PM14, fifteenth PMOS transistor PM15, sixteenth PMOS transistor PM16, seventeenth PMOS transistor PM17, eighteenth PMOS transistor PM18, nineteenth PMOS transistor PM19, and twentieth PMOS transistor PM20. The drain of the eleventh PMOS transistor PM11 is connected to the drain of the fifth NMOS transistor NM5 and the first terminal of the twenty-fourth resistor R24. The drain of the twelfth PMOS transistor PM12 is connected to the drain of the sixth NMOS transistor NM6 and the first terminal of the twenty-fifth resistor R25. The drain of the thirteenth PMOS transistor PM13 is connected to the drain of the seventh NMOS transistor NM7 and the first terminal of the twenty-sixth resistor R26. The drain of the fourteenth PMOS transistor PM14 is connected to the drain of the eighth NMOS transistor NM8 and the first terminal of the twenty-seventh resistor R27. The drain of the fifteenth PMOS transistor PM15 is connected to the drain of the ninth NMOS transistor NM9 and the first terminal of the twenty-eighth resistor R28. The drain of the sixteenth PMOS transistor PM16 is connected to the drain of the tenth NMOS transistor NM10 and the first terminal of the twenty-ninth resistor R29. The drain of the seventeenth PMOS transistor PM17 is connected to the drain of the eleventh NMOS transistor NM11 and the first terminal of the thirtieth resistor R30. The drain of the eighteenth PMOS transistor PM18 is connected to the drain of the twelfth NMOS transistor NM12 and the first terminal of the thirty-first resistor R31. The drain of the nineteenth PMOS transistor PM19 is connected to the thirteenth NMOS transistor NM13. The drain of the twentieth PMOS transistor PM20 is connected to the first terminal of the thirtieth NMOS transistor NM14, and the drain of the fourteenth NMOS transistor NM14 is connected to the first terminal of the thirty-third resistor R33. The sources of the fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM10, eleventh NMOS transistor NM11, twelfth NMOS transistor NM12, thirteenth NMOS transistor NM13, and fourteenth NMOS transistor NM14 are all connected to ground. The second terminals of the twenty-fourth resistor R24, twenty-fifth resistor R25, twenty-sixth resistor R26, twenty-seventh resistor R27, twenty-eighth resistor R28, twenty-ninth resistor R29, thirtieth resistor R30, thirty-first resistor R31, thirty-second resistor R32, and thirty-third resistor R33 are all connected to the RXD port.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention, through the ingenious combination of a resistor divider module, a hysteresis comparator module, a shaping module, and an output stage module, achieves a wide common-mode input range of ±30V, significantly superior to traditional ±12V designs. Specifically, the semi-floating structure of the fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, fifth BJT Q5, sixth BJT Q6, seventh BJT Q7, and eighth BJT Q8 in the hysteresis comparator module, compared to a directly grounded circuit structure, enables the hysteresis comparator module to handle a wider common-mode input range, adapting to more complex voltage scenarios.

[0012] 2. By optimizing the circuit design of the hysteresis comparator module and the shaping module, this invention significantly reduces the temperature sensitivity of the upper and lower threshold voltages of the hysteresis comparator and greatly improves the working stability of the circuit in a wide temperature range of -40℃ to 125℃. The hysteresis comparator module uses a two-stage operational amplifier structure consisting of the sixth BJT Q6, the seventh BJT Q7, the tenth to thirteenth BJTs Q10 to Q13, the eighteenth resistor R18, the nineteenth resistor R19, the twenty-second resistor R22, the twenty-third resistor R23, the first NMOS transistor NM1, the second NMOS transistor NM2, and the sixth to ninth PMOS transistors PM6 to PM9. This structure effectively improves the gain of the hysteresis comparator module, enabling it to respond quickly to the threshold of the differential signal. Furthermore, the voltage difference Vbe13 generated by connecting the base and emitter of the thirteenth BJT Q13 introduces a compensation voltage with a negative temperature coefficient. This makes the emitter voltage of the thirteenth BJT Q13 the difference between the power supply VCC and Vbe13. Compared to directly connecting to the power supply VCC, this effectively compensates for the non-ideal drift caused by temperature changes in other components, significantly increasing the tolerance margin for temperature effects and avoiding threshold misjudgment caused by ambient temperature fluctuations.

[0013] 3. This invention simplifies redundant circuit modules, optimizes signal transmission paths, and designs a dedicated compensation current branch in the shaping module, effectively shortening signal transmission delay and significantly improving overall signal processing efficiency. Specifically, the third NMOS transistor NM3, the third switch S3, and the sixth current source I6 in the shaping module constitute a targeted compensation circuit. When the signal drops to a specific voltage junction, the third switch S3 automatically turns on according to the OUT port voltage state, and the sixth current source I6 injects a stable compensation current into the junction, reducing parasitic capacitance charging time. When the signal rises to a specific voltage junction, the third NMOS transistor M3 turns on, injecting current into the twenty-third resistor R23 and the second NMOS transistor NM2 of the hysteresis comparator module to meet the real-time communication requirements of the high-speed CAN bus.

[0014] In summary, this invention achieves wide common-mode input, low temperature drift, and low latency through resistor voltage division and multi-module collaborative design, hysteresis comparator temperature drift optimization, and simplified circuit structure. It has the advantages of strong adaptability, high stability, and fast response. Attached Figure Description

[0015] Figure 1 This is an overall control block diagram of the present invention.

[0016] Figure 2 This is a circuit diagram of the resistor voltage divider module of the present invention.

[0017] Figure 3 This is a circuit diagram of the hysteresis comparator module of the present invention.

[0018] Figure 4 This is a circuit diagram of the shaping module of the present invention.

[0019] Figure 5 This is a circuit diagram of the output stage module of the present invention.

[0020] Figure 6 The output waveform of the receiver in this embodiment of the invention is shown at ±30V bus voltage and -40~150℃.

[0021] Figure 7 This is a diagram showing the receiver transmission delay test results in an embodiment of the present invention.

[0022] Where: R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; R5 is the fifth resistor; R6 is the sixth resistor; R7, the seventh resistor; R8, the eighth resistor; R9, the ninth resistor; R10, the tenth resistor; R11, the eleventh resistor; R12, the twelfth resistor; R13, the thirteenth resistor; R14, the fourteenth resistor; R15, the fifteenth resistor; R16, the sixteenth resistor; R17, the seventeenth resistor; R18, the eighteenth resistor; R19, the nineteenth resistor; R20, the twentieth resistor; R21, the twenty-first resistor; R22, the twenty-second resistor; R23, the twenty-third resistor; R24, the twenty-fourth resistor; R25, the twenty-fifth resistor; R26, the twenty-sixth resistor; R27, the twenty-seventh resistor; R28, the twenty-eighth resistor; R29, the twenty-ninth resistor; R30, the thirtieth resistor; R31, the thirty-first resistor; R32, the thirty-second resistor; R33, the thirty-third resistor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; C4, the fourth capacitor; I1 I1, I2, I3, I4, I5, I6, I7, I8, I9, I0, I1, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I1, I2, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I11, I2, I2, I2, I3, I4, I5, I6 ...2, I3, I4, I5, I6, I1, I2, I2, I2, I2, I3, I4, I5, I6, I1, I2, I2, I2, I2, I2, I3, I4, I5, I6, I1, I2, I2, I2, I2, I2, I2, I3, I4, I5, I6, I1, I2, I2, I2, I2, I2, I2, I2, I2, I2, I3, I4, I5, I6, I2, I2, I2, I2, I2, I2, I2, I2, I2, I2, 11. Eleventh BJT transistor; Q12. Twelfth BJT transistor; Q13. Thirteenth BJT transistor; Q14. Fourteenth BJT transistor; PM1. First PMOS transistor; PM2. Second PMOS transistor; PM3. Third PMOS transistor; PM4. Fourth PMOS transistor; PM5. Fifth PMOS transistor; PM6. Sixth PMOS transistor; PM7. Seventh PMOS transistor; PM8. Eighth PMOS transistor; PM9. Ninth PMOS transistor; PM10, the 10th PMOS transistor; PM11, the 11th PMOS transistor; PM12, the 12th PMOS transistor; PM13, the 13th PMOS transistor; PM14, the 14th PMOS transistor; PM15, the 15th PMOS transistor; PM16, the 16th PMOS transistor; PM17, the 17th PMOS transistor; PM18, the 18th PMOS transistor; PM19, the 19th PMOS transistor; PM20, the 20th PMOS transistor; NM1, the 1st NMOS transistor; NM2, the 2nd NMOS transistor; NM3, the 3rd NMOS transistor; NM4, the 4th NMOS transistor; NM5, the 5th NMOS transistor; NM6, the 6th NMOS transistor; NM7, the 7th NMOS transistor; NM8, the 8th NMOS transistor; NM9, the 9th NMOS transistor; NM10, the 10th NMOS transistor; NM11, the 11th NMOS transistor; NM12, the 12th NMOS transistor; NM13, the 13th NMOS transistor;NM14, the fourteenth NMOS transistor; S1, the first switch; S2, the second switch; S3, the third switch; INV1, the first inverter; INV2, the second inverter; INV3, the third inverter; INV4, the fourth inverter; INV5, the fifth inverter; INV6, the sixth inverter; INV7, the seventh inverter; INV8, the eighth inverter; INV9, the ninth inverter; INV10, the tenth inverter; INV11, the eleventh inverter. Detailed Implementation

[0023] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of the present invention.

[0024] This invention discloses a low-temperature drift receiver for a high-speed CAN (Controller Area Network) transceiver, belonging to the field of integrated circuit technology, specifically the field of CAN bus physical layer interface technology. Addressing the problems of narrow common-mode input range (±12V) and high transmission delay (>100ns) in traditional receivers, this invention uses a resistor divider module to proportionally attenuate the high-voltage bus signal, combined with the first-stage amplifier structure of a hysteresis comparator module to achieve a wide common-mode input range of ±30V (150% improvement over traditional methods), and supports fault protection extended to ±58V (compliant with ISO11898-2:2016 extended level requirements). Simultaneously, the second-stage amplifier structure of the hysteresis comparator module adopts a folded cascode differential amplifier architecture to optimize the signal path, and the shaping module accelerates edge transition through cascaded inverters, reducing the input-to-output transmission delay to within 60ns (40% improvement over traditional solutions), with a threshold voltage temperature drift of less than 0.14mV / ℃ and a hysteresis threshold temperature drift of less than 0.07mV / ℃. This design significantly enhances the real-time performance and anti-interference capabilities of high-speed CAN FD communication, making it suitable for scenarios with stringent requirements for reliability and timeliness, such as automotive electronics and industrial control.

[0025] like Figure 1 As shown, a low-temperature drift receiver for a high-speed CAN transceiver includes: The resistor voltage divider module adopts a resistor series voltage divider structure. The input ports of the resistor voltage divider module are CANH port and CANL port. The output terminal of the resistor voltage divider module is connected to the hysteresis comparator module. It is used to divide the voltage on the input ports CANH port and CANL port according to the resistance value ratio, and transmit the divided voltages CANH_0 and CANL_0 to the hysteresis comparator module. like Figure 2As shown, the resistor divider module includes: a power supply VCC, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a CANH port and a CANL port. One end of the power supply VCC is connected to the first end of the fifth resistor R5 and the first end of the tenth resistor R10. The second end of the fifth resistor R5 is connected to the first end of the fourth resistor R4 and the first end of the second capacitor C2. The second end of the second capacitor C2 is grounded. The second end of the tenth resistor R10 is connected to the first end of the ninth resistor R9 and the first end of the fourth capacitor C4. The second end of the fourth capacitor C4 is grounded. The second end of the fourth resistor R4 is connected to the first end of the third resistor R3 and the CANH port. The second end of the ninth resistor R9 is connected to the first end of the eighth resistor R8 and the CANL port. The second end of the third resistor R3 is connected to the first end of the second resistor R2 and the first capacitor C1. The first terminal of the first capacitor C1 is grounded. The second terminal of the eighth resistor R8 is connected to the first terminal of the seventh resistor R7 and the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is grounded. The second terminal of the second resistor R2 is connected to the first terminal of the first resistor R1. The connection between the second resistor R2 and the first resistor R1 leads to the CANH_0 terminal. The second terminal of the seventh resistor R7 is connected to the first terminal of the sixth resistor R6. The connection between the seventh resistor R7 and the sixth resistor R6 leads to the CANL_0 terminal. The CANH_0 terminal and the CANL_0 terminal simultaneously output signals to the hysteresis comparator module. The second terminals of the first resistor R1 and the sixth resistor R6 are connected to each other and then grounded together.

[0026] Resistor voltage divider module, such as Figure 2 As shown, the inputs are: CANH port and CANL port; The resistor voltage divider module divides the input signal using a resistor network. The fifth resistor R5 and the tenth resistor R10 have the same resistance value; the fourth resistor R4 and the ninth resistor R9 have the same resistance value; the third resistor R3 and the eighth resistor R8 have the same resistance value; the second resistor R2 and the seventh resistor R7 have the same resistance value; and the first resistor R1 and the sixth resistor R6 have the same resistance value. The resulting voltage after voltage division can be expressed as follows: Formula 1 Formula 2 Let the proportionality coefficient (K<1) The differential voltage relationship can then be expressed as follows: The first to fourth capacitors C1 to C4 are used to suppress high-frequency noise.

[0027] The hysteresis comparator module adopts a two-stage differential operational amplifier structure with positive feedback. The input terminal of the hysteresis comparator module is connected to the output terminal of the resistor voltage divider module, and the output terminal of the hysteresis comparator module is connected to the shaping module. It is used to receive the voltages CANH_0 and CANL_0 after voltage division at the input ports CANH and CANL, convert the voltages CANH_0 and CANL_0 into single-ended Vo terminal analog signals, and output them to the shaping module. like Figure 3As shown, the hysteresis comparator module includes: power supply VCC, first current source I1, second current source I2, third current source I3, fourth current source I4 and fifth current source I5, first BJT transistor Q1, second BJT transistor Q2, third BJT transistor Q3, fourth BJT transistor Q4, fifth BJT transistor Q5, sixth BJT transistor Q6, seventh BJT transistor Q7, eighth BJT transistor Q8, ninth BJT transistor Q9, tenth BJT transistor Q10, eleventh BJT transistor Q11 and twelfth BJT transistor Q12, thirteenth BJT transistor Q13, first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3, fourth PMOS transistor PM4, fifth PMOS transistor PM5, sixth PMOS transistor PM6, seventh PMOS transistor PM7, eighth PMOS transistor PM8 and ninth PMOS transistor PM9, and first NMOS transistor. The system includes NM1, NM2, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, sixteenth resistor R16, seventeenth resistor R17, eighteenth resistor R18, nineteenth resistor R19, twentieth resistor R20, twenty-first resistor R21, twenty-second resistor R22 and twenty-third resistor R23, first switch S1, and second switch S2. One end of the power supply VCC is connected to the first terminal of the first current source I1, the first terminal of the second current source I2, the first terminal of the third current source I3, the first terminal of the fourth current source I4, the first terminal of the fifth current source I5, the source terminals of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the sixth PMOS transistor PM6 and the eighth PMOS transistor PM8, the collector of the first BJT transistor Q1, and the base and collector of the thirteenth BJT transistor Q13. The second terminal is connected to the base of the first BJT transistor Q1 and the collector of the third BJT transistor Q3. The emitter of the first BJT transistor Q1 is connected to the base and collector of the second BJT transistor Q2, the base of the third BJT transistor Q3, the base of the fourth BJT transistor Q4, the base of the ninth BJT transistor Q9, and the base of the tenth BJT transistor Q10. The emitters of the second BJT transistor Q2, the third BJT transistor Q3, the fourth BJT transistor Q4, the ninth BJT transistor Q9, and the tenth BJT transistor Q10 are grounded through the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the twentieth resistor R20, and the twenty-first resistor R21, respectively. The gate and drain of the first PMOS transistor PM1 are shorted and connected to the gate of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, and the collector of the fourth BJT transistor Q4.The drain of the second PMOS transistor PM2 is connected to the base and collector of the fifth BJT transistor Q5 and the base of the sixth BJT transistor Q6. The emitter of the fifth BJT transistor Q5 is connected to the first terminal of the fourteenth resistor R14, the second terminal of the first switch S1, and the second terminal of the second current source I2. The first terminal of the first switch S1 is connected to the second terminal of the third current source I3. The second terminal of the fourteenth resistor R14 is connected to the second terminal of the fifteenth resistor R15. The connection between the fourteenth resistor R14 and the fifteenth resistor R15 leads to the CANL_0 terminal, which is used to receive the signal from the CANL_0 terminal of the resistor divider module. The drain of the third PMOS transistor PM3 is connected to the base and collector of the eighth BJT transistor Q8 and the base of the seventh BJT transistor Q7. The emitter of the eighth BJT transistor Q8 is connected to the first terminal of the seventeenth resistor R17. The second terminal of the seventeenth resistor R17 is connected to the second terminal of the fourth current source I4 and the second switch S14. The second terminal of S2 and the second terminal of the sixteenth resistor R16; the connection point of the seventeenth resistor R17 with the fourth current source I4, the second switch S2, and the sixteenth resistor R16 leads to the CANH_0 terminal, used to receive the signal from the CANH_0 terminal of the resistor divider module; the first terminal of the second switch S2 is connected to the second terminal of the fifth current source I5; the emitter of the thirteenth BJT transistor Q13 is connected to the first terminal of the eighteenth resistor R18 and the first terminal of the nineteenth resistor R19; the second terminal of the eighteenth resistor R18 is connected to the collector of the sixth BJT transistor Q6 and the base of the eleventh transistor Q11; the second terminal of the nineteenth resistor R19 is connected to the collector of the seventh BJT transistor Q7 and the base of the twelfth BJT transistor Q12; the emitter of the sixth BJT transistor Q6 is connected to the emitter of the seventh BJT transistor Q7, the first terminal of the fifteenth resistor R15, and the first terminal of the sixteenth resistor R16; the fourth PMOS transistor PM4 The gate of the fourth PMOS transistor PM4 is connected to the gate of the sixth PMOS transistor PM6, the gate of the eighth PMOS transistor PM8, the drain of the fifth PMOS transistor PM5, and the collector of the ninth BJT transistor Q9. The drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5. The drain of the sixth PMOS transistor PM6 is connected to the collector of the eleventh BJT transistor Q11 and the source of the seventh PMOS transistor Q7. The drain of the eighth PMOS transistor PM8 is connected to the collector of the twelfth BJT transistor Q12 and the source of the ninth PMOS transistor Q9. The gate of the fifth PMOS transistor PM5 is connected to the gate of the seventh PMOS transistor PM7 and the gate of the ninth PMOS transistor PM9, and is connected to the bias voltage Vbias1.The drain of the seventh PMOS transistor PM7 is connected to the first terminal of the twenty-second resistor R22. The second terminal of the twenty-second resistor R22 is connected to the gate and drain of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2. The source of the first NMOS transistor NM1 is grounded. The drain of the ninth PMOS transistor PM9 is connected to the first terminal of the twenty-third resistor R23. The connection between the drain of the ninth PMOS transistor PM9 and the twenty-third resistor R23 leads to the Vo terminal, which simultaneously outputs a signal to the shaping module. The second terminal of the twenty-third resistor R23 is connected to the drain of the second NMOS transistor NM2, and the source of the second NMOS transistor NM2 is grounded.

[0028] Hysteresis comparator module, such as Figure 3 As shown, the first current source I1 is the PTAT current source generated inside the chip. For ease of subsequent description, the common junction voltage of the base and collector of the second BJT Q2 with the emitter of the first BJT Q1, the base of the third BJT Q3, the base of the fourth BJT Q4, the base of the ninth BJT Q9, and the base of the tenth BJT Q10 is defined as Vref. The first BJT to the fourth BJT Q1 to Q4, the ninth BJT Q9, the tenth BJT Q10, and the eleventh to thirteenth resistors R11 to R13, the twentieth resistor R20, and the twenty-first resistor R21 constitute a current mirror structure. The reference voltage generation relationship is as follows: Formula 3 By adjusting the size and resistance ratio of the BJT transistors, a low temperature coefficient voltage Vref1 can be obtained. This voltage is then mirrored to other circuits via the third BJT transistor Q3, the fourth BJT transistor Q4, the ninth BJT transistor Q9, and the tenth BJT transistor Q10. Finally, it is mirrored to other circuits via the first PMOS transistor to the third PMOS transistor PM1 to PM3 and the fourth PMOS transistor to the ninth PMOS transistor PM4 to PM9.

[0029] The first stage amplifier consists of the first PMOS transistors (PM1-PM3), the fourth BJT transistors (Q4-Q9), the ninth BJT transistors (Q4-Q9), the thirteenth resistors (R13-R19), the second current source (I2-I5), the first switch (S1), and the second switch (S2). The second stage amplifier consists of the first NMOS transistor (NM1), the second NMOS transistor (NM2), the fourth PMOS transistors (PM4-PM9), the ninth BJT transistors (Q9-Q12), and the twentieth resistors (R20-R24).

[0030] In the first-stage amplifier, the second current source I2 and the fourth current source I4 are low-temperature coefficient current sources (which can be generated by a reference bandgap image). The third current source I3, the first switch S1, the fifth current source I5, and the second switch S2 constitute a current source controlled by the Vo terminal to generate hysteresis. When the Vo terminal is low, the first switch S1 and the second switch S2 are closed, and when the Vo terminal is high, the first switch S1 and the second switch S2 are open.

[0031] For ease of subsequent description, the common junction voltage between the base of the sixth BJT transistor and the drain of the second PMOS transistor PM2, and the collector and base of the fifth BJT transistor Q5 is defined as Va; the common junction voltage between the base of the seventh BJT transistor and the drain of the third PMOS transistor PM3, and the collector and base of the eighth BJT transistor Q8 is defined as Vb; the current flowing through the second PMOS transistor PM2 is defined as I7; and the current flowing through the third PMOS transistor PM3 is defined as I8.

[0032] The voltages Va and Vb can be approximated using formulas 4 and 5: Formula 4 Formula 5 Among them, the resistance value of the fourteenth resistor R14 is the same as that of the seventeenth resistor R17. The second PMOS transistor PM2 and the third PMOS transistor PM3 are devices of the same size, so the current values ​​of I7 and I8 are the same. Since the fifth BJT transistor Q5 and the eighth BJT transistor Q8 are symmetrical and have the same current, the voltage difference Vbe5 between the base and emitter of the fifth BJT transistor Q5 and the eighth BJT transistor Q8 is the same as Vbe8. When the Vo terminal is low, the state of the first switch S1 can be regarded as 1, and when the Vo terminal is high, the state of the first switch S1 can be regarded as 0. From formulas 4 and 5, we can obtain: Formula 6 From formula 6, we can see that (1) when Vdiff is 0V, at this time When the value is less than 0, the Vo terminal outputs a low level, and the state of the first switch S1 can be considered as 1. If Vdiff gradually increases, at that time (2) When Vdiff is 2V, the level flips and the Vo terminal is high; When Vo outputs a high level (>0), the state of the first switch S1 can be considered as 0. If Vdiff gradually decreases, when When Vdiff is low, the voltage level flips, and the Vo terminal is low. According to the ISO 11898 protocol, the RXD port should be dominant (low level) when Vdiff ≥ 0.9V and recessive (high level) when Vdiff ≤ 0.5V. This can be achieved by properly setting the current source and resistor parameters.

[0033] Formula 7 Formula 8 Due to V CANH_0 End, V CANL_0 The current source is independent of temperature. The first current source I1 and the third current source I3 are current sources with extremely low temperature coefficients, so V can be ignored when the temperature changes. CANH_0 End, V CANL_0 The influence of the terminal, the first current source I1, and the third current source I3 on ​​the temperature coefficient. Currents I7 and I8 are currents with the same positive temperature coefficient. As can be seen from formulas 7 and 8, by adjusting the ratio of currents I7 and I8 to the first current source I1, Va and Vb with lower temperature coefficients can be obtained, thereby obtaining the threshold voltage for low temperature drift.

[0034] For ease of subsequent description, the common node of the emitter of the sixth BJT Q6, the emitter of the seventh BJT Q7, the fifteenth resistor R15, and the sixteenth resistor R16 is defined as Vx. The common node voltage of the collector of the sixth BJT Q6, the eighteenth resistor R18, and the base of the eleventh BJT Q11 is defined as Va_o. The common node voltage of the collector of the seventh BJT Q7, the nineteenth resistor R19, and the base of the twelfth BJT Q12 is defined as Vb_o. The voltage of Vx can be approximately expressed as... Va_o and Vb_o can be expressed by the following formula: Formula 9 Formula 10 Because the temperature coefficient of Vbe is negative, Since the temperature coefficient is positive, it can be seen from Formulas 9 and 10 that by appropriately adjusting the ratio of the BJT tube and the resistor, an output with a lower temperature coefficient can be obtained.

[0035] In the second-stage amplifier, the output signal of the first-stage amplifier is boosted to a level threshold recognizable by the shaping module by a folded amplifier. The amplification factor of the second-stage amplifier can be approximately expressed by the following formula: Formula 11 The shaping module uses a biased inverter as a comparison structure. The input of the shaping module is connected to the output of the hysteresis comparator module, and the output of the shaping module is connected to the input of the output stage module. It is used to receive the single-ended analog signal at the Vo end output by the hysteresis comparator module, convert the output single-ended analog signal at the Vo end into a digital signal in phase with the Vo end, and output it to the output stage module through the OUT end. like Figure 4 As shown, the shaping module includes: a power supply VCC, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a tenth PMOS transistor PM10, a fourteenth BJT transistor Q14, a sixth current source I6, a third switch S3, a first inverter INV1, a second inverter INV2, and a third inverter INV3; the power supply VCC is connected to the drain of the third NMOS transistor NM3 and the source of the tenth PMOS transistor PM10, respectively; the gate of the third NMOS transistor NM3 is connected to the bias voltage Vbias2; a Vo terminal is led out from the connection between the source of the third NMOS transistor NM3 and the gate of the tenth PMOS transistor PM10 and the gate of the fourth NMOS transistor NM4, for receiving the Vo terminal signal from the hysteresis comparator module; the source of the third NMOS transistor NM3 is connected to the Vo terminal, the gate of the tenth PMOS transistor PM10, and the gate of the fourth NMOS transistor NM4; the drain of the tenth PMOS transistor PM10 is connected to the fourth NMOS transistor NM4. The drain terminal of the first inverter INV1 is connected to the input terminal of the first inverter INV1; the source terminal of the fourth NMOS transistor NM4 is connected to the collector and base of the fourteenth BJT transistor Q14 and the first terminal of the third switch S3, and the emitter of the fourteenth BJT transistor Q14 is grounded; the first terminal of the sixth current source I6 is connected to the second terminal of the third switch S3, and the second terminal of the sixth current source I6 is grounded; the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is led out to the OUT terminal, which simultaneously outputs a signal to the output stage module.

[0036] Shaping module such as Figure 4 As shown, Vbias1 is the bias voltage generated inside the chip; the third switch S3 is a switch controlled by the OUT terminal. When the OUT terminal is high, the third switch S3 is closed, and when the OUT terminal is low, the third switch S3 is open.

[0037] when When the output at the OUT terminal is low, the third NMOS transistor NM3 turns on, injecting current into the second NMOS transistor NM2 in the amplifier module, suppressing the drop at the Vo terminal; when When the output of the OUT terminal is high, the third switch S3 is closed, and the sixth current source I6, through the fourth NMOS transistor NM4, acts as a pull-down to suppress the rise of the Vo terminal.

[0038] The output stage module adopts a cascaded inverter structure. The input terminal of the output stage module is connected to the output terminal OUT of the shaping module. The output terminal of the output stage module is the final output terminal RXD port of the low temperature drift receiver. The signal at the output terminal OUT of the shaping module is converted into the RXD port signal that is inverted with the signal at the OUT terminal. In the output stage module, the aspect ratio of the components is increased step by step to improve the load capacity of the circuit.

[0039] like Figure 5As shown, the output stage module includes the following transistors: fourth inverter INV4, fifth inverter INV5, sixth inverter INV6, seventh inverter INV7, eighth inverter INV8, ninth inverter INV9, tenth inverter INV10, eleventh inverter INV11, eleventh PMOS transistor PM11, twelfth PMOS transistor PM12, thirteenth PMOS transistor PM13, fourteenth PMOS transistor PM14, fifteenth PMOS transistor PM15, sixteenth PMOS transistor PM16, seventeenth PMOS transistor PM17, eighteenth PMOS transistor PM18, nineteenth PMOS transistor PM19, twentieth PMOS transistor PM20, fifth NMOS transistor NM5, sixth NMOS transistor NM6, and seventh NMOS transistor NM7. The circuit consists of NMOS transistors NM8 (eighth), NM9 (ninth), NM10 (tenth), NM11 (eleventh), NM12 (twelfth), NM13 (thirteenth), and NM14 (fourteenth); resistors R24 (twenty-fourth), R25 (twenty-fifth), R26 (twenty-sixth), R27 (twenty-seventh), R28 (twenty-eighth), R29 (twenty-ninth), R30 (thirtieth), R31 (thirtieth), R32 (thirtieth), and R33 (thirtieth); and power supply ports VIO and RXD. The input terminal of inverter INV4 leads to an OUT terminal to receive the OUT signal from the shaping module. The output terminal of inverter INV4 is connected to inverter INV5. The input terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6, and the output terminal of the sixth inverter INV6 is connected to the input terminals of the seventh inverter INV7 and the eighth inverter INV8. The output terminal of the ninth inverter INV9 is connected to the input terminal of the tenth inverter INV10, and the output terminal of the tenth inverter INV10 is connected to the input terminal of the eleventh inverter IN11. The output terminal of the seventh inverter INV7 is connected to the eleventh PMOS transistor. The gate terminals of PMOS transistors PM11, PM12, PM13, PM14, and PM15 are connected; the output terminal of the eighth inverter INV8 is connected to the gate terminals of PMOS transistors PM16, PM17, PM18, PM19, and PM20; the output terminal of the eleventh inverter INV11 is connected to the gate terminals of NMOS transistors NM5, NM6, NM7, NM8, NM9, NM10, NM11, NM12, NM13, and NM14.The power supply VIO is connected to the sources of the eleventh PMOS transistor PM11, twelfth PMOS transistor PM12, thirteenth PMOS transistor PM13, fourteenth PMOS transistor PM14, fifteenth PMOS transistor PM15, sixteenth PMOS transistor PM16, seventeenth PMOS transistor PM17, eighteenth PMOS transistor PM18, nineteenth PMOS transistor PM19, and twentieth PMOS transistor PM20. The drain of the eleventh PMOS transistor PM11 is connected to the drain of the fifth NMOS transistor NM5 and the first terminal of the twenty-fourth resistor R24. The drain of the twelfth PMOS transistor PM12 is connected to the drain of the sixth NMOS transistor NM6 and the first terminal of the twenty-fifth resistor R25. The drain of the thirteenth PMOS transistor PM13 is connected to the drain of the seventh NMOS transistor NM7 and the first terminal of the twenty-sixth resistor R26. The drain of the fourteenth PMOS transistor PM14 is connected to the drain of the eighth NMOS transistor NM8 and the first terminal of the twenty-seventh resistor R27. The drain of the fifteenth PMOS transistor PM15 is connected to the drain of the ninth NMOS transistor NM9 and the first terminal of the twenty-eighth resistor R28. The drain of the sixteenth PMOS transistor PM16 is connected to the drain of the tenth NMOS transistor NM10 and the first terminal of the twenty-ninth resistor R29. The drain of the seventeenth PMOS transistor PM17 is connected to the drain of the eleventh NMOS transistor NM11 and the first terminal of the thirtieth resistor R30. The drain of the eighteenth PMOS transistor PM18 is connected to the drain of the twelfth NMOS transistor NM12 and the first terminal of the thirty-first resistor R31. The drain of the nineteenth PMOS transistor PM19 is connected to the thirteenth NMOS transistor NM13. The drain of the twentieth PMOS transistor PM20 is connected to the first terminal of the thirtieth NMOS transistor NM14, and the drain of the fourteenth NMOS transistor NM14 is connected to the first terminal of the thirty-third resistor R33. The sources of the fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM10, eleventh NMOS transistor NM11, twelfth NMOS transistor NM12, thirteenth NMOS transistor NM13, and fourteenth NMOS transistor NM14 are all connected to ground. The second terminals of the twenty-fourth resistor R24, twenty-fifth resistor R25, twenty-sixth resistor R26, twenty-seventh resistor R27, twenty-eighth resistor R28, twenty-ninth resistor R29, thirtieth resistor R30, thirty-first resistor R31, thirty-second resistor R32, and thirty-third resistor R33 are all connected to the RXD port.

[0040] Output stage module circuit such as Figure 5 As shown, this is a multi-stage inverter cascade. By progressively increasing the size of the devices at each stage, the driving capability of the output terminal is improved and the signal transmission delay is reduced.

[0041] like Figure 6As shown, the horizontal axis represents VDF (voltage difference between the CANH and CANL ports), and the vertical axis represents the voltage at the RXD port. Simulation results show that, under different temperatures (-40℃~150℃) and different CAN bus common-mode voltages (±30V), when VDF changes, the voltage switching range from high to low is 607.98mV and 635.53mV, and the voltage transition characteristics are consistent across different temperatures. This indicates that the circuit of this invention has stable level switching performance under wide temperature environments (-40℃~150℃) and wide common-mode levels (±30V).

[0042] like Figure 7 As shown, the horizontal axis represents time (in µs) and the vertical axis represents voltage (in V), reflecting the transient response characteristics of the circuit signal as it changes over time. Simulation results show that in the circuit of this invention, when the CANH port changes from 2.5V to 3.5V and the CANL port changes from 2.5V to 1.5V, referring to the definition of the CAN bus standard level in ISO 11898, the RXD port receives the signal change after 59.22 ns, meaning the transmission delay of the circuit of this invention is less than 60 ns. Therefore, the receiver of this invention has the ability to quickly convert signals from the CANH port and the CANL port into single-ended signals.

Claims

1. A low-temperature drift receiver for a high-speed CAN transceiver, characterized in that, include: The resistor voltage divider module adopts a resistor series voltage divider structure. The input ports of the resistor voltage divider module are CANH port and CANL port. The output terminal of the resistor voltage divider module is connected to the hysteresis comparator module. It is used to divide the voltage on the input ports CANH port and CANL port according to the resistance value ratio, and transmit the divided voltages CANH_0 and CANL_0 to the hysteresis comparator module. The hysteresis comparator module adopts a two-stage differential operational amplifier structure with positive feedback. The input terminal of the hysteresis comparator module is connected to the output terminal of the resistor voltage divider module, and the output terminal of the hysteresis comparator module is connected to the shaping module. It is used to receive the voltages CANH_0 and CANL_0 after voltage division at the input ports CANH and CANL, convert the voltages CANH_0 and CANL_0 into single-ended analog signals, and output them to the shaping module. The shaping module uses a biased inverter as a comparison structure. The input of the shaping module is connected to the output of the hysteresis comparator module, and the output of the shaping module is connected to the input of the output stage module. It is used to receive the single-ended analog signal output by the hysteresis comparator module, convert the output single-ended analog signal into a digital signal in phase with the port, and output it to the output stage module. The output stage module adopts an inverter cascade structure. The input terminal of the output stage module is connected to the output terminal of the shaping module. The output terminal of the output stage module is the final output terminal of the low temperature drift receiver. It converts the signal at the output terminal of the shaping module into a signal that is inverted with the signal at this port. In the output stage module, the width-to-length ratio of the devices is increased step by step to improve the load capacity of the circuit.

2. A low-temperature drift receiver for a high-speed CAN transceiver according to claim 1, characterized in that, The resistor voltage divider module includes: power supply VCC, first resistor (R1), second resistor (R2), third resistor (R3), fourth resistor (R4), fifth resistor (R5), sixth resistor (R6), seventh resistor (R7), eighth resistor (R8), ninth resistor (R9), tenth resistor (R10), first capacitor (C1), second capacitor (C2), third capacitor (C3), fourth capacitor (C4), and CANH port and CANL port; One end of the power supply VCC is connected to the first end of the fifth resistor (R5) and the first end of the tenth resistor (R10). The second end of the fifth resistor (R5) is connected to the first end of the fourth resistor (R4) and the first end of the second capacitor (C2). The second end of the second capacitor (C2) is grounded. The second end of the tenth resistor (R10) is connected to the first end of the ninth resistor (R9) and the first end of the fourth capacitor (C4). The second end of the fourth capacitor (C4) is grounded. The second end of the fourth resistor (R4) is connected to the first end of the third resistor (R3) and the CANH port. The second end of the ninth resistor (R9) is connected to the first end of the eighth resistor (R8) and the CANL port. The second end of the third resistor (R3) is connected to the first end of the second resistor (R2) and the first end of the first capacitor (C1). The second end of the first capacitor (C1) is grounded. The second end of the eighth resistor (R8) is connected to the first end of the seventh resistor (R7) and the first end of the third capacitor (C3). The second end of the third capacitor (C3) is grounded. The second resistor (R2)... The second end of the first resistor (R1) is connected to the first end of the first resistor (R1). The connection between the second resistor (R2) and the first resistor (R1) leads to the CANH_0 terminal. The second end of the seventh resistor (R7) is connected to the first end of the sixth resistor (R6). The connection between the seventh resistor (R7) and the sixth resistor (R6) leads to the CANL_0 terminal. The CANH_0 terminal and the CANL_0 terminal simultaneously output signals to the hysteresis comparator module. The second end of the first resistor (R1) and the second end of the sixth resistor (R6) are connected to each other and then grounded together.

3. A low-temperature drift receiver for a high-speed CAN transceiver according to claim 1, characterized in that, The hysteresis comparator module includes: power supply VCC, a first current source (I1), a second current source (I2), a third current source (I3), a fourth current source (I4), and a fifth current source (I5), a first BJT transistor (Q1), a second BJT transistor (Q2), a third BJT transistor (Q3), a fourth BJT transistor (Q4), a fifth BJT transistor (Q5), a sixth BJT transistor (Q6), a seventh BJT transistor (Q7), an eighth BJT transistor (Q8), a ninth BJT transistor (Q9), and a tenth BJT transistor (Q1). JT transistor (Q10), eleventh BJT transistor (Q11), twelfth BJT transistor (Q12), thirteenth BJT transistor (Q13), first PMOS transistor (PM1), second PMOS transistor (PM2), third PMOS transistor (PM3), fourth PMOS transistor (PM4), fifth PMOS transistor (PM5), sixth PMOS transistor (PM6), seventh PMOS transistor (PM7), eighth PMOS transistor (PM8) and ninth PMOS transistor (PM9), first NMOS transistor Transistor (NM1), second NMOS transistor (NM2), eleventh resistor (R11), twelfth resistor (R12), thirteenth resistor (R13), fourteenth resistor (R14), fifteenth resistor (R15), sixteenth resistor (R16), seventeenth resistor (R17), eighteenth resistor (R18), nineteenth resistor (R19), twentieth resistor (R20), twenty-first resistor (R21), twenty-second resistor (R22) and twenty-third resistor (R23), first switch (S1), second switch (S2); One end of the power supply VCC is connected to the first terminal of the first current source (I1), the first terminal of the second current source (I2), the first terminal of the third current source (I3), the first terminal of the fourth current source (I4), the first terminal of the fifth current source (I5), the source terminals of the first PMOS transistor (PM1), the second PMOS transistor (PM2), the third PMOS transistor (PM3), the fourth PMOS transistor (PM4), the sixth PMOS transistor (PM6), and the eighth PMOS transistor (PM8), the collector of the first BJT transistor (Q1), and the base and collector of the thirteenth BJT transistor (Q13). The second end of the first current source (I1) is connected to the base of the first BJT transistor (Q1) and the collector of the third BJT transistor (Q3). The emitter of the first BJT transistor (Q1) is connected to the base and collector of the second BJT transistor (Q2) and the third BJT transistor (Q3). The bases of the first, second, third, fourth, ninth, and tenth BJT transistors (Q10), the base of the fourth BJT transistor (Q4), the base of the ninth BJT transistor (Q9), and the base of the tenth BJT transistor (Q10); the emitters of the second, third, fourth, ninth, and tenth BJT transistors (Q2, Q3, Q4, Q9, and Q10) are grounded via the eleventh resistor (R11), the twelfth resistor (R12), the thirteenth resistor (R13), the twentieth resistor (R20), and the twenty-first resistor (R21), respectively; the gate and drain of the first PMOS transistor (PM1) are shorted and connected to the gate of the second PMOS transistor (PM2) and the third PMOS transistor (PM3). The gate terminal of the first BJT transistor (Q4) and the collector terminal of the fourth BJT transistor (Q4); the drain terminal of the second PMOS transistor (PM2) is connected to the base and collector of the fifth BJT transistor (Q5) and the base of the sixth BJT transistor (Q6); the emitter of the fifth BJT transistor (Q5) is connected to the first terminal of the fourteenth resistor (R14), the second terminal of the first switch (S1), and the second terminal of the second current source (I2); the first terminal of the first switch (S1) is connected to the second terminal of the third current source (I3); the second terminal of the fourteenth resistor (R14) is connected to the second terminal of the fifteenth resistor (R15); the connection point between the fourteenth resistor (R14) and the fifteenth resistor (R15) leads to the CANL_0 terminal, which is used to receive the signal from the CANL_0 terminal of the resistor divider module. The drain of the third PMOS transistor (PM3) is connected to the base and collector of the eighth BJT transistor (Q8) and the base of the seventh BJT transistor (Q7). The emitter of the eighth BJT transistor (Q8) is connected to the first terminal of the seventeenth resistor (R17). The second terminal of the seventeenth resistor (R17) is connected to the second terminal of the fourth current source (I4), the second terminal of the second switch (S2), and the second terminal of the sixteenth resistor (R16). A CANH_0 terminal is led out from the connection point of the seventeenth resistor (R17) with the fourth current source (I4), the second switch (S2), and the sixteenth resistor (R16) to receive the signal from the CANH_0 terminal of the resistor divider module. The first terminal of the second switch (S2) is connected to the second terminal of the fifth current source (I5).The emitter of the thirteenth BJT (Q13) is connected to the first terminal of the eighteenth resistor (R18) and the first terminal of the nineteenth resistor (R19). The second terminal of the eighteenth resistor (R18) is connected to the collector of the sixth BJT (Q6) and the base of the eleventh transistor (Q11). The second terminal of the nineteenth resistor (R19) is connected to the collector of the seventh BJT (Q7) and the base of the twelfth BJT (Q12). The emitter of the sixth BJT (Q6) is connected to the emitter of the seventh BJT (Q7), the first terminal of the fifteenth resistor (R15), and the first terminal of the sixteenth resistor (R16). The gate of the fourth PMOS transistor (PM4) is connected to the gate of the sixth PMOS transistor (PM6), the gate of the eighth PMOS transistor (PM8), the drain of the fifth PMOS transistor (PM5), and the collector of the ninth BJT (Q9). The drain of the fourth PMOS transistor (PM4) is connected to the fifth PMOS transistor (PM5). The source terminal of the sixth PMOS transistor (PM6) is connected to the collector of the eleventh BJT transistor (Q11) and the source terminal of the seventh PMOS transistor (Q7); the drain terminal of the eighth PMOS transistor (PM8) is connected to the collector of the twelfth BJT transistor (Q12) and the source terminal of the ninth PMOS transistor (Q9); the gate terminal of the fifth PMOS transistor (PM5) is connected to the gate terminal of the seventh PMOS transistor (PM7) and the gate terminal of the ninth PMOS transistor (PM9), and is connected to the bias voltage Vbias1; the drain terminal of the seventh PMOS transistor (PM7) is connected to the first terminal of the twenty-second resistor (R22). The second terminal of the twenty-second resistor (R22) is connected to the gate and drain of the first NMOS transistor (NM1) and the gate of the second NMOS transistor (NM2). The source of the first NMOS transistor (NM1) is grounded. The drain of the ninth PMOS transistor (PM9) is connected to the first terminal of the twenty-third resistor (R23). The connection between the drain of the ninth PMOS transistor (PM9) and the twenty-third resistor (R23) leads to the Vo terminal, which simultaneously outputs a signal to the shaping module. The second terminal of the twenty-third resistor (R23) is connected to the drain of the second NMOS transistor (NM2), and the source of the second NMOS transistor (NM2) is grounded.

4. A low-temperature drift receiver for a high-speed CAN transceiver according to claim 1, characterized in that, The shaping module includes: power supply VCC, third NMOS transistor (NM3), fourth NMOS transistor (NM4), tenth PMOS transistor (PM10), fourteenth BJT transistor (Q14), sixth current source (I6), third switch (S3), first inverter (INV1), second inverter (INV2), and third inverter (INV3); The power supply VCC is connected to the drain of the third NMOS transistor (NM3) and the source of the tenth PMOS transistor (PM10). The gate of the third NMOS transistor (NM3) is connected to the bias voltage Vbias2. A Vo terminal is drawn from the connection between the source of the third NMOS transistor (NM3), the gate of the tenth PMOS transistor (PM10), and the gate of the fourth NMOS transistor (NM4), and is used to receive the Vo terminal signal from the hysteresis comparator module. The source of the third NMOS transistor (NM3) is connected to the Vo terminal, the gate of the tenth PMOS transistor (PM10), and the fourth NMOS transistor (NM4). The gate terminal of the transistor (NM4); the drain terminal of the tenth PMOS transistor (PM10) is connected to the drain terminal of the fourth NMOS transistor (NM4) and the input terminal of the first inverter (INV1); the source terminal of the fourth NMOS transistor (NM4) is connected to the collector and base of the thirteenth BJT transistor (Q13) and the first terminal of the third switch (S3), and the emitter of the thirteenth BJT transistor (Q13) is grounded; the first terminal of the sixth current source (I6) is connected to the second terminal of the third switch (S3), and the second terminal of the sixth current source (I6) is grounded; the output terminal of the first inverter INV is connected to the input terminal of the second inverter (INV2), the output terminal of the second inverter (INV2) is connected to the input terminal of the third inverter (INV3), and the output terminal of the third inverter (INV3) is led out to the OUT terminal, which simultaneously outputs a signal to the output stage module.

5. A low-temperature drift receiver for a high-speed CAN transceiver according to claim 1, characterized in that, The output stage module includes the following inverters: fourth inverter (INV4), fifth inverter (INV5), sixth inverter (INV6), seventh inverter (INV7), eighth inverter (INV8), ninth inverter (INV9), tenth inverter (INV10), eleventh inverter (INV11), eleventh PMOS transistor (PM11), twelfth PMOS transistor (PM12), thirteenth PMOS transistor (PM13), fourteenth PMOS transistor (PM14), fifteenth PMOS transistor (PM15), sixteenth PMOS transistor (PM16), seventeenth PMOS transistor (PM17), eighteenth PMOS transistor (PM18), nineteenth PMOS transistor (PM19), twentieth PMOS transistor (PM20), fifth NMOS transistor (NM5), sixth NMOS transistor (NM6), and seventh NMOS transistor (NM7). The circuit includes eight NMOS transistors (NM8), nine NMOS transistors (NM9), tenth NMOS transistors (NM10), eleventh NMOS transistors (NM11), twelfth NMOS transistors (NM12), thirteenth NMOS transistors (NM13), and fourteenth NMOS transistors (NM14); twenty-fourth resistors (R24), twenty-fifth resistors (R25), twenty-sixth resistors (R26), twenty-seventh resistors (R27), twenty-eighth resistors (R28), twenty-ninth resistors (R29), thirtieth resistors (R30), thirty-first resistors (R31), thirty-second resistors (R32), and thirty-third resistors (R33); and power supply ports VIO and RXD; the input terminal of the fourth inverter (INV4) leads to the OUT terminal, used to receive the OUT terminal signal of the shaping module; the output terminal of the fourth inverter (INV4) is connected to the fifth inverter (INV5). The input terminal of the fifth inverter (INV5) is connected to the input terminal of the sixth inverter (INV6), and the output terminal of the sixth inverter (INV6) is connected to the input terminals of the seventh inverter (INV7) and the eighth inverter (INV8). The output terminal of the ninth inverter (INV9) is connected to the input terminal of the tenth inverter (INV10), and the output terminal of the tenth inverter (INV10) is connected to the input terminal of the eleventh inverter (IN11). The output terminal of the seventh inverter (INV7) is connected to the eleventh PMOS transistor. The gate terminals of the 12th PMOS transistor (PM11), 13th PMOS transistor (PM13), 14th PMOS transistor (PM14), and 15th PMOS transistor (PM15); the output terminal of the 8th inverter (INV8) is connected to the gate terminals of the 16th PMOS transistor (PM16), 17th PMOS transistor (PM17), 18th PMOS transistor (PM18), 19th PMOS transistor (PM19), and 20th PMOS transistor (PM20);The output of the eleventh inverter (INV11) is connected to the gate terminals of the fifth NMOS transistor (NM5), sixth NMOS transistor (NM6), seventh NMOS transistor (NM7), eighth NMOS transistor (NM8), ninth NMOS transistor (NM9), tenth NMOS transistor (NM10), eleventh NMOS transistor (NM11), twelfth NMOS transistor (NM12), thirteenth NMOS transistor (NM13), and fourteenth NMOS transistor (NM14); the power supply VIO is connected to the eleventh PMOS transistor (PM11), twelfth PMOS transistor (PM12), and thirteenth PMOS transistor (PM13). The sources of the fourteenth PMOS transistor (PM14), fifteenth PMOS transistor (PM15), sixteenth PMOS transistor (PM16), seventeenth PMOS transistor (PM17), eighteenth PMOS transistor (PM18), nineteenth PMOS transistor (PM19), and twentieth PMOS transistor (PM20) are connected. The drain of the eleventh PMOS transistor (PM11) is connected to the drain of the fifth NMOS transistor (NM5) and the first terminal of the twenty-fourth resistor (R24). The drain of the twelfth PMOS transistor (PM12) is connected to the drain of the sixth NMOS transistor (NM6) and the first terminal of the twenty-fifth resistor (R25). The drain of the thirteenth PMOS transistor (PM13) is connected to the drain of the seventh NMOS transistor (NM7) and the first terminal of the twenty-sixth resistor (R26). The drain of the fourteenth PMOS transistor (PM14) is connected to the drain of the eighth NMOS transistor (NM8) and the first terminal of the twenty-seventh resistor (R27). The drain of the fifteenth PMOS transistor (PM15) is connected to the drain of the ninth NMOS transistor (NM9) and the first terminal of the twenty-eighth resistor (R28). The drain of the sixteenth PMOS transistor (PM16) is connected to the drain of the tenth NMOS transistor (NM10) and the first terminal of the twenty-ninth resistor (R29). The drain of the seventeenth PMOS transistor (PM17) is connected to the drain of the eleventh NMOS transistor (NM11) and the first terminal of the thirtieth resistor (R30). The drain of the eighteenth PMOS transistor (PM18) is connected to the drain of the twelfth NMOS transistor (NM11). The drain of the OS transistor (NM12) is connected to the first terminal of the thirty-first resistor (R31); the drain of the nineteenth PMOS transistor (PM19) is connected to the drain of the thirteenth NMOS transistor (NM13) and the first terminal of the thirty-second resistor (R32); the drain of the twentieth PMOS transistor (PM20) is connected to the drain of the fourteenth NMOS transistor (NM14) and the first terminal of the thirty-third resistor (R33); the sources of the fifth NMOS transistor (NM5), sixth NMOS transistor (NM6), seventh NMOS transistor (NM7), eighth NMOS transistor (NM8), ninth NMOS transistor (NM9), tenth NMOS transistor (NM10), eleventh NMOS transistor (NM11), twelfth NMOS transistor (NM12), thirteenth NMOS transistor (NM13), and fourteenth NMOS transistor (NM14) are all connected to ground.The second terminals of resistors 24 (R24), 25 (R25), 26 (R26), 27 (R27), 28 (R28), 29 (R29), 30 (R30), 31 (R31), 32 (R32), and 33 (R33) are all connected to the RXD port.

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