Semiconductor device

Abstract

The invention relates to a semiconductor device. The present invention addresses the problem of improving the reliability of a semiconductor device including an oxide semiconductor. The semiconductor device includes: a gate electrode over an insulating surface; a gate insulating layer on the gate electrode; an oxide semiconductor layer over the gate insulating layer; a first insulating layer on the oxide semiconductor layer; and a first pattern layer comprising an insulating material on the first insulating layer, the oxide semiconductor layer having a channel portion and a conductive portion, and the first pattern layer overlapping the channel portion in plan view.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. Background Technology

[0002] In recent years, oxide semiconductors have attracted attention as materials for semiconductor devices, replacing amorphous silicon, polycrystalline silicon, and monocrystalline silicon. In particular, thin-film transistors (TFTs) using oxide semiconductors as channels are being developed as semiconductor devices incorporating oxide semiconductors (e.g., Patent Documents 1-6). TFTs using oxide semiconductors as channels can be fabricated with simple structures and low-temperature processes, just like semiconductor devices using amorphous silicon as channels. TFTs using oxide semiconductors as channels are known to have higher field-effect mobility than TFTs using amorphous silicon as channels.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2021-141338 Patent Document 2: Japanese Patent Application Publication No. 2014-099601 Patent Document 3: Japanese Patent Application Publication No. 2021-153196 Patent Document 4: Japanese Patent Application Publication No. 2018-006730 Patent Document 5: Japanese Patent Application Publication No. 2016-184771 Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the Invention

[0004] The problem that the invention aims to solve Previously, various device structures, including top-gate and bottom-gate structures, have been studied for thin-film transistors using oxide semiconductors. However, from a reliability perspective, several issues remain. For example, in conventional device structures, it is difficult to simultaneously ensure the withstand voltage characteristics of the gate insulating layer (specifically, its tolerance to high voltages applied between the gate and source or between the gate and drain) and suppress damage to the oxide semiconductor layer. Therefore, there is still room for improvement in the reliability of thin-film transistors using existing oxide semiconductors.

[0005] One of the objectives of this invention is to improve the reliability of semiconductor devices, including oxide semiconductors.

[0006] Methods for solving problems An embodiment of the present invention relates to a semiconductor device comprising: a gate electrode on an insulating surface; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a first insulating layer on the oxide semiconductor layer; and a first patterned layer made of an insulating material on the first insulating layer, wherein the oxide semiconductor layer has a channel portion and a conductive portion, and in plan view, the first patterned layer overlaps with the channel portion. Attached Figure Description

[0007] [ Figure 1 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0008] [ Figure 2 [Illustrated view] is a schematic top view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0009] [ Figure 3 [Illustration 1] is a sequence diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0010] [ Figure 4 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0011] [ Figure 5 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0012] [ Figure 6 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] [ Figure 7 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] [ Figure 8 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] [ Figure 9 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] [ Figure 10 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] [ Figure 11 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] [ Figure 12 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0019] [ Figure 13 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0020] [ Figure 14 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0021] [ Figure 15 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0022] [ Figure 16 [Illustration 1] is a sequence diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] [ Figure 17 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0024] [ Figure 18 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0025] [ Figure 19 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0026] [ Figure 20 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0027] [ Figure 21 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0028] [ Figure 22 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0029] [ Figure 23 [Illustration 1] is a sequence diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] [ Figure 24 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] [ Figure 25 [Illustrated view] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0032] [ Figure 26 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention.

[0033] [ Figure 27 [Illustrated view] is a schematic top view showing the overall configuration of a display device according to an embodiment of the present invention.

[0034] [ Figure 28 [Illustration 1] is a block diagram showing the circuit configuration of a display device according to an embodiment of the present invention.

[0035] [ Figure 29 [Illustration 1] is a circuit diagram showing the configuration of the pixel circuit of a display device according to an embodiment of the present invention.

[0036] [ Figure 30 [Illustration 1] is a cross-sectional view showing the configuration of pixels in a display device according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures 10-40, 10a, 10b, 20a, 20b… Semiconductor device, 51… Pixel, 52… Liquid crystal area, 54… Sealing area, 56… Terminal area, 100… Substrate, 105… Gate electrode, 108… Gate electrode, 110… Gate insulating layer, 120… Metal oxide layer, 130… Oxide semiconductor layer, 131… Channel portion, 131a, 131b… Edge, 132… Conductive portion, 134… LDD portion, 134a… Edge, 140… Insulating layer, 141… Contact hole, 142… Pattern layer, 150… Metal oxide layer, 151… Pattern layer, 151a… Edge, 160… Insulating layer, 161… Pattern layer, 161a… Edge, 171… Terminal electrode, 180… Insulating layer, 181… …Contact hole, 191…Terminal electrode, 210, 220…Resist mask, 300…Array substrate, 301…Pixel circuit, 302…Source driving circuit, 303…Gate driving circuit, 304…Data signal line, 305…Scan signal line, 306…Terminal portion, 307, 308…Connection wiring, 310…Sealing portion, 311…Liquid crystal element, 311a…Liquid crystal layer, 320…Opposing substrate, 330…Flexible printed circuit board, 340…Chip, 360…Insulating layer, 370…Common electrode, 380…Insulating layer, 381…Contact hole, 390…Pixel electrode, 410…Switching element, 411…Gate electrode, 412…Source electrode, 413…Drain electrode, 420…Holding capacitor, 500…Display device Detailed Implementation

[0038] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely illustrative. Configurations readily conceived by those skilled in the art through appropriate modifications to the configuration of the embodiments while maintaining the spirit of the invention are of course included within the scope of the invention. With regard to the drawings, to make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form. However, the shapes shown are merely examples and do not limit the interpretation of the invention. In this specification and the drawings, the same reference numerals are used for elements that are the same as those described with respect to previously presented figures, and detailed descriptions are sometimes appropriately omitted.

[0039] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". For ease of explanation, the terms "up" or "below" are used, but the vertical relationship between the substrate and the oxide semiconductor layer may be configured in the opposite manner to the illustration. In the following description, the term "oxide semiconductor layer on the substrate" is merely used to describe the vertical relationship between the substrate and the oxide semiconductor layer as described above; other components may also be arranged between the substrate and the oxide semiconductor layer.

[0040] "Display device" refers to a structure that uses an electro-optic layer to display images. For example, the term "display device" sometimes refers to a display panel that includes an electro-optic layer, or sometimes it refers to a structure that is equipped with other optical components (such as polarizing components, backlights, touch panels, etc.) relative to the display unit. As long as there is no technical contradiction, the "electro-optic layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, regarding the embodiments described later, an organic EL display device including an organic EL layer is illustrated as a display device, but the structure in this embodiment can be applied to liquid crystal display devices that include a liquid crystal layer, as well as display devices that include other electro-optic layers as described above.

[0041] In this specification, unless otherwise expressly stated, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, the above expressions do not exclude the possibility that α includes other elements.

[0042] In this specification, "consistent" means not only complete consistency but also substantial consistency. "Substantial consistency" means that although not completely consistent, it falls within a range of minor differences that can be considered consistent, such as within an error range of ±5% (preferably ±3%).

[0043] <First Implementation> The semiconductor device according to one embodiment of the present invention will be described using a thin-film transistor as an example. The semiconductor device of the embodiments shown below may be a thin-film transistor used in display devices (e.g., organic EL display devices or liquid crystal display devices), or, for example, a thin-film transistor used in integrated circuits (ICs) or memory circuits such as microprocessors (MPUs).

[0044] [Semiconductor Device Structure] The configuration of a semiconductor device 10 in one embodiment of the present invention will be described. Figure 1 This is a schematic cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention. Figure 2 This is a schematic top view illustrating the configuration of a semiconductor device 10 according to one embodiment of the present invention. Specifically, Figure 1 Along Figure 2 The sectional view shown corresponds to the one obtained by cutting with a single-dot dashed line represented by A-A'.

[0045] First, use Figure 1 The cross-sectional structure of the semiconductor device 10 will be described. For example... Figure 1 As shown, a semiconductor device 10 is disposed above a substrate 100. The semiconductor device 10 includes a gate electrode 105, a gate insulating layer 110, an oxide semiconductor layer 130, an insulating layer 140, a patterned layer 151 made of metal oxide, a patterned layer 161 made of an insulating material, and a terminal electrode 171.

[0046] A gate electrode 105 is disposed on the substrate 100. The gate electrode 105 functions as the gate of the semiconductor device 10 (thin-film transistor). Specifically, the gate electrode 105 applies a gate voltage to the channel portion 131 of the oxide semiconductor layer 130, which will be described later. An insulating layer (not shown) may also be disposed on the substrate 100. That is, the gate electrode 105 can be disposed directly or indirectly on the substrate 100. In other words, the gate electrode 105 is disposed on an insulating surface.

[0047] A gate insulating layer 110 is disposed on the substrate 100 and the gate electrode 105. The gate insulating layer 110 functions as a barrier film to shield impurities diffusing from the substrate 100 toward the oxide semiconductor layer 130 and as a substrate of the oxide semiconductor layer 130 disposed thereon.

[0048] Although the illustrations are omitted, in conjunction with the functions described above, the gate insulating layer 110 is configured as a double-layer structure in this embodiment. Specifically, a silicon nitride layer is used as the lower insulating layer (the side closest to the substrate 100), and a silicon oxide layer is used as the upper insulating layer (the side closest to the oxide semiconductor layer 130). In this embodiment, the thickness of the lower insulating layer is 200 nm, and the thickness of the upper insulating layer is 100 nm, therefore the thickness of the gate insulating layer 110 is 300 nm. That is, in this embodiment, the thickness of the gate insulating layer 110 can be 200 nm or more (preferably 300 nm or more, more preferably 400 nm or more).

[0049] An oxide semiconductor layer 130 is disposed on the gate insulating layer 110. The oxide semiconductor layer 130 has a channel portion 131 and a conductive portion 132 that are continuous in a first direction. The channel portion 131 functions as a channel region of the semiconductor device 10. The conductive portion 132 functions as a source region or a drain region of the semiconductor device 10. The conductive portion 132 is a region with a lower resistance than the channel portion 131 and has the function of transferring charge carriers flowing in the channel portion 131 to the terminal electrode 171.

[0050] An insulating layer 140 is disposed on the oxide semiconductor layer 130. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 is a dielectric layer that electrically insulates the layer on which the terminal electrode 171 (described later) is formed from the layer on which the oxide semiconductor layer 130 is formed. The thickness of the insulating layer 140 is 50 nm to 200 nm (preferably 50 nm to 150 nm, more preferably 50 nm to 100 nm). The thickness of the insulating layer 140 is thinner than the thickness of the gate insulating layer 110. The advantages of the thinner insulating layer 140 will be described later.

[0051] A patterned layer 151 made of metal oxide is disposed on the insulating layer 140. The patterned layer 151 is obtained by patterning the metal oxide layer into island shapes. The patterned layer 151 functions as a barrier layer to suppress hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130. As will be described in detail later, the patterned layer 151 is the metal oxide layer 150 used in the manufacturing process of the semiconductor device 10 during the heat treatment for supplying oxygen to the oxide semiconductor layer 130 (see [link to semiconductor device manufacturing process]). Figure 6 Layers obtained by patterning.

[0052] The patterned layer 151 is disposed above the oxide semiconductor layer 130 via the insulating layer 140. That is, the insulating layer 140 is in contact with both the oxide semiconductor layer 130 and the patterned layer 151. The patterned layer 151 overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as... Figure 1As shown by a single-dotted line in the cross-sectional view, the position of the edge 151a of the pattern layer 151 coincides with the position of the edge 131a of the channel portion 131 in the vertical direction. In other words, in the cross-sectional view, the position of the edge 151a of the pattern layer 151 coincides with the position of the boundary between the channel portion 131 and the conductive portion 132 in the vertical direction. The reason for this alignment of the position of the edge 151a of the pattern layer 151 with the position of the edge 131a of the channel portion 131 will be explained later.

[0053] A patterned layer 161 made of an insulating material is disposed on the patterned layer 151. The patterned layer 161 is obtained by patterning an insulating layer such as silicon oxide into island shapes. The patterned layer 161 functions as a barrier layer to suppress hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130. For example, when an insulating layer containing a large amount of oxygen or an insulating layer containing a large number of defects is used as the insulating layer constituting the patterned layer 161, the oxygen and / or defects function as hydrogen traps.

[0054] In this embodiment, the resist mask 210 used when patterning the pattern layer 161 is used (see [reference]). Figure 7 A pattern layer 151 is formed, and therefore pattern layer 151 has the same pattern shape as pattern layer 161. That is, pattern layer 161 overlaps with the channel portion 131 of oxide semiconductor layer 130 in the same way as pattern layer 151. More specifically, as Figure 1 As shown by a single-dotted line, in cross-section, the position of the edge 161a of the pattern layer 161 coincides with the position of the edge 131a of the channel portion 131 in the vertical direction. In other words, in cross-section, the position of the edge 161a of the pattern layer 161 coincides with the position of the boundary between the channel portion 131 and the conductive portion 132 in the vertical direction.

[0055] Terminal electrode 171 is disposed on insulating layer 140 and electrically connected to conductive portion 132 via contact hole 141 provided in insulating layer 140. Terminal electrode 171 has the function of supplying charge carriers to conductive portion 132 and extracting charge carriers from conductive portion 132. That is, terminal electrode 171 functions as source electrode or drain electrode of semiconductor device 10 (thin-film transistor) depending on the function of conductive portion 132. Specifically, when electrically connected conductive portion 132 functions as source region, terminal electrode 171 functions as source electrode; when electrically connected conductive portion 132 functions as drain region, terminal electrode 171 functions as drain electrode.

[0056] In this embodiment, a bottom-gate transistor with a gate electrode 105 disposed below the oxide semiconductor layer 130 is exemplified as the semiconductor device 10, but its configuration is not limited to this. For example, it can also be constructed above the insulating layer 140 (in... Figure 1In the example shown, additional gate electrodes are configured above the pattern layer 151, thereby enabling the semiconductor device 10 to function as a dual-gate transistor.

[0057] Next, use Figure 2 The planar structure of the semiconductor device 10 will be described. For example... Figure 2 As shown, the first direction (D1 direction) is the direction in which the two terminal electrodes 171 are connected to each other (the direction in which the channel portion 131 and the conductive portion 132 are continuous), corresponding to the direction of carrier movement. The length of the channel portion 131 in the oxide semiconductor layer 130 in the first direction is the channel length (L), and the length of the channel portion 131 in the second direction (D2 direction) is the channel width (W). It should be noted that the second direction is a direction that intersects with the first direction. In this embodiment, the second direction represents a direction orthogonal to the first direction, but depending on the layout of the oxide semiconductor layer 130, the first direction and the second direction may not be orthogonal.

[0058] In this embodiment, in the first direction, the width of the gate electrode 105 is wider than the length (channel length) of the channel portion 131. The reason for this configuration is to effectively prevent external light from entering the channel portion 131. However, this is not limited to this example; the width of the gate electrode 105 may also be the same as the length of the channel portion 131.

[0059] like Figure 2 As shown, in top view, the patterned layer 161, made of an insulating material, is configured to overlap with the oxide semiconductor layer 130. Specifically, in top view, the patterned layer 161 is configured to intersect the channel portion 131 of the oxide semiconductor layer 130. It is desirable that the width of the patterned layer 161 in the second direction is wider than the width (W) of the oxide semiconductor layer 130 in the second direction. This configuration is effective in efficiently performing the function of the patterned layer 161 described above (the function of suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130).

[0060] Furthermore, in top view, the outer edge of the portion of patterned layer 161 that overlaps with oxide semiconductor layer 130 coincides with the outer edge of channel portion 131. In other words, patterned layer 161 intersects with channel portion 131 but does not overlap with conductive portion 132. However, the statement "patterned layer 161 intersects with channel portion 131 but does not overlap with conductive portion 132" includes the possibility that patterned layer 161 partially overlaps with conductive portion 132 within a margin of error. As described later, conductive portion 132 is formed by adding impurities to oxide semiconductor layer 130 using methods such as ion implantation. Therefore, due to the spread of impurities downwards from patterned layer 161, it is possible that a portion of conductive portion 132 slightly overlaps with patterned layer 161. It should be noted that the positional relationship between patterned layer 161 and oxide semiconductor layer 130 has been described here. However, as mentioned above, since patterned layer 151 and patterned layer 161 have the same pattern shape, the positional relationship between patterned layer 151 and oxide semiconductor layer 130 is also the same.

[0061] exist Figure 2 The illustration shows a configuration where the terminal electrode 171 and the gate electrode 105 do not overlap in top view, but the configuration is not limited to this. For example, in top view, either or both of the two terminal electrodes 171 may overlap with the gate electrode 105.

[0062] [Materials of each layer in a semiconductor device] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate with light transmittance, such as a glass substrate, quartz substrate, or sapphire substrate, can be used as the substrate. Alternatively, a rigid substrate without light transmittance, such as a silicon substrate, can also be used. Furthermore, a flexible substrate with light transmittance, such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate, can be used as the substrate. To improve the heat resistance of the substrate 100, impurities can be introduced into the aforementioned resin substrates. It should be noted that a substrate on which a silicon oxide film or a silicon nitride film is formed on the aforementioned rigid or flexible substrate can also be used as the substrate 100.

[0063] As described above, the gate electrode 105 has an area larger than the channel portion 131 of the oxide semiconductor layer 130, therefore it is preferable to use a material capable of blocking external light incident on the channel portion 131. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds thereof, can be used as the gate electrode 105. The gate electrode 105 can be a single-layer structure or a multilayer structure.

[0064] As the gate insulating layer 110, silicon oxide (SiOx), silicon nitride oxide (SiOxNy), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum oxide (AlOx), aluminum nitride oxide (AlOxNy), aluminum oxide nitride (AlNxOy), and aluminum nitride (AlNx) can be used, for example. Here, silicon nitride oxide (SiOxNy) and aluminum nitride oxide (AlOxNy) are silicon compounds and aluminum compounds containing a nitrogen (N) in a ratio less than oxygen (O) (x>y), respectively. Similarly, silicon oxide nitride (SiNxOy) and aluminum oxide nitride (AlNxOy) are silicon compounds and aluminum compounds containing oxygen in a ratio less than nitrogen (x>y), respectively. In this embodiment, the gate insulating layer 110 is configured as a double-layer structure, using a silicon nitride layer as the lower insulating layer and a silicon oxide layer as the upper insulating layer.

[0065] The oxide semiconductor layer 130 can have an amorphous structure or a polycrystalline structure.

[0066] The insulating layer 140 comprises an oxide with insulating properties. Specifically, silicon oxide (SiOx), silicon nitride oxide (SiOxNy), aluminum oxide (AlOx), aluminum nitride oxide (AlOxNy), etc., can be used as the insulating layer 140. In this embodiment, a silicon oxide layer with a thickness of 50 nm to 200 nm (preferably 50 nm to 150 nm, more preferably 50 nm to 100 nm) is used as the insulating layer 140.

[0067] The pattern layer 151 is composed of a metal oxide. In this embodiment, an oxide with aluminum as the main component (e.g., aluminum oxide) is used as the metal oxide constituting the pattern layer 151. Aluminum oxide has high gas barrier properties, therefore the pattern layer 151 has the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. The thickness of the pattern layer 151 can be set, for example, to 5 nm or more but less than 100 nm, 5 nm or more but less than 50 nm, 5 nm or more but less than 30 nm, or 7 nm or more but less than 15 nm.

[0068] The pattern layer 161 is composed of an insulating material. In this embodiment, silicon-based insulating materials such as silicon oxide (SiOx), silicon nitride oxide (SiOxNy), silicon nitride (SiNx), and silicon oxide nitride (SiNxOy) can be used as the insulating material constituting the pattern layer 161. As described above, by using an insulating material containing a large amount of oxygen or an insulating material containing a large number of defects as the insulating material, the pattern layer 161 can be given the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. The thickness of the pattern layer 161 can be set, for example, to 100 nm or more and 300 nm or less, 150 nm or more and 250 nm or less, or 175 nm or more and 200 nm or less.

[0069] Terminal electrode 171 is conductive. Materials used for terminal electrode 171 include, for example, copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds thereof. Terminal electrode 171 can be a single-layer structure or a multilayer structure.

[0070] [Semiconductor device manufacturing method] Next, a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3 This is a sequence diagram illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 12 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention.

[0071] like Figure 3 and Figure 4 As shown, a gate electrode 105 is formed on the substrate 100, and a gate insulating layer 110 is formed on the gate electrode 105. Figure 4 Step S1001). For example, a stacked structure of a silicon nitride layer and a silicon oxide layer is formed as a gate insulating layer 110. The gate insulating layer 110 is formed by CVD (Chemical Vapor Deposition). In this specification, the act of forming a film on a substrate by sputtering, CVD, or other methods is sometimes described as "forming a thin film," but it is used in the same way as the expression "forming a thin film."

[0072] When a silicon nitride layer is disposed near the substrate 100 as part of the gate insulating layer 110, impurities can be prevented from diffusing from the substrate 100 towards the oxide semiconductor layer 130. When a silicon oxide layer is disposed on the side adjacent to the subsequently formed oxide semiconductor layer 130 as part of the gate insulating layer 110, the characteristics of the interface between the gate insulating layer 110 and the oxide semiconductor layer 130 can be improved.

[0073] Regarding the silicon oxide layer, by setting the film deposition temperature to a lower level, the oxygen content can be increased. As described later, by increasing the oxygen content in the gate insulating layer 110, the amount of hydrogen diffusing into the oxide semiconductor layer 130 can be reduced. It should be noted that the film deposition temperature of the gate insulating layer 110 can be set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, more preferably 325°C or higher and 400°C or lower).

[0074] Next, as Figure 3 and Figure 5 As shown, a patterned oxide semiconductor layer 130 is formed on the gate insulating layer 110. Figure 3 Step S1002). In this embodiment, the process of forming the oxide semiconductor layer 130 is referred to as "OS patterning". That is, the oxide semiconductor layer 130 is formed by patterning an oxide semiconductor layer deposited on the gate insulating layer 110. In the description of this embodiment, when referred to as "oxide semiconductor layer" without the attached reference numerals, it refers to the oxide semiconductor layer in the state after film formation (i.e., the unprocessed state).

[0075] Etching of oxide semiconductor layers can be done using either wet etching or dry etching. In wet etching, acidic etchants (oxalic acid or hydrofluoric acid) can be used, for example.

[0076] In this embodiment, the oxide semiconductor layer is formed by sputtering. The thickness of the formed oxide semiconductor layer is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm.

[0077] When a thin film is formed on a substrate by sputtering, the temperature of the substrate rises during the thin film formation process because ions generated in the plasma and atoms ejected by the sputtering target collide with the object being formed (specifically, the structure formed on the substrate 100).

[0078] To control the substrate temperature (i.e., film formation temperature) during the formation of the oxide semiconductor layer, thin film formation can be performed while the substrate is being cooled. For example, the substrate can be cooled from the side opposite to the surface being formed so that the film formation temperature is below 100°C, 70°C, 50°C, or 30°C. In particular, the film formation temperature of the oxide semiconductor layer in this embodiment is preferably below 50°C. In this embodiment, the oxide semiconductor layer is formed at a film formation temperature of 50°C or lower, and OS annealing (described later) is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, it is preferable that the difference between the temperature during oxide semiconductor layer formation and the temperature during OS annealing of the oxide semiconductor layer 130 is 350°C or higher.

[0079] Next, after the oxide semiconductor layer 130 is patterned, the oxide semiconductor layer 130 is subjected to heat treatment (OS annealing). Figure 3(Step S1003). In OS annealing, the oxide semiconductor layer 130 is heat-treated in an atmospheric atmosphere at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C). The heating atmosphere is not limited to an atmospheric atmosphere, but is preferably an oxidizing atmosphere (an atmosphere containing oxygen). In addition, after reaching the specified temperature, the heat treatment time is 15 minutes to 120 minutes, or 30 minutes to 60 minutes.

[0080] In this embodiment, a substrate with an oxide semiconductor layer 130 formed thereon is placed in a furnace containing a heating medium (e.g., a support plate) that is pre-maintained at a set temperature (between 250°C and 500°C). The support plate, serving as the heating medium, supports the substrate and heats the substrate and the coating (including the oxide semiconductor layer 130) formed on it. When the substrate with the oxide semiconductor layer 130 formed thereon is placed on the support plate, the oxide semiconductor layer 130 is rapidly heated. When the substrate is placed in the furnace, it is desirable to suppress the temperature drop of the support plate to within 15%, 10%, or 5% of the set temperature. That is, it is preferable to control the temperature of the support plate in a manner that allows the oxide semiconductor layer 130 to reach the set temperature in the shortest possible time.

[0081] Next, as Figure 3 and Figure 6 As shown, an insulating layer 140 and a metal oxide layer 150 are formed. Figure 3 (Step S1004). For example, a silicon oxide layer is formed as an insulating layer 140. The insulating layer 140 is formed by CVD. In this embodiment, the film formation temperature of the insulating layer 140 is set to 350°C. The thickness of the insulating layer 140 is, for example, 50 nm to 200 nm, 50 nm to 150 nm, or 50 nm to 100 nm. In this embodiment, the thickness of the insulating layer 140 is set to 100 nm.

[0082] The metal oxide layer 150 is formed by sputtering. By using sputtering in the formation of the metal oxide layer 150, oxygen is injected into the insulating layer 140 during the formation of the metal oxide layer 150. Therefore, the insulating layer 140 after the formation of the metal oxide layer 150 contains a large amount of oxygen. The thickness of the metal oxide layer 150 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, alumina is used as the metal oxide layer 150. As described above, alumina has high gas barrier properties, thus suppressing the upward diffusion of oxygen injected into the insulating layer 140 during the heat treatment described later.

[0083] When a metal oxide layer 150 is formed using sputtering, the process gas used in sputtering may remain in the film of the metal oxide layer 150. For example, when Ar is used as the sputtering process gas, Ar may sometimes remain in the film of the metal oxide layer 150. The residual Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 150. That is, when Ar is used as the sputtering process gas, Ar can be detected by SIMS analysis or the like on the patterned layer 151 obtained by patterning the metal oxide layer 150.

[0084] Next, with the metal oxide layer 150 formed on the insulating layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 130. Figure 3 (Step S1005). During the process from forming the oxide semiconductor layer 130 to forming the insulating layer 140 on the oxide semiconductor layer 130, oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 130. By oxidation annealing, oxygen released from the gate insulating layer 110 and the insulating layer 140 is supplied to the oxide semiconductor layer 130, and the oxygen defects are repaired. The oxidation annealing can be performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C).

[0085] Oxygen released from the gate insulating layer 110 and the insulating layer 140 is supplied to the oxide semiconductor layer 130 through oxidation annealing. In the case where a portion of the gate insulating layer 110 uses a silicon nitride layer, hydrogen is sometimes released from the gate insulating layer 110 through the above-described oxidation annealing, but most of the released hydrogen is captured by oxygen contained in the upper silicon oxide layer before reaching the oxide semiconductor layer 130.

[0086] As described above, oxygen can be supplied to the oxide semiconductor layer 130 through oxidation annealing. During oxidation annealing, the upward diffusion of oxygen injected into the insulating layer 140 is blocked by the metal oxide layer 150, thus suppressing the release of oxygen into the atmosphere. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during oxidation annealing.

[0087] Next, as Figure 3 and Figure 7 As shown, an insulating layer 160 is formed on the metal oxide layer 150, and a resist mask 210 is further formed on the insulating layer 160. Figure 3(Step S1006). A silicon nitride (SiOxNy) layer is used as the insulating layer 160 in this embodiment. Since the insulating layer 160 is a silicon nitride layer, the oxygen content can be increased by setting the film formation temperature to a lower level. By increasing the oxygen content in the insulating layer 160, hydrogen diffusion from above into the oxide semiconductor layer 130 can be effectively suppressed. It should be noted that the film formation temperature of the insulating layer 160 can be set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, more preferably 325°C or higher and 400°C or lower).

[0088] The resist mask 210 is configured to overlap with the oxide semiconductor layer 130. As described later, the portion of the oxide semiconductor layer 130 that overlaps with the resist mask 210 corresponds to the portion where the channel portion 131 is formed. Figure 2 As shown, the resist mask 210 is configured to intersect the oxide semiconductor layer 130 in the second direction.

[0089] Next, as Figure 3 and Figure 8 As shown, the metal oxide layer 150 and the insulating layer 160 are etched by using the resist mask 210 as a mask to form a patterned layer 151 made of metal oxide and a patterned layer 161 made of insulating material. Figure 3 (Step S1007). The etching of the metal oxide layer 150 and the insulating layer 160 can be either wet etching or dry etching. In wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0090] When etching the insulating layer 160, a large selectivity ratio between the metal oxide layer 150 and the insulating layer 160 is preferable. A large selectivity ratio allows the metal oxide layer 150 to be used as an etch stop layer during the etching of the insulating layer 160. In this case, after etching the insulating layer 160, the etchant or etching gas can be changed to etch the metal oxide layer 150. Furthermore, a large selectivity ratio between the insulating layer 140 and the metal oxide layer 150 is also preferable when etching the metal oxide layer 150.

[0091] Next, as Figure 3 and Figure 9 As shown, the resist mask 210 is removed. Figure 3 Step S1008). By removing the resist mask 210, a patterned layer 151 made of metal oxide and a patterned layer 161 made of insulating material remain on the insulating layer 140.

[0092] Next, as Figure 3 and Figure 10As shown, ion implantation is performed above the patterned layer 161 made of an insulating material to add impurities to the oxide semiconductor layer 130. Figure 3 (Step S1009). Phosphorus, boron, argon, etc., can be used as impurities. The purpose of adding impurities is to create oxygen defects in a portion of the oxide semiconductor layer 130 to improve conductivity; therefore, elements with large atomic radii are preferred as impurities. This embodiment shows an example of adding impurities by ion implantation, but ion doping can also be used. In this embodiment, ion implantation is used to add boron. The ion implantation conditions in this embodiment are an accelerating voltage of 30 keV and a dose of 1 × 10⁻⁶. 15 / cm 2 However, this is not the only example.

[0093] like Figure 10 As shown, when impurities are implanted into the oxide semiconductor layer 130 by ion implantation, conductive portions 132 are formed in the oxide semiconductor layer 130. At this time, the region that remains unchanged without impurity implantation functions as a channel portion 131. That is, in cross-section, the positions of the edges of the pattern layers 151 and 161 are aligned with the positions of the edges of the channel portions 131 in the vertical direction.

[0094] Impurities are added to the conductive portion 132 via the insulating layer 140. As described above, the conductive portion 132 functions as the source region or drain region of the semiconductor device 10.

[0095] In this embodiment, the insulating layer 140 does not need to be used as a gate insulating layer, so the thickness can be set to 50 nm or more and 200 nm or less (preferably 50 nm or more and 150 nm or less, more preferably 50 nm or more and 100 nm or less). Furthermore, in the area other than directly below the patterned layer 161, since the metal oxide layer 150 is removed, the insulating layer 140 is exposed. That is, impurities can be added to the oxide semiconductor layer 130 without passing through a metal oxide layer with high gas barrier properties. In this way, in this embodiment, the thickness of the insulating layer 140 can be reduced, and it is not necessary to pass through a dense metal oxide layer, so even with a lower accelerating voltage, the impurity dosage can be increased. That is, the manufacturing apparatus used for impurity addition is not subjected to excessive burden, a sufficient amount of impurities can be added to the oxide semiconductor layer 130, and thus the resistance value of the conductive portion 132 can be sufficiently reduced.

[0096] Furthermore, in this embodiment, the pattern layer 161 can be used as a mask, so it is not necessary to use the resist mask 210 as a mask for impurity addition. If a large amount of impurities is injected into the resist mask 210, it can sometimes be difficult to remove the resist mask 210, but this problem does not occur in this embodiment. However, it is not limited to this example; impurity addition can also be performed while the resist mask 210 remains on the pattern layer 161.

[0097] Next, as Figure 3 and Figure 11 As shown, a contact hole 141 is formed in the insulating layer 140. Figure 3 (Step S1010). The contact hole 141 exposes a portion of the conductive portion 132. At this time, in this embodiment, the metal oxide layer 150 located directly above the conductive portion 132 is removed, thus having the advantage of being easy to form the contact hole 141.

[0098] Finally, as Figure 3 and Figure 12 As shown, a terminal electrode 171 is formed on the conductive portion 132 exposed through the contact hole 141. Figure 3 Step S1011). Through the process described above, the following steps are completed. Figure 1 The semiconductor device 10 shown.

[0099] The semiconductor device 10 of this embodiment can use an insulating layer with a thickness of 200 nm or more (preferably 300 nm or more) as the gate insulating layer 110, thus sufficiently ensuring the withstand voltage characteristics of the gate insulating layer. Furthermore, when forming the conductive portion 132 in the oxide semiconductor layer 130, low resistance is achieved by adding impurities via the insulating layer 140, thus suppressing damage to the oxide semiconductor layer 130 (especially damage to the channel portion 131). At this time, the film thickness of the insulating layer 140 is 200 nm or less (preferably 150 nm or less), thus suppressing the load on the impurity addition device and adding a sufficient amount of impurities, thereby sufficiently reducing the resistance value of the conductive portion 132. As described above, according to this embodiment, the reliability of the semiconductor device 10 including the oxide semiconductor can be improved.

[0100] In this specification, "field-effect mobility" refers to the field-effect mobility in the saturation region of the semiconductor device 10. It is the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source and drain is greater than the value obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage supplied to the gate (Vg).

[0101] (Modification 1 of the first embodiment) In the semiconductor device 10 described above, an example is shown in which the metal oxide layer 150 is etched to form a pattern layer 151 made of metal oxide, but it is also possible not to etch the metal oxide layer 150 and leave it as is.

[0102] Figure 13 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 10a in a modified embodiment of the present invention. In this modified example, the semiconductor device 10a has a metal oxide layer 150 remaining on the insulating layer 140 without patterning. That is, the metal oxide layer 150 overlaps not only with the channel portion 131 of the oxide semiconductor layer 130, but also with the conductive portion 132.

[0103] In the semiconductor device 10a of this modified example, the metal oxide layer 150 and Figure 1 The patterned layer 151 shown also functions as a barrier layer to suppress hydrogen diffusion from above into the oxide semiconductor layer 130.

[0104] (Modification 2 of the first embodiment) In the semiconductor device 10 described above, an example is shown in which the metal oxide layer 150 is etched to form a patterned layer 151 made of metal oxide, but it is also possible to remove the metal oxide layer 150 by etching without patterning it.

[0105] Figure 14 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 10b in a modified embodiment of the present invention. Regarding the semiconductor device 10b of this modified embodiment, in... Figure 3 After the oxidation annealing shown in step S1005, the metal oxide layer 150 formed on the insulating layer 140 is etched to completely remove it. That is, in this modified example, the metal oxide layer 150 and the pattern layer 151 composed of metal oxides do not exist on the insulating layer 140.

[0106] According to this variation, in Figure 3 In the process of adding impurities to the oxide semiconductor layer 130 as shown in S1009, even if the accelerating voltage is set low, the dosage of the added impurities can be sufficiently high. Furthermore, according to this modified example, Figure 3 Forming contact holes 141 into the insulating layer 140 as shown in S1010 is easy.

[0107] It should be noted that, in this modified example, dry etching is preferably used when etching the insulating layer 160 to form the patterned layer 161 made of an insulating material. In this embodiment, the insulating layer 140 serving as the substrate is a silicon oxide layer, and the insulating layer 160 is a silicon nitride oxide layer containing nitrogen in the silicon oxide layer. Therefore, by monitoring the amount of nitrogen in the reaction gas, the endpoints of the etching of the insulating layer 160 can be identified. By using this technique, over-etching of the insulating layer 140 serving as the substrate can be prevented after the patterned layer 161 made of an insulating material is formed.

[0108] <Second Implementation Method> In this embodiment, a semiconductor device 20 with a layer structure different from that of the semiconductor device 10 in the first embodiment will be described. In the description of this embodiment, elements that are the same as those in the first embodiment are sometimes indicated by the same reference numerals in the drawings and their descriptions are omitted.

[0109] [Semiconductor Device Structure] Figure 15 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 20 according to one embodiment of the present invention. Figure 1 The semiconductor device 10 shown is different in that an insulating layer 180 is provided on the insulating layer 140 and the patterned layer 161 made of insulating material, and a terminal electrode 191 is provided on the insulating layer 180.

[0110] In this embodiment, insulating layers 140 and 180 are used to insulate the oxide semiconductor layer 130 from the terminal electrode 191. The insulating layer 180 can be selected from, for example, any insulating layer among silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiOxNy), or silicon oxide nitride (SiOxNy). Alternatively, the insulating layer 180 can also be made of resin materials such as acrylic acid or polyimide. Furthermore, the insulating layer 180 can be a single-layer structure comprising layers made of the above-mentioned materials, or it can be a multilayer structure.

[0111] Terminal electrode 191 is electrically connected to conductive portion 132 of oxide semiconductor layer 130 via contact hole 181 formed in a stacked structure composed of insulating layer 140 and insulating layer 180. In this embodiment, the layer on which terminal electrode 191 is formed and the layer on which oxide semiconductor layer 130 is formed are separated by a distance equal to the combined thickness of insulating layers 140 and 180. Therefore, it has the advantage of high insulation between the layer on which terminal electrode 191 is formed and the layer on which oxide semiconductor layer 130 is formed.

[0112] The semiconductor device 20 of this embodiment has the same other effects as the semiconductor device 10 of the first embodiment.

[0113] [Semiconductor device manufacturing method] Next, a method for manufacturing the semiconductor device 20 according to one embodiment of the present invention will be described. Figure 16 This is a sequence diagram illustrating a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention. Figures 17-19 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 20 according to an embodiment of the present invention.

[0114] In the manufacturing method of the semiconductor device 20 of this embodiment, up to the first embodiment... Figure 3 The processes from steps S1001 to S1009 shown are the same as the manufacturing method described in the first embodiment. The manufacturing method of this embodiment includes... Figure 16 The steps S1110 to S1112 shown are used instead. Figure 3 The steps S1010 and S1011 shown are different from the manufacturing method of the first embodiment in this respect.

[0115] Similar to the first embodiment, by Figure 3 After adding impurities to the oxide semiconductor layer 130 in steps S1001 to S1009, as follows: Figure 16 and Figure 17 As shown, an insulating layer 180 is formed on the insulating layer 140 and the patterned layer 161 made of insulating material. Figure 16 (Step S1110). As described above, the material constituting the insulating layer 180 can be any material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiOxNy), silicon nitride oxide (SiOxNy), or resin.

[0116] In this embodiment, a laminated structure consisting of a silicon oxide layer and a silicon nitride layer is formed using a CVD method as the insulating layer 180. The thickness of the insulating layer 180 can be, for example, 30 nm to 500 nm. In this embodiment, the thickness of the lower silicon oxide layer is 100 nm, and the thickness of the upper silicon nitride layer is 300 nm. That is, the thickness of the insulating layer 180 in this embodiment is 400 nm. However, the thickness of the insulating layer 180 is not limited to this example; it can be further thickened or thinned.

[0117] The film-forming temperature of the insulating layer 180 is preferably set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, and more preferably 325°C or higher and 400°C or lower).

[0118] The insulating layer 180 functions as a passivation layer (protective layer) to prevent gases and moisture from entering from the outside. Additionally, as described above, it also serves to insulate and separate the terminal electrode 191 from the conductive portion 132 of the oxide semiconductor layer 130. Furthermore, in this embodiment, a silicon nitride layer is used in a portion of the insulating layer 180, which contributes to reducing the resistance of the conductive portion 132.

[0119] When forming the silicon nitride layer by CVD, ammonia is used as the feed gas, resulting in a silicon nitride layer containing a large amount of hydrogen. Therefore, during and after the formation of the insulating layer 180, hydrogen diffuses from the silicon nitride layer by heating the insulating layer 180. The diffused hydrogen reaches the conductive portion 132 via the silicon oxide layer below the insulating layer 180 and the insulating layer 140. At this time, the hydrogen is captured by oxygen defects inside the conductive portion 132 formed by the aforementioned ion implantation, forming donor levels. This contributes to the low resistance of the conductive portion 132. In this case, the patterned layer 151 made of metal oxide (aluminum oxide) and the patterned layer 161 made of insulating material (silicon nitride oxide) function as barrier layers to suppress the movement of hydrogen diffusing from the insulating layer 170 toward the channel portion 131 of the oxide semiconductor layer 130.

[0120] Next, as Figure 16 and Figure 18 As shown, a contact hole 181 is formed in the laminated structure consisting of insulating layer 140 and insulating layer 180. Figure 16 (Step S1111). The contact hole 181 exposes a portion of the conductive portion 132. In this embodiment, the metal oxide layer 150 located directly above the conductive portion 132 is removed in the same manner as in the first embodiment, thus providing the advantage of easily forming the contact hole 181.

[0121] Finally, as Figure 16 and Figure 19 As shown, a terminal electrode 191 is formed on the conductive portion 132 exposed through the contact hole 181. Figure 16 Step S1112). Through the process described above, the following steps are completed. Figure 15 The semiconductor device 20 shown.

[0122] (Modification 1 of the second embodiment) In the semiconductor device 20 described above, an example is shown in which the metal oxide layer 150 is etched to form a pattern layer 151 made of metal oxide, but it is also possible not to etch the metal oxide layer 150 and leave it as is.

[0123] Figure 20This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 20a in a modified embodiment of the present invention. In this modified semiconductor device 20a, a metal oxide layer 150 remains on the insulating layer 140 without patterning. That is, the metal oxide layer 150 overlaps not only with the channel portion 131 of the oxide semiconductor layer 130, but also with the conductive portion 132.

[0124] In the semiconductor device 20a of this modified example, the metal oxide layer 150 and Figure 15 The patterned layer 151 shown also functions as a barrier layer to suppress hydrogen diffusion from above into the oxide semiconductor layer 130.

[0125] (Modification 2 of the second embodiment) In the semiconductor device 20 described above, an example is shown in which the metal oxide layer 150 is etched to form a patterned layer 151 made of metal oxide, but it is also possible to remove the metal oxide layer 150 by etching without patterning it.

[0126] Figure 21 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 20b in a modified embodiment of the present invention. Regarding the semiconductor device 20b of this modified embodiment, in... Figure 16 After the oxidation annealing shown in step S1005, the metal oxide layer 150 formed on the insulating layer 140 is etched to completely remove it. That is, in this modified example, the metal oxide layer 150 and the pattern layer 151 composed of metal oxides do not exist on the insulating layer 140.

[0127] According to this variation, in Figure 16 In the process of adding impurities to the oxide semiconductor layer 130 as shown in S1009, even if the accelerating voltage is set low, the dosage of the added impurities can be sufficiently high. Furthermore, according to this modified example, Figure 16 It is easy to form contact hole 181 in the laminated structure of insulating layer 140 and insulating layer 180 as shown in S1111.

[0128] <Third Implementation Method> In this embodiment, a semiconductor device 30 with a different configuration of oxide semiconductor layer 130 than the semiconductor device 20 of the second embodiment will be described. In the description of this embodiment, the same reference numerals are sometimes used in the drawings to indicate elements identical to those in the second embodiment, and descriptions are omitted.

[0129] [Semiconductor Device Structure] Figure 22 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 30 according to one embodiment of the present invention. Figure 15One difference in the semiconductor device 20 shown is that an LDD section 134 is provided in the oxide semiconductor layer 130. "LDD" is short for "Light Doped Drain." That is, the LDD section 134 refers to the portion whose resistance is lower than that of the channel section 131 and higher than that of the conductive section 132. For example... Figure 22 As shown, the LDD portion 134 is disposed between the channel portion 131 and the conductive portion 132. That is, the oxide semiconductor layer 130 of this embodiment has a structure in which the channel portion 131, the LDD portion 134 and the conductive portion 132 are continuous in the first direction.

[0130] The patterned layer 151, made of metal oxide, overlaps with the channel portion 131 and the conductive portion 132. In this embodiment, in cross-section, the position of the edge 151a of the patterned layer 151 coincides vertically with the position of the edge 134a on the conductive portion 132 side of the LDD portion 134. In other words, in cross-section, the position of the edge 151a of the patterned layer 151 coincides vertically with the position of the boundary between the LDD portion 134 and the conductive portion 132. Thus, in this embodiment, the width of the patterned layer 151 is wider than the width of the channel portion 131 in the first direction, which is effective in effectively performing the function of the patterned layer 151 (suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130). However, its configuration is not limited to this, and the patterned layer 151 may not overlap with the LDD portion 134.

[0131] Furthermore, the patterned layer 161, made of an insulating material, overlaps with the channel portion 131. In this embodiment, in cross-section, the position of the edge 161a of the patterned layer 161 coincides vertically with the position of the edge 134b on the channel portion 131 side of the LDD portion 134. In other words, in cross-section, the position of the edge 161a of the patterned layer 161 coincides vertically with the position of the boundary between the channel portion 131 and the LDD portion 134.

[0132] In addition, Figure 22 In the example shown, the portion of the insulating layer 140 that overlaps with the conductive portion 132 is removed, forming a patterned layer 142 made of an insulating material. That is, in the semiconductor device 30 of this embodiment, the insulating layer 180 is in contact with the side surface of the patterned layer 142 and the conductive portion 132.

[0133] The semiconductor device 30 of this embodiment has the same other effects as the semiconductor device 10 of the first embodiment.

[0134] [Semiconductor device manufacturing method] Next, a method for manufacturing the semiconductor device 30 according to one embodiment of the present invention will be described. Figure 23This is a sequence diagram illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention. Figures 24-26 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 30 according to an embodiment of the present invention.

[0135] In the manufacturing method of the semiconductor device 30 of this embodiment, up to the second embodiment... Figure 16 The processes from steps S1001 to S1009 shown are the same as the manufacturing method described in the second embodiment. The manufacturing method of this embodiment is... Figure 16 An additional step was added between steps S1009 and S1110 shown. Figure 23 The steps S1201 to S1203 shown are different from the manufacturing method of the second embodiment in this respect.

[0136] First, similar to the second embodiment, by Figure 16 Steps S1001 to S1009 involve adding impurities to the oxide semiconductor layer 130 to form a conductive portion 132. Next, as... Figure 23 and Figure 24 As shown, a resist mask 220 is formed again on top of the patterned layer 161 made of an insulating material. At this time, as... Figure 24 As shown, in the first direction, the width of the resist mask 220 is narrower than the width of the pattern layer 161. Then, the pattern layer 161 is etched using the resist mask 220 as a mask. Figure 23 Step S1201).

[0137] In step S1201, the pattern layer 161 exposed from the resist mask 220 is removed. In this embodiment, a silicon nitride layer is used as the pattern layer 161, and a silicon oxide layer is used as the insulating layer 140. Therefore, the selectivity for etching between the pattern layer 161 and the insulating layer 140 is small, so when the pattern layer 161 is etched, the insulating layer 140 exposed from the pattern layer 151 made of metal oxide is also removed.

[0138] The etching process of pattern layer 161 stops at the point when a portion of the upper surface of the pattern layer 151 below is exposed. In this embodiment, since the thickness of pattern layer 161 is greater than the thickness of insulating layer 140, the insulating layer 140 directly above conductive portion 132 is removed, exposing conductive portion 132.

[0139] Next, as Figure 23 and Figure 25 As shown, the resist mask is removed. Figure 23 Step S1202). Then, ion implantation is performed above the patterned layer 161 to perform a second impurity addition to the oxide semiconductor layer 130 ( Figure 23Step S1203). The added impurities are used in conjunction with... Figure 23 The same impurities (phosphorus, boron, argon, etc.) are added in step S1009.

[0140] The conditions for ion implantation can be related to Figure 23 Step S1009 can be the same or different. In this embodiment, the accelerating voltage is set to 30 keV and the dose is set to 1 × 10⁻⁶. 13 / cm 2 .like Figure 25 As shown, in this embodiment, an LDD portion 134 is formed at the end of the channel portion 131 in the first direction (the portion that does not overlap with the pattern layer 161) by adding impurities a second time. Since impurities are added to the LDD portion 134 via the pattern layer 151 and the insulating layer 140, even when impurities are added under the same conditions as in step S1009, the amount of impurities added is less than that of the conductive portion 132. That is, the resistance value of the LDD portion 134 is higher than that of the conductive portion 132.

[0141] After the LDD section 134 is formed through the above process, it undergoes... Figure 23 Steps S1110 to S1112 shown are complete. Figure 22 The semiconductor device 30 shown. Steps S1110 to S1112 are as described in the second embodiment.

[0142] (Modification 1 of the third embodiment) Regarding the aforementioned semiconductor device 30, it is explained that because a patterned layer 151 composed of metal oxide is formed on the insulating layer 140, it enables the implementation of... Figure 23 In step S1201 (etching process of the side of the pattern layer 161), the insulating layer 140 located directly above the conductive portion 132 is removed. However, as described in variations 1 and 2 of the second embodiment, the final device structure differs depending on whether the metal oxide layer 150 remains or is completely removed.

[0143] For example, in the case of Modification 1 of the second embodiment, the metal oxide layer 150 remains on the insulating layer 140 without being etched. In this case, even if... Figure 23 In step S1201, the metal oxide layer 150 also functions as an etch stop layer, thus preventing the insulating layer 140 from being etched. In this case, Figure 22 In the device structure, an insulating layer 140 is provided instead of a pattern layer 142, and a metal oxide layer 150 is provided instead of a pattern layer 151.

[0144] Furthermore, in the case of Modification 2 of the second embodiment, the metal oxide layer 150 and the pattern layer 151 are not present on the insulating layer 140. In this case, if implemented... Figure 23 In step S1201, the portion of the insulating layer 140 that does not overlap with the resist mask 220 (i.e., the portion that does not overlap with the pattern layer 161) is completely removed. Therefore, at the end of the etching process, the end of the channel portion 131 (the portion that does not overlap with the resist mask 220) is exposed. In this case, Figure 23 In the process of adding impurities to the oxide semiconductor layer 130 as shown in S1203, even if the accelerating voltage is set to a low level, the amount of impurities added to the LDD section 134 can be sufficiently high.

[0145] (Modification 2 of the third embodiment) exist Figure 22 The illustrated structure shows an example of electrically connecting the terminal electrode 191 to the conductive portion 132 via a contact hole 181 provided in the insulating layer 180, but is not limited to this example. For example, the insulating layer 180 may not be provided, and the terminal electrode 191 may be directly connected to the conductive portion 132. In this case, Figure 23 In process S1203, after adding impurities to the oxide semiconductor layer 130, a conductive layer covering the oxide semiconductor layer 130 and the pattern layer 161 is formed. Then, the conductive layer is patterned to form a terminal electrode 191 that is connected to the conductive portion 132.

[0146] <Fourth Implementation Method> In the first embodiment, an example is shown where the oxide semiconductor layer 130 is disposed in contact with the gate insulating layer 110, but a metal oxide layer may also be disposed between the gate insulating layer 110 and the oxide semiconductor layer 130. In the description of this embodiment, the same reference numerals are sometimes used in the drawings for elements that are the same as in the first embodiment, and the description is omitted.

[0147] Figure 26 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 40 according to one embodiment of the present invention. The basic structure and... Figure 1 The semiconductor device 10 shown is similar, but in this embodiment, the semiconductor device 40 has a metal oxide layer 120 disposed between the gate insulating layer 110 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 120 uses a metal oxide with aluminum as the main component (specifically, an aluminum oxide (AlOx) layer). The metal oxide layer 120 can be formed, for example, by sputtering.

[0148] like Figure 26As shown, in this embodiment, the metal oxide layer 120 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, during implementation... Figure 3 After step S1001, a metal oxide layer 120 and an oxide semiconductor layer 130 are continuously formed. Then, the following steps are performed: Figure 3 The oxide semiconductor layer 130 is obtained by processes S1002 and S1003. Furthermore, by etching the oxide semiconductor layer 130 and the metal oxide layer 120, a metal oxide layer 120 having the same pattern shape as the oxide semiconductor layer 130 can be formed.

[0149] The thickness of the metal oxide layer 120 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 120 is set to 3 nm. In this embodiment, even if the aluminum oxide layer used as the metal oxide layer 120 has a thickness of 1 nm to 10 nm, it still has high barrier properties against gases. Therefore, the metal oxide layer 120 of this embodiment blocks hydrogen and oxygen emitted from the gate insulating layer 110 and suppresses hydrogen and oxygen emitted from below from reaching the oxide semiconductor layer 130.

[0150] The metal oxide layer 120 is used to block hydrogen released from the gate insulating layer 110, which is preferred in suppressing the reduction reaction of the oxide semiconductor layer 130.

[0151] Furthermore, after the oxide semiconductor layer 130 is formed, during various manufacturing processes (such as patterning), more oxygen defects are formed on the upper side of the oxide semiconductor layer 130 than on the lower side. That is, the oxygen defects in the oxide semiconductor layer 130 exist in a non-uniform distribution along the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen defects formed on the upper side of the oxide semiconductor layer 130, then an excessive amount of oxygen will be supplied to the lower side of the oxide semiconductor layer 130. As a result, defect energy levels different from those of the oxygen defects are formed due to the excessive oxygen supply, sometimes leading to changes in characteristics or a decrease in field-effect mobility during reliability testing. Therefore, it is preferable to use the metal oxide layer 120 to block oxygen released from the gate insulating layer 110 in order to suppress the excessive oxygen supply to the lower side of the oxide semiconductor layer 130.

[0152] In this embodiment, as shown, during the... Figure 3During the oxidation annealing shown in step S1005, oxygen supply to the lower surface of the oxide semiconductor layer 130, where the amount of oxygen deficiency is small, can be suppressed, while oxygen supply to the upper surface and sides of the oxide semiconductor layer 130, where the amount of oxygen deficiency is relatively large, can be performed. Therefore, during oxidation annealing, oxygen can be efficiently supplied to the oxide semiconductor layer 130, thereby improving the reliability of the semiconductor device 40.

[0153] It should be noted that this embodiment describes the application of the first embodiment. Figure 1 The example of semiconductor device 10 shown can also be applied to other semiconductor devices shown in the second or third embodiment.

[0154] <Fifth Implementation> In this embodiment, a display device 500 using the semiconductor device 10 according to one embodiment of the present invention will be described. In the embodiments shown below, the semiconductor device 10 described in the first embodiment will be used as an element in the circuit constituting a liquid crystal display device. However, this is not limited to this example; the semiconductor device described in the second to fourth embodiments may also be used as an element in the circuit constituting a liquid crystal display device. Furthermore, it may be used instead of an element in the circuit constituting a liquid crystal display device as an element in the circuit constituting another display device such as an organic EL display device.

[0155] [Overview of the display device] Figure 27 This is a schematic top view illustrating the overall configuration of a display device 500 according to one embodiment of the present invention. Figure 27 As shown, the display device 500 includes an array substrate 300, a sealing portion 310, an opposing substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the opposing substrate 320 are bonded together by the sealing portion 310. A plurality of pixels 51 are arranged in a matrix in a liquid crystal region 52 surrounded by the sealing portion 310. That is, a display region is formed by a plurality of pixels 51 arranged in the X and Y directions respectively. The liquid crystal region 52 is the region that overlaps with the liquid crystal element 311 described later in a top view. It should be noted that, regarding the pixels 51, the letters "R", "G", and "B" correspond to pixels for displaying red, green, and blue, respectively.

[0156] The sealing region 54, where the sealing portion 310 is provided, is the region surrounding the liquid crystal region 52. A flexible printed circuit board 330 is provided in the terminal region 56. The terminal region 56 is the region in the array substrate 300 exposed from the opposing substrate 320, and is located outside the sealing region 54. The outer side of the sealing region 54 refers to the area where the sealing portion 310 is provided and the outer side of the area surrounded by the sealing portion 310. An IC chip 340 is provided on the flexible printed circuit board 330. The IC chip 340 supplies power to the pixel circuits 301 (see [link to relevant documentation]) for driving each pixel circuit 301 disposed in each pixel 51. Figure 28 (The signal).

[0157] [Circuit configuration of the display device] Figure 28 This is a block diagram illustrating the circuit configuration of a display device 500 according to one embodiment of the present invention. Figure 28 As shown, multiple pixel circuits 301 and Figure 27 The pixels 51 shown are arranged in a matrix. A source drive circuit 302 is positioned adjacent to the liquid crystal region 52 where the pixel circuit 301 is located in the Y direction (column direction). A gate drive circuit 303 is positioned adjacent to the liquid crystal region 52 in the X direction (row direction). The source drive circuit 302 and the gate drive circuit 303 are located in the aforementioned sealed region 54. However, the area where the source drive circuit 302 and the gate drive circuit 303 are located is not limited to the sealed region 54; it can be located anywhere outside the region where the pixel circuit 301 is located.

[0158] Data signal line 304 extends from source drive circuit 302 along the Y direction and is connected to a plurality of pixel circuits 301 arranged in the Y direction. Scan signal line 305 extends from gate drive circuit 303 along the X direction and is connected to a plurality of pixel circuits 301 arranged in the X direction.

[0159] A terminal portion 306 is provided in the terminal region 56. The terminal portion 306 is connected to the source drive circuit 302 by a connection wiring 307. Similarly, the terminal portion 306 is connected to the gate drive circuit 303 by a connection wiring 308. By connecting the flexible printed circuit board 330 to the terminal portion 306, an external machine is connected to the display device 500 via the flexible printed circuit board 330. Each pixel circuit 301 provided in the display device 500 is driven by a signal from the external machine input via the flexible printed circuit board 330.

[0160] The semiconductor device 10 shown in the first embodiment is used as a switching element or current control element included in the pixel circuit 301, the source driving circuit 302, and the gate driving circuit 303.

[0161] [Pixel circuit of display device] Figure 29 This is a circuit diagram illustrating the configuration of the pixel circuit 301 of a display device 500 according to one embodiment of the present invention. Figure 29 As shown, the pixel circuit 301 includes components such as a switching element 410, a holding capacitor 420, and a liquid crystal element 311.

[0162] The switching element 410 is configured as a semiconductor device 10 according to the first embodiment. The switching element 410 has a gate electrode 411, a source electrode 412, and a drain electrode 413. The gate electrode 411 is connected to the scan signal line 305. However, the gate electrode 411 and the scan signal line 305 may also be formed from a single conductive layer. The source electrode 412 is connected to the data signal line 304. However, the source electrode 412 and the data signal line 304 may also be formed from a single conductive layer.

[0163] The drain electrode 413 is connected to the holding capacitor 420 and the liquid crystal element 311. It should be noted that the source electrode 412 and the drain electrode 413 sometimes switch functions depending on the relationship between the voltage supplied to the data signal line 304 and the voltage accumulated in the holding capacitor 420. That is, sometimes the source electrode 412 functions as the drain electrode, and the drain electrode 413 functions as the source electrode.

[0164] [Pixel structure of display device] Figure 30 This is a cross-sectional view showing the pixel structure of a display device 500 according to one embodiment of the present invention. The display device 500 uses the semiconductor device 10 described in the first embodiment as a switching element 410 included in the pixel circuit 301. In the following description, the configuration of the semiconductor device 10 is similar to... Figure 1 The semiconductor device 10 shown is the same, so detailed descriptions are omitted.

[0165] An insulating layer 360 is provided on the terminal electrode 171 of the semiconductor device 10. Acrylic resin can be used as an example for the insulating layer 360. A common electrode 370 shared by multiple pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. A silicon nitride layer can be used as an example for the insulating layer 380. Contact holes 381 are provided on the insulating layers 360 and 380. A pixel electrode 390 is provided on the insulating layer 380 and connected to the terminal electrode 171 via the contact holes 381.

[0166] The common electrode 370 and pixel electrode 390 use a transparent conductive layer. In this embodiment, ITO (Indium Tin Oxide) is used as the material constituting the transparent conductive layer of the common electrode 370 and pixel electrode 390, but other metal oxide layers can also be used. The common electrode 370 is composed of a plate-shaped transparent conductive layer. Although in Figure 30 Not shown in the diagram, but the pixel electrode 390 is composed of a comb-shaped transparent conductive layer consisting of a portion extending in the first direction and a portion extending in the second direction. The portion extending in the second direction is composed of multiple linear electrodes, each connected to an electrode corresponding to a trunk extending in the first direction.

[0167] A liquid crystal layer 311a is sealed between an active matrix substrate forming pixel electrodes 390 on a substrate 100 and an opposing substrate 320. The liquid crystal layer 311a is disposed across multiple pixels 51. The area where the liquid crystal layer 311a is disposed and... Figure 27 The liquid crystal area 52 shown corresponds to this.

[0168] like Figure 30 As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 when viewed from above, and a non-overlapping region that does not overlap with the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a lateral electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This lateral electric field causes the liquid crystal molecules contained in the liquid crystal layer 311a to move, thereby determining the grayscale of light passing through the pixel 51.

[0169] The embodiments described above as embodiments of the present invention (including variations thereof) can be appropriately combined and implemented as long as they do not contradict each other. Furthermore, solutions obtained by adding, deleting, or designing constituent elements based on the embodiments, or solutions obtained by adding, omitting, or changing processes or conditions, are also included within the scope of the present invention, provided they possess the spirit of the present invention.

[0170] Even if other effects are different from those achieved through the above-described embodiments, if they are effects that are clearly known from the description in this specification or that can be easily predicted by those skilled in the art, they shall of course be understood as effects achieved through the present invention.

Claims

1. A semiconductor device, comprising: Gate electrode above an insulating surface; The gate insulating layer above the gate electrode; The oxide semiconductor layer above the gate insulating layer; The first insulating layer above the oxide semiconductor layer; and The first patterned layer composed of insulating material above the first insulating layer, The oxide semiconductor layer has a channel portion and a conductive portion. Viewed from above, the first pattern layer overlaps with the channel portion.

2. The semiconductor device of claim 1, wherein, Viewed from above, the outer edge of the portion of the first patterned layer that overlaps with the oxide semiconductor layer coincides with the outer edge of the channel portion.

3. The semiconductor device as claimed in claim 1, wherein, The channel portion and the conductive portion are continuously arranged in the first direction. Viewed from above, the first patterned layer intersects the oxide semiconductor layer in a second direction that intersects the first direction.

4. The semiconductor device of claim 1, wherein, The first patterned layer is composed of an insulating material containing silicon.

5. The semiconductor device of claim 1, wherein, The thickness of the first insulating layer is less than 200 nm.

6. The semiconductor device of claim 1, wherein, The first insulating layer is connected to the oxide semiconductor layer.

7. The semiconductor device of claim 6, wherein, The first insulating layer comprises one selected from silicon oxide, silicon oxide nitride, or silicon nitride oxynitride.

8. The semiconductor device of claim 1, further comprising a terminal electrode disposed on the first insulating layer and electrically connected to the conductive portion.

9. The semiconductor device of claim 1, wherein, An aluminum-containing metal oxide layer is also included between the first insulating layer and the first patterned layer.

10. The semiconductor device of claim 1, wherein, A second patterned layer composed of metal oxides is also included between the first insulating layer and the first patterned layer.

11. The semiconductor device of claim 10, wherein, The second pattern layer has the same pattern shape as the first pattern layer.

12. The semiconductor device of claim 1, 9, or 10, further comprising: The second insulating layer above the first patterned layer; and Terminal electrodes disposed on the second insulating layer and electrically connected to the conductive portion.

13. The semiconductor device of claim 12, wherein, The second insulating layer comprises a silicon nitride layer.

14. The semiconductor device of claim 1, wherein, The oxide semiconductor layer has an LDD portion between the channel portion and the conductive portion.

15. The semiconductor device of claim 14, wherein, The LDD portion has a lower resistance value compared to the channel portion and a higher resistance value compared to the conductive portion.

16. The semiconductor device of claim 14, wherein, The position of the edge of the first pattern layer is consistent with the position of the edge of the channel portion in the LDD portion in the vertical direction.

17. The semiconductor device of claim 1, wherein, Between the gate insulating layer and the oxide semiconductor layer, there is also an aluminum-containing metal oxide layer that is in contact with the oxide semiconductor layer.

18. The semiconductor device of claim 17, wherein, The metal oxide layer has the same pattern shape as the oxide semiconductor layer.

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