Semiconductor device and display device

Abstract

The reliability of a semiconductor device including an oxide semiconductor is improved. The semiconductor device includes: a gate electrode over an insulating surface; a gate insulating layer over the gate electrode; an oxide semiconductor layer over the gate insulating layer; a first insulating layer on the oxide semiconductor layer; and a pattern layer comprising a metal oxide on the first insulating layer, the oxide semiconductor layer having a channel portion and a conductive portion, and the pattern layer overlapping the channel portion in plan view.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. Background Technology

[0002] In recent years, oxide semiconductors have been gaining attention as a material to replace amorphous silicon, polycrystalline silicon, and monocrystalline silicon in semiconductor devices. In particular, the development of thin-film transistors (TFTs) that use oxide semiconductors as channels is underway (e.g., Patent Documents 1-6). Like semiconductor devices using amorphous silicon as channels, TFTs using oxide semiconductors as channels can be fabricated with a simple structure and low-temperature processes. It is known that TFTs using oxide semiconductors as channels have higher field-effect mobility than TFTs using amorphous silicon as channels. Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-141338 Patent Document 2: Japanese Patent Application Publication No. 2014-099601 Patent Document 3: Japanese Patent Application Publication No. 2021-153196 Patent Document 4: Japanese Patent Application Publication No. 2018-006730 Patent Document 5: Japanese Patent Application Publication No. 2016-184771 Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the Invention

[0004] Previously, various device structures, including top-gate and bottom-gate structures, have been explored for thin-film transistors using oxide semiconductors. However, from a reliability perspective, several issues remain. For example, in conventional device structures, it is difficult to simultaneously ensure the withstand voltage characteristics of the gate insulating layer (specifically, its withstand capability relative to high voltages applied between the gate and source, or between the gate and drain) and suppress damage to the oxide semiconductor layer. Therefore, there is still room for improvement in the reliability of thin-film transistors using conventional oxide semiconductors.

[0005] One of the objectives of this invention is to improve the reliability of semiconductor devices comprising oxide semiconductors.

[0006] A semiconductor device according to one embodiment of the present invention includes: a gate electrode on an insulating surface; a gate insulating layer on the gate electrode; an oxide semiconductor layer on the gate insulating layer; a first insulating layer on the oxide semiconductor layer; and a patterned layer made of metal oxide on the first insulating layer, the oxide semiconductor layer having a channel portion and a conductive portion, wherein the patterned layer overlaps with the channel portion when viewed from above. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 2 This is a schematic top view illustrating the configuration of a semiconductor device in one embodiment of the present invention. Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 4 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 5 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 6 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 7 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 8 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 10 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 12 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 13 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 14 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 15 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 16 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 17 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 18 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 19 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 20 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 21 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 22 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 23 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 26 This is a schematic cross-sectional view showing the configuration of a semiconductor device in one embodiment of the present invention. Figure 27 This is a schematic top view showing the overall configuration of a display device according to one embodiment of the present invention. Figure 28 This is a block diagram illustrating the circuit configuration of a display device according to one embodiment of the present invention. Figure 29 This is a circuit diagram illustrating the configuration of the pixel circuit of a display device according to one embodiment of the present invention. Figure 30 This is a cross-sectional view showing the pixel configuration of a display device according to one embodiment of the present invention. Explanation of reference numerals in the attached figures 10-40, 10a, 10b, 20a, 20b… Semiconductor device, 51… Pixel, 52… Liquid crystal area, 54… Sealing area, 56… Terminal area, 100… Substrate, 105… Gate electrode, 108… Gate electrode, 110… Gate insulating layer, 120… Metal oxide layer, 130… Oxide semiconductor layer, 131… Channel portion, 131a… Edge, 132… Conductive portion, 134… LDD portion, 134a… Edge, 140… Insulating layer, 141… Contact hole, 150… Metal oxide layer, 151… Pattern layer, 151a… Edge, 161… Terminal electrode, 170… Insulating layer, 171… Contact hole, 181… Terminal electrode, 210… Anti-… Etching mask, 300…array substrate, 301…pixel circuit, 302…source driving circuit, 303…gate driving circuit, 304…data signal line, 305…scan signal line, 306…terminal portion, 307, 308…connection wiring, 310…sealing portion, 311…liquid crystal element, 311a…liquid crystal layer, 320…opposing substrate, 330…flexible printed circuit board, 340…chip, 360…insulating layer, 370…common electrode, 380…insulating layer, 381…contact hole, 390…pixel electrode, 410…switching element, 411…gate electrode, 412…source electrode, 413…drain electrode, 420…holding capacitor, 500…display device Detailed Implementation

[0008] The following is a reference to the appendix. Figure 1 Various embodiments of the present invention will be described below. The following disclosure is merely an example. Configurations readily conceived by those skilled in the art through appropriate modifications to the embodiments while maintaining the spirit of the invention are also included within the scope of the invention. To make the description clearer, the width, thickness, shape, etc., of various parts are sometimes schematically shown compared to the actual form. However, the shapes illustrated are merely examples and are not intended to limit the interpretation of the invention. In this specification and the figures, the same reference numerals are used for the same elements as those described with respect to the existing drawings, and detailed descriptions are appropriately omitted.

[0009] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for ease of explanation, the terms "up" or "below" are used, but it is also possible that, for example, the vertical relationship between the substrate and the oxide semiconductor layer is arranged in a manner opposite to that shown in the figures. In the following description, for example, this representation of the oxide semiconductor layer on the substrate is merely to illustrate the vertical relationship between the substrate and the oxide semiconductor layer as described above; other components may also be arranged between the substrate and the oxide semiconductor layer.

[0010] "Display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure that has other optical components (such as polarizing components, backlights, touch panels, etc.) mounted relative to the display unit. The "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer, provided that no technical inconsistencies arise. Therefore, regarding the embodiments described later, an organic EL display device including an organic EL layer is used as an example of a display device, but the structure in this embodiment can also be applied to liquid crystal display devices including liquid crystal layers, and other display devices including other electro-optical layers as described above.

[0011] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C," unless otherwise specified, do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these expressions do not preclude the possibility that α may contain other elements.

[0012] In this specification, "consistent" includes not only cases of complete consistency but also cases of substantial consistency. "Substantial consistency" refers to cases where, although not completely consistent, the consistency falls within a small range that can be considered consistent, such as cases within an error range of ±5% (preferably ±3%).

[0013] <First Embodiment> The semiconductor device of one embodiment of the present invention will be described using a thin-film transistor as an example. In addition to thin-film transistors used in display devices (e.g., organic EL display devices or liquid crystal display devices), the semiconductor devices shown in the following embodiments may also be integrated circuits (ICs) such as microprocessors (MPUs), or thin-film transistors used in memory circuits.

[0014] [Semiconductor Device Structure] The configuration of a semiconductor device 10 in one embodiment of the present invention will be described. Figure 1 This is a schematic cross-sectional view showing the configuration of a semiconductor device 10 in one embodiment of the present invention. Figure 2 This is a schematic top view illustrating the configuration of a semiconductor device 10 according to one embodiment of the present invention. Specifically, Figure 1 Corresponding to along Figure 2 The sectional view shown is cut by a single-dot dashed line represented by A-A'.

[0015] First, use Figure 1 Describe the cross-sectional structure of semiconductor device 10. For example... Figure 1As shown, a semiconductor device 10 is disposed above a substrate 100. The semiconductor device 10 includes a gate electrode 105, a gate insulating layer 110, an oxide semiconductor layer 130, an insulating layer 140, a patterning layer 151, and a terminal electrode 161.

[0016] A gate electrode 105 is disposed on the substrate 100. The gate electrode 105 functions as the gate of the semiconductor device 10 (thin-film transistor). Specifically, the gate electrode 105 applies a gate voltage to the channel portion 131 of the oxide semiconductor layer 130, which will be described later. An insulating layer (not shown) may also be disposed on the substrate 100. That is, the gate electrode 105 can be disposed directly or indirectly on the substrate 100. In other words, the gate electrode 105 is disposed on an insulating surface.

[0017] A gate insulating layer 110 is disposed on the substrate 100 and the gate electrode 105. The gate insulating layer 110 functions as a barrier film that shields impurities diffusing from the substrate 100 toward the oxide semiconductor layer 130, and as a base layer of the oxide semiconductor layer 130 disposed thereon.

[0018] Although the illustration is omitted, in conjunction with the functions described above, the gate insulating layer 110 is configured as a double-layer structure in this embodiment. Specifically, a silicon nitride layer is used as the insulating layer on the lower side (the side closer to the substrate 100), and a silicon oxide layer is used as the insulating layer on the upper side (the side closer to the oxide semiconductor layer 130). In this embodiment, the thickness of the lower insulating layer is 200 nm, and the thickness of the upper insulating layer is 100 nm, thereby the thickness of the gate insulating layer 110 is 300 nm. That is, in this embodiment, the thickness of the gate insulating layer 110 can be set to 200 nm or more (preferably 300 nm or more, more preferably 400 nm or more).

[0019] An oxide semiconductor layer 130 is disposed on the gate insulating layer 110. The oxide semiconductor layer 130 has a channel portion 131 and a conductive portion 132 that are continuous along a first direction. The channel portion 131 functions as the channel region of the semiconductor device 10. The conductive portion 132 functions as the source region or drain region of the semiconductor device 10. The conductive portion 132 is a region with a lower resistance than the channel portion 131 and has the function of transferring the carrier flowing in the channel portion 131 to the terminal electrode 161.

[0020] An insulating layer 140 is disposed on the oxide semiconductor layer 130. In this embodiment, a silicon oxide layer is used as the insulating layer 140. The insulating layer 140 is a dielectric layer that electrically insulates the layer on which the terminal electrode 161 (described later) is formed from the layer on which the oxide semiconductor layer 130 is formed. The thickness of the insulating layer 140 is 50 nm or more and 200 nm or less (preferably 50 nm or more and 150 nm or less, more preferably 50 nm or more and 100 nm or less). The thickness of the insulating layer 140 is thinner than the thickness of the gate insulating layer 110. The advantages of the thin thickness of the insulating layer 140 will be explained next.

[0021] A patterned layer 151 is disposed on top of the insulating layer 140. In this embodiment, the patterned layer 151 is made of a metal oxide. Specifically, the patterned layer 151 is obtained by patterning the metal oxide layer to form an isolated state. The patterned layer 151 functions as a barrier layer to suppress hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130. Although detailed descriptions will follow, the patterned layer 151 refers to the metal oxide layer 150 (see reference 140) used in the semiconductor device 10 manufacturing process when a heat treatment is performed to supply oxygen to the oxide semiconductor layer 130. Figure 6 The layer is obtained by patterning.

[0022] The patterned layer 151 is disposed above the oxide semiconductor layer 130, sandwiching the insulating layer 140. That is, the insulating layer 140 is in contact with both the oxide semiconductor layer 130 and the patterned layer 151. The patterned layer 151 overlaps with the channel portion 131 of the oxide semiconductor layer 130. More specifically, as... Figure 1 As shown by the dashed line, when viewed in cross-section, the position of the edge 151a of the pattern layer 151 and the position of the edge 131a of the channel portion 131 are aligned in the vertical direction. In other words, when viewed in cross-section, the position of the edge 151a of the pattern layer 151 and the position of the boundary between the channel portion 131 and the conductive portion 132 are aligned in the vertical direction. The reason for aligning the positions of the edge 151a of the pattern layer 151 and the edge 131a of the channel portion 131 will be explained below.

[0023] Terminal electrode 161 is disposed on insulating layer 140 and electrically connected to conductive portion 132 via contact hole 141 provided in insulating layer 140. Terminal electrode 161 has the function of supplying carrier to conductive portion 132 or removing carrier from conductive portion 132. That is, terminal electrode 161 functions as source electrode or drain electrode of semiconductor device 10 (thin-film transistor) depending on the function of conductive portion 132. Specifically, terminal electrode 161 functions as source electrode when the electrically connected conductive portion 132 functions as source region, and functions as drain electrode when the electrically connected conductive portion 132 functions as drain region.

[0024] In this embodiment, a bottom-gate transistor with a gate electrode 105 disposed below the oxide semiconductor layer 130 is exemplified as the semiconductor device 10, but it is not limited to this configuration. For example, it can also be disposed above the insulating layer 140 ( Figure 1 In the example shown, other gate electrodes are disposed above the pattern layer 151, thereby setting the semiconductor device 10 as a dual-gate transistor.

[0025] Next, use Figure 2 This describes the planar structure of semiconductor device 10. For example... Figure 2 As shown, the first direction (D1 direction) is the direction in which the two terminal electrodes 161 are connected to each other (the direction in which the channel portion 131 and the conductive portion 132 are continuous), corresponding to the direction of carrier movement. The length of the channel portion 131 in the oxide semiconductor layer 130 in the first direction is the channel length (L), and the length of the channel portion 131 in the second direction (D2 direction) is the channel width (W). Furthermore, the second direction is a direction that intersects the first direction. In this embodiment, the second direction represents a direction orthogonal to the first direction, but depending on the layout of the oxide semiconductor layer 130, there may also be a case where the first direction and the second direction are not orthogonal.

[0026] In this embodiment, in the first direction, the width of the gate electrode 105 is greater than the length (channel length) of the channel portion 131. The reason for this configuration is to effectively prevent external light from entering the channel portion 131. However, it is not limited to this example; the width of the gate electrode 105 may also be the same as the length of the channel portion 131.

[0027] like Figure 2 As shown, when viewed from above, the patterned layer 151, made of metal oxide, is arranged to overlap with the oxide semiconductor layer 130. Specifically, when viewed from above, the patterned layer 151 is arranged to intersect with the channel portion 131 of the oxide semiconductor layer 130. Preferably, the width of the patterned layer 151 in the second direction is larger than the width (W) of the oxide semiconductor layer 130 in the second direction. This configuration is effective in maximizing the function of the patterned layer 151 described above (suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130).

[0028] Furthermore, when viewed from above, the outer edge of the portion of the patterned layer 151 that overlaps with the oxide semiconductor layer 130 coincides with the outer edge of the channel portion 131. In other words, the patterned layer 151 intersects with the channel portion 131 but does not overlap with the conductive portion 132. However, this "intersection of the patterned layer 151 and the channel portion 131 without overlapping with the conductive portion 132" includes the possibility that the patterned layer 151 overlaps with a portion of the conductive portion 132 within a margin of error. As will be described later, the conductive portion 132 is formed by adding impurities relative to the oxide semiconductor layer 130 using methods such as ion implantation. Therefore, due to the wrapping of impurities under the patterned layer 151, it is possible that a portion of the conductive portion 132 slightly overlaps with the patterned layer 151.

[0029] Figure 2 The example given illustrates a configuration in which the terminal electrode 161 does not overlap with the gate electrode 105 when viewed from above, but is not limited to this configuration. For example, it is also possible that, when viewed from above, both or one of the two terminal electrodes 161 overlap with the gate electrode 105.

[0030] [Materials of each layer in a semiconductor device] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate with light transmittance, such as a glass substrate, quartz substrate, or sapphire substrate, can be used as the substrate. Alternatively, a rigid substrate without light transmittance, such as a silicon substrate, can also be used. Furthermore, a flexible substrate with light transmittance, such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate, can be used as the substrate. To improve the heat resistance of the substrate 100, impurities can be introduced into the aforementioned resin substrates. In addition, a substrate on which a silicon oxide film or a silicon nitride film is formed on the aforementioned rigid or flexible substrate can also be used as the substrate 100.

[0031] As described above, the gate electrode 105 has an area larger than the channel portion 131 of the oxide semiconductor layer 130, and therefore it is preferable to use a material capable of shielding external light incident on the channel portion 131. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds of these elements, can be used as the gate electrode 105. The gate electrode 105 can be a single-layer structure or a multilayer structure.

[0032] As the gate insulating layer 110, silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon oxynitride (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum oxynitride (AlNxOy), and aluminum nitride (AlNx) can be used, for example. Here, silicon oxynitride (SiOxNy) and aluminum oxynitride (AlOxNy) are silicon and aluminum compounds, respectively, in which the proportion of nitrogen (N) (x>y) is less than that of (O). In addition, silicon oxynitride (SiNxOy) and aluminum oxynitride (AlNxOy) are silicon and aluminum compounds, respectively, in which the proportion of oxygen (x>y) is less than that of nitrogen. In this embodiment, the gate insulating layer 110 is configured as a double-layer structure, with a silicon nitride layer used as the lower insulating layer and a silicon oxide layer used as the upper insulating layer.

[0033] The oxide semiconductor layer 130 can have an amorphous structure or a polycrystalline structure.

[0034] The insulating layer 140 comprises an oxide with insulating properties. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), etc., can be used as the insulating layer 140. In this embodiment, a silicon oxide layer with a thickness of 50 nm to 200 nm (preferably 50 nm to 150 nm, more preferably 50 nm to 100 nm) is used as the insulating layer 140.

[0035] The pattern layer 151 is composed of a metal oxide. In this embodiment, an oxide with aluminum as the main component (e.g., aluminum oxide) is used as the metal oxide constituting the pattern layer 151. Aluminum oxide has high barrier properties against gases, thereby the pattern layer 151 has the function of mitigating hydrogen diffusion into the channel portion 131 of the oxide semiconductor layer 130. The thickness of the pattern layer 151 can be set, for example, to 5 nm or more but less than 100 nm, 5 nm or more but less than 50 nm, 5 nm or more but less than 30 nm, or 7 nm or more but less than 15 nm.

[0036] Terminal electrode 161 is conductive. Materials used for terminal electrode 161 include, for example, copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys or compounds of these elements. Terminal electrode 161 can be a single-layer structure or a multilayer structure.

[0037] [Semiconductor device manufacturing methods] Next, a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described. Figure 3This is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 4 to 12 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention.

[0038] like Figure 3 as well as Figure 4 As shown, a gate electrode 105 is formed on the substrate 100, and a gate insulating layer 110 is formed on the gate electrode 105. Figure 4 (Step S1001). As the gate insulating layer 110, for example, a stacked structure of a silicon nitride layer and a silicon oxide layer is formed. The gate insulating layer 110 is formed by CVD (Chemical Vapor Deposition). In this specification, although the situation of forming a film on a substrate by methods such as sputtering and CVD is sometimes expressed as "forming a thin film", it is used in the same sense as "forming a thin film".

[0039] When a silicon nitride layer is provided on the side of the gate insulating layer 110 closer to the substrate 100, it can block impurities that diffuse from the substrate 100 side toward the oxide semiconductor layer 130. When a silicon oxide layer is provided on the side of the gate insulating layer 110 in contact with the subsequently formed oxide semiconductor layer 130, the characteristics of the interface between the gate insulating layer 110 and the oxide semiconductor layer 130 are improved.

[0040] By setting the film-forming temperature of the silicon oxide layer to a relatively low level, the oxygen content can be increased. As will be described later, by increasing the oxygen content contained in the gate insulating layer 110, the amount of oxygen diffusing into the oxide semiconductor layer 130 can be reduced. Furthermore, the film-forming temperature of the gate insulating layer 110 can be set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, more preferably 325°C or higher and 400°C or lower).

[0041] Next, as Figure 3 as well as Figure 5 As shown, a patterned oxide semiconductor layer 130 is formed on the gate insulating layer 110. Figure 3 Step S1002). In this embodiment, the process of forming the oxide semiconductor layer 130 is referred to as "OS patterning". That is, the oxide semiconductor layer 130 is formed by performing patterning processing on the oxide semiconductor layer deposited on the gate insulating layer 110. In the description of this embodiment, the case where it is referred to as "oxide semiconductor layer" without reference numerals refers to the oxide semiconductor layer in the state where film deposition has been performed (that is, in the state without processing).

[0042] Etching of oxide semiconductor layers can be done using either wet etching or dry etching. In wet etching, acidic etchants (oxalic acid or hydrofluoric acid) can be used, for example.

[0043] In this embodiment, the oxide semiconductor layer is formed by sputtering. The thickness of the oxide semiconductor layer to be formed is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm.

[0044] If a thin film is formed relative to a substrate by sputtering, ions generated in the plasma and atoms bounced off the sputtering target will collide with the object being formed (specifically, the structure formed on the substrate 100), thereby causing the temperature of the substrate to rise during the thin film formation process.

[0045] To control the substrate temperature (i.e., film formation temperature) during the formation of the oxide semiconductor layer, thin film formation can be performed while the substrate is being cooled. For example, the substrate can be cooled from the side opposite to the surface being formed, such that the film formation temperature is below 100°C, 70°C, 50°C, or 30°C. In particular, the film formation temperature of the oxide semiconductor layer in this embodiment is preferably below 50°C. In this embodiment, the temperature difference between the temperature during oxide semiconductor layer formation and the temperature during OS annealing of the oxide semiconductor layer 130 is preferably 350°C or higher.

[0046] Next, after the oxide semiconductor layer 130 is formed by patterning, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 130. Figure 3 Step S1003). In OS annealing, the oxide semiconductor layer 130 is subjected to heat treatment in an atmospheric gas at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C). The heating environment gas is not limited to atmospheric gas, but is preferably an oxidizing environment gas (an environment gas containing oxygen). In addition, the heat treatment time is 15 minutes to 120 minutes or 30 minutes to 60 minutes after the specified temperature is reached.

[0047] In this embodiment, a substrate with an oxide semiconductor layer 130 is placed in a furnace containing a heating medium (e.g., a support plate) that is pre-maintained at a set temperature (250°C to 500°C). The support plate, as the heating medium, serves to support the substrate and heat the substrate and the cover film formed on it (including the oxide semiconductor layer 130). When the substrate with the oxide semiconductor layer 130 is placed on the support plate, the oxide semiconductor layer 130 is rapidly heated. When the substrate is placed in the furnace, it is desirable to suppress the temperature drop of the support plate to within 15%, 10%, or 5% of the set temperature. Preferably, the temperature of the support plate is controlled in such a way that the oxide semiconductor layer 130 reaches the set temperature in a very short time.

[0048] Next, as Figure 3 as well as Figure 6 As shown, an insulating layer 140 and a metal oxide layer 150 are formed. Figure 3 (Step S1004). As the insulating layer 140, for example, a silicon oxide layer is formed. The insulating layer 140 is formed by CVD. The thickness of the insulating layer 140 is, for example, 50 nm to 200 nm, 50 nm to 150 nm, or 50 nm to 100 nm. In this embodiment, the thickness of the insulating layer 140 is set to 100 nm.

[0049] The metal oxide layer 150 is formed by sputtering. By using sputtering to form the metal oxide layer 150, oxygen is introduced into the insulating layer 140 during the formation of the metal oxide layer 150. Therefore, the insulating layer 140 after the formation of the metal oxide layer 150 contains a large amount of oxygen. The thickness of the metal oxide layer 150 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 150. As described above, aluminum oxide has high barrier properties against gases, thereby suppressing the upward diffusion of oxygen introduced into the insulating layer 140 during the heat treatment described later.

[0050] When the metal oxide layer 150 is formed by sputtering, the process gas used for sputtering may remain in the film of the metal oxide layer 150. For example, if Ar is used as the sputtering process gas, Ar may sometimes remain in the film of the metal oxide layer 150. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis relative to the metal oxide layer 150. That is, when Ar is used as the sputtering process gas, Ar can be detected by SIMS analysis relative to the patterned layer 151 obtained by patterning the metal oxide layer 150.

[0051] Next, with the metal oxide layer 150 formed on the insulating layer 140, a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 130 is performed. Figure 3 (Step S1005). During the process from forming the oxide semiconductor layer 130 to forming the insulating layer 140 on the oxide semiconductor layer 130, oxygen deficiency may occur on the upper surface and side surfaces of the oxide semiconductor layer 130. By oxidation annealing, oxygen released from the gate insulating layer 110 and the insulating layer 140 is supplied to the oxide semiconductor layer 130 to repair the oxygen deficiency. Oxidation annealing can be performed at a temperature of 250°C to 500°C (preferably 300°C to 500°C, more preferably 350°C to 450°C).

[0052] Oxygen released from the gate insulating layer 110 and the insulating layer 140 is supplied to the oxide semiconductor layer 130 through oxidation annealing. In the case where a silicon nitride layer is used for a portion of the gate insulating layer 110, hydrogen may sometimes be released from the gate insulating layer 110 through the oxidation annealing described above, but almost all of the released hydrogen is captured by oxygen contained in the silicon oxide layer disposed on the upper side before reaching the oxide semiconductor layer 130.

[0053] As described above, oxygen can be supplied to the oxide semiconductor layer 130 through oxidation annealing. During oxidation annealing, the upward diffusion of oxygen into the insulating layer 140 is blocked by the metal oxide layer 150, thereby suppressing its release into the atmosphere. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during oxidation annealing.

[0054] Next, as Figure 3 as well as Figure 7 As shown, a resist mask 210 is formed on the metal oxide layer 150. Figure 3 Step S1006). The resist mask 210 is configured to overlap with the oxide semiconductor layer 130. As described later, the portion of the oxide semiconductor layer 130 that overlaps with the resist mask 210 corresponds to the portion where the channel portion 131 is formed. Figure 2 As shown, the resist mask 210 is configured to intersect with the oxide semiconductor layer 130 in the second direction.

[0055] Next, as Figure 3 as well as Figure 8 As shown, the metal oxide layer 150 is etched and a patterned layer 151 composed of metal oxide is formed by using a resist mask 210 as a mask. Figure 3(Step S1007). The etching of the metal oxide layer 150 can be either wet etching or dry etching.

[0056] Next, as Figure 3 as well as Figure 9 As shown, ion implantation is performed above the resist mask 210, adding impurities relative to the oxide semiconductor layer 130. Figure 3 (Step S1008). Phosphorus, boron, argon, etc., can be used as impurities. The purpose of adding impurities is to improve conductivity by creating oxygen deficiencies in a region relative to a portion of the oxide semiconductor layer 130. Therefore, elements with large atomic radii are preferably used as impurities. In this embodiment, an example of adding impurities by ion implantation is shown, but ion doping can also be used. In this embodiment, boron is added by ion implantation. The ion implantation conditions in this embodiment are an accelerating voltage of 30 keV and a supply amount of 1 × 10⁻⁶ kJ / L. 15 / cm 2 However, this is not the only example.

[0057] like Figure 9 As shown, if ion implantation of impurities is performed into the oxide semiconductor layer 130, a conductive portion 132 is formed in the oxide semiconductor layer 130. At this time, the region that remains in its original state without impurity implantation functions as a channel portion 131. That is, when viewed in cross-section, the positions of the edges of the resist mask 210 and the pattern layer 151 are aligned with the positions of the edges of the channel portion 131 in the vertical direction.

[0058] Impurities are added via insulating layer 140 relative to conductive portion 132. Conductive portion 132 functions as the source or drain region of semiconductor device 10 as described above.

[0059] In this embodiment, the insulating layer 140 does not need to be used as a gate insulating layer, thereby allowing the thickness to be set to 50 nm to 200 nm (preferably 50 nm to 150 nm, more preferably 50 nm to 100 nm). Furthermore, the metal oxide layer 150 is removed from the area directly below the resist mask 210, thus exposing the insulating layer 140. That is, impurities can be added to the oxide semiconductor layer 130 without passing through a metal oxide layer, which has high barrier properties against gases. Thus, in this embodiment, the thickness of the insulating layer 140 can be reduced, and a fine metal oxide layer does not need to pass through, thereby increasing the impurity supply even at relatively low accelerating voltages. In other words, the manufacturing apparatus used for impurity addition is not subjected to excessive strain, and a sufficient amount of impurities can be added to the oxide semiconductor layer 130, thereby sufficiently reducing the resistance value of the conductive portion 132.

[0060] Next, as Figure 3 as well as Figure 10 As shown, the resist mask 210 is removed. Figure 3 (Step S1009). By removing the resist mask 210, a patterned layer 151 composed of metal oxides remains on the insulating layer 140.

[0061] Next, as Figure 3 as well as Figure 11 As shown, a contact hole 141 is formed in the insulating layer 140. Figure 3 (Step S1010). The contact hole 141 exposes a portion of the conductive portion 132. At this time, in this embodiment, the metal oxide layer 150 located directly above the conductive portion 132 is removed, thereby having the advantage that the contact hole 141 is easy to form.

[0062] Finally, as Figure 3 as well as Figure 12 As shown, a terminal electrode 161 is formed on the conductive portion 132 exposed through the contact hole 141. Figure 3 Step S1011). Through the procedures described above, the process is completed. Figure 1 The semiconductor device 10 shown.

[0063] In this embodiment, the semiconductor device 10 can use an insulating layer with a thickness of 200 nm or more (preferably 300 nm or more) as the gate insulating layer 110, thereby sufficiently ensuring the withstand voltage characteristics of the gate insulating layer. Furthermore, when the conductive portion 132 is formed in the oxide semiconductor layer 130, low resistance is achieved by adding impurities through the insulating layer 140, thereby suppressing damage to the oxide semiconductor layer 130 (especially damage to the channel portion 131). Since the film thickness of the insulating layer 140 is 200 nm or less (preferably 150 nm or less), a sufficient amount of impurities is added while suppressing the load on the impurity addition device, thereby sufficiently reducing the resistance value of the conductive portion 132. As described above, according to this embodiment, the reliability of the semiconductor device 10 containing the oxide semiconductor can be improved.

[0064] In this specification, "field-effect mobility" means the field-effect mobility in the saturation region of semiconductor device 10, which is the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source and drain is greater than the value obtained by subtracting the threshold voltage (Vth) of semiconductor device 10 from the voltage supplied to the gate (Vg).

[0065] (Modification 1 of the first embodiment) In the semiconductor device 10 described above, an example is shown in which the metal oxide layer 150 is etched to form a patterned layer 151 made of metal oxide, but it is also possible to leave the metal oxide layer 150 intact without etching it.

[0066] Figure 13 This is a schematic cross-sectional view showing the configuration of a semiconductor device 10a in a modified embodiment of the present invention. In this modified example, the semiconductor device 10a has a metal oxide layer 150 remaining on the insulating layer 140 without patterning. That is, the metal oxide layer 150 overlaps with the channel portion 131 of the oxide semiconductor layer 130 and also overlaps with the conductive portion 132.

[0067] In the semiconductor device 10a of this modified example, the metal oxide layer 150 and Figure 1 Similarly, the patterned layer 151 shown also functions as a barrier layer to suppress hydrogen diffusion from above into the oxide semiconductor layer 130.

[0068] (Modification 2 of the first embodiment) In the semiconductor device 10 described above, an example is shown in which the metal oxide layer 150 is etched to form a patterned layer 151 made of metal oxide, but it is also possible to remove the metal oxide layer 150 by etching without patterning it.

[0069] Figure 14 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 10b in a modified embodiment of the present invention. The semiconductor device 10b in this modified embodiment... Figure 3 After the oxidation annealing shown in step S1005, the metal oxide layer 150 formed on the insulating layer 140 is etched and completely removed. That is, in this modified example, the metal oxide layer 150 and the pattern layer 151 composed of metal oxide do not exist on the insulating layer 140.

[0070] According to this variation, in Figure 3 In the impurity addition process to the oxide semiconductor layer 130 shown in S1008, even with a low accelerating voltage, the supply amount of the added impurities can be sufficiently increased. Furthermore, according to this modified example, Figure 3 The formation of the contact hole 141 of the insulating layer 140 shown in S1010 is easy.

[0071] <Second Embodiment> In this embodiment, a semiconductor device 20 with a layer structure different from that of the semiconductor device 10 in the first embodiment is described. In the description of this embodiment, the same reference numerals are sometimes used to indicate the same elements as in the first embodiment, and the description is omitted.

[0072] [Semiconductor Device Structure] Figure 15 This is a schematic cross-sectional view showing the configuration of a semiconductor device 20 according to one embodiment of the present invention. Figure 1 The semiconductor device 10 shown is different in that an insulating layer 170 is provided on the insulating layer 140 and the patterned layer 151 made of metal oxide, and a terminal electrode 181 is provided on the insulating layer 170.

[0073] In this embodiment, insulating layers 140 and 170 are used to insulate the oxide semiconductor layer 130 from the terminal electrode 181. Insulating layer 170 can be selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or silicon oxynitride (SiOxNy). Alternatively, insulating layer 170 can also be made of resin materials such as acrylic or polyimide. Furthermore, insulating layer 170 can be a single-layer structure comprising layers made of the aforementioned materials, or it can be a multilayer structure.

[0074] Terminal electrode 181 is electrically connected to conductive portion 132 of oxide semiconductor layer 130 via contact hole 171 formed in a laminated structure composed of insulating layer 140 and insulating layer 170. In this embodiment, the layer formed of terminal electrode 181 and the layer formed of oxide semiconductor layer 130 are separated by a distance equal to the combined thickness of insulating layers 140 and 170. Therefore, it has the advantage of high insulation between the layer formed of terminal electrode 181 and the layer formed of oxide semiconductor layer 130.

[0075] The other effects of the semiconductor device 20 in this embodiment are the same as those of the semiconductor device 10 in the first embodiment.

[0076] [Semiconductor device manufacturing methods] Next, a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention will be described. Figure 16 This is a flowchart illustrating a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention. Figures 17-19 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 20 according to one embodiment of the present invention.

[0077] The method for manufacturing the semiconductor device 20 in this embodiment up to the first embodiment. Figure 3 Up to steps S1001 to S1009, the manufacturing process is the same as that described in the first embodiment. The difference between the manufacturing method of this embodiment and the manufacturing method of the first embodiment lies in the substitution... Figure 3 The steps S1010 and S1011 shown include Figure 16Steps S1110 to S1112 are shown.

[0078] Similar to the first embodiment, in the process of... Figure 3 After removing the resist mask 210 in steps S1001 to S1009, as follows: Figure 16 as well as Figure 17 As shown, an insulating layer 170 is formed on the insulating layer 140 and the patterned layer 151 made of metal oxide. Figure 16 (Step S1110). The material constituting the insulating layer 170 can be any material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxynitride (SiOxNy), or resin, as described above.

[0079] In this embodiment, the insulating layer 170 is formed using a CVD method, comprising a silicon oxide layer and a silicon nitride layer in a stacked structure. The thickness of the insulating layer 170 can be set to, for example, 30 nm to 500 nm. In this embodiment, the thickness of the lower silicon oxide layer is 100 nm, and the thickness of the upper silicon nitride layer is 300 nm. That is, the thickness of the insulating layer 170 in this embodiment is 400 nm. However, the thickness of the insulating layer 170 is not limited to this example; it can be thicker or thinner.

[0080] The film-forming temperature of the insulating layer 170 is preferably set to 250°C or higher and 500°C or lower (preferably 300°C or higher and 450°C or lower, more preferably 325°C or higher and 400°C or lower).

[0081] The insulating layer 170 functions as a protective layer to prevent gas and moisture from penetrating from the outside. Additionally, as described above, it also serves to insulate and separate the terminal electrode 181 from the conductive portion 132 of the oxide semiconductor layer 130. Furthermore, in this embodiment, since a silicon nitride layer is used for a portion of the insulating layer 170, it contributes to reducing the resistance of the conductive portion 132.

[0082] When a silicon nitride layer is formed by CVD, ammonia is used as the feed gas, resulting in a silicon nitride layer containing a large amount of hydrogen. Therefore, during and after the formation of the insulating layer 170, hydrogen diffuses from the silicon nitride layer by heating the insulating layer 170. The diffused hydrogen reaches the conductive portion 132 via the silicon oxide layer below the insulating layer 170 and the insulating layer 140. At this time, the hydrogen is captured in the oxygen-deficient sites inside the conductive portion 132 formed by the aforementioned ion implantation, forming a donor level. This contributes to the low resistance of the conductive portion 132. In this case, the patterned layer 151 made of metal oxide functions as a barrier layer to suppress the movement of hydrogen diffusing from the insulating layer 170 toward the channel portion 131 of the oxide semiconductor layer 130.

[0083] Next, as Figure 16 as well as Figure 18 As shown, a contact hole 171 is formed in the laminated structure consisting of insulating layer 140 and insulating layer 170. Figure 16 (Step S1111). Contact hole 171 exposes a portion of conductive portion 132. In this embodiment, similar to the first embodiment, since the metal oxide layer 150 located directly above conductive portion 132 is removed, it has the advantage that the contact hole 171 is easy to form.

[0084] Finally, as Figure 16 as well as Figure 19 As shown, a terminal electrode 181 is formed on the conductive portion 132 exposed through the contact hole 171. Figure 16 Step S1112). Through the procedures described above, the process is completed. Figure 15 The semiconductor device 20 shown.

[0085] (Modification 1 of the second embodiment) In the semiconductor device 20 described above, an example is shown in which the metal oxide layer 150 is etched to form a pattern layer 151 made of metal oxide, but it is also possible to leave the metal oxide layer 150 intact without etching it.

[0086] Figure 20 This is a schematic cross-sectional view showing the configuration of a semiconductor device 20a in a modified embodiment of the present invention. In this modified example, the semiconductor device 20a has a metal oxide layer 150 remaining on the insulating layer 140 without patterning. That is, the metal oxide layer 150 also overlaps with the conductive portion 132 on the basis of the channel portion 131 of the oxide semiconductor layer 130.

[0087] In the semiconductor device 20a of this modified example, the metal oxide layer 150 and Figure 15Similarly, the patterned layer 151 shown also functions as a barrier layer to suppress hydrogen diffusion from above into the oxide semiconductor layer 130.

[0088] (Modification 2 of the second embodiment) In the semiconductor device 20 described above, an example is shown in which the metal oxide layer 150 is etched to form a patterned layer 151 made of metal oxide, but it is also possible to remove the metal oxide layer 150 by etching without patterning it.

[0089] Figure 21 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 20b in a modified embodiment of the present invention. The semiconductor device 20b in this modified embodiment... Figure 16 After the oxidation annealing shown in step S1005, the metal oxide layer 150 formed on the insulating layer 140 is etched and completely removed. That is, in this modified example, the metal oxide layer 150 and the pattern layer 151 composed of metal oxide do not exist on the insulating layer 140.

[0090] According to this variation, in Figure 16 In the impurity addition process to the oxide semiconductor layer 130 shown in S1008, even with a low accelerating voltage, the supply amount of the added impurities can be sufficiently increased. Furthermore, according to this modified example, Figure 16 The contact hole 171 shown in S1111 is easy to form in the laminated structure of insulating layer 140 and insulating layer 170.

[0091] <Third Embodiment> In this embodiment, a semiconductor device 30 with an oxide semiconductor layer 130 structure different from that of the semiconductor device 10 in the first embodiment will be described. In the description of this embodiment, the same reference numerals are sometimes used to indicate the same elements as in the first embodiment, and the description is omitted.

[0092] [Semiconductor Device Structure] Figure 22 This is a schematic cross-sectional view showing the configuration of a semiconductor device 30 according to one embodiment of the present invention. Figure 1 The difference in the semiconductor device 10 shown is that an LDD section 134 is provided in the oxide semiconductor layer 130. "LDD" is an abbreviation for "Light Doped Drain." That is, the LDD section 134 refers to the portion whose resistance is lower than that of the channel section 131 and higher than that of the conductive section 132. For example... Figure 22As shown, the LDD portion 134 is disposed between the channel portion 131 and the conductive portion 132. That is, in this embodiment, the oxide semiconductor layer 130 is configured as the channel portion 131, the LDD portion 134 and the conductive portion 132 are continuous in the first direction.

[0093] The patterned layer 151, made of metal oxide, overlaps with the channel portion 131 and the conductive portion 132. In this embodiment, when viewed in cross-section, the position of the edge 151a of the patterned layer 151 and the position of the edge 134a of the LDD portion 134 are aligned vertically. In other words, when viewed in cross-section, the position of the edge 151a of the patterned layer 151 and the position of the boundary between the LDD portion 134 and the conductive portion 132 are aligned vertically. Thus, in this embodiment, in the first direction, the width of the patterned layer 151 is greater than the width of the channel portion 131, which is effective in maximizing the function of the patterned layer 151 (the function of suppressing hydrogen diffusion from above into the channel portion 131 of the oxide semiconductor layer 130). However, this configuration is not limited to this; the patterned layer 151 may not overlap with the LDD portion 134.

[0094] The other effects of the semiconductor device 30 in this embodiment are the same as those of the semiconductor device 10 in the first embodiment.

[0095] [Semiconductor device manufacturing methods] Next, a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention will be described. Figure 23 This is a flowchart illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention. Figures 24-25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 30 according to one embodiment of the present invention.

[0096] The method for manufacturing the semiconductor device 30 in this embodiment is described in the first embodiment. Figure 3 Up to steps S1001 to S1008, the manufacturing process is the same as that described in the first embodiment. The difference between the manufacturing method of this embodiment and the manufacturing method of the first embodiment lies in that... Figure 3 Between steps S1008 and S1009, the following was added: Figure 23 The steps S1201 and S1202 are shown.

[0097] First, similar to the first embodiment, by Figure 3 In steps S1001 to S1008, impurities are added to the oxide semiconductor layer 130 to form a conductive portion 132. Next, as... Figure 23 as well as Figure 24 As shown, in an oxygen-rich environment, the resist mask 210 is ashed ( Figure 23 (Step S1201). By performing an ashing process, the width of the resist mask 210 in the first direction is narrowed, exposing a portion of the patterned layer 151 composed of metal oxides.

[0098] Next, as Figure 23 as well as Figure 25 As shown, ion implantation is performed above the resist mask 210, and a second impurity addition is performed relative to the oxide semiconductor layer 130. Figure 23 Step S1202). The added impurities are used in conjunction with... Figure 23 In step S1008, the same impurities (phosphorus, boron, argon, etc.) can be added.

[0099] The conditions for ion implantation can be related to Figure 23 Step S1008 can be the same or different. In this embodiment, the accelerating voltage is set to 30keV and the supply is set to 1×10 13 / cm 2 .like Figure 25 As shown, in this embodiment, an LDD portion 134 is formed at the end of the channel portion 131 in the first direction (the portion that does not overlap with the resist mask 210) by a second impurity addition. At this time, impurities are added to the LDD portion 134 via the pattern layer 151 and the insulating layer 140, so that even if impurities are added under the same conditions as in step S1008, the amount of impurities added is less than that of the conductive portion 132. That is, the resistance value of the LDD portion 134 is higher than that of the conductive portion 132.

[0100] After the LDD section 134 is formed through the above processes, Figure 23 The process is completed by steps S1009 to S1011 as shown. Figure 22 The semiconductor device 30 shown. Steps S1009 to S1011 are the same as those described in the first embodiment.

[0101] (A variation of the third embodiment) In the aforementioned semiconductor device 30, it is shown that after ashing treatment relative to the resist mask 210, the patterned layer 151 made of metal oxide is not processed, but instead... Figure 25 The illustrated process is an example, but the resist mask 210 can also be used as a mask to remove a portion of the pattern layer 151. That is, Figure 24 Alternatively, the resist mask 210 can be used as a mask to etch the ends of the pattern layer 151, removing the portion exposed from the resist mask 210.

[0102] In this modified example, Figure 25In the process shown, impurities were added to the LDD section 134 via the insulating layer 140. That is, the pattern layer 151 did not overlap with the LDD section 134; therefore, if compared with... Figure 23 If impurities are added under the same conditions as in S1008, LDD portion 134 will not be formed, but conductive portion 132 will be formed. Therefore, in this modified example, it is preferable that when the second impurity is added ( Figure 23 In step S1202), the accelerating voltage and the supply amount are adjusted in accordance with the first impurity addition process. Figure 23 Compared to step S1008, the amount of impurities added to the LDD section 134 is appropriately controlled.

[0103] <Fourth Implementation> In the first embodiment, an example is shown where the oxide semiconductor layer 130 is provided in contact with the gate insulating layer 110, but a metal oxide layer may also be provided between the gate insulating layer 110 and the oxide semiconductor layer 130. In the description of this embodiment, the same reference numerals are sometimes used to indicate the same elements as in the first embodiment, and the description is omitted.

[0104] Figure 26 This is a schematic cross-sectional view showing the configuration of a semiconductor device 40 according to one embodiment of the present invention. Basic structure and... Figure 1 The semiconductor device 10 shown is similar, but in this embodiment, the semiconductor device 40 has a metal oxide layer 120 disposed between the gate insulating layer 110 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 120 uses a metal oxide with aluminum as the main component (specifically, an aluminum oxide (AlOx) layer). The metal oxide layer 120 can be formed, for example, by sputtering.

[0105] like Figure 26 As shown, in this embodiment, the metal oxide layer 120 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, during execution... Figure 3 After step S1001, the metal oxide layer 120 and the oxide semiconductor layer 130 are continuously deposited. Then, the following steps are performed: Figure 3 In steps S1002 and S1003, an oxide semiconductor layer 130 is obtained. Furthermore, by etching the oxide semiconductor layer 130 and the metal oxide layer 120, a metal oxide layer 120 having the same pattern shape as the oxide semiconductor layer 130 can be formed.

[0106] The thickness of the metal oxide layer 120 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 120 is set to 3 nm. In this embodiment, the alumina layer used as the metal oxide layer 120 has high gas barrier properties even if its thickness is 1 nm to 10 nm. Therefore, the metal oxide layer 120 of this embodiment blocks hydrogen and oxygen released from the gate insulating layer 110, suppressing hydrogen and oxygen released from below from reaching the oxide semiconductor layer 130. The blocking of hydrogen released from the gate insulating layer 110 by the metal oxide layer 120 is preferred in suppressing the reduction reaction of the oxide semiconductor layer 130.

[0107] Furthermore, after the oxide semiconductor layer 130 is formed, during various manufacturing processes (such as patterning), more oxygen defects are formed on the upper side of the oxide semiconductor layer 130 than on the lower side. That is, the oxygen defects in the oxide semiconductor layer 130 exist in a non-uniform distribution along the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen defects formed on the upper side of the oxide semiconductor layer 130, an excess of oxygen will be supplied to the lower side of the oxide semiconductor layer 130. This results in the formation of defect levels different from those of the oxygen defects due to the excess oxygen supply, which can sometimes lead to changes in characteristics during reliability testing or a decrease in field-effect mobility. Therefore, it can be said that, in terms of suppressing the excess oxygen supply to the lower side of the oxide semiconductor layer 130, the oxygen barrier released from the gate insulating layer 110 by the metal oxide layer 120 is preferable.

[0108] Thus, in this embodiment, when performing Figure 3 During the oxidation annealing shown in step S1005, oxygen supply to the upper surface and sides of the oxide semiconductor layer 130, which has a relatively high oxygen deficiency, can be achieved while suppressing oxygen supply to the lower surface of the oxide semiconductor layer 130 with low oxygen deficiency. Therefore, during oxidation annealing, oxygen can be efficiently supplied to the oxide semiconductor layer 130, thereby improving the reliability of the semiconductor device 40.

[0109] Furthermore, in this embodiment, the method applicable to the first embodiment is described. Figure 1 The example of semiconductor device 10 shown is applicable to other semiconductor devices shown in the second or third embodiment.

[0110] <Fifth Embodiment> In this embodiment, a display device 500 using the semiconductor device 10 according to one embodiment of the present invention is described. In the embodiments shown below, the semiconductor device 10 described in the first embodiment is described as an element in the circuit constituting a liquid crystal display device. However, this is not limited to this example; the semiconductor devices described in the second to fourth embodiments may also be used as elements in the circuit constituting a liquid crystal display device. Furthermore, elements that constitute the circuit constituting a liquid crystal display device may be used as elements in the circuit constituting other display devices such as organic EL display devices, instead of elements constituting the liquid crystal display device.

[0111] [Overview of the display device] Figure 27 This is a schematic top view showing the overall configuration of a display device 500 according to one embodiment of the present invention. Figure 27 As shown, the display device 500 includes an array substrate 300, a sealing portion 310, a counter substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the sealing portion 310. Within the liquid crystal region 52 surrounded by the sealing portion 310, a plurality of pixels 51 are arranged in a matrix. That is, the display region is formed by the plurality of pixels 51 arranged along the X and Y directions respectively. The liquid crystal region 52 is the region that overlaps with the liquid crystal element 311 described later when viewed from above. Furthermore, regarding the pixels 51, the labels "R", "G", and "B" respectively indicate pixels corresponding to pixels for displaying red, pixels for displaying green, and pixels for displaying blue.

[0112] The sealing region 54, with the sealing portion 310, is the area surrounding the liquid crystal region 52. A flexible printed circuit board 330 is disposed on the terminal region 56. The terminal region 56 is the area in the array substrate 300 exposed from the opposing substrate 320, and is disposed outside the sealing region 54. "Outside the sealing region 54" means the area with the sealing portion 310 and the area surrounded by the sealing portion 310. An IC chip 340 is disposed on the flexible printed circuit board 330. The IC chip 340 supplies power to the pixel circuits 301 (see reference 51) configured in each pixel 51. Figure 28 () The signal driven by.

[0113] [Circuit configuration of the display device] Figure 28 This is a block diagram illustrating the circuit configuration of a display device 500 according to one embodiment of the present invention. Figure 28 As shown, with Figure 27Each pixel 51 shown is correspondingly provided with a plurality of pixel circuits 301 arranged in a matrix. A source driving circuit 302 is provided at a position adjacent to the liquid crystal region 52 where the pixel circuits 301 are located in the Y direction (column direction). Furthermore, a gate driving circuit 303 is provided at a position adjacent to the liquid crystal region 52 in the X direction (row direction). The source driving circuit 302 and the gate driving circuit 303 are located in the aforementioned sealed region 54. However, the region where the source driving circuit 302 and the gate driving circuit 303 are located is not limited to the sealed region 54, and may also be located outside the region where the pixel circuits 301 are located.

[0114] Data signal line 304 extends from source drive circuit 302 along the Y direction and is connected to a plurality of pixel circuits 301 arranged along the Y direction. Scan signal line 305 extends from gate drive circuit 303 along the X direction and is connected to a plurality of pixel circuits 301 arranged along the X direction.

[0115] A terminal portion 306 is provided in the terminal region 56. The terminal portion 306 and the source drive circuit 302 are connected by a connection wiring 307. Similarly, the terminal portion 306 and the gate drive circuit 303 are connected by a connection wiring 308. A flexible printed circuit board 330 is connected to the terminal portion 306, thereby connecting external devices and the display device 500 via the flexible printed circuit board 330. Each pixel circuit 301 provided in the display device 500 is driven by signals from external devices input via the flexible printed circuit board 330.

[0116] The semiconductor device 10 shown in the first embodiment is used as a switching element or current control element included in the pixel circuit 301, the source driving circuit 302, and the gate driving circuit 303.

[0117] [Pixel circuit of display device] Figure 29 This is a circuit diagram illustrating the configuration of the pixel circuit 301 of the display device 500 in one embodiment of the present invention. For example... Figure 29 As shown, the pixel circuit 301 includes components such as a switching element 410, a holding capacitor 420, and a liquid crystal element 311.

[0118] The switching element 410 is constructed from the semiconductor device 10 of the first embodiment. The switching element 410 has a gate electrode 411, a source electrode 412, and a drain electrode 413. The gate electrode 411 is connected to the scan signal line 305. However, the gate electrode 411 and the scan signal line 305 may also be formed from a single conductive layer. The source electrode 412 is connected to the data signal line 304. However, the source electrode 412 and the data signal line 304 may also be formed from a single conductive layer.

[0119] The drain electrode 413 is connected to the holding capacitor 420 and the liquid crystal element 311. Furthermore, the source electrode 412 and the drain electrode 413 can alternate in function depending on the relationship between the voltage supplied to the data signal line 304 and the voltage stored in the holding capacitor 420. That is, sometimes the source electrode 412 functions as the drain electrode, and sometimes the drain electrode 413 functions as the source electrode.

[0120] [Pixel structure of display device] Figure 30 This is a cross-sectional view showing the pixel structure of a display device 500 according to one embodiment of the present invention. The display device 500 uses a semiconductor device 10 as described in the first embodiment as a switching element 410 included in the pixel circuit 301. In the following description, the configuration of the semiconductor device 10 is similar to... Figure 1 The semiconductor device 10 shown is the same, so detailed descriptions are omitted.

[0121] An insulating layer 360 is provided on the terminal electrode 161 of the semiconductor device 10. Acrylic resin can be used as an example for the insulating layer 360. A common electrode 370 shared by multiple pixels is provided on the insulating layer 360. An insulating layer 380 is provided on the common electrode 370. A silicon nitride layer can be used as an example for the insulating layer 380. Contact holes 381 are provided on the insulating layers 360 and 380. A pixel electrode 390 connected to the terminal electrode 161 via the contact holes 381 is provided on the insulating layer 380.

[0122] Both the common electrode 370 and the pixel electrode 390 utilize transparent conductive layers. In this embodiment, ITO (Indium Tin Oxide) is used as the material for the transparent conductive layers constituting the common electrode 370 and the pixel electrode 390, but other metal oxide layers may also be used. The common electrode 370 is composed of a plate-shaped transparent conductive layer. Although in Figure 30 Although not illustrated, the pixel electrode 390 is composed of a comb-shaped transparent conductive layer consisting of a portion extending along a first direction and a portion extending along a second direction. The portion extending along the second direction consists of multiple linear electrodes, each connected to an electrode corresponding to a main branch extending along the first direction.

[0123] A liquid crystal layer 311a is sealed between the active matrix substrate formed from the substrate 100 to the pixel electrode 390 and the opposing substrate 320. The liquid crystal layer 311a is arranged across a plurality of pixels 51. The area where the liquid crystal layer 311a is arranged corresponds to Figure 27 The liquid crystal area 52 shown.

[0124] like Figure 30As shown, the common electrode 370 has an overlapping region that overlaps with the pixel electrode 390 when viewed from above, and a non-overlapping region that is different from the pixel electrode 390. When a voltage is supplied between the pixel electrode 390 and the common electrode 370, a lateral electric field is formed from the pixel electrode 390 in the overlapping region toward the common electrode 370 in the non-overlapping region. This lateral electric field causes the liquid crystal molecules contained in the liquid crystal layer 311a to move, thereby determining the color of the light passing through the pixel 51.

[0125] The various embodiments described as embodiments of the present invention (including variations thereof) can be appropriately combined and implemented as long as they do not contradict each other. In addition, based on the various embodiments, those skilled in the art can appropriately add or remove constituent elements, make design changes, or add or omit processes or change conditions, etc., and such modifications are also included within the scope of the present invention as long as they capture the essence of the present invention.

[0126] Furthermore, regarding other effects resulting from the methods described in the above embodiments, any effects that are clear from the description in this specification or that can be reasonably conceived by those skilled in the art should naturally be considered as effects brought about by the present invention.

Claims

1. A semiconductor device, wherein, include: Gate electrode above an insulating surface; Gate insulating layer above the gate electrode; The oxide semiconductor layer above the gate insulating layer; The first insulating layer above the oxide semiconductor layer; and The patterned layer composed of metal oxides above the first insulating layer, The oxide semiconductor layer has a channel portion and a conductive portion. When viewed from above, the pattern layer overlaps with the channel portion.

2. The semiconductor device according to claim 1, wherein, When viewed from above, the outer edge of the portion of the patterned layer that overlaps with the oxide semiconductor layer coincides with the outer edge of the channel portion.

3. The semiconductor device according to claim 1, wherein, The channel portion and the conductive portion are arranged continuously in the first direction. When viewed from above, the patterned layer intersects the oxide semiconductor layer in a second direction that intersects the first direction.

4. The semiconductor device according to claim 1, wherein, The metal oxide is an aluminum-containing oxide.

5. The semiconductor device according to claim 1, wherein, The thickness of the first insulating layer is less than 200 nm.

6. The semiconductor device according to claim 1, wherein, The first insulating layer is in contact with the oxide semiconductor layer and the patterned layer.

7. The semiconductor device according to claim 6, wherein, The first insulating layer includes one selected from a silicon oxide layer, a silicon oxynitride layer, or a silicon oxynitride layer.

8. The semiconductor device according to claim 1, wherein, It also includes terminal electrodes disposed on the first insulating layer and electrically connected to the conductive portion.

9. The semiconductor device of claim 1, wherein, Also includes: A second insulating layer above the patterned layer; and Terminal electrodes disposed on the second insulating layer and electrically connected to the conductive portion.

10. The semiconductor device according to claim 9, wherein, The second insulating layer includes a silicon nitride layer.

11. The semiconductor device according to claim 1, wherein, The oxide semiconductor layer further comprises an LDD portion serving as a lightly doped drain portion between the channel portion and the conductive portion.

12. The semiconductor device according to claim 11, wherein, The LDD portion has a lower resistance value compared to the channel portion, and a higher resistance value compared to the conductive portion.

13. The semiconductor device according to claim 11, wherein, The pattern layer overlaps with the channel portion and the LDD portion.

14. The semiconductor device according to claim 1, wherein, A metal oxide layer, which is in contact with the oxide semiconductor layer, is also included between the gate insulating layer and the oxide semiconductor layer.

15. The semiconductor device according to claim 14, wherein, The metal oxide layer has the same pattern shape as the oxide semiconductor layer.

16. The semiconductor device according to claim 15, wherein, The metal oxide layer is an aluminum-containing oxide layer.

17. A display device, wherein, Each pixel includes the semiconductor device as described in any one of claims 1 to 16.

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