A mosfet device with low gate charge and method of making the same

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a MOSFET device with low gate charge and a preparation method thereof, which comprises a P-type Si substrate, a LOCOS isolation layer, a shallowly-buried P-type electric field regulating layer under a channel, a transversely-doped gradient channel, a gate dielectric layer, a main gate, a shielding gate structure, an asymmetric LDD region, a source-side doping concentration of 1*10 18 cm ‑3 , a width of 0.1 mu m and a depth of 50 nm, a drain-side doping concentration of 5*10 17 cm ‑3 , a width of 0.15 mu m and a depth of 50 nm, two-stage stepped grooves in a drain region, a source-drain heavily-doped region and a metal electrode comprising a source, a main gate, a shielding gate and a drain. The application reduces the gate-drain coupling capacitance and the gate capacitance, suppresses the Miller effect, reduces the gate driving loss by combining the ultrathin gate and the NiSi silicide, simultaneously suppresses the sub-threshold leakage, doubly reduces the static and dynamic power consumption and prolongs the endurance of a sensor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a low-gate-charge MOSFET device and its fabrication method. Background Technology

[0002] With the rapid development of the Internet of Things, wearable devices, and portable medical monitoring, low-power high-frequency sensor switches, as core control components, directly determine the power consumption level, response speed, and operational stability of sensor systems. Currently, low-power high-frequency sensor switches present a triple requirement for core components: low power consumption, high frequency, and high reliability. On the one hand, sensor systems often rely on battery power, requiring switching devices to have extremely low static and dynamic power consumption to reduce energy loss and extend battery life. On the other hand, the operating frequency of high-frequency sensors (such as RF sensors, vibration sensors, and high-speed data acquisition sensors) is constantly increasing, requiring switching devices to have fast switching response, low gate charge (Qg), and low gate leakage capacitance (Cgd) characteristics to avoid switching delay and signal distortion. Simultaneously, sensor operating environments are often complex scenarios (such as frequent start-stop of portable devices and the high-precision requirements of medical equipment), placing stringent demands on the device's leakage current suppression, threshold voltage stability, and long-term operational reliability.

[0003] Existing MOSFET devices, as the mainstream choice for sensor switches, face a technical bottleneck in balancing low power consumption and high-frequency performance: traditional MOSFETs have a high gate charge (Qg), resulting in significant gate drive losses during high-frequency switching, leading to increased dynamic power consumption and failing to meet the endurance requirements of low-power sensors; some low-Qg MOSFETs achieve low charge characteristics by thinning the gate dielectric and simplifying the gate structure, but this sacrifices leakage current suppression and threshold voltage stability, easily leading to problems such as excessive subthreshold leakage current and waveform distortion during high-frequency operation, affecting the control accuracy of sensor switches; therefore, how to balance low power consumption and high-frequency performance to a certain extent is the technical problem that the present invention aims to solve. Summary of the Invention

[0004] The purpose of this invention is to provide a MOSFET device with low gate charge and a method for fabricating the same, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A low-gate-charge MOSFET device, the device comprising:

[0007] P-type Si substrate, doping concentration 1×10⁻⁶ 15 cm -3 The thickness is 500μm;

[0008] The LOCOS isolation layer is made of SiO2 material, with a thickness of 300nm and an isolation spacing of 1μm, reserving only the device operating window;

[0009] A shallowly buried P-type electric field modulation layer is located 100 nm below the channel, with a doping concentration of 1×10⁻⁶. 17 cm -3 It has a thickness of 80nm and covers the entire channel area;

[0010] Laterally doped gradient channel, p-type lightly doped Si material, with doping concentration decreasing gradually from the source to the drain, and the doping concentration at the source being 5 × 10⁻⁶. 16 cm -3 The doping concentration at the drain end is 2×10⁻⁶. 16 cm -3 The channel has a length of 0.5 μm, a width of 50 μm, and a thickness of 50 nm.

[0011] Gate dielectric layer; the gate dielectric layer is a composite structure, with the bottom layer being SiO2 with a thickness of 5nm, the top layer being HfO2 with a thickness of 10nm, and the total thickness being 15nm;

[0012] The main gate has an N-type heavily doped polysilicon bottom layer with a thickness of 120nm and a NiSi silicide layer on the surface with a thickness of 30nm.

[0013] The shielding gate structure is made of heavily doped N-type polycrystalline silicon material, with a width of 0.1 μm, a thickness of 180 nm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 ;

[0014] The asymmetric LDD region has a source-side doping concentration of 1×10⁻⁶. 18 cm -3 Width 0.1 μm, depth 50 nm; drain-side doping concentration 5 × 10⁻⁶ 17 cm -3 Width 0.15μm, depth 50nm;

[0015] The drain region has a two-stage stepped groove structure, both located within the heavily doped drain region. The first-stage groove covers the entire heavily doped drain region with a depth of 30 nm. The second-stage groove is located only in a portion of the heavily doped drain region near the gate edge, with a depth of 15 nm and a width consistent with the drain LDD region, which is 0.15 μm.

[0016] The source and drain heavily doped regions are made of N-type heavily doped Si material with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The depth is 100nm, the source side is a planar structure, and the drain side is a stepped groove structure;

[0017] The metal electrode has an Al top layer with a thickness of 300 nm and includes a source, main gate, shielding gate and drain. The contact resistance does not exceed 1 Ω·mm.

[0018] The contact holes are through-hole structures with a diameter of 0.3μm. There are four in total, corresponding to the source, main gate, shield gate, and drain, respectively.

[0019] As a further aspect of the present invention: the distance between the shielding gate structure and the main gate is 0.05 μm, and the width is 0.1 μm.

[0020] The present invention also provides a method for fabricating a MOSFET device with low gate charge, the method comprising:

[0021] Step S1: Provide a P-type Si substrate with a doping concentration of 1×10⁻⁶. 15 cm -3 The substrate is 500 μm thick. The substrate is cleaned to remove the native oxide layer on the surface.

[0022] Step S2: Prepare a LOCOS isolation layer with a thickness of 300 nm and an isolation spacing of 1 μm;

[0023] Step S3: Fabricate a shallowly buried P-type electric field modulation layer under the channel above the substrate, with a doping concentration of 1×10⁻⁶. 17 cm -3 The thickness is 80nm, and it is activated by high-energy ion implantation and annealing.

[0024] Step S4: Fabricate a lateral doped gradient channel using photolithography and ion implantation, with the doping concentration from the source to the drain increasing from 5 × 10⁻⁶. 16 cm -3 Reduced to 2×10 16 cm -3 ;

[0025] Step S5: Prepare a deposited gate dielectric composite structure with a bottom layer of SiO2 and a thickness of 5 nm and an upper layer of HfO2 and a thickness of 10 nm.

[0026] Step S6: Deposit an ultra-thin main gate using LPCVD. The polysilicon thickness is 120nm, and the surface is covered with a NiSi silicide layer with a thickness of 30nm.

[0027] Step S7: Deposit and lithographically define a split-gate structure with a width of 0.1 μm and a doping concentration of 1 × 10⁻⁶. 20 cm -3 The thickness is 180nm;

[0028] Step S8: Form an asymmetric LDD region by photolithography and ion implantation, with a source-side doping concentration of 1×10⁻⁶. 18cm -3 The drain-side doping concentration is 5×10 17 cm -3 ;

[0029] Step S9: Prepare a two-level stepped groove in the drain region. The two-level stepped groove in the drain region is a two-level groove structure, both located in the heavily doped region on the drain side. The first-level groove covers the entire heavily doped region on the drain side and has a depth of 30nm. The second-level groove is only located in a part of the heavily doped region on the drain side near the gate edge, with a depth of 15nm and a width consistent with the drain-side LDD region, which is 0.15μm.

[0030] Step S10: Deposit and etch a metal electrode with an Al top layer, a thickness of 300 nm, and a contact resistance not exceeding 1 Ω·mm;

[0031] Step S11: Form an Al-Si alloy by metallization and annealing.

[0032] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention, through the synergistic effect of a shallowly buried P-type electric field control layer under the channel, a shielding gate, a two-stage stepped groove in the drain region, and a composite gate dielectric, fundamentally reduces the gate-drain coupling capacitance and gate capacitance, suppresses the Miller effect, and combines an ultra-thin gate + NiSi silicide to reduce gate drive losses while suppressing subthreshold leakage current, thus doubly reducing static and dynamic power consumption and extending sensor lifespan. By optimizing the electric field distribution through a lateral gradient-doped channel and reducing overlapping capacitance in the asymmetric LDD region, the switching response speed is fundamentally improved, and high-frequency signal distortion is reduced, ensuring that the device's switching frequency and response speed match the requirements of high-frequency sensors and guaranteeing detection accuracy. Based on the principle of electric field control, the shallowly buried P-type electric field control layer under the channel optimizes the longitudinal electric field, and the lateral gradient-doped channel stabilizes the threshold voltage. Combined with a LOCOS isolation layer to avoid current crosstalk and standardized processes to ensure consistency, this improves the long-term operational stability of the device and adapts it to complex scenarios. Detailed Implementation

[0033] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0034] Regarding the materials and equipment used in the embodiments, unless otherwise specified, the methods used in this invention are all conventional methods known to those skilled in the art, and the reagents and other materials used are all commercially available products unless otherwise specified.

[0035] Example 1

[0036] In this embodiment of the invention, a low-gate-charge MOSFET device and its fabrication method are provided, the device comprising:

[0037] The substrate is made of p-type Si with a crystal orientation of (100), a thickness of 500 μm, and a doping concentration of 1 × 10⁻⁶. 15 cm -3 The substrate is the foundation of the device, supporting all upper structures, and is a conventional layer.

[0038] The isolation structure is made of SiO2 with a thickness of 300nm and an isolation spacing of 1μm, reserving only the device operating window (channel, source / drain and gate regions); its function is to isolate adjacent devices and avoid current crosstalk.

[0039] The channel region is made of p-type Si (lightly doped), with a channel length of 0.5 μm, a width of 50 μm, and a doping concentration of 5 × 10⁻⁶. 15 cm -3 The thickness matches the LDD region (50nm), which is the core conductive region. The threshold voltage is controlled (0.4~0.6V) to reduce the on-resistance.

[0040] The gate dielectric structure includes a bottom layer of SiO2 (interface layer) and an upper layer of HfO2 (high κ dielectric), with a total thickness of 15nm, of which SiO2 is 5nm and HfO2 is 10nm. The coverage area is completely matched with the channel and the gate, which is used to isolate the gate and the channel and reduce the gate capacitance.

[0041] The main gate is made of polycrystalline silicon (heavily N-type doped), with a thickness of 200 nm, a gate length of 0.5 μm, a gate width of 50 μm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 It only covers the channel area to control channel on / off and reduce overlap capacitance;

[0042] The Si3N4 sidewalls are made of Si3N4 and are 50nm thick. They vertically wrap around the gate sidewalls but do not cover the upper and lower surfaces of the gate. This is used to isolate the gate from the source and drain regions and reduce the overlap capacitance.

[0043] The source-side LDD region employs an asymmetric structure and is made of N-type Si (lightly doped) with a doping concentration of 1×10⁻⁶. 18 cm -3 It has a width of 0.1μm and a depth of 50nm, and is located on the left side of the gate and the outside of the sidewall; it is used to buffer the source and the channel, reduce the overlap capacitance between the source and the gate, and does not affect the conduction performance.

[0044] The drain-side LDD region employs an asymmetric structure and is made of N-type Si (lightly doped) with a doping concentration of 5 × 10⁻⁶. 17 cm -3(Below the source side), 0.15μm wide (wider than the source side), 50nm deep, located on the right side of the gate and outside the sidewall; used to suppress the Miller effect, reduce the gate-drain overlap capacitance Cgd, and reduce Qg;

[0045] The drain region features a stepped groove made of N-type Si (heavily doped, consistent with the heavily doped drain region). It consists of two levels of grooves, both located within the heavily doped drain region: the first level is 30nm deep (covering the entire heavily doped drain region); the second level is 15nm deep (only near the gate edge, with a width consistent with the drain-side LDD region, 0.15μm). This is used to further reduce the gate-drain overlap capacitance Cgd, suppress the Miller effect, and improve high-frequency performance.

[0046] The source and drain heavily doped regions are made of N-type Si (heavily doped) with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The depth is 100nm; the source side has a planar structure and the drain side has a stepped groove structure; this is the core conductive region, which connects to the metal contact layer to ensure smooth current conduction.

[0047] The metal contact structure is made of Al metal, with a contact hole diameter of 0.3μm, a metal layer thickness of 300nm, and a contact resistance of no more than 1Ω·mm. It corresponds to the source, drain, and gate, respectively, and is used to connect the device to the external circuit, reduce contact resistance, and reduce conduction loss.

[0048] Preparation method:

[0049] Step 1: Substrate cleaning:

[0050] 1. The substrate used is a p-type Si substrate with a crystal orientation of (100), a thickness of 500 μm, and a doping concentration of 1×10⁻⁶. 15 cm -3 Remove the original oxide layer from the surface after procurement;

[0051] 2. Standard RCA cleaning:

[0052] Acetone cleaning: Soak at room temperature for 10 minutes, then sonicate for 5 minutes (100W) to remove organic impurities;

[0053] Anhydrous ethanol cleaning: Soak at room temperature for 5 minutes, then sonicate for 3 minutes to remove acetone residue;

[0054] Rinse with deionized water: Rinse slowly for 10 minutes at room temperature, avoiding scratching the substrate;

[0055] RCA-1 cleaning: NH4OH:H2O2:H2O=1:1:5 (volume ratio), 70℃, soak for 15 minutes to remove metal impurities;

[0056] Rinse with deionized water for 10 minutes, then clean with RCA-2 (HCl:H2O2:H2O = 1:1:6 by volume) at 70°C for 10 minutes to remove oxide layer and residual metal.

[0057] Rinse with deionized water for 10 minutes, dry at 120℃ for 30 minutes, and set aside.

[0058] Step 2: LOCOS isolation layer preparation:

[0059] 1. Pretreatment: Tube furnace, nitrogen atmosphere (50 sccm), annealing at 800℃ for 30 min to remove substrate stress;

[0060] 2. Si3N4 deposition: LPCVD equipment, 750℃, 100mTorr, SiH4 20sccm, NH3 30sccm, deposit a 200nm thick Si3N4 layer;

[0061] 3. Photolithography (isolation area definition): positive resist, apply resist at 3000 rpm for 30 seconds, dry at 90℃ for 10 minutes (resin thickness 1 μm); exposure dose 100 mJ / cm² 2 10s time (isolation gap 1μm); positive gel developer at room temperature for 60s, rinse with deionized water for 5min, dry at 120℃ for 5min;

[0062] 4. Si3N4 etching: dry etching (plasma etching), CF4:O2=4:1, 100W, 50mTorr, etching for 60s, etching to the surface of the Si substrate;

[0063] 5. Adhesive removal: Plasma adhesive remover, oxygen atmosphere, 150W, 30s;

[0064] 6. Local oxidation: Tube furnace, oxygen atmosphere (80 sccm), 1000℃, oxidation for 120 min, to prepare a 500 nm thick SiO2 isolation layer;

[0065] 7. Removal of Si3N4: HF:HNO3:H2O=1:3:10 (volume ratio), soak at room temperature for 30 seconds, rinse with deionized water for 10 minutes, and dry.

[0066] Step 3: Channel region doping:

[0067] 1. Photolithography (channel region definition): positive resist, coating at 3000 rpm for 30 seconds, drying at 90℃ for 10 minutes; exposure (channel size 0.5μm × 50μm), dose 100mJ / cm². 2 Development time 10s; developing, rinsing, drying;

[0068] 2. Ion implantation (P-type): B⁺ ions, energy 50keV, dose 5×10⁻⁶12 cm -2 (Corresponding doping concentration 5×10) 15 cm -3 ), injection angle 7°, to avoid channeling effect;

[0069] 3. Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0070] 4. Annealing activation: Tube furnace, nitrogen atmosphere (50 sccm), anneal at 950℃ for 30 min to activate doped ions and repair implantation damage.

[0071] Step 4: Gate dielectric fabrication:

[0072] 1. Preparation of SiO2 interface layer: Tube furnace, oxygen atmosphere (80 sccm), 850℃ for 10 min, to prepare a 5 nm thick SiO2 layer;

[0073] 2. HfO2 high-κ medium deposition: ALD equipment, precursors HfCl4 and H2O, 300℃, 1 Torr; HfCl4 pulse 0.5s, purge 2s; H2O pulse 0.5s, purge 2s; 100 cycles to prepare a 10nm thick HfO2 layer;

[0074] 3. Grid dielectric annealing: tube furnace, nitrogen atmosphere (50 sccm), annealing at 700℃ for 20 min to optimize interface quality.

[0075] Step 5: Main gate fabrication:

[0076] 1. Polycrystalline silicon deposition: LPCVD equipment, 650℃, 200mTorr, SiH4 25sccm, deposition for 40min, to prepare a 200nm thick polycrystalline silicon layer;

[0077] 2. Polycrystalline silicon doping (N-type): P⁺ ion implantation, energy 80keV, dose 1×10⁻⁶ 15 cm -2 (corresponding to a doping concentration of 1×10) 20 cm -3 ), injection angle 7°;

[0078] 3. Photolithography (gate definition): positive resist, coat at 3500 rpm for 30 s, dry at 90℃ for 10 min (resin thickness 1.2 μm); exposure (gate length 0.5 μm, gate width 50 μm), dose 120 mJ / cm². 2 Development time: 12 seconds; Developing, rinsing, and drying;

[0079] 4. Polysilicon etching: Dry etching, Cl2:O2=5:1, 120W, 50mTorr, etching for 80s, etching to the gate dielectric surface;

[0080] 5. Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0081] 6. Gate annealing: tube furnace, nitrogen atmosphere (50 sccm), annealing at 900℃ for 20 min to repair etching damage.

[0082] Step 6: Sidewall Preparation

[0083] 1. Si3N4 deposition: LPCVD equipment, 750℃, 100mTorr, SiH4 20sccm, NH3 30sccm, deposition for 8min, to prepare a 50nm thick Si3N4 layer;

[0084] 2. Anisotropic etching: Dry etching, CF4:O2=4:1, 100W, 50mTorr, etching for 40s, only removing horizontal Si3N4, retaining gate sidewall Si3N4 (sidewall).

[0085] 3. Resin removal: Plasma resin remover, 150W, 30s, removes residual polymer from etching.

[0086] Step 7: Doping of the asymmetric LDD region:

[0087] 1. Source-side LDD region doping (light N-type doping), including:

[0088] Photolithography (source-side LDD definition): positive resist, coating at 3000 rpm for 30 seconds, drying at 90°C for 10 minutes; exposure (covering only the left side of the gate and the outer sidewall, width 0.1 μm), dose 100 mJ / cm². 2 Development time 10s; developing, rinsing, drying;

[0089] Ion implantation: As⁺ ions, energy 40keV, dose 1×10⁻⁶ 13 cm -2 (corresponding to a doping concentration of 1×10) 18 cm -3 ), injection angle 7°;

[0090] Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0091] 2. Drain-side LDD region doping (lightly doped N-type, asymmetric with the source side), including:

[0092] Photolithography (drain-side LDD definition): positive resist, coating at 3000 rpm for 30 seconds, drying at 90°C for 10 minutes; exposure (covering only the right side of the gate and the outer sidewall, width 0.15 μm), dose 100 mJ / cm². 2 Development time 10s; developing, rinsing, drying;

[0093] Ion implantation: As⁺ ions, energy 40keV, dose 5×10⁻⁶ 12 cm -2 (Corresponding doping concentration 5×10) 17 cm -3 (lower than the source side), injection angle 7°;

[0094] Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0095] 3. Annealing activation: tube furnace, nitrogen atmosphere (50 sccm), anneal at 900℃ for 20 min to activate LDD region doped ions and repair implantation damage.

[0096] Step 8: Fabrication of heavily doped source / drain regions:

[0097] 1. Photolithography (definition of heavily doped source and drain regions): positive resist, coating at 3000 rpm for 30 seconds, drying at 90°C for 10 minutes; exposure (source side covers the outer side of the source-side LDD region, drain side covers the outer side of the drain-side LDD region), dose 100 mJ / cm² 2 Time: 10 seconds; Develop, rinse, and dry;

[0098] 2. Ion implantation: As⁺ ions, energy 60keV, dose 5×10⁻⁶ 14 cm -2 (Corresponding doping concentration 5×10) 19 cm -3 With an injection angle of 7°, a 100nm deep source / drain heavily doped region was prepared.

[0099] 3. Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0100] Step 9: Preparation of stepped grooves in the leak area:

[0101] 1. First-stage trench fabrication (30nm depth, covering the entire heavily doped drain-side region), including:

[0102] Photolithography (definition of first-level groove): positive resist, coating at 3500 r / min for 30 s, drying at 90℃ for 10 min; exposure (covering the entire drain-side heavily doped region), dose 120 mJ / cm². 2 Time: 12 seconds; Develop, rinse, dry;

[0103] Plasma etching, etching depth 30nm (real-time monitoring of etching status to avoid over-etching);

[0104] Rinse with deionized water for 10 minutes, then dry at 120℃ for 5 minutes;

[0105] Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0106] 2. Fabrication of the second-stage trench (15nm depth, only near the gate edge), including:

[0107] Photolithography (definition of second-level groove): positive resist, coating at 3500 r / min for 30 s, drying at 90℃ for 10 min; exposure (only covering the heavily doped drain region near the gate edge, 0.15 μm wide, consistent with the drain-side LDD region), dose 120 mJ / cm² 2 Time: 12 seconds; Develop, rinse, dry;

[0108] Plasma etching (etching depth 15nm, half the time of the first-stage etching);

[0109] Rinse with deionized water for 10 minutes, then dry at 120℃ for 5 minutes;

[0110] Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0111] 3. Annealing repair: tube furnace, nitrogen atmosphere (50 sccm), anneal at 950℃ for 30 min to repair etching damage and activate source drain heavy doped ions.

[0112] Step 10: Metallization:

[0113] 1. Contact hole fabrication: Photolithography (contact hole definition, diameter 0.3μm, corresponding to source, drain, and gate); dry etching (CF4:O23:1, 100W, 50mTorr, etching for 60s); resist removal;

[0114] 2. Al metal deposition: Electron beam evaporation equipment, vacuum degree 1×10⁻⁶ -5 Pa, evaporation rate 5 Å / s, 300 nm thick Al metal layer deposited at room temperature;

[0115] 3. Metal patterning: photolithography (definition of metal electrodes); wet etching (Al etching solution, phosphoric acid:nitric acid:acetic acid:water 8:1:1:20, immersion at room temperature for 30 seconds); rinsing and drying; resist removal.

[0116] Step 11: Annealing:

[0117] Tube furnace, nitrogen atmosphere (50 sccm), annealing at 450℃ for 30 min (time controlled to avoid silicon puncture) to form Al-Si alloy and reduce contact resistance; then cooled to room temperature with the furnace.

[0118] Example 2:

[0119] Unlike Example 1, a new shielding gate structure is added, including:

[0120] The split-gate is made of polycrystalline silicon (heavily N-type doped, the same as the main gate), with a width of 0.1 μm and a thickness of 180 nm (slightly thinner than the main gate), and a doping concentration of 1 × 10⁻⁶. 20 cm -3 Located between the main gate and the drain region, with a spacing of 0.05 μm from the main gate; electrically connected to the source, so that the electric field of the drain region is preferentially coupled to the shield gate, reducing the coupling capacitance Cgd between the main gate and the drain region;

[0121] The shielding gate and the main gate are insulated with SiO2 material, with a thickness of 10nm. The shielding gate covers the right sidewall of the main gate, the left sidewall of the shielding gate and the area between them. This is used to isolate the main gate and the shielding gate, prevent short circuits between them and ensure the normal operation of the shielding gate.

[0122] The shielding gate does not cover the channel region, but is located only on the right side of the main gate and the left side of the drain-side LDD region. It is electrically connected to the source (through a metal contact layer) and is isolated from the main gate by a 10nm SiO2 insulating layer, which does not affect the conductivity of the original structure.

[0123] Preparation method:

[0124] Unlike Example 1, the following additional steps are added after the main gate fabrication is completed and before the sidewall fabrication (after step 5 and before step 6):

[0125] 1. Preparation of insulating layer (SiO2) between shielding gate and main gate:

[0126] A 10 nm thick SiO2 insulating layer was prepared on the right sidewall and surrounding area of ​​the main gate by oxidation at 800 °C for 8 min in a tube furnace under an oxygen atmosphere (80 sccm).

[0127] Rinse with deionized water for 10 minutes, then dry at 120℃ for 5 minutes;

[0128] 2. Shielding gate polysilicon deposition:

[0129] LPCVD equipment, 650℃, 200mTorr, SiH425sccm, deposition for 36min, to prepare a 180nm thick polycrystalline silicon layer (covering the right side of the main gate, the insulating layer and the reserved area on the drain side).

[0130] 3. Doped (N-type) polysilicon shielding gate:

[0131] Ion implantation: P⁺ ions, energy 80 keV, dose 1×10⁻⁶ 15 cm -2 (Consistent with the main gate doping), injection angle 7°;

[0132] 4. Shielding gate lithography and etching:

[0133] Photolithography (definition of shielding gate): positive resist, coating at 3500 rpm for 30 seconds, drying at 90°C for 10 minutes; exposure (shielding gate width 0.1 μm, located to the right of the main gate, with a spacing of 0.05 μm from the main gate), dose 120 mJ / cm². 2 Development time: 12 seconds; Developing, rinsing, and drying;

[0134] Dry etching: Cl2:O25:1, 120W, 50mTorr, etching for 72s (etching to the surface of the insulating layer to avoid damaging the insulating layer and the main gate).

[0135] Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0136] 5. Shielding gate annealing activation:

[0137] Tube furnace, nitrogen atmosphere (50 sccm), annealing at 900℃ for 20 min to repair etching damage and activate doped ions.

[0138] Accordingly, for the relevant steps, in the sidewall preparation: the preparation method of Example 1 is followed, but the Si3N4 sidewall only covers the left sidewall of the main gate and the right sidewall of the shielding gate, and does not cover the insulating layer area between the main gate and the shielding gate; in the metallization step, in the metal contact preparation, the electrical connection between the shielding gate and the source is increased (the shielding gate is connected to the source electrode through the Al metal layer to ensure that the shielding gate is electrically connected to the source electrode).

[0139] Example 3:

[0140] Unlike Example 2, a new lateral doping gradient design is added to the channel (doping gradually decreases from the source to the drain), specifically replacing the channel parameters with:

[0141] Channel region (lateral doping gradient): P-type Si (lightly doped, lateral gradient distribution) is used, with a channel length of 0.5 μm, a width of 50 μm, and a thickness of 50 nm; the doping concentration gradually decreases from the source to the drain: 5 × 10⁻⁶ at the source. 16 cm -3 4×10 in the middle 16 cm -3 2×10 at the drain end 16 cm -3 This is achieved through multi-energy B⁺ ion implantation;

[0142] Preparation method:

[0143] When doping the channel region (step 3), replace it with the following multi-energy ion implantation process to ensure the realization of the lateral doping gradient:

[0144] 1. Photolithography (channel region definition): Same as in Example 2 (positive resist coating, exposure, development, channel size 0.5μm×50μm);

[0145] 2. Multi-energy B⁺ ion implantation (implanted in three stages to achieve lateral gradient doping):

[0146] First implantation (highly doped source end, 5 × 10⁻⁶) 16 cm -3 ,): B⁺ ions, energy 30keV, dose 6×10 12 cm -2 Injection angle 7°; focus injection into the source area of ​​the channel (using a photomask to block the drain and middle).

[0147] Second implantation (middle doping, 4 × 10⁻⁶) 16 cm -3 ,): B⁺ ions, energy 40keV, dose 5×10 12 cm -2 Injection angle 7°; focus injection in the middle area of ​​the channel (the source and drain ends are blocked by a photomask).

[0148] Third implantation (low doping at the drain, 2×10) 16 cm -3 ,): B⁺ ions, energy 50keV, dose 2.5×10 12 cm -2 Injection angle 7°; focus injection into the drain area of ​​the channel (the source and middle are blocked by a photomask).

[0149] 3. Adhesive removal: Plasma adhesive remover, 150W, 30s;

[0150] 4. Annealing activation: Tube furnace, nitrogen atmosphere (50 sccm), anneal at 950℃ for 30 min to activate doped ions, repair implantation damage, and ensure uniform doping gradient.

[0151] Its function is to widen the drain depletion region, reduce dynamic gate charge storage, improve high-frequency stability, and further reduce Qg.

[0152] It should be noted that the above content is different from the asymmetric LDD region. The asymmetric LDD region is located on both sides of the gate and is a shallowly extended doped region; the lateral doped gradient channel is located below the gate and is a body doped gradient structure; the two are independent of each other in terms of physical location and formation process.

[0153] Example 4

[0154] Unlike Example 3, the gate structure parameters were updated and a silicide layer was added, as detailed below:

[0155] Polycrystalline silicon gate: The material is polycrystalline silicon (heavily N-type doped), with the thickness reduced from 200nm to 120nm, a gate length of 0.5μm, a gate width of 50μm, and a doping concentration of 1×10⁻⁶. 20 cm -3 It only covers the ditch area;

[0156] The NiSi silicide layer, made of NiSi (nickel silicide) with a thickness of 30nm, covers the upper surface of the polysilicon main gate and is tightly bonded to the polysilicon.

[0157] Preparation method:

[0158] The original step 5, the main gate fabrication process, is replaced by an ultra-thin main gate and silicide layer fabrication process, specifically:

[0159] 1. Ultrathin polycrystalline silicon deposition:

[0160] LPCVD equipment, 650℃, 200mTorr, SiH425sccm, deposition for 24min, to prepare a 120nm thick polycrystalline silicon layer (16min less deposition time than in Example 3).

[0161] 2. Polycrystalline silicon doped (N-type):

[0162] Consistent with Example 3: P⁺ ion implantation, energy 80 keV, dose 1 × 10⁻⁶ 15 cm -2 Injection angle 7°;

[0163] 3. Main gate photolithography and etching:

[0164] Consistent with Example 3: photolithography (gate size 0.5μm×50μm), dry etching (Cl2:O25:1, 120W, 50mTorr, etching 48s, etching time shortened due to polysilicon thinning).

[0165] 4. Preparation of NiSi silicide layer (new step):

[0166] Ni metal deposition: Electron beam evaporation equipment, vacuum level 1×10⁻⁶ -5 Pa, evaporation rate 3 Å / s, room temperature deposition of 25 nm thick Ni metal layer (covering the entire upper surface of the main gate).

[0167] Siliconization annealing: tube furnace, nitrogen atmosphere (50 sccm), annealing at 400℃ for 30 min, so that Ni reacts with polycrystalline silicon to form a NiSi silicide layer (thickness of about 30 nm).

[0168] Excess Ni metal removal: Wet etching was performed using a Ni etching solution (HNO3:AcOH:H2O 1:3:6, volume ratio), and the sample was immersed at room temperature for 20 seconds to remove unreacted Ni metal.

[0169] Rinse with deionized water for 10 minutes, then dry at 120℃ for 5 minutes;

[0170] 5. Main gate annealing activation:

[0171] Consistent with Example 3: tube furnace, nitrogen atmosphere (50 sccm), annealing at 900°C for 20 min.

[0172] Example 5:

[0173] Unlike Example 4, a shallowly buried P-type electric field modulation layer is introduced under the channel. The material used is P-type Si (lightly doped), located 100 nm below the channel, with a doping concentration of 1×10⁻⁶. 17 cm -3 The thickness is about 80nm, covering the entire channel region, and is achieved by high-energy B⁺ ion implantation; the electric field modulation layer is located inside the substrate, below the channel, and does not contact any upper structure. It is 80nm thick, and the upper surface is 100nm away from the lower surface of the channel to ensure that it does not affect the channel conduction and other structural performance.

[0174] Preparation method:

[0175] New process insertion location: After substrate cleaning and LOCOS isolation layer fabrication are completed, the specific steps are as follows:

[0176] 1. Photolithography (definition of electric field modulation layer):

[0177] Apply adhesive at 3000 rpm for 30 seconds, then dry at 90°C for 10 minutes; expose (covering the entire working area of ​​the device, consistent with the subsequent channel region), with a dosage of 100 mJ / cm². 2 Development time 10s; developing, rinsing, drying;

[0178] 2. High-energy B⁺ ion implantation:

[0179] Implanted ions: B⁺ ions (P-type); Implantation parameters: Energy 70keV (high-energy implantation, ensuring a depth of 100nm below the channel), Dose 1×10⁻⁶ 13 cm -2 (corresponding to a doping concentration of 1×10) 17 cm -3 Implantation angle: 7° to avoid channeling effect; Implantation depth: through high-energy implantation, doped ions reach 100~180nm inside the substrate (forming an 80nm thick control layer, 100nm on the upper surface and 180nm on the lower surface).

[0180] 3. Remove glue:

[0181] Plasma resist remover, 150W, 30s, thoroughly removes photoresist.

[0182] 4. Annealing activation and damage repair:

[0183] Tube furnace, nitrogen atmosphere (50 sccm), annealing at 1000℃ for 40 min to activate dopant ions, repair substrate damage caused by high-energy implantation, and ensure uniform doping of the control layer; cool to room temperature with the furnace.

[0184] Comparative Example 1:

[0185] A MOSFET device and a method for fabricating the same are provided, the device comprising:

[0186] 1. Substrate: P-type Si (100), doping concentration 1×10⁻⁶ 15 cm -3 The thickness is 500 μm, consistent with this application;

[0187] 2. Isolation layer: LOCOS isolation, SiO2 material, 300nm thickness, consistent with this application;

[0188] 3. Channel: Uniformly doped P-type Si, doping concentration 4×10⁻⁶ 16 cm -3 It has no lateral gradient doping and no shallow buried electric field control layer under the channel;

[0189] 4. Gate dielectric: Single SiO2 layer, 15nm thick, without high-κ dielectric composite structure;

[0190] 5. Gate: Single polysilicon structure, 150nm thick, N⁺ doped, without NiSi silicide modification;

[0191] 6. LDD region: Symmetrical structure, with source and drain doping concentrations both at 8 × 10⁻⁶. 17 cm -3 Width 0.12μm;

[0192] 7. Source / drain heavily doped regions: N⁺Si, doping concentration 5×10⁻⁶ 19 cm -3 100nm deep, with no leaky stepped grooves;

[0193] 8. Contact holes: 0.3 μm in diameter, one each for source, gate, and drain, with a structure consistent with this application;

[0194] 9. Top metal electrode: Al material, 300nm thick, including source, gate, and drain, with no shielded gate structure;

[0195] Preparation methods include:

[0196] 1. Substrate cleaning: Standard RCA cleaning is used, followed by drying at 120℃;

[0197] 2. LOCOS isolation layer fabrication: Si3N4 masking, dry oxidation, and mask removal;

[0198] 3. Channel fabrication: Single-energy B⁺ ion implantation, annealing activation, no gradient doping, and no electric field modulation layer implantation;

[0199] 4. Gate dielectric preparation: A single SiO2 layer is prepared by oxidation in a tube furnace, without the deposition of high-κ dielectric.

[0200] 5. Gate fabrication: LPCVD deposition of polysilicon, P⁺ ion implantation, photolithography etching, NiSi silicide-free fabrication;

[0201] 6. Si3N4 sidewall fabrication: LPCVD deposition and anisotropic etching;

[0202] 7. LDD region and source / drain heavy doping implantation: symmetric LDD implantation, source / drain heavy doping implantation, and no drain region stepped groove etching;

[0203] 8. Contact hole preparation, metallization and alloy annealing.

[0204] Experimental preparation:

[0205] 1. Sample preparation: Select 5 MOSFET devices prepared according to each of the five embodiments of the present invention and one comparative example (to ensure batch consistency), and use the MOSFET device of the comparative example as the control group;

[0206] 2. Equipment Calibration: Calibrate the semiconductor parameter analyzer, high-frequency LCR tester, oscilloscope, and tube furnace (for annealing verification) to ensure test accuracy;

[0207] 3. Environmental control: All experiments shall be conducted in a cleanroom (cleanliness level ≥ 1000), at a room temperature of 25°C and under normal pressure to avoid environmental interference.

[0208] Experimental methods:

[0209] Experiment 1: Gate charge (Qg) and gate-drain capacitance (Cgd) test:

[0210] 1. Connect the device to a high-frequency LCR tester, set the test frequency to 1MHz, gate-source voltage to 0-5V, and drain-source voltage to 0-10V;

[0211] 2. Test and record the Qg and Cgd values ​​of the device.

[0212] Experiment 2: Power Consumption Test

[0213] 1. A semiconductor parameter analyzer was used to test the device's static power consumption (subthreshold leakage current in the off-state) and dynamic power consumption (drive loss in the high-frequency switching state); test conditions: Vgs=0V, Vds=1.8V; unit: nA;

[0214] 2. Static power consumption: Test subthreshold leakage current; Dynamic power consumption: Set the switching frequency to 200MHz and record the drive loss; PQg×Vg×f, take Vg=1.8V, f=200MHz; Unit: mW.

[0215] Experiment 3: High-frequency switching performance test:

[0216] 1. Connect the device to the oscilloscope and signal generator, and gradually increase the switching frequency from 100MHz to 200MHz;

[0217] 2. Record the switching edge time and waveform distortion. When there is no distortion in the waveform at the edge time, record the maximum stable switching frequency as the data. The measured data are the rise time tr (ns) and the maximum stable frequency.

[0218] Experiment 4: Threshold voltage stability test: The threshold voltage of the device was tested at 25℃, 85℃ and -40℃. The threshold drift after 1000h was calculated based on the measured threshold voltage of the device. The unit is mV.

[0219] III. Experimental Data:

[0220] 1. For any embodiment and comparative example, the average of the tested data is taken as the final test result.

[0221] The test data for Experiment 1 are shown in the table below:

[0222] Table 1

[0223] Group Mean value of Qg (nC) Mean Cgd (pF) Comparative Example 6.2 20.6 Example 1 4.4 13.9 Example 2 3.3 8.7 Example 3 3.2 8.1 Example 4 2.8 7.2 Example 5 2.5 6.3

[0224] The test data for Experiment 2 are shown in the table below:

[0225] Table 2

[0226] Group Average leakage current (nA) Dynamic average power consumption (mW) Comparative Example 102 2.3 Example 1 88 1.7 Example 2 81 1.2 Example 3 70 1.2 Example 4 62 1.1 Example 5 43 1.0

[0227] The test data for Experiment 3 are shown in the table below:

[0228] Table 3

[0229] Group mean tr (ns) Stable operating frequency Comparative Example 4.2 120MHz Example 1 3.6 150MHz Example 2 3.0 170MHz Example 3 2.7 180MHz Example 4 2.2 190MHz Example 5 2.0 200MHz

[0230] The test data for Experiment 4 are shown in the table below:

[0231] Table 4

[0232] Group 25℃ 85℃ -40℃ Comparative Example 18 35 15 Example 1 15 28 12 Example 2 14 25 10 Example 3 12 20 9 Example 4 11 18 8 Example 5 8 12 6

[0233] Example 1 introduces an asymmetric LDD structure and a stepped drain trench design based on the traditional symmetrical LDD planar MOS structure. By reducing the peak value of the drain lateral electric field and shrinking the equivalent coupling area of ​​the gate-drain overlap region, a significant reduction in Miller capacitance is achieved. Experimental data shows that Cgd decreases from 20.6 pF in the comparative example to 13.9 pF, a reduction of approximately 32%, and Qg decreases from 6.2 nC to 4.4 nC, a reduction of approximately 29%. This indicates that the drain electric field modulation effectively reduces the charge charging and discharging burden on the gate during high-frequency switching. Simultaneously, the drain current decreases from 102 nA to 88 nA, and the threshold drift decreases from 35 mV to 28 mV at 85°C. This indicates that the hot carrier injection effect is weakened after the drain electric field peak is reduced, and interface state growth is suppressed, thus improving reliability simultaneously. This example only adds one doping mask and one trench etching step, resulting in lower process complexity. It achieves a significant improvement in dynamic performance under controllable cost conditions, making it a cost-effective improvement solution.

[0234] Example 2 further introduces a shielded gate structure based on Example 1, causing the drain-end electric field to preferentially couple to the shielded gate rather than the main gate, substantially weakening the Miller coupling path of the gate-drain capacitance from the perspective of electric field distribution. Experimental results show that Cgd further decreases to 8.7 pF, a reduction of approximately 58% compared to the comparative example, Qg decreases to 3.3 nC, a reduction of approximately 47% compared to the comparative example, and dynamic power consumption decreases from 2.3 mW to 1.2 mW, indicating a significant reduction in the charge and discharge load borne by the main gate under high-frequency driving conditions. The rise time tr is shortened from 4.2 ns to 3.0 ns, and the maximum stable frequency increases from 120 MHz to 170 MHz, indicating that the shielded gate has a particularly significant effect on improving high-frequency switching performance. At the same time, the threshold drift decreases to 25 mV at 85°C, indicating that electric field redistribution also has a positive effect on long-term stability. Although adding a gate pattern and isolation process increases manufacturing complexity, its suppression effect on Cgd and Qg is the most significant, representing a key node for performance leap.

[0235] Example 3 introduces a lateral doped gradient channel structure based on Example 2. By gradually decreasing the channel doping concentration from the source to the drain, the width of the drain depletion region is expanded, and the lateral electric field distribution is further smoothed. This structure offers limited reduction in dynamic capacitance, with Cgd decreasing only from 8.7 pF to 8.1 pF and Qg from 3.3 nC to 3.2 nC. However, it exhibits significant advantages in reliability, with leakage current reduced to 70 nA and threshold drift at 85°C decreasing to 20 mV, indicating that gradient doping effectively mitigates hot carrier effects and short-channel effects. Rise time is improved to 2.7 ns, and the stable frequency is increased to 180 MHz, demonstrating that channel engineering focuses more on electric field optimization and long-term stability improvement than simply capacitance compression. Due to the need for multi-energy ion implantation and finer doping control, process window control becomes more difficult, and costs increase relatively, but it has significant value in high-reliability applications.

[0236] Example 4 introduces a gate silicide (such as NiSi) structure based on Example 3, significantly reducing the gate resistance Rg and thus the RC time constant. This structure has a relatively small impact on Cgd, but by reducing Rg, it directly shortens the switching edge time. Experimental results show that tr is further shortened from 2.7ns to 2.2ns, the stable operating frequency is increased to 190MHz, Qg is reduced to 2.8nC, and dynamic power consumption is reduced to 1.1mW, indicating improved charge transport efficiency under high-frequency drive. Since silicide technology is a mature CMOS standard process, the increased manufacturing cost is relatively limited, while significantly improving high-frequency performance. Therefore, it demonstrates excellent performance in terms of overall performance and cost balance, with the threshold drift further reduced to 18mV (85℃), indicating that the optimization effect of electric field and heat distribution is continued.

[0237] Example 5 adds a shallowly buried P-type electric field modulation layer under the channel, based on Example 4. By reshaping the longitudinal electric field distribution, the electric field strength borne by the gate oxide layer is further reduced, while suppressing hot carrier injection at the drain end. Experimental data shows that this example achieves optimal performance in all aspects: Cgd is reduced to 6.3 pF, Qg to 2.5 nC, leakage current to 43 nA, rise time is shortened to 2.0 ns, maximum stable frequency reaches 200 MHz, and threshold drift is only 12 mV at 85°C, demonstrating optimal long-term stability and high-frequency performance. From a physical perspective, the buried layer effectively smooths the longitudinal electric field distribution and reduces the interface state generation rate, which is the core factor in improving reliability. However, this structure requires high-energy ion implantation and more complex deep doping control, resulting in the highest manufacturing cost and process difficulty, making it suitable for high-end applications with extremely high performance and reliability requirements.

[0238] Comparing the five embodiments, Embodiment 5 is the best in terms of performance. However, considering the overall evaluation of cost and mass production feasibility, Embodiment 4 achieves the best balance between high-frequency performance, power consumption reduction, and process maturity. Therefore, in the application of low-power high-frequency sensors for large-scale industrialization, Embodiment 4 can be regarded as the preferred implementation method, while Embodiment 5 can be regarded as a high-end reliability enhancement solution.

[0239] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A MOSFET device with low gate charge, characterized in that, The device includes: P-type Si substrate, doping concentration 1×10⁻⁶ 15 cm -3 The thickness is 500μm; The LOCOS isolation layer is made of SiO2 material, with a thickness of 300nm and an isolation spacing of 1μm, reserving only the device operating window; A shallowly buried P-type electric field modulation layer is located 100 nm below the channel, with a doping concentration of 1×10⁻⁶. 17 cm -3 It has a thickness of 80nm and covers the entire channel area; Laterally doped gradient channel, p-type lightly doped Si material, with doping concentration decreasing gradually from the source to the drain, and the doping concentration at the source being 5 × 10⁻⁶. 16 cm -3 The doping concentration at the drain end is 2×10⁻⁶. 16 cm -3 The channel has a length of 0.5 μm, a width of 50 μm, and a thickness of 50 nm. Gate dielectric layer; the gate dielectric layer is a composite structure, with the bottom layer being SiO2 with a thickness of 5nm, the top layer being HfO2 with a thickness of 10nm, and the total thickness being 15nm; The main gate has an N-type heavily doped polysilicon bottom layer with a thickness of 120nm and a NiSi silicide layer on the surface with a thickness of 30nm. The shielding gate structure is made of heavily doped N-type polycrystalline silicon material, with a width of 0.1 μm, a thickness of 180 nm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 ; The asymmetric LDD region has a source-side doping concentration of 1×10⁻⁶. 18 cm -3 Width 0.1 μm, depth 50 nm; drain-side doping concentration 5 × 10⁻⁶ 17 cm -3 Width 0.15μm, depth 50nm; The drain region has a two-stage stepped groove structure, both located within the heavily doped drain region. The first-stage groove covers the entire heavily doped drain region with a depth of 30 nm. The second-stage groove is located only in a portion of the heavily doped drain region near the gate edge, with a depth of 15 nm and a width consistent with the drain LDD region, which is 0.15 μm. The source and drain heavily doped regions are made of N-type heavily doped Si material with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The depth is 100nm, the source side is a planar structure, and the drain side is a stepped groove structure; The metal electrode has an Al top layer with a thickness of 300 nm and includes a source, main gate, shielding gate and drain. The contact resistance does not exceed 1 Ω·mm. The contact holes are through-hole structures with a diameter of 0.3μm. There are four in total, corresponding to the source, main gate, shield gate, and drain, respectively.

2. The low gate charge MOSFET device according to claim 1, characterized in that, The distance between the shielding gate structure and the main gate is 0.05 μm, and the width is 0.1 μm.

3. A method for fabricating a low-gate-charge MOSFET device as described in claim 1 or 2, characterized in that, The preparation method includes: Step S1: Provide a P-type Si substrate with a doping concentration of 1×10⁻⁶. 15 cm -3 The substrate is 500 μm thick. The substrate is cleaned to remove the native oxide layer on the surface. Step S2: Prepare a LOCOS isolation layer with a thickness of 300 nm and an isolation spacing of 1 μm; Step S3: Fabricate a shallowly buried P-type electric field modulation layer under the channel above the substrate, with a doping concentration of 1×10⁻⁶. 17 cm -3 The thickness is 80nm, and it is activated by high-energy ion implantation and annealing. Step S4: Fabricate a lateral doped gradient channel using photolithography and ion implantation, with the doping concentration from the source to the drain increasing from 5 × 10⁻⁶. 16 cm -3 Reduced to 2×10 16 cm -3 ; Step S5: Prepare a deposited gate dielectric composite structure with a bottom layer of SiO2 and a thickness of 5 nm and an upper layer of HfO2 and a thickness of 10 nm. Step S6: Deposit an ultra-thin main gate using LPCVD. The polysilicon thickness is 120nm, and the surface is covered with a NiSi silicide layer with a thickness of 30nm. Step S7: Deposit and lithographically define a split-gate structure with a width of 0.1 μm and a doping concentration of 1 × 10⁻⁶. 20 cm -3 The thickness is 180nm; Step S8: Form an asymmetric LDD region by photolithography and ion implantation, with a source-side doping concentration of 1×10⁻⁶. 18 cm -3 The drain-side doping concentration is 5×10 17 cm -3 ; Step S9: Prepare a two-level stepped groove in the drain region. The two-level stepped groove in the drain region is a two-level groove structure, both located in the heavily doped region on the drain side. The first-level groove covers the entire heavily doped region on the drain side and has a depth of 30nm. The second-level groove is only located in a part of the heavily doped region on the drain side near the gate edge, with a depth of 15nm and a width consistent with the drain-side LDD region, which is 0.15μm. Step S10: Deposit and etch a metal electrode with an Al top layer, a thickness of 300 nm, and a contact resistance not exceeding 1 Ω·mm; Step S11: Form an Al-Si alloy by metallization and annealing.