Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a hard mask layer on the surface of a substrate, and enabling the hard mask layer to expose a part of a first region; etching the first region by taking the hard mask layer as a mask, and forming a plurality of gate trenches in the first region; forming trench gate oxide layers on the side walls and the bottom surfaces of the plurality of gate trenches; after the trench gate oxide layers are formed, trench gate layers are formed in the gate trenches; after the trench gate layer is formed, a plurality of first isolation structures are formed in the second region through a shallow trench isolation process, and the forming method of the plurality of first isolation structures comprises the steps that the second region and the hard mask layer on the second region are etched, and a plurality of first isolation trenches are formed in the second region; forming a first isolation structure in the plurality of first isolation grooves; removing the hard mask layer; the BCD gate oxide layer and the BCD gate layer on the surface of the BCD gate oxide layer are formed on the surface of a part of the second region, and only one photoetching is needed to form the BCD gate oxide layer and the trench gate oxide layer, so that the process is saved, and the production cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process that fabricates bipolar transistor (BJT) devices, complementary metal-oxide-semiconductor (CMOS) devices, and double-diffused metal-oxide-semiconductor (DMOS) devices on the same chip, offering advantages such as high-precision analog and low-power digital performance.

[0003] Metal-oxide-semiconductor field-effect transistors (MOS) are commonly used semiconductor devices widely applied in electronic circuits for switching, amplification, modulation, and other functions. Among them, trench MOS devices have advantages such as low specific on-resistance (RSp), low switching losses, and high current drive performance.

[0004] Integrating Trench MOS devices with BCD technology offers reliable intelligent digital and driver circuit synergy, while significantly reducing the need for external source components, and has become a key research focus in the industry.

[0005] However, the performance of existing Trench MOS devices integrated with BCD technology still needs further improvement. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first region and a second region; a plurality of gate trenches located within the first region; a trench gate oxide layer located on the sidewalls and bottom surfaces of the plurality of gate trenches; a trench gate layer located on the surface of the trench gate oxide layer; a plurality of first isolation trenches located within the second region; a first isolation structure located within the plurality of first isolation trenches; a BCD gate oxide layer located on a portion of the surface of the second region and a BCD gate layer on its surface.

[0008] Optionally, the top surface of the trench gate layer is flush with the substrate surface; the top surface of the first isolation structure is higher than the substrate surface.

[0009] Optionally, the substrate further includes a third region; the third region has a second isolation trench, the second isolation trench has a second isolation structure; and a Zener diode is located on the second isolation structure.

[0010] Optionally, the Zener diode includes a diode layer, a P-type doped region and an N-type doped region located within the diode layer, wherein the P-type doped region and the N-type doped region are discrete from each other and located at opposite ends of the diode layer.

[0011] Optionally, it also includes: a trench source region located in the first region on both sides of the gate trench; and a source / drain region located in the second region on both sides of the BCD gate layer.

[0012] Optionally, the substrate includes a substrate and an epitaxial layer located on the surface of the substrate, the substrate and the epitaxial layer have the same conductivity type, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer; the epitaxial layer in the second region further includes a buried layer, the buried layer is in contact with the surface of the substrate, and the buried layer has a different conductivity type than the substrate.

[0013] Optionally, it further includes: a body region located in the first region, the body region having a different conductivity type from the epitaxial layer; a well region located in the second region, the well region being located above a portion of the buried layer; a plurality of gate trenches located in the body region, and the depth of the gate trenches being greater than the depth of the body region; a trench source region located in the body region; and a source / drain region located in the well region.

[0014] Optionally, it may also include: lead-out regions located in the body region on both sides of the gate trench, wherein the lead-out regions have the same conductivity type as the body region.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a hard mask layer on the surface of the substrate, the hard mask layer exposing a portion of the first region; using the hard mask layer as a mask, etching the first region to form a plurality of gate trenches within the first region; forming a trench gate oxide layer on the sidewalls and bottom surfaces of the plurality of gate trenches; after forming the trench gate oxide layer, forming a trench gate layer within the plurality of gate trenches; after forming the trench gate layer, forming a plurality of first isolation structures within the second region using a shallow trench isolation process, the method for forming the plurality of first isolation structures comprising: etching the second region and the hard mask layer on the second region to form a plurality of first isolation trenches within the second region; forming a first isolation structure within the plurality of first isolation trenches; removing the hard mask layer; and forming a BCD gate oxide layer and a BCD gate layer on the surface of a portion of the second region.

[0016] Optionally, the method for forming the trench gate layer includes: forming a trench gate material layer in a plurality of the gate trenches and on the surface of the hard mask layer; and etching back the trench gate material layer.

[0017] Optionally, after forming the trench gate layer and before forming the plurality of the first isolation structures, the method further includes forming a protective layer on the surface of the trench gate layer.

[0018] Optionally, a method for forming a plurality of the first isolation trenches includes: forming a patterned layer on the surface of the hard mask layer and the surface of the trench gate layer, the patterned layer exposing a portion of the surface of the hard mask layer on the second region; and etching the hard mask layer and the second region using the patterned layer as a mask.

[0019] Optionally, the method of forming the first isolation structure includes: forming a dielectric material layer in a plurality of first isolation trenches and on the surface of the hard mask layer; planarizing the dielectric material layer until the surface of the hard mask layer is exposed.

[0020] Optionally, the method further includes: forming a trench source region in the first region on both sides of the gate trench; and forming a source / drain region in the second region on both sides of the BCD gate layer.

[0021] Optionally, the substrate includes a substrate and an epitaxial layer located on the surface of the substrate, the substrate and the epitaxial layer have the same conductivity type, and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer; a buried layer is also formed in the epitaxial layer of the second region, the buried layer is in contact with the surface of the substrate, and the buried layer has a different conductivity type than the substrate.

[0022] Optionally, before forming the plurality of gate trenches, the method includes: forming a body region in the first region, the body region having a different conductivity type from the epitaxial layer; forming a well region above a portion of the buried layer in the second region; forming the plurality of gate trenches in the body region, wherein the depth of the gate trenches is greater than the depth of the body region; forming the trench source region in the body region; and forming the source / drain region in the well region.

[0023] Optionally, the substrate further includes a third region; the method further includes: forming a second isolation trench in the third region while forming a plurality of first isolation trenches; forming a second isolation structure in the second isolation trench while forming the first isolation structure; forming a diode layer on the second isolation structure while forming the BCD gate layer; and forming a Zener diode with the diode layer.

[0024] Optionally, the Zener diode includes a P-type doped region and an N-type doped region, which are discrete from each other and located at opposite ends of the diode layer.

[0025] Optionally, the method for forming the Zener diode includes: forming a P-type doped region at one end of the diode layer; and forming an N-type doped region at the other end of the diode layer.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the semiconductor structure formation method provided by the present invention, a plurality of gate trenches are first formed, and a trench gate oxide layer and a trench gate layer are formed in the plurality of gate trenches. Then, a plurality of first isolation structures are formed in the second region through a shallow trench isolation process. After removing the hard mask layer, a BCD gate oxide layer and a BCD gate layer are formed, thereby realizing the integration of TrenchMOS device and BCD process. Since the BCD gate oxide layer and the trench gate oxide layer are formed separately in different processes, they do not need to share the same gate oxide material. Therefore, their thicknesses can be adjusted separately. Furthermore, based on the self-alignment effect of the gate trench on the trench gate layer and the trench gate oxide layer, the formation of the BCD gate oxide layer and the trench gate oxide layer only requires one photolithography step, which helps to save processes and reduce production costs.

[0027] Furthermore, a diode layer is formed on the second isolation structure, and a Zener diode is formed on the diode layer 317. Due to the insulating effect of the second isolation structure, compared with forming a Zener diode in the substrate, it is beneficial to reduce parasitic effects. When it is forward conducting, it can be used as a temperature sensor, and when it is reverse cut off, it can realize a clamping function. Thus, the Zener diode can be flexibly applied by connecting it in forward and reverse series. Attached Figure Description

[0028] Figures 1 to 5 This is a schematic diagram of the steps involved in forming a semiconductor structure. Figures 6 to 16 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention; Figures 17 to 24 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0029] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0030] As described in the background section, the performance of existing Trench MOS devices integrated with BCD processes still needs further improvement. A method for forming a semiconductor structure will now be explained and analyzed.

[0031] Figure 1 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0032] Please refer to Figure 1 A substrate is provided, the substrate including a trench region I and a BCD region II, the substrate including a base 100 and an epitaxial layer 101 located on the surface of the base 100, the base 100 and the epitaxial layer are both N-type conductive, the epitaxial layer 101 in the BCD region II has a P-type buried layer 102, the P-type buried layer 102 is in contact with the base 100; a mask layer 103 is formed on the surface of the substrate, the mask layer 103 exposes part of the surface of the epitaxial layer 101; an isolation layer 104 is formed in the exposed epitaxial layer 101 by local oxidation of silicon (LOCOS) technology.

[0033] Please refer to Figure 2 Remove the mask layer 103; form a plurality of trenches 105 in the epitaxial layer 101 in the Trench region I.

[0034] Please refer to Figure 3 A gate oxide layer 106 is formed in a plurality of the trenches 105 and on the surface of the substrate; a first gate material layer 107 is formed on the surface of the gate oxide layer 106.

[0035] Please refer to Figure 4 The first gate material layer 107 is etched until the gate oxide material layer 106 is exposed, and a trench gate layer 108 is formed in a plurality of trenches 105.

[0036] Please refer to Figure 5 A second gate material layer (not shown) is formed on the surface of the substrate; the second gate material layer and the gate oxide material layer 106 are etched until the surface of the substrate 100 is exposed, so as to form a BCD gate oxide layer 109 and a BCD gate layer 110 on the BCD region II, and a trench gate oxide layer 111 is formed with the gate oxide material layers 106 in a plurality of trenches 105; source and drain regions 112 are formed in the BCD region II on both sides of the BCD gate layer 110; and source regions 113 are formed in the trench region I on both sides of the trench gate layer 108.

[0037] The above method is used for Trench MOS device and BCD process integration. The BCD gate oxide layer 109 and the trench gate oxide layer 111 are both formed in the same etching process through a shared gate oxide material layer 106. Compared with using two photolithography steps to form the BCD gate oxide layer and the trench gate oxide layer separately, it is beneficial to save process time.

[0038] However, in the process of forming the trench gate layer 108 (such as...) Figure 4As shown, the gate oxide material layer 106 serves as an etching stop layer when etching the first gate material layer 107. This will inevitably cause etching damage to the gate oxide material layer 106, thereby reducing the performance of the BCD gate oxide layer 109 on the BCD region II and reducing the reliability of the device.

[0039] To address the aforementioned issues, this invention provides a semiconductor structure and its formation method. First, several gate trenches are formed, and then a trench gate oxide layer and a trench gate layer are formed within these trenches. Next, several first isolation structures are formed in a second region using a shallow trench isolation process. After removing the hard mask layer, a BCD gate oxide layer and a BCD gate layer are formed, thereby achieving the integration of Trench MOS devices and BCD technology. Since the BCD gate oxide layer and the trench gate oxide layer are formed separately in different processes, they do not need to share a gate oxide material. Therefore, their thicknesses can be adjusted independently. Furthermore, based on the self-alignment effect of the gate trenches on the trench gate layer and the trench gate oxide layer, forming the BCD gate oxide layer and the trench gate oxide layer only requires one photolithography step, which helps save on processes and reduce production costs.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 6 to 16 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 6 A substrate is provided, the substrate comprising a first region I and a second region II.

[0043] In this embodiment, the substrate is made of silicon.

[0044] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0045] In this embodiment, the substrate includes a substrate 200 and an epitaxial layer 201 located on the surface of the substrate 200. The substrate 200 and the epitaxial layer 201 have the same conductivity type, and the doping concentration of the substrate 200 is greater than that of the epitaxial layer 201.

[0046] In this embodiment, both the substrate 200 and the epitaxial layer 201 are N-type.

[0047] In another embodiment, the substrate and the epitaxial layer may be P-type.

[0048] The substrate 200 serves as a support while also functioning as the drain region for the Trench MOS device.

[0049] The first region I is used to define the location of Trench MOS devices, and the second region II is used to define the location of BCD process devices.

[0050] In this embodiment, a buried layer 202 is also formed in the epitaxial layer 201 of the second region II. The buried layer 202 is in contact with the surface of the substrate 200, and the buried layer 202 has a different conductivity type than the substrate 200.

[0051] In this embodiment, the buried layer 202 has a P-type conductivity.

[0052] In this embodiment, before forming a plurality of gate trenches, a body region 203 is formed in the first region I. The body region 203 and the epitaxial layer 201 have different conductivity types.

[0053] Specifically, the conductivity type of the body region 203 is P-type.

[0054] In this embodiment, a well region 204 is also formed above a portion of the buried layer 202 in the second region II. Both the well region 204 and the body region 203 extend from the substrate surface into the interior of the substrate.

[0055] The conductivity type of the well region 204 depends on the type of BCD process device formed, which includes one or more of BJT devices, CMOS devices, and DMOS devices.

[0056] For illustration purposes, an NMOS device is subsequently formed in the second region II, and the conductivity type of the well region 204 is P-type.

[0057] Please refer to Figure 6 A hard mask layer 205 is formed on the surface of the substrate, and the hard mask layer 205 exposes a portion of the first region I.

[0058] Specifically, the hard mask layer 205 is formed on the surface of the epitaxial layer 201.

[0059] The material of the hard mask layer 205 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0060] In this embodiment, the hard mask layer 205 is a double layer, which includes a silicon oxide layer (not shown in the figure) and a silicon nitride layer (not shown in the figure) located on the surface of the silicon oxide layer.

[0061] In other embodiments, the hard mask layer may be a single layer or multiple layers.

[0062] Please refer to Figure 7 Using the hard mask layer 205 as a mask, the first region I is etched to form a plurality of gate trenches 206 in the first region I.

[0063] In this embodiment, a plurality of gate trenches 206 are formed within the body region 203, and the depth of the gate trenches 206 is greater than the depth of the body region 203. The gate trenches 206 are used to define the location of the trench gate structure.

[0064] The formation process of the plurality of gate trenches 206 includes one or a combination of dry etching and wet etching processes. In this embodiment, a dry etching process is used to form the plurality of gate trenches 206, which is beneficial to improving the morphology of the formed gate trenches 206.

[0065] Please refer to Figure 8 A trench gate oxide layer 207 is formed on the sidewalls and bottom surface of several of the gate trenches 206.

[0066] In this embodiment, the formation process of the trench gate oxide layer 207 includes a thermal oxidation process.

[0067] Subsequently, after forming the trench gate oxide layer 207, a trench gate layer is formed within the plurality of gate trenches 206. In this embodiment, the method for forming the trench gate layer is described in reference [reference needed]. Figures 9 to 10 .

[0068] Please refer to Figure 9 A trench gate material layer 208 is formed in a plurality of the gate trenches 206 and on the surface of the hard mask layer 205.

[0069] In this embodiment, the trench gate material layer 208 is made of polysilicon.

[0070] The trench gate material layer 208 contains doped ions, including N-type doped ions or P-type doped ions.

[0071] In this embodiment, the dopant ion is N-type. Specifically, the dopant ion is phosphorus.

[0072] The trench gate material layer 208 is used to form a trench gate layer, and the doped ions are used to control the threshold voltage of the subsequently formed Trench MOS device.

[0073] Please refer to Figure 10 The trench gate material layer 208 is etched back to form the trench gate layer 209.

[0074] In this embodiment, the top surface of the trench gate layer 209 is flush with the surface of the substrate.

[0075] In this embodiment, the process of etching back the trench gate material layer 208 is a dry etching process.

[0076] Subsequently, after forming the trench gate layer, several first isolation structures are formed in the second region II using a shallow trench isolation process.

[0077] In this embodiment, after the trench gate layer 209 is formed and before the plurality of the first isolation structures are formed, please also refer to Figure 11 .

[0078] Please refer to Figure 11 A protective layer 210 is formed on the surface of the trench gate layer 209.

[0079] The protective layer 210 is used to prevent doped ions in the trench gate layer 209 from diffusing outward, causing impurity contamination and affecting device performance.

[0080] The material of the protective layer 210 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0081] In this embodiment, the material of the protective layer 210 is silicon oxide.

[0082] In this embodiment, the method for forming the plurality of first isolation structures is referred to Figures 12 to 14 .

[0083] Please refer to Figure 12 The second region II and the hard mask layer 205 on the second region II are etched to form a plurality of first isolation trenches 211 in the second region II.

[0084] In this embodiment, the method for forming a plurality of first isolation trenches 211 includes: forming a patterned layer (not shown in the figure) on the surface of the hard mask layer 205 and the surface of the trench gate layer 209; using the patterned layer as a mask, etching the hard mask layer 205 and the second region II.

[0085] Specifically, a patterned layer is formed on the surface of the protective layer 210; and a plurality of the first isolation trenches 211 are formed in the sidewall of the hard mask layer 205 and in the epitaxial layer 201.

[0086] In this embodiment, the material of the patterning layer includes photoresist.

[0087] Please refer to Figure 13A first isolation structure 212 is formed within a plurality of the first isolation trenches 211.

[0088] In this embodiment, forming a first isolation structure 212 within a plurality of first isolation trenches 211 includes: forming a dielectric material layer (not shown in the figure) within the plurality of first isolation trenches 211 and on the surface of the hard mask layer 205; planarizing the dielectric material layer until the surface of the hard mask layer 205 is exposed, so as to form a first isolation structure 212 within the plurality of first isolation trenches 211.

[0089] The first isolation structure 212 includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the first isolation structure 212 is used to form a first isolation structure, and its material is silicon oxide.

[0090] The process for planarizing the dielectric material layer includes a mechanical-chemical polishing process.

[0091] The first isolation structure 212 is used to achieve electrical isolation in BCD process devices.

[0092] Please refer to Figure 14 Remove the hard mask layer 205.

[0093] In this embodiment, the hard mask layer 205 is removed using a wet etching process.

[0094] Please refer to Figure 15 A BCD gate oxide layer 213 and a BCD gate layer 214 are formed on a portion of the surface of the second region II.

[0095] First, several gate trenches 206 are formed, and then trench gate oxide layers 207 and trench gate layers 209 are formed within these trenches. Next, several first isolation structures 212 are formed in the second region II using a shallow trench isolation process. After removing the hard mask layer 205, BCD gate oxide layers 213 and BCD gate layers 214 are formed, thus achieving the integration of Trench MOS devices and BCD processes. Since the BCD gate oxide layer 213 and trench gate oxide layer 207 are formed separately in different processes, they do not need to share gate oxide materials, and their thicknesses can be adjusted independently. Furthermore, based on the self-alignment effect of the gate trenches 206 on the trench gate layers 209 and 207, forming the BCD gate oxide layer 213 and trench gate oxide layer 207 only requires one photolithography step, which helps to save processes and reduce production costs.

[0096] In this embodiment, the method for forming the BCD gate oxide layer 213 and the BCD gate layer 214 includes: forming a BCD gate oxide material layer (not shown in the figure) on the surface of the substrate; forming a BCD gate material layer (not shown in the figure) on the surface of the BCD gate oxide material layer; forming a second patterning layer (not shown in the figure) on the surface of the BCD gate material layer and the BCD gate oxide material layer; using the second patterning layer as a mask, etching the BCD gate material layer and the BCD gate oxide material layer until the surface of the substrate is exposed, forming the BCD gate layer with the BCD gate material layer, and forming the BCD gate oxide layer with the BCD gate oxide material layer.

[0097] Please refer to Figure 16 In the gate trench 206 (e.g. Figure 8 Trench source regions 215 are formed in the first region I on both sides of the BCD gate layer 214; source and drain regions 216 are formed in the second region II on both sides of the BCD gate layer 214.

[0098] Specifically, the trench source region 215 is formed in the body region 203; and the source-drain region 216 is formed in the sink region 204.

[0099] In this embodiment, there is also a lead-out region 218 in the body region 203 on both sides of the gate trench 206, and the lead-out region 218 has the same conductivity type as the body region 203.

[0100] In this embodiment, before forming the source / drain region 216, a sidewall 217 is also formed on the sidewall of the BCD gate structure (BCD gate oxide layer 213 and BCD gate layer 214).

[0101] Specifically, the source / drain region 216 is formed using the sidewall 217 and the BCD gate structure as a mask.

[0102] In this embodiment, the sidewall 217 is a double sidewall, which includes a first sidewall (not shown in the figure) and a second sidewall (not shown in the figure) on the sidewall of the first sidewall. The first sidewall is also located on the surface of the substrate.

[0103] In other embodiments, the sidewall may be a single layer or multiple layers.

[0104] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 16 It includes: a substrate, said substrate comprising a first region I and a second region II; and a plurality of gate trenches 206 located within the first region I (e.g., Figure 8(as shown); trench gate oxide layer 207 located on the sidewalls and bottom surfaces of the plurality of gate trenches 206; trench gate layer 209 located on the surface of the trench gate oxide layer 207; a plurality of first isolation trenches 211 located in the second region II (as shown); Figure 12 (as shown); a first isolation structure 212 located within a plurality of first isolation trenches 211; a BCD gate oxide layer 213 located on a portion of the surface of the second region II and a BCD gate layer 214 on its surface.

[0105] In this embodiment, the top surface of the trench gate layer 209 is flush with the surface of the substrate.

[0106] In this embodiment, the top surface of the first isolation structure 212 is higher than the surface of the substrate.

[0107] In this embodiment, the semiconductor structure further includes: located in the gate trench 206 (e.g. Figure 8 The trench source region 215 is located in the first region I on both sides of the BCD gate layer 214; the source and drain regions 216 are located in the second region II on both sides of the BCD gate layer 214.

[0108] In this embodiment, the substrate includes a substrate 200 and an epitaxial layer 201 located on the surface of the substrate 200. The substrate 200 and the epitaxial layer 201 have the same conductivity type, and the doping concentration of the substrate 200 is greater than that of the epitaxial layer 201.

[0109] In this embodiment, the epitaxial layer 201 in the second region II also has a buried layer 202, which is in contact with the surface of the substrate 200, and the buried layer 202 has a different conductivity type than the substrate 200.

[0110] In this embodiment, the semiconductor structure further includes: a body region 203 located in the first region I, wherein the body region 203 and the epitaxial layer 201 have different conductivity types; and a well region 204 located in the second region II, wherein the well region 204 is located above a portion of the buried layer 202.

[0111] In this embodiment, several of the gate trenches 206 (such as...) Figure 8 The gate trench 206 (as shown) is located within the body region 203, and the depth of the gate trench 206 is greater than the depth of the body region 203; the trench source region 215 is located within the body region 203; and the source / drain region 216 is located within the well region 204.

[0112] In this embodiment, the semiconductor structure further includes: located in the gate trench 206 (e.g. Figure 8 (As shown) Lead-out regions 218 within the body region 203 on both sides, the lead-out regions 218 having the same conductivity type as the body region 203.

[0113] Figures 17 to 24 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0114] In this embodiment, the substrate includes a first region, a second region, and a third region. The structures and formation methods of the first and second regions can be found in the description of the previous embodiment. The third region is used to define the location of the Zener diode; the structure and formation method of the third region will be described in detail below.

[0115] Please refer to Figure 17 A substrate is provided, the substrate comprising a first region I, a second region II and a third region III.

[0116] In this embodiment, the substrate includes a substrate 300 and an epitaxial layer 301 located on the surface of the substrate 300. The substrate 300 and the epitaxial layer 301 have the same conductivity type, and the doping concentration of the substrate 300 is greater than that of the epitaxial layer 301.

[0117] In this embodiment, a buried layer 302 is also formed in the epitaxial layer 301 of the second region II and the third region II. The buried layer 302 is in contact with the surface of the substrate 300, and the buried layer 302 has a different conductivity type than the substrate 300.

[0118] In this embodiment, before forming a plurality of gate trenches, a body region 303 is formed in the first region I. The body region 303 and the epitaxial layer 301 have different conductivity types.

[0119] In this embodiment, a well region 304 is also formed above a portion of the buried layer 302 in the second region II. Both the well region 304 and the body region 303 extend from the substrate surface into the substrate interior.

[0120] Please refer to Figure 18 A hard mask layer 305 is formed on the surface of the substrate, and the hard mask layer 305 exposes a portion of the first region I; using the hard mask layer 305 as a mask, the first region I is etched to form a plurality of gate trenches 306 in the first region I.

[0121] In this embodiment, a plurality of gate trenches 306 are formed within the body region 303, and the depth of the gate trenches 306 is greater than the depth of the body region 303. The gate trenches 306 are used to define the location of the trench gate structure (trench gate oxide layer and trench gate layer).

[0122] Please refer to Figure 19A trench gate oxide layer 307 is formed on the sidewalls and bottom surfaces of a plurality of gate trenches 306; after the trench gate oxide layer 307 is formed, a trench gate layer 309 is formed in the plurality of gate trenches 306.

[0123] In this embodiment, the method for forming the trench gate layer 309 includes: forming a trench gate material layer (not shown in the figure) in a plurality of the gate trenches 306 and on the surface of the hard mask layer 305; and etching back the trench gate material layer to form the trench gate layer 309.

[0124] In this embodiment, the top surface of the trench gate layer 309 is flush with the surface of the substrate.

[0125] After forming the trench gate layer 309, a plurality of first isolation structures are formed in the second region II using a shallow trench isolation process. The method for forming the plurality of first isolation structures is described in [reference needed]. Figures 20 to 21 .

[0126] Please refer to Figure 20 The second region II and the hard mask layer 305 on the second region II are etched to form a plurality of first isolation trenches 311 in the second region II. At the same time as forming the plurality of first isolation trenches 311, a second isolation trench 312 is formed in the third region III.

[0127] Please refer to Figure 21 A first isolation structure 313 is formed in a plurality of first isolation trenches 211, and a second isolation structure 314 is formed in the second isolation trenches 312 at the same time as the first isolation structure 313 is formed.

[0128] Please refer to Figure 22 Remove the hard mask layer 305.

[0129] Here, the hard mask layer 305 is removed, so that the top surfaces of the first isolation structure 313 and the second isolation structure 314 both protrude from the substrate surface.

[0130] Please refer to Figure 23 A BCD gate oxide layer 315 and a BCD gate layer 316 are formed on a portion of the surface of the second region II, and a diode layer 317 is formed on the second isolation structure 314 while the BCD gate layer 316 is being formed.

[0131] First, several gate trenches 306 are formed, and then trench gate oxide layers 307 and trench gate layers 309 are formed within these trenches. Next, several first isolation structures 313 are formed in the second region II using a shallow trench isolation process. After removing the hard mask layer 305, BCD gate oxide layers 315 and BCD gate layers 316 are formed, thus achieving the integration of Trench MOS devices and BCD processes. Since the BCD gate oxide layer 315 and trench gate oxide layer 307 are formed separately in different processes, they do not need to share gate oxide materials, and their thicknesses can be adjusted independently. Furthermore, based on the self-alignment effect of the gate trenches 306 on the trench gate layers 309 and 307, forming the BCD gate oxide layer 315 and trench gate oxide layer 307 only requires one photolithography step, which helps save on processes and reduce production costs.

[0132] In this embodiment, the method for forming the BCD gate oxide layer 315 and the BCD gate layer 316 includes: forming a BCD gate oxide material layer (not shown in the figure) on the surface of the substrate; forming a BCD gate material layer (not shown in the figure) on the surface of the BCD gate oxide material layer; forming a second patterning layer (not shown in the figure) on the surface of the BCD gate material layer and the BCD gate oxide material layer; using the second patterning layer as a mask, etching the BCD gate material layer and the BCD gate oxide material layer until the substrate surface is exposed, so as to form the BCD gate oxide layer 315 and the BCD gate layer 316 on the second region II, forming the diode layer 317 on the third region II, forming the BCD gate layer 316 and the diode layer 317 with the BCD gate material layer, and forming the BCD gate oxide layer 315 with the BCD gate oxide material layer.

[0133] Please refer to Figure 24 A Zener diode is formed using the diode layer 317.

[0134] Thus, the Zener diode is formed on the second isolation structure 314. Due to the insulating effect of the second isolation structure 314, compared with forming the Zener diode in the substrate, it is beneficial to reduce parasitic effects. When it is forward conducting, it can be used as a temperature sensor. When it is reverse cut off, it can realize the clamping function. Therefore, the Zener diode can be flexibly applied by connecting it in forward and reverse series.

[0135] In this embodiment, the Zener diode includes a diode layer 317, a P-type doped region 318 and an N-type doped region 319 located within the diode layer 317. The P-type doped region 318 and the N-type doped region 319 are discrete from each other and located at opposite ends of the diode layer 317.

[0136] In this embodiment, the method for forming the Zener diode includes: forming the P-type doped region 318 in one end region (not shown in the figure) of the diode layer 317; and forming the N-type doped region 319 in the other end region (not shown in the figure) of the diode layer 317.

[0137] In this embodiment, the gate trench 306 (e.g.) Figure 8 A trench source region 320 is formed in the first region I on both sides of the BCD gate layer 316; and a source / drain region 321 is formed in the second region II on both sides of the BCD gate layer 316.

[0138] Specifically, sidewalls 323 are formed on the sidewalls of the BCD gate oxide layer 315 and the BCD gate layer 316, and the source / drain regions 321 are formed after the sidewalls 323 are formed.

[0139] In this embodiment, there is also a lead-out region 322 in the body region 303 on both sides of the gate trench 306, and the lead-out region 322 has the same conductivity type as the body region 303.

[0140] The P-type doped region 318 can be formed simultaneously with one or more of the source / drain region 321, the trench source region 320, and the extraction region 322. The N-type doped region 319 can be formed simultaneously with one or more of the source / drain region 321, the trench source region 320, and the extraction region 322. Whether they can be formed simultaneously depends on whether the doping type and doping concentration are consistent.

[0141] For illustrative purposes, taking the formed Trench MOS device as N-type and the MOS device in the BCD process as N-type as an example, the body region 303, the lead-out region 322, the buried layer 302, and the well region 304 are P-type, and the substrate, the trench source region 320, and the source / drain region 321 are N-type. The P-type doped region 318 can be formed simultaneously with the lead-out region 322 using the same ion implantation process, and the N-type doped region 319 can be formed simultaneously with the trench source region 320 and the source / drain region 321 using the same ion implantation process.

[0142] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 24 It includes: a substrate, said substrate comprising a first region I, a second region II, and a third region III; and a plurality of gate trenches 306 located within the first region I (e.g., Figure 18 (as shown); trench gate oxide layer 307 located on the sidewalls and bottom surfaces of several gate trenches 306; trench gate layer 309 located on the surface of the trench gate oxide layer 307; several first isolation trenches 311 located in the second region II (as shown); Figure 20As shown), a plurality of the first isolation trenches 311 have a first isolation structure 313; the second isolation trenches 312 located in the third region III (as shown) Figure 20 As shown), the second isolation trench 312 has a second isolation structure 314; a BCD gate oxide layer 315 located on a portion of the surface of the second region II and a BCD gate layer 316 on its surface; and a Zener diode located on the second isolation structure 314.

[0143] In this embodiment, the Zener diode includes a diode layer 317, a P-type doped region 318 and an N-type doped region 319 located within the diode layer 317. The P-type doped region 318 and the N-type doped region 319 are discrete from each other and located at opposite ends of the diode layer 317.

[0144] The structures of the first region I and the second region II are described in the previous embodiment and will not be repeated here.

[0145] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first region and a second region; Several grid trenches located within the first region; The trench gate oxide layer located on the sidewalls and bottom surfaces of several of the gate trenches; The trench gate layer located on the surface of the trench gate oxide layer; Several first isolation trenches located within the second zone; A first isolation structure located within a plurality of the first isolation trenches; The BCD gate oxide layer located on a portion of the surface of the second region and the BCD gate layer on its surface.

2. The semiconductor structure as described in claim 1, characterized in that, The top surface of the trench gate layer is flush with the surface of the substrate; the top surface of the first isolation structure is higher than the surface of the substrate.

3. The semiconductor structure as described in claim 1, characterized in that, The substrate further includes a third region; the third region has a second isolation trench, and the second isolation trench has a second isolation structure; Zener diode located on the second isolation structure.

4. The semiconductor structure as described in claim 3, characterized in that, The Zener diode includes a diode layer, a P-type doped region and an N-type doped region located within the diode layer, wherein the P-type doped region and the N-type doped region are separate from each other and located at opposite ends of the diode layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: The trench source region is located in the first region on both sides of the gate trench; the source / drain region is located in the second region on both sides of the BCD gate layer.

6. The semiconductor structure as described in claim 5, characterized in that, The substrate includes a substrate and an epitaxial layer located on the surface of the substrate. The substrate and the epitaxial layer have the same conductivity type, and the doping concentration of the substrate is greater than that of the epitaxial layer. The epitaxial layer in the second region also has a buried layer, which is in contact with the surface of the substrate and has a different conductivity type than the substrate.

7. The semiconductor structure as described in claim 6, characterized in that, Also includes: The body region is located within the first region, and the conductivity type of the body region is different from that of the epitaxial layer; the well region is located within the second region, and the well region is located above a portion of the buried layer; a plurality of gate trenches are located within the body region, and the depth of the gate trenches is greater than the depth of the body region; the trench source region is located within the body region; and the source / drain region is located within the well region.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: The lead-out areas located in the body regions on both sides of the gate trench have the same conductivity type as the body regions.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A hard mask layer is formed on the surface of the substrate, the hard mask layer exposing a portion of the first region; Using the hard mask layer as a mask, the first region is etched to form a plurality of gate trenches in the first region; A trench gate oxide layer is formed on the sidewalls and bottom surfaces of several of the aforementioned gate trenches; After the trench gate oxide layer is formed, a trench gate layer is formed within a plurality of the gate trenches; After forming the trench gate layer, a plurality of first isolation structures are formed in the second region by a shallow trench isolation process. The method for forming the plurality of first isolation structures includes: etching the second region and the hard mask layer on the second region to form a plurality of first isolation trenches in the second region; forming first isolation structures in the plurality of first isolation trenches; and removing the hard mask layer. A BCD gate oxide layer and a BCD gate layer on the surface of a portion of the second region are formed.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the trench gate layer includes: forming a trench gate material layer in a plurality of gate trenches and on the surface of the hard mask layer; and etching back the trench gate material layer.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the trench gate layer and before forming the plurality of the first isolation structures, the method further includes forming a protective layer on the surface of the trench gate layer.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, A method for forming a plurality of the first isolation trenches includes: forming a patterned layer on the surface of the hard mask layer and the surface of the trench gate layer, the patterned layer exposing a portion of the surface of the hard mask layer on the second region; and etching the hard mask layer and the second region using the patterned layer as a mask.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method of forming the first isolation structure includes: forming a dielectric material layer in a plurality of first isolation trenches and on the surface of the hard mask layer; planarizing the dielectric material layer until the surface of the hard mask layer is exposed.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method further includes: forming a trench source region in the first region on both sides of the gate trench; and forming a source / drain region in the second region on both sides of the BCD gate layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The substrate includes a substrate and an epitaxial layer located on the surface of the substrate. The substrate and the epitaxial layer have the same conductivity type, and the doping concentration of the substrate is greater than that of the epitaxial layer. A buried layer is also formed in the epitaxial layer of the second region. The buried layer is in contact with the surface of the substrate, and the buried layer has a different conductivity type than the substrate.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, Before forming the plurality of gate trenches, the method includes: forming a body region in the first region, the body region having a different conductivity type from the epitaxial layer; forming a well region above a portion of the buried layer in the second region; forming the plurality of gate trenches in the body region, wherein the depth of the gate trenches is greater than the depth of the body region; forming the trench source region in the body region; and forming the source / drain region in the well region.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The substrate further includes a third region; the method further includes: forming a second isolation trench in the third region while forming a plurality of first isolation trenches; forming a second isolation structure in the second isolation trench while forming the first isolation structure; forming a diode layer on the second isolation structure while forming the BCD gate layer; and forming a Zener diode with the diode layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The Zener diode includes a P-type doped region and an N-type doped region, which are discrete from each other and located at opposite ends of the diode layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method for forming the Zener diode includes: forming a P-type doped region at one end of the diode layer; and forming an N-type doped region at the other end of the diode layer.

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