Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a first source / drain region; a second source / drain region over the first source / drain region; a side via structure connected to the second source / drain region; a first backside contact plug on the first source / drain region; a second backside contact plug on the side via structure; a first backside metal line on the first backside contact plug; a second backside metal line on the second backside contact plug; and a first deep trench isolation structure on a side surface of the second backside contact plug.

Description

Technical Field

[0001] The apparatus and methods consistent with this disclosure relate to stacked semiconductor devices in which a back-side contact plug for a side-channel structure is embedded in a berth structure. Background Technology

[0002] In response to the increasing demand for semiconductor devices with high device density and performance, stacked field-effect transistor (FET) devices have been introduced. A stacked semiconductor device may include a first FET at a first level and a second FET at a second level above the first level, wherein each of the two FETs may be a FinFET, a nanosheet transistor, a fork transistor, or any other type of FET. Stacked semiconductor devices formed from FinFETs, nanosheet transistors, or fork transistors may also be referred to as three-dimensional stacked (3D stacked) semiconductor devices.

[0003] FinFETs have one or more fin structures protruding from a substrate as channel structures and gate structures surrounding at least three surfaces of each fin structure. Nanosheet transistors are characterized by one or more nanosheet channel layers (which are vertically stacked or arranged on a substrate as channel structures) and gate structures surrounding all four surfaces of each nanosheet channel layer. Nanosheet transistors are also known as gate-all-around (GAA) transistors or multi-bridge channel field-effect transistors (MBCFETs). Fork-plate transistors are combinations of two nanosheet transistors with an isolation wall between them. In a fork-plate transistor, the nanosheet channel layer of each nanosheet transistor is formed on each side of the isolation wall and extends parallel to the isolation wall through the gate structure.

[0004] In addition to stacked semiconductor devices, Back Side Distribution Network (BSPDN) structures formed on the back side of semiconductor devices have been introduced to address the heavy traffic of signal lines and power rails, high device density, and increased contact resistance between structural elements of stacked semiconductor devices on the front side. Here, the front side refers to the side relative to the substrate of the semiconductor device where a transistor structure including a channel structure, gate structure, and source / drain regions is formed, and the back side refers to the side opposite the front side. A BSPDN structure may include back-side metal lines, such as buried power rails connected to a voltage source and buried signal lines connected to another circuit element. Furthermore, a BSPDN structure may include back-side contact plugs that connect active elements of the semiconductor device (such as source / drain regions) to buried power rails or signal lines via the back side of the semiconductor device. BSPDN structures may be particularly useful for stacked semiconductor devices.

[0005] Stacked semiconductor devices can be implemented in standard cells and fabricated based on the layout of the semiconductor cells. However, as the cell height of standard cells including stacked semiconductor devices becomes smaller in response to the increasing demand for high-density semiconductor devices, the formation of back-side contact plugs that connect the source / drain regions of the stacked semiconductor devices to buried power rails or signal lines exposes various risks, including increased contact resistance and misaligned connections between device elements.

[0006] The information disclosed in this background section was already known or derived by the inventors before or during the implementation of the embodiments of this application, or it is technical information acquired during the implementation of the embodiments. Therefore, it may contain information that does not form prior art already known to the public. Summary of the Invention

[0007] This disclosure provides a stacked semiconductor device in which a filled front contact plug is formed to contact the side surface of an upper source / drain region, and side spacers are formed on the side surface of a lower source / drain region to isolate it from the lower source / drain region. This filled front contact plug can be formed in a semiconductor device with a simplified process and a reduced cell height.

[0008] According to one aspect of this disclosure, a semiconductor device is provided, which may include: a first source / drain region; a second source / drain region above the first source / drain region; a side passage structure connected to the second source / drain region; a first back-side contact plug on the first source / drain region; a second back-side contact plug on the side passage structure; a first back-side metal line on the first back-side contact plug; and a second back-side metal line on the second back-side contact plug.

[0009] According to one aspect of this disclosure, the semiconductor device may further include a deep trench isolation structure on the side surface of the second back-side contact plug.

[0010] According to one aspect of this disclosure, a semiconductor device is provided, which may include: a source / drain region; a back-side contact plug on the bottom surface of the source / drain region; and a deep trench isolation structure on the side surface of the back-side contact plug.

[0011] According to one aspect of this disclosure, the semiconductor device may further include a shallow trench isolation (STI) structure above a first deep trench isolation structure, wherein the STI structure is also on the side surface of the back-side contact plug.

[0012] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first source / drain region and a second source / drain region above the first source / drain region; forming a side-channel structure connected to the second source / drain region; forming a first back-side contact plug on the first source / drain region; forming a second back-side contact plug on the side-channel structure; forming a first back-side metal line on the first back-side contact plug; and forming a second back-side metal line on the second back-side contact plug. Attached Figure Description

[0013] The exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1A The illustration shows a layout of a semiconductor cell according to one or more embodiments, in which a semiconductor device including back-side contact plugs and side-channel structures for source / drain regions is formed. Figure 1B It is according to one or more embodiments along Figure 1A The cross-sectional view of the semiconductor cell shown by line I-I' is shown, and Figure 1C It is based on one or more embodiments by Figure 1A and Figure 1B A schematic diagram of an inverter circuit implemented using stacked semiconductor devices.

[0015] Figure 2 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more embodiments.

[0016] Figure 3 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more other embodiments.

[0017] Figure 4 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more other embodiments.

[0018] Figures 5A to 5N The manufacturing process according to one or more embodiments is illustrated. Figure 2 The intermediate semiconductor device obtained after the corresponding steps of the semiconductor device 200 shown includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0019] Figure 6A and Figure 6B Manufacturing according to one or more embodiments, such as Figure 2The flowchart shown is of a semiconductor device 200, which includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0020] Figures 7A to 7N The manufacturing process according to one or more embodiments is illustrated. Figure 3 The intermediate semiconductor device obtained after the corresponding steps of the semiconductor device 300 shown includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0021] Figure 8A and Figure 8B Manufacturing according to one or more embodiments, such as Figure 3 The flowchart shown illustrates a semiconductor device 300, which includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0022] Figure 9 This is a schematic block diagram illustrating an electronic device including one or more semiconductor devices according to one or more embodiments, the one or more semiconductor devices including back-side contact plugs and side-channel structures for source / drain regions. Detailed Implementation

[0023] All embodiments of this disclosure described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, such matter may be understood to be related to or combined with a different example or embodiment unless otherwise mentioned in its description. Furthermore, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of this disclosure are intended to cover their structural and functional equivalents. Moreover, these equivalents should be understood to include not only currently known equivalents but also equivalents to be developed in the future, i.e., all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer, and isolation layer described herein may take different types or forms, as long as this disclosure is applicable to them.

[0024] It will be understood that when an element, component, layer, pattern, structure, region, etc., of a semiconductor device (hereinafter collectively referred to as "element") is described as being "above," "over," "on top," "below," "below," "connected to," or "coupled to" another element of the semiconductor device, it may be directly above, above, above, below, below, or connected to or coupled to the other element, or intermediate elements may be present. In contrast, when an element of a semiconductor device is described as being "directly above," "directly above," "directly above," "directly above," "directly below," "directly below," "directly below," "directly connected to," or "directly coupled to" another element of the semiconductor device, no intermediate elements are present. Throughout this disclosure, the same reference numerals refer to the same elements.

[0025] Spatial relative terms, such as “above,” “over,” “on top,” “upper,” “lower,” “below,” “below,” “left,” “right,” “lower left,” “lower right,” “upper left,” “upper right,” “center,” “middle,” etc., may be used herein for ease of description to describe the relationship between one element and another as shown in the figure. It will be understood that spatial relative terms are intended to cover different orientations of a semiconductor device in use or operation other than those depicted in the figure. For example, if the semiconductor device in the figure is flipped, an element described as “below” or “below” another element would be oriented as “above” another element. Thus, the term “below” can cover both above and below orientations. Semiconductor devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly. As another example, elements referred to as “left” and “right” elements may be “right” and “left” elements when the device or structure including these elements is oriented differently.

[0026] It will be understood that although the terms “first,” “second,” “third,” “fourth,” “fifth,” “sixth,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element described in the description of embodiments may be referred to as a second element in the description of another element or one or more claims, and vice versa.

[0027] As used in this article, expressions such as "at least one of..." modify the entire list of elements when they follow a list of elements, without modifying any individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0028] In this document, degree terms including "substantially" or "approximately" may be used. In one or more examples, when a parameter X is specified as substantially the same as parameter Y, the term "substantially" can be understood as X being within 10% of Y. In one or more examples, when a parameter is specified as approximately X, the term "approximately" can be understood as being within 10% of X. Still, when the term "same" is used to compare the parameters of two or more elements, the term can encompass parameters that are "substantially the same".

[0029] It will be understood that when the term "contact" is used to describe two metallic elements (e.g., metal wires and via structures), a barrier metal layer may be formed therebetween, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), but not limited thereto. Furthermore, it will be understood that when the metal contact structure is described as being formed on the surface of the source / drain region or on the surface contacting the source / drain region, a silicide layer may be formed therebetween, such as cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), or tungsten silicide (WSi2), but not limited thereto.

[0030] It will also be understood that even if a step or operation in manufacturing an apparatus or structure is described as being performed later than another step or operation, that step or operation may be performed later than that other step or operation, unless that other step or operation is described as being performed after that step or operation.

[0031] This document describes numerous embodiments with reference to cross-sectional views, which are schematic illustrations of embodiments (and intermediate structures). Thus, variations in the illustrated shapes are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations caused by manufacturing processes. The various areas shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of areas of the device, nor are they intended to limit the scope of this disclosure. Furthermore, in the figures, the dimensions and relative dimensions of layers and areas may be exaggerated for clarity.

[0032] For the sake of brevity, conventional elements, structures, or layers of semiconductor devices, including nanosheet transistors, and the materials forming them, may or may not be described in detail herein. For example, when a particular isolation layer or structure of a semiconductor device is not a novel feature of the embodiment, such isolation layer or structure and the materials forming said isolation layer or structure may be omitted herein. Furthermore, when the materials forming known structural elements of a semiconductor device are not a novel feature of the embodiment, descriptions of these materials may be omitted herein. In this document, the term "isolation" refers to electrical insulation or separation between structures, layers, components, or regions in a corresponding device or structure.

[0033] Figure 1A The illustration shows a layout of a semiconductor cell according to one or more embodiments, in which a semiconductor device including back-side contact plugs and side-channel structures for source / drain regions is formed. Figure 1B It is according to one or more embodiments along Figure 1A The cross-sectional view of the semiconductor cell shown by line I-I' is shown, and Figure 1C It is based on one or more embodiments by Figure 1A and Figure 1B A schematic diagram of an inverter circuit implemented using stacked semiconductor devices.

[0034] It should be understood that Figure 1A Only selected elements of the front side of the semiconductor device are shown, such as active patterns including source / drain regions, gate structures, and side-channel structures. Therefore, for simplicity, some structural elements, such as metal lines and contact plugs formed vertically above or below the active patterns, are not shown. Furthermore, to aid in a better understanding of stacked semiconductor devices, Figure 1B Some structural elements of the stacked semiconductor device (e.g., channel structures) are also shown using dashed lines, which can be seen in the cross-sectional view taken along line II-II'.

[0035] refer to Figure 1A The semiconductor cell 10 may include a plurality of first active patterns 110 and second active patterns 120 extending in the D1 direction and arranged in the D2 direction intersecting the D1 direction. The second active patterns 120 may be stacked on top of the first active patterns 110 in the D3 direction intersecting both the D1 and D2 directions, and partially overlap with the first active patterns 110 in the D3 direction. Therefore, the first active pattern 110 partially overlapped by the second active patterns 120 may have a larger width in the D2 direction than the second active pattern 120. The semiconductor cell 10 may also be formed of a plurality of gate structures 150 arranged along the D1 direction and extending across the active patterns 110 and 120 in the D2 direction. Figure 1AThe semiconductor unit 10 shown may include, but is not limited to, multiple stacked semiconductor devices, multiple active devices of different types, and multiple passive devices.

[0036] The D1 direction refers to the length direction of the channel through which current flows between the two source / drain regions connected by the channel structure. The D2 direction is the channel width direction or cell height direction, and the D3 direction is the channel thickness direction. The D1 and D2 directions can each be referred to as the horizontal direction, and the D3 direction can be referred to as the vertical direction.

[0037] refer to Figure 1A and Figure 1B The semiconductor device 100 included in the semiconductor cell 10 can be formed from a first stacked semiconductor device 11 and a second stacked semiconductor device 12 facing each other in the D2 direction on the substrate layer 101. The two stacked semiconductor devices 11 and 12 can be formed at the same level in the D3 direction on the substrate layer 101. Furthermore, the two stacked semiconductor devices 11 and 12 can have the same structural elements, and therefore, only the structural elements of the first stacked semiconductor device 11 can be described below as needed. The substrate layer 101 may include a back-side isolation layer 106, which is formed by replacing the silicon (Si) substrate and includes a plurality of back-side contact plugs and a plurality of back-side metal lines, which will be described later. The back-side isolation layer 106 can be formed from a low-k material such as silicon oxide (e.g., SiO2), but is not limited thereto.

[0038] Each of the stacked semiconductor devices 11 and 12 can be formed by a first field-effect transistor (FET) and a second FET, wherein the first FET is an n-type field-effect transistor (NFET) at a first level (or lower stack), and the second FET is a p-type field-effect transistor (PFET) at a second level (or upper stack) above the first level in the D3 direction. The first FET and the second FET can be formed based on a first active pattern in a first active pattern 110 and a second active pattern 120 stacked thereon in the D3 direction, respectively, and a corresponding gate structure 150. The two stacked semiconductor devices 11 and 12 can be formed as follows: Figure 1C The inverter circuit shown is composed of four (4) FETs, which will be described further later.

[0039] A first active pattern 110 for a first FET may form a first channel structure 112 and a first source / drain region 113 at a first level. The first channel structure 112 may include a plurality of first nanosheets epitaxially grown from a silicon substrate beneath it, and therefore, the first nanosheets may also be formed of silicon (Si). The n-type first source / drain regions 113 may be epitaxially grown from the first nanosheets of the first channel structure 112 and may be formed of silicon doped with n-type impurities (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). The first channel structure 112 may be surrounded by a gate structure 150, which controls the current flow through the first channel structure 112 between the first source / drain regions 113. The gate structure 150 may include a gate dielectric layer surrounding the first nanosheets, a first work function metal layer formed on the gate dielectric layer, and a gate electrode formed on the first work function metal layer. Therefore, the first channel structure 112 including the first nanosheet layer, the first source / drain region 113 and the gate structure 150 can form a first FET as an NFET implemented by a nanosheet transistor at the first level.

[0040] A second active pattern 120 for the second FET can form a second channel structure 122 and a second source / drain region 123 at a second level. The second channel structure 122 may include a plurality of second nanosheets also epitaxially grown from a silicon substrate, and therefore, the second nanosheets may also be formed of silicon. The second source / drain regions 123 may be epitaxially grown from the second nanosheets of the second channel structure 122 and may be formed of silicon-germanium (SiGe) doped with p-type impurities (e.g., boron (B), gallium (Ga), or indium (In)). The second channel structure 122 may also be surrounded by a gate structure 150, which controls the current flow through the second channel structure 122 between the second source / drain regions 123. A gate dielectric layer surrounding the first channel structure 112 may extend to also surround the second channel structure 122, and a second work function metal layer may be formed on the gate dielectric layer; furthermore, a gate electrode on the second work function metal layer may also extend to surround the second work function metal layer. Therefore, the second channel structure 122 including the second nanosheet layer, the second source / drain region 123 and the gate structure 150 can form a second FET as a PFET implemented by a nanosheet transistor at the second level.

[0041] As previously described, the second active pattern 120 has a smaller width in the D2 direction than the first active pattern 110. Therefore, the second nanosheet forming the second channel structure 122 of the second FET can have a smaller width in the D2 direction than the first nanosheet forming the first channel structure 112 of the first FET, and the second channel structure 122 can only partially overlap with the first channel structure 112 in the D3 direction.

[0042] For example, in stacked semiconductor device 11, the right side surface of the second nanosheet layer can be aligned or coplanar with the right side surface of the first nanosheet layer in the D3 direction, while the left side surface of the second nanosheet layer is not aligned or coplanar with the left side surface of the first nanosheet layer in the D3 direction. In contrast, in stacked semiconductor device 12, the left side surface of the second nanosheet layer of the second FET can be aligned or coplanar with the left side surface of the first nanosheet layer of the first FET in the D3 direction, while the right side surface of the second nanosheet layer is not aligned or coplanar with the right side surface of the first nanosheet layer in the D3 direction. Therefore, the second source / drain region 123 epitaxially grown from the second nanosheet layer can also be formed to have a smaller width in the D2 direction than the first source / drain region 113 epitaxially grown from the first nanosheet layer. Furthermore, in stacked semiconductor device 11, the left side surface of the first source / drain region 113 may not overlap with the second source / drain region 123, while in stacked semiconductor device 12, the right side surface of the first source / drain region 113 may not overlap with the second source / drain region 123. This width difference between the source / drain regions provides free space above the top surface of each of the first source / drain regions 113 that are not vertically overlapped by the second source / drain region 123, allowing other circuit elements (such as source / drain contact plugs) to be formed through this space to contact at least a portion of the top surface of the first source / drain region 113.

[0043] The aforementioned characteristics of the channel structure and source / drain regions can be provided to address the increasing demand for high device density in semiconductor devices, including stacked semiconductor devices.

[0044] In each of the stacked semiconductor devices 11 and 12, the second channel structure 122 forming the second FET may have a greater number of nanosheets than the first channel structure 112 forming the first FET, such that the two FETs may have the same or substantially the same effective channel width (W). eff For example, the second channel structure 122 may have three nanosheets, while the first channel structure 112 has two nanosheets.

[0045] Different channel widths and different numbers of nanosheets (i.e., channel layers) can facilitate the optimization of the semiconductor devices stacked in the semiconductor unit 10, not only in terms of area gain of high-density semiconductor devices, but also in terms of device performance such as current velocity, workload distribution, power efficiency, contact resistance, thermal control, and structural stability.

[0046] The first channel structure 112 and the second channel structure 122 can be isolated from each other by an intermediate isolation layer 115, which can be formed of an isolation or insulating material such as SiBCN, SiCN, SiOC, SiOCN, or Si3N4. Furthermore, in the stacked semiconductor device 11, side spacers 115S can be disposed on the right side surface of the first source / drain region 113 as a residual structure of the intermediate isolation layer 115, which remains after the intermediate isolation layer 115 replaces the intermediate sacrificial layer formed between the two channel structures 112 and 122 during the formation of the first stacked semiconductor device 11. In contrast, in the stacked semiconductor device 12, side spacers 115S can be disposed on the left side surface of the first source / drain region 113 as a residual structure of the intermediate isolation layer 115, which remains after the intermediate isolation layer 115 replaces the intermediate sacrificial layer formed between the two channel structures 112 and 122 during the formation of the second stacked semiconductor device 12.

[0047] Due to the width difference between the two active patterns 110 and 120, the side spacer 115S can be formed only on the right side of the two side surfaces of the first source / drain region 113 in the first stacked semiconductor device 11. In contrast, in the stacked semiconductor device 12, the side spacer 115S can be formed only on the left side of the two side surfaces of the first source / drain region 113. Reference will be made later. Figures 5A to 5N Describe the formation of the lateral spacer 115S.

[0048] A front-side isolation layer 116 may be formed on the front side of the semiconductor device 100 to isolate the stacked semiconductor devices 11 and 12 from each other and from other semiconductor devices. Similar to the back-side isolation layer 106, the front-side isolation layer 116 may be formed of a low-k dielectric material such as silicon oxide (e.g., SiO2), but is not limited thereto.

[0049] A BSPDN structure including a back-side contact plug 104 and back-side metal lines 109A and 109B can be formed on the back side of semiconductor device 100. The back-side contact plug 104 can be formed on the bottom surface of the first source / drain region 113 of each of the stacked semiconductor devices 11 and 12, and can be connected to the back-side metal line 109A buried in the back-side isolation layer 106. The back-side contact plug 104 can connect the n-type first source / drain region 113 to a negative voltage source (VSS or ground) via the back-side metal line 109A. Therefore, the first source / drain region 113 of each of the stacked semiconductor devices 11 and 12 can be powered by a negative voltage source. The back-side contact plug 104 can take the form of a pillar as a pathway structure vertically connecting, for example, two metal lines extending in the D1 or D2 directions at different vertical levels in the D3 direction. In contrast, the back-side metal line 109A can extend in the D1 direction beyond the length of the first source / drain region 113 in the D1 direction.

[0050] The upper portion of the back-side contact plug 104 may be disposed between shallow trench isolation (STI) structures 102, which isolate the stacked semiconductor devices 11 and 12 from each other and from other semiconductor devices in or outside the semiconductor cell 10. The STI structure 102 may be formed of a low-k dielectric material such as silicon oxide (e.g., SiO2), but is not limited thereto.

[0051] Although, as described above, the first source / drain region 113 can be connected to a negative voltage source via the back contact plug 104 and the back metal line 109A, the second source / drain region 123 can be connected to a positive voltage source (VDD) via a side passage structure 117 formed on the back metal line 109B, which is isolated from the back metal line 109A, in the front isolation layer 116 and the back isolation layer 106.

[0052] The side-path structure 117 may have a "T" shape formed by wing portions (or contact portions) 117C and a passage portion 117V, the wing portions 117C being connected to the side surfaces of the second source / drain regions 123 facing each other, and the passage portion 117V extending vertically downward through the front isolation layer 116, the STI structure 102, and the back isolation layer 106 between the two stacked semiconductor devices 11 and 12 to connect to the top surface of the back metal line 109B. Each of the wing portions 117C of the side-path structure 117 may also be connected to at least a portion of the top surface of each of the second source / drain regions 123. The side-path structure 117 may also be referred to as a via power rail (VPR). The side-channel structure 117 may be a single continuous structure formed by a single deposition operation in the process of manufacturing the semiconductor device 100, and therefore, when observed in, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM), there may be no connecting surface, interface or junction between the wing portion 117C connected to each of the second source / drain regions 123 and the channel portion 117V connected to the back-side metal line 109B.

[0053] Multiple front-side metal lines 119 may be formed above the stacked semiconductor devices 11 and 12, which are provided to connect other circuit elements of the semiconductor devices, including the stacked semiconductor devices 11 and 12, in the semiconductor cell 10 to positive voltage sources, negative voltage sources, or other circuit elements in or outside the semiconductor cell 10.

[0054] The back contact plug 104, the side passage structure 117, and the metal wires 109A, 109B, and 119 can be formed of the same metal or metal alloy or different metals or metal alloys, which can be, for example, tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), or alloys thereof.

[0055] When stacked semiconductor devices 11 and 12 form their circuit diagram as shown in the figure Figure 1C When the inverter circuit shown is used, Figure 1B The first source / drain regions 113 shown are all connected to a negative voltage source, and Figure 1B The second source / drain regions 123 shown are all connected to a positive voltage source. In contrast, those connected to... Figure 1B The other first source / drain regions 113' of the first channel structure 112 shown herein and connected to Figure 1B The other second source / drain regions 123' of the second channel structure 122 shown are all connected to each other through the front metal line 119 and the cover metal line to form the common output of the inverter circuit.

[0056] Due to the side-channel structure 117 and the BSPDN structure including the back-side contact plug 104 and back-side metal lines 109A and 109B, not only the first source / drain region 113 of the first FET at the first level but also the second source / drain region 123 of the second FET at the second level can be connected to the voltage source via the back side of the stacked semiconductor devices 100 in the semiconductor cell 10. Therefore, the semiconductor cell 10 can avoid heavy traffic on signal lines and power rails and an increase in contact resistance between structural elements on the front side of the semiconductor devices including the stacked semiconductor devices 11 and 12.

[0057] Furthermore, the stacked semiconductor devices 11 and 12 are formed symmetrically with respect to the side passage structure 117 along the D2 direction, such that the upper portion of the side passage structure 117 is connected to the right surface of the second source / drain region 123 in the first stacked semiconductor device 11, which vertically overlaps with the right surface of the first source / drain region 113 on which the side spacer 115S is located, and the left surface of the second source / drain region 123 in the second stacked semiconductor device 12, which vertically overlaps with the left surface of the first source / drain region 113 on which the side spacer 115S is located. This symmetrical formation of the stacked semiconductor devices 11 and 12 can be implemented to shorten the length of the upper portion of the side passage structure 117 in the D2 direction and reduce the cell height of the semiconductor cell 10.

[0058] However, with the increasing demand for scaled-down semiconductor cells, the fabrication of stacked semiconductor devices such as stacked semiconductor devices 11 and 12 has become more challenging. This is at least because the fabrication of the side-channel structure 117 with a high aspect ratio has very small process margins when further reduction in the spacing between two adjacent stacked semiconductor devices in the D2 direction is required. Figure 1B As shown, a side-channel structure 117 is required to extend further downward to contact the top surface of the back-side metal line 109B through the front-side isolation layer 116, the STI structure 102, and the back-side isolation layer 106. Therefore, the risk of misalignment between the side-channel structure 117 and the back-side metal line 109B may increase during the process of manufacturing the semiconductor device 100.

[0059] Therefore, the following embodiments solve the difficulties in forming the side-channel structure 117 of the stacked semiconductor devices 11 and 12.

[0060] Figure 2 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more embodiments.

[0061] Reference corresponds to Figure 1B of Figure 2Semiconductor device 200 may include the same structural elements as semiconductor device 100, and therefore, repeated descriptions thereof may be omitted herein, and semiconductor device 200 may be described below using the same reference numerals or characters used to indicate these structural elements of semiconductor device 100.

[0062] However, the semiconductor device 200 may include different side-access structures 217, and also includes a back-side contact plug 205 on the side-access structure 217, which is surrounded by a deep trench isolation structure 203. The side-access structure 217 may have a smaller height than the side-access structure 117 of the semiconductor device 100, at least because the side-access structure 217 does not extend downward into the back-side isolation layer 106 to connect to the back-side metal line 109B. Instead, the back-side contact plug 205 can connect the side-access structure 217 to the back-side metal line 109B, thereby enabling the formation of a side-access structure 217 with a smaller height. The deep trench isolation structure 203 may surround the side surface of the back-side contact plug 205 and at least the lower portion of each of the back-side contact plugs 104.

[0063] The deep trench isolation structure 203 can be formed of an isolation or insulating material such as silicon nitride (e.g., Si3N4), but is not limited thereto. Alternatively, the deep trench isolation structure 203 can be formed of aluminum oxide (e.g., Al2O3). The back-side contact plug 205, which connects to the bottom surface of the side passage structure 217, can be formed of a metal or metal alloy, and can be the same as or different from the metal or metal alloy forming the side passage structure 217. (See reference later.) Figures 5A to 5N As described, the side-channel structure 217 and the back-side contact plug 205 thereon can be formed at different steps, and therefore, when observed in, for example, SEM or TEM, the bottom surface of the side-channel structure 217 and the top surface of the back-side contact plug 205 can form a connecting surface, interface, or junction between them, even if the two structures can be formed of the same metal or metal alloy. A deep trench isolation structure 203 can be used to form the back-side contact plugs 104 and 205 and can be retained when the semiconductor device 200 is completed.

[0064] Two adjacent deep trench isolation structures 203 of the plurality of deep trench isolation structures 203 surrounding the back-side contact plug 205 may be located on two opposite side surfaces of the back-side contact plug 205, and each of these two deep trench isolation structures 203 surrounding the back-side contact plug 205 may also be located on the lower side surface of the back-side contact plug 104, which is formed on the bottom surface of the first source / drain region 113 of each of the stacked semiconductor devices 11 and 12. Another deep trench isolation structure 203 may be formed on the opposite lower side surface of the back-side contact plug 104. The bottom surface of the deep trench isolation structure 203 may be at the same level as the bottom surfaces of the back-side contact plugs 104 and 205. The top surface of the deep trench isolation structure 203 may be at the same level as the bottom surface of the STI structure 102 and the top surface of the back-side isolation layer 106.

[0065] The top surface of the deep trench isolation structure 203 for the back contact plugs 104 and 205 can be connected to the bottom surface of the STI structure 102, and the bottom surface of the deep trench isolation structure 203 can be buried in the back isolation layer 106 and can be connected to a portion of the back metal wire 109B.

[0066] Since the back-side contact plug 205, surrounded by the deep trench isolation structure 203, is formed in the semiconductor device 200, the aspect ratio of the side-channel structure 217 can be reduced compared to the side-channel structure 117 of the semiconductor device 100, facilitating the formation of the side-channel structure 217 through the front isolation layer 116 and the STI structure 102. For example, since the height of the side-channel structure 217 of the semiconductor device 200 is smaller than the height of the side-channel structure 117 of the semiconductor device 100, the process allowance for forming the side-channel structure 217 can be increased, and therefore, in the process of manufacturing the semiconductor device 200, the risk of misalignment between the side-channel structure 217 and the back-side metal line 109B can be reduced due to the back-side contact plug 205.

[0067] As described above, the semiconductor device 200 can be characterized by back-side contact plugs 104 and 205 and a deep trench isolation structure 203 for forming these back-side contact plugs 104 and 205, and retains the finished form of the semiconductor device 200. However, the back-side contact plugs 205 can be formed differently when manufacturing a semiconductor device including stacked semiconductor devices.

[0068] Figure 3 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more other embodiments.

[0069] Reference corresponds to Figure 2 of Figure 3Semiconductor device 300 may include the same structural elements as semiconductor device 200, and therefore, repeated descriptions thereof may be omitted herein, and semiconductor device 300 may be described below using the same reference numerals or characters used to indicate these structural elements of semiconductor device 200.

[0070] However, the difference between semiconductor device 300 and semiconductor device 200 lies in the fact that the two deep trench isolation structures 303 may only surround the two opposite side surfaces of the back contact plugs 205 on the side passage structure 217, while the deep trench isolation structure 203 of semiconductor device 200 surrounds at least the lower portion of each of the back contact plugs 104 and the back contact plug 205. Therefore, in semiconductor device 300, deep trench isolation structures may not be formed on the side surfaces of the back contact plugs 104 that are respectively connected to the bottom surface of the first source / drain region 113. Instead, the back isolation layer 106 may be on the lower side surface of the back contact plug 104, and the STI structure 102 may be on the upper side surface of the back contact plug 104. Furthermore, the bottom surface of the deep trench isolation structure 303 can be at the same level as the bottom surface of the back contact plug 205, and the top surface of the deep trench isolation structure 303 can be at the same level as the top surface of the back contact plug 205 and the bottom surface of the STI structure 102.

[0071] This deep trench isolation structure 303 can be formed from the same isolation or insulating material that forms the deep trench isolation structure 203. The deep trench isolation structure 303 can be used to form only the back-side contact plug 205 on the side passage structure 217 and is retained in the semiconductor device 300 when the semiconductor device 300 is completed. In the semiconductor device 200, the deep trench isolation structure 203 can be used to form the back-side contact plug 104 on the first source / drain region 113 and the back-side contact plug 205 on the side passage structure 217, and is retained when the semiconductor device 200 is completed.

[0072] Meanwhile, the side passage structures 117 and 217 formed in the semiconductor devices 100, 200, and 300 of the above embodiments are formed as a single continuous structure without connecting surfaces, interfaces, or junctions between the wing portion and the passage portion, as described above. However, this disclosure is not limited thereto, such as Figure 3 As shown.

[0073] Figure 4 A semiconductor device including a back-side contact plug and a side-channel structure for the source / drain regions is shown according to one or more other embodiments.

[0074] Reference corresponds to Figure 3 of Figure 4Semiconductor device 400 may include the same structural elements as semiconductor device 300, and therefore, repeated descriptions thereof may be omitted herein, and semiconductor device 400 may be described below using the same reference numerals or characters used to indicate these structural elements of semiconductor device 300.

[0075] However, the difference between semiconductor device 400 and semiconductor device 300 lies in that the side passage structure 417 is formed by three different structural elements (two front contact structures 417C and a passage structure 417V). The front contact structure 417C can be connected to the right side surface of the second source / drain region 123 of the first stacked semiconductor device 11 and the left side surface of the second source / drain region 123 of the second stacked semiconductor device 12, respectively, and the passage structure 417V can be connected to the back metal line 109B through the back contact plug 205 thereon.

[0076] The front contact structure 417C and the via structure 417V of the semiconductor device 400 can correspond to the wing portion 217C and the via portion 217V of the side via structure 217 of the semiconductor device 300, respectively. The via structure 417V can be formed at a step different from the step of forming the front contact structure 417C, and therefore, when observed in, for example, SEM or TEM, a connecting surface, interface, or junction can be formed between them, even if these structures can be formed of the same metal or metal alloy.

[0077] The following provides a method for manufacturing a semiconductor device according to one or more embodiments, the semiconductor device including a back-side contact plug and a side-channel structure for source / drain regions.

[0078] Figures 5A to 5N The manufacturing process according to one or more embodiments is illustrated. Figure 2 The intermediate semiconductor device obtained after the corresponding steps of the illustrated semiconductor device 200 includes back-side contact plugs and side-channel structures for the source / drain regions. In the following description, repeated descriptions, including those concerning materials and structures, may be omitted, and the same reference numerals may be used in the hereinafter description.

[0079] refer to Figure 5A An intermediate semiconductor device 200' can be formed by epitaxially growing multiple semiconductor layers (nanosheet layers) on a substrate 101'.

[0080] The semiconductor layers can be epitaxially grown from the substrate 101' in the following order: a lower stack including a first sacrificial layer 111 and a first channel layer 112 stacked vertically in an alternating manner; an intermediate sacrificial layer 115'; and an upper stack including a second sacrificial layer 121 and a second channel layer 122 stacked vertically on the intermediate sacrificial layer 115' in an alternating manner. (References herein) Figures 5A to 5N The first channel layer 112 and the second channel layer 122 described may refer to... Figures 2 to 4 The first channel structure 112 and the second channel structure 122 are described.

[0081] The substrate 101' and channel layers 112 and 122 are formed of silicon (Si), while the sacrificial layers 111, 115', and 121 can be formed of silicon-germanium (SiGe) having corresponding Ge concentrations. The intermediate sacrificial layer 115' can have a higher Ge concentration than the first sacrificial layer 111 and the second sacrificial layer 121. For example, the intermediate sacrificial layer 115' can have a Ge concentration of 40-45%, and the first sacrificial layer 111 and the second sacrificial layer 121 can have a Ge concentration of 25-30%.

[0082] Here, sacrificial layers 111, 115' and 121 are referred to as such because in later steps of manufacturing the semiconductor device from the intermediate semiconductor device 200', these layers will be removed and replaced by other layers or structures.

[0083] refer to Figure 5B The intermediate semiconductor device 200' can be patterned to obtain a first semiconductor stack 11' and a second semiconductor stack 12' facing each other on the substrate 101', and furthermore, the substrate 101' can be patterned to form a shallow trench ST thereon.

[0084] The intermediate semiconductor device 200' can be patterned into two semiconductor stacks 11' and 12', such that the upper stack of each of the two semiconductor stacks 11' and 12' has a smaller width than the lower stack having the intermediate sacrificial layer 115' thereon, and the two semiconductor stacks 11' and 12' face each other in the D2 direction, with a first recess R0 between them. For example, the patterning can be performed such that the lower stack partially overlaps in the D3 direction. Furthermore, the patterning can be performed such that the right surface of the first semiconductor stack 11', formed by the right surfaces of its lower stack, intermediate sacrificial layer 115', and upper stack that are perpendicularly aligned or coplanar with each other, faces the left surface of the second semiconductor stack 12', formed by the left surfaces of its lower stack, intermediate sacrificial layer 115', and upper stack that are perpendicularly aligned or coplanar with each other. Here, the lower stack and upper stack of each of the semiconductor stacks 11' and 12' can respectively refer to... Figure 1A The first active pattern 110 and the second active pattern 120 are shown.

[0085] Furthermore, the patterning of substrate 101' can be achieved by forming multiple shallow trenches ST in the substrate at locations where they do not overlap with the two semiconductor stacks 11' and 12'. For example, the shallow trenches ST can be formed on the left side of the first semiconductor stack 11', the right side of the second semiconductor stack 12', and on substrate 101' between the first semiconductor stack 11' and the second semiconductor stack 12'. A portion of substrate 101' having protrusions between the shallow trenches ST can be referred to as an active region, which can be doped with impurities or dopants. For the first semiconductor stack 11' and the second semiconductor stack 12', a first active region AR1 and a second active region AR2 can be formed on substrate 101', respectively. The patterning of the intermediate semiconductor device 200' and substrate 101' in this step can be performed, for example, by dry etching (e.g., reactive ion etching (RIE)) based on a pseudo-gate structure with a hard mask pattern thereon.

[0086] refer to Figure 5C Multiple deep trenches DT can be formed in the substrate 101' at each side of the active regions AR1 and AR2 in the shallow trench ST.

[0087] For example, deep trench DT can be achieved through a later step ( Figure 5N The back contact plugs and side passage structures for the source / drain regions are formed from a portion of the top patterned substrate 101'.

[0088] To form a deep trench (DT), an additional hard mask pattern on substrate 101' can be used to perform another dry etching operation (e.g., RIE) after forming a shallow trench (ST).

[0089] refer to Figure 5D Multiple deep trench isolation structures 203 can be formed in the corresponding deep trench DT, and shallow trench isolation (STI) structures 102 can be formed in the shallow trench ST.

[0090] The deep trench isolation structure 203 can be formed by depositing silicon nitride (e.g., Si3N4) or aluminum oxide (e.g., Al2O3) in a deep trench DT using, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof, followed by planarization using, for example, chemical mechanical polishing (CMP). Subsequently, the STI structure 102 can be formed on a substrate 101' in a shallow trench ST by depositing silicon oxide (e.g., SiO2) using, for example, CVD, PVD, PECVD, or a combination thereof, followed by planarization using, for example, CMP. Thus, the bottom surface of the STI structure 102 can be on or in contact with the top surfaces of the substrate 101' and the deep trench isolation structure 203.

[0091] refer to Figure 5E The intermediate sacrificial layer 115' can be removed and replaced by an intermediate isolation layer 115 surrounding each of the lower and upper stacks of semiconductor stacks 11' and 12'.

[0092] The removal of the intermediate sacrificial layer 115' can be performed, for example, by wet etching using an etchant such as an ammonia-peroxide mixture, which removes the intermediate sacrificial layer 115' of SiGe with a high Ge concentration, while the silicon (Si) channel layers 112 and 122 and the sacrificial layers 111 and 121 of SiGe with a low Ge concentration are not etched or are etched by the etchant to a minimum.

[0093] Furthermore, an isolation material such as SiBCN, SiCN, SiOC, SiOCN, SiN, Si3N4, etc., can fill the space where the intermediate sacrificial layer 115' has been removed, thereby forming an intermediate isolation layer 115. The formation of the intermediate isolation layer 115 can be performed, for example, by ALD or PEALD. In this case, the intermediate isolation layer 115 can be laid out to conformally surround the outer contours of both the lower and upper stacks of each of the semiconductor stacks 11' and 12', as well as the top surface of the STI structure 102.

[0094] The intermediate isolation layer 115 can be formed to isolate the channel structure to be formed from the bottom stack and the channel structure to be formed from the top stack in each of the semiconductor stacks 11' and 12'.

[0095] refer to Figure 5FEach of the first semiconductor stack 11' and the second semiconductor stack 12' can be patterned to form spaces S1 and S2, where a lower source / drain region and an upper source / drain region above it will be formed. Furthermore, the substrate 101' exposed by the patterning of the semiconductor stacks 11' and 12' can be patterned to form placeholder recesses PR1 and PR2. At this time, the intermediate isolation layer 115 can also be patterned to remain only as a side spacer 115S between the lower and upper stacks of each of the semiconductor stacks 11' and 12' and on the side surfaces of the lower stacks facing each other in the D2 direction.

[0096] The upper and lower stacks of each of the semiconductor stacks 11' and 12' (i.e., the second active pattern 120 and the first active pattern 110 below it) Figure 1A )) can be achieved through, for example, such as Figure 1A The dummy gate structures 150 shown are patterned by dry or wet etching to form spaces S1 and S2 therein, in which source / drain regions for the first semiconductor stack 11' and the second semiconductor stack 12' will be formed in later steps.

[0097] When the upper and lower stacks are patterned to form spaces S1 and S2, the intermediate isolation layer 115 surrounding the outer contours of the upper and lower stacks can also be patterned from the top. Therefore, the intermediate isolation layer 115 can be removed from the top surface, left and right surfaces of the upper stack, the top surface of the lower stack (which is not perpendicularly overlapped by the upper stack), the left surface of the lower stack, and the top surface of the STI structure 102. However, at this time, the intermediate isolation layer 115 can remain in the space between the upper and lower stacks without being patterned to isolate the two channel structures that will be formed from the upper and lower stacks in a later step. Furthermore, the intermediate isolation layer 115 can also remain as a side spacer 115S at the side surface of the lower stack, which is perpendicularly aligned with or coplanar with the side surface of the upper stack above it.

[0098] In the first semiconductor stack 11', the intermediate isolation layer 115 may be retained as a side spacer 115S on the right side surface of the lower stack, which is perpendicularly aligned with or coplanar with the right side surface of the upper stack, although its upper portion may be partially removed. This residual structure of the intermediate isolation layer 115 may be retained on the right side surface of the lower stack due to the different widths of the lower and upper stacks in the D2 direction and the alignment and coplanarity of the right side surfaces of the upper and lower stacks.

[0099] For example, when forming the space S1 for the upper source / drain region and the lower source / drain region, the intermediate isolation layer 115 formed on the left side surface of the upper stack and the intermediate isolation layer 115 formed on the right side surface of the upper stack can be removed simultaneously because these two portions of the intermediate isolation layer 115 have the same vertical length from the top surface. At this time, the intermediate isolation layer 115 formed on the left side surface of the lower stack can also be removed. This is because the left side surface of the lower stack is not overlapped by the upper stack, and therefore, it undergoes patterning of the intermediate isolation layer 115 on the side surface of the upper stack simultaneously. Furthermore, the intermediate isolation layer 115 formed on the left side surface of the lower stack has a smaller vertical length than the intermediate isolation layer 115 formed on the side surface of the upper stack. Therefore, when undergoing the same patterning simultaneously, the intermediate isolation layer 115 on the left side surface of the lower stack can be patterned earlier than the intermediate isolation layer 115 on the side surface of the upper stack.

[0100] When the intermediate isolation layer 115 is removed from the side surface of the upper stack, the intermediate isolation layer 115 formed on the top surface of the upper stack, the top surface of the lower stack that is not overlapped by the upper stack, and the top surface of the STI structure 102 can also be removed. This is because these portions of the intermediate isolation layer 115 undergo the same patterning as the intermediate isolation layer 115 on the side surface of the upper stack, and have a smaller vertical length than the intermediate isolation layer 115 on the side surface of the upper stack.

[0101] Therefore, when the intermediate isolation layer 115 is removed from the top surface, left surface and right surface of the upper stack, the top surface of the lower stack which is not vertically overlapped by the upper stack, the left surface of the lower stack and the top surface of the STI structure 102, the intermediate isolation layer 115 can still remain at the right surface of the lower stack as a side spacer 115S.

[0102] For the same reasons as described above, the intermediate isolation layer 115 formed in the second semiconductor stack 12' can be retained in the space between the lower stack and the upper stack as a side spacer 115S on the left side surface of the lower stack.

[0103] After patterning the upper and lower stacks and the intermediate isolation layer 115, the substrate 101' exposed below the spaces S1 and S2 formed by patterning the lower and upper stacks can be patterned to form placeholder recesses PR1 and PR2, in which corresponding placeholder structures will be formed in the next step. Placeholder structures are formed in these two placeholder recesses PR1 and PR2 to reserve space for back-side contact plugs that will be formed on the bottom surface of the source / drain regions in a later step. The patterning operations for forming spaces S1 and S2 and the placeholder recesses PR1 and PR2 below them can be performed, for example, by dry etching or wet etching.

[0104] refer to Figure 5G The recesses PR1 and PR2 of the spacer can be filled with spacer structures P1 and P2, respectively.

[0105] The occupant structures P1 and P2 can be obtained from the substrate 101' that forms the inner surfaces of the occupant recesses PR1 and PR2 in the previous step ( Figure 5F Epitaxial growth is performed in spaces S1 and S2 obtained in the STI structure 102, such that the top surface of each of the occupant structures P1 and P2 can be at the same level as the top surface of the STI structure 102 and the corresponding bottom surfaces of the bottommost sacrificial layer 111 and the side spacers 115S. The occupant structures P1 and P2 can be formed of silicon germanium (SiGe).

[0106] refer to Figure 5H The first source / drain region 113 and the second source / drain region 123 can be formed in a previous step ( Figure 5F In each of the lower and upper stacks of patterned semiconductor stacks 11' and 12', spaces S1 and S2 are obtained, and a front isolation layer 116 can be formed around semiconductor stacks 11' and 12' to form a first stacked semiconductor device 11 and a second stacked semiconductor device 12.

[0107] The first source / drain region 113 can be epitaxially grown from the first channel layer 112 formed by removing the first sacrificial layer 111 in spaces S1 and S2, and the second source / drain region 123 can be epitaxially grown from the second channel layer 122 formed by removing the first sacrificial layer 111 in spaces S1 and S2. When performing the epitaxial growth of the source / drain regions 113 and 123, n-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb) can be in-situ doped in the epitaxial structure for the first source / drain region 113, and p-type impurities such as boron (B), gallium (Ga), or indium (In) can be in-situ doped in the epitaxial structure for the second source / drain region 123.

[0108] When the first source / drain region 113 grows from the first channel layer 112 of the first semiconductor stack 11', the right side surface of the first source / drain region 113 can contact the side spacers 115S formed on the right side surface of the lower stack of the first semiconductor stack 11'. Similarly, the left side surface of the first source / drain region 113 grown from the first channel layer 112 of the second semiconductor stack 12' can contact the side spacers 115S formed on the left side surface of the lower stack of the second semiconductor stack 12'. Therefore, the entire right side surface of one first source / drain region 113 and the entire left side surface of the other first source / drain region 113 can be covered by the corresponding side spacers 115S.

[0109] When forming source / drain regions 113 and 123, the front isolation layer 116 can be formed around the semiconductor stacks 11' and 12' to isolate the semiconductor stacks 11' and 12' from each other or from other circuit elements. The front isolation layer 116 can be formed by depositing a low-k material such as silicon oxide (e.g., SiO2) using methods such as CVD, PVD, or PECVD. Since the front isolation layer 116 surrounds the semiconductor stacks 11' and 12', the first recess R0 formed therebetween can also be filled with the front isolation layer 116.

[0110] After the first front-side isolation layer 116 is formed, the dummy gate structures and sacrificial layers 111 and 121 surrounding the semiconductor stacks 11' and 12' can be removed and replaced with corresponding gate structures 150 surrounding the channel layers 112 and 122.

[0111] refer to Figure 5I The side-channel structure 217 can be formed in the front isolation layer 116 to contact the second source / drain region 123 of the semiconductor stacks 11' and 12', and extend downward to contact the top surface of the substrate 101' through the STI structure 102 between the stacked semiconductor devices 11 and 12.

[0112] Side pathway structure 217 can be formed to pass through in a later step ( Figure 5N The back-side contact plug and back-side metal wire formed in the second source / drain region 123 connect the second source / drain region 123 to the positive voltage source.

[0113] To form the side-channel structure 217, the front isolation layer 116 can be patterned therein, for example, by dry etching or wet etching, to form a recess R1 that exposes at least a portion of the top surface and at least a portion of the side surface of each of the second source / drain regions 123 and a portion of the top surface of the substrate 101' between the semiconductor stacks 11' and 12'. Subsequently, the side-channel structure 217 can be formed in the recess R1 by depositing metal or metal alloy in the recess R1, for example, using CVD, PVD, PECVD, or a combination thereof, and then planarized using, for example, a CMP operation, such that the side-channel structure 217 can connect at least a portion of the top surface and at least a portion of the side surface of each of the second source / drain regions 123 to a portion of the top surface of the substrate 101' between the semiconductor stacks 11' and 12'.

[0114] like Figure 5IAs shown, the side-channel structure 217 may have a “T” shape formed by wing portions 217C and channel portions 217V. Each of the wing portions 217C may be connected to at least a portion of the top surface and at least a portion of the side surface of the second source / drain region 123 of each of the semiconductor stacks 11' and 12'. The channel portion 217V may extend horizontally and vertically downward from the top surface of the front isolation layer 116 in the recess R1 through the STI structure 102 formed between the semiconductor stacks 11' and 12' on the substrate 101'.

[0115] The wing portion 217C and the passage portion 217V can be formed simultaneously by a single deposition operation to form the side passage structure 217, and therefore, when observed in, for example, SEM or TEM, no connecting surface, interface, or junction may be formed between the wing portion 217C and the passage portion 217V. However, the wing portion 217C may be formed at a different step than the step of forming the passage portion 217V, in which case the side passage structure 217 may have a similar appearance to that formed by... Figure 4 The front contact structure 417C and the passage structure 417V shown form the same side passage structure 417. In this case, when observed in, for example, SEM or TEM, a connecting surface, interface or junction may be formed between the wing portion 217C and the passage portion 217V, even if these structures may be formed of the same metal or metal alloy.

[0116] Here, since the aspect ratio of the side passage structure 217 can be smaller than that of the side passage structure 117, the side passage structure 117 penetrates into the back-side isolation layer 106 of the replacement substrate 101' (e.g., Figure 1B As shown), the formation of the side passage structure 217 can be easier than that of the side passage structure 117 in the front isolation layer 116.

[0117] refer to Figure 5J Additional insulating material is formed on the top surface of the front insulating layer 116 to extend the front insulating layer 116, and multiple front metal lines 119 can be formed above the side passage structure 217.

[0118] The front isolation layer 116 can be extended by depositing an isolation material such as silicon oxide (e.g., SiO2) on the top surface of the front isolation layer 116, for example using CVD, PVD, PECVD or combinations thereof, and then planarizing it using, for example, a CMP operation.

[0119] In the extended front isolation layer 116, front metal lines 119 can be formed using the same or different metal or metal alloy as the side via structure 217, through, for example, a damascene process or a direct etching operation. Front metal lines 119 can be provided to connect other circuit elements of the semiconductor stacks 11' and 12' to positive voltage sources, negative voltage sources, or other circuit elements of other semiconductor devices.

[0120] refer to Figure 5K The substrate 101' can be thinned to expose the occupant structures P1 and P2 and the deep trench isolation structure 203, and the remaining substrate 101' can be removed and replaced by the back side isolation layer 106.

[0121] The substrate 101' can be thinned by, for example, a back-side thinning operation in which the substrate 101' is mechanically ground to expose the bottom surfaces of the occupant structures P1 and P2 and the deep trench isolation structure 203, and then dry or wet etching is performed to remove the remaining substrate 101' surrounding the occupant structures P1 and P2 and the deep trench isolation structure 203.

[0122] The space obtained by removing the substrate 101' can be filled with a low-k material such as silicon oxide (e.g., SiO2) to form a back-side isolation layer 106, which is then planarized using, for example, a CMP operation to expose the bottom surfaces of the occupant structures P1 and P2 and the deep trench isolation structure 203 again.

[0123] To perform the substrate removal operation in this step and the subsequent back-side operation, the substrate removal operation in the previous step ( Figure 5J The intermediate semiconductor device 200' obtained is inverted to facilitate back-side operation.

[0124] refer to Figure 5L A portion of the back side isolation layer 106 vertically below the side passage structure 217 can be removed based on the two adjacent deep trench isolation structures 203 between the semiconductor stacks 11' and 12' to form a first back side recess BR1 in the back side isolation layer 106 to expose the bottom surface of the side passage structure 217.

[0125] The removal of a portion of the back-side isolation layer 106 in this step can be performed, for example, by dry etching or wet etching of the back-side isolation layer 106 between two adjacent deep trench isolation structures 203, at a position vertically below the side passage structure 217, using an etchant such as hydrofluoric acid (HF). This etchant selectively etches the silicon oxide (e.g., SiO2) forming the back-side isolation layer 106 relative to the material forming the deep trench isolation structure 203 (e.g., Si3N4 or Al2O3).

[0126] refer to Figure 5M The back-side isolation layer 106 surrounding the occupant structures P1 and P2, as well as the occupant structures P1 and P2, can be removed to form a second back-side recess BR2 to expose the bottom surface of the first source / drain region 113 of the corresponding semiconductor stacks 11' and 12'.

[0127] Similar to the previous steps ( Figure 5L The removal of the back-side isolation layer 106 can be performed, for example, by dry etching or by wet etching using an etchant such as hydrofluoric acid (HF) relative to the material forming the two adjacent deep trench isolation structures 203 (e.g., Si3N4 or Al2O3), forming berth structures P1 and P2 with the back-side isolation layer 106 thereon between the two adjacent deep trench isolation structures 203. The removal of the berth structures P1 and P2 can be performed, for example, by dry etching or wet etching using an etchant such as an ammonia-peroxide mixture, which selectively etches the material forming the berth structures P1 and P2 (e.g., SiGe) relative to the material forming the deep trench isolation structure 203 (e.g., Si3N4 or Al2O3) and the silicon oxide (e.g., SiO2) forming the back-side isolation layer 106.

[0128] refer to Figure 5N The back-side recesses BR1 and BR2 on the bottom surfaces of the exposed side passage structure 217 and the first source / drain region 113 can be filled with back-side contact plugs 205 and 104 respectively, thereby completing the semiconductor device 200.

[0129] A metal or metal alloy similar to or different from the metal or metal alloy of the side passage structure 217 can be filled in the back recesses BR1 and BR2 by means of, for example, CVD, PVD, PECVD, etc., to form a back contact plug 205 on the bottom surface of the side passage structure 217 and a back contact plug 104 on the bottom surface of the corresponding first source / drain regions 113 of the stacked semiconductor devices 11 and 12.

[0130] Subsequently, the back-side isolation layer 106 can be extended by depositing an isolation material such as silicon oxide (e.g., SiO2) on the bottom surface of the back-side isolation layer 106, the deep trench isolation structure 203, and the back-side contact plugs 205 and 104, for example, using CVD, PVD, PECVD, or combinations thereof, and then planarizing it using, for example, a CMP operation.

[0131] In the extended back-side isolation layer 106, multiple back-side metal lines 109A and 109B can be formed using the same or different metal or metal alloy as the back-side contact plugs 205 and 104, through processes such as damascus etching or direct etching. Back-side metal lines 109A and 109B can be provided to connect other circuit elements of the stacked semiconductor devices 11 and 12 to positive voltage sources, negative voltage sources, or other circuit elements of other semiconductor devices.

[0132] The back-side metal line 109A can connect a negative voltage source to the first source / drain region 113 via the back-side contact plug 104, and the back-side metal line 109B can connect a positive voltage source to the second source / drain region 123 via the back-side contact plug 205 and the side passage structure 217.

[0133] Therefore, the first semiconductor stack 11' and the second semiconductor stack 12' can be formed as a first stacked semiconductor device 11 and a second stacked semiconductor device 12, respectively. In each first stacked semiconductor device 11 and the second stacked semiconductor device 12, the lower stack forms an NFET and the upper stack forms a PFET to complete the stacked semiconductor device 200.

[0134] Figure 6A and Figure 6B Manufacturing according to one or more embodiments, such as Figure 2 The flowchart shown is of a semiconductor device 200, which includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0135] To pass Figure 6A and Figure 6B The semiconductor device formed by the flowchart can be compared with the reference Figures 5A to 5N The manufactured semiconductor devices are identical or similar to 200.

[0136] In step S10, an initial semiconductor stack including a lower stack and an upper stack is provided on a substrate and patterned to form a first semiconductor stack and a second semiconductor stack, wherein shallow trenches are present on the substrate at the sides of each of the semiconductor stacks and between the semiconductor stacks.

[0137] In step S20, the top surface of the substrate exposed through the shallow trenches can be patterned to form deep trenches, which are then filled with deep trench isolation structures. The deep trenches can be formed by patterning portions of the substrate at locations where back-side contact plugs and side-channel structures for source / drain regions are formed therebetween in a later step. The deep trench isolation structures can be formed of silicon nitride or aluminum oxide.

[0138] In step S30, a shallow trench isolation (STI) structure can be formed on the deep trench isolation structure in the shallow trench.

[0139] In step S40, the two semiconductor stacks at the location where the source / drain regions are to be formed and the substrate below them can be patterned to form corresponding placeholder recesses.

[0140] In step S50, a occupant structure can be formed in the occupant recess, and a first source / drain region and a second source / drain region can be formed on the lower and upper stacks of each of the two semiconductor stacks.

[0141] In step S60, a front isolation layer may be formed to surround the source / drain region, and a side passage structure may be formed in the front isolation layer, the side passage structure connecting to the second source / drain region of the two semiconductor stacks and connecting to a portion of the top surface of the substrate between the top surfaces of the adjacent deep trench isolation structures formed between the two semiconductor stacks.

[0142] In step S70, the substrate may be removed and replaced by a back-side isolation layer, which is patterned at a location between two adjacent deep trench isolation structures formed between two semiconductor stacks to form a first back-side recess on the bottom surface of the exposed side-channel structure.

[0143] In step S80, the occupier structure may be removed to form a second back-side recess that exposes the bottom surface of the first source / drain region respectively.

[0144] In step S90, the back side recess can be filled with corresponding back side contact plugs connected to the bottom surface of the first source / drain region and the side passage structure of the two semiconductor stacks, and then back side metal lines connected to the back side contact plugs are formed respectively.

[0145] Figures 7A to 7N The manufacturing process according to one or more embodiments is illustrated. Figure 3 The intermediate semiconductor device obtained after the corresponding steps of the illustrated semiconductor device 300 includes back-side contact plugs and side-channel structures for the source / drain regions. In the following description, repeated descriptions, including those concerning materials and structures, may be omitted, and the same reference numerals may be used in the hereinafter description.

[0146] refer to Figure 7A and Figure 7B An intermediate semiconductor device 300' can be formed by epitaxially growing multiple semiconductor layers (nanosheet layers) on a substrate 101', and the intermediate semiconductor device 300' can be patterned to obtain a first semiconductor stack 11' and a second semiconductor stack 12' facing each other on the substrate 101', and the substrate 101' can also be patterned to form a shallow trench ST thereon. Because these steps are consistent with reference... Figure 5Aand Figure 5B The steps described are the same, so their repeated description can be omitted in this article.

[0147] refer to Figure 7C A deep trench DT can be formed in the substrate 101' between two semiconductor stacks 11' and 12' in a shallow trench ST.

[0148] For example, deep trench DT can be achieved in a later step ( Figure 7N The location of the back contact plug for the side passage structure is formed from a portion of the top patterned substrate 101'.

[0149] To form a deep trench (DT), an additional hard mask pattern on substrate 101' can be used to perform another dry etching operation (e.g., RIE) after forming a shallow trench (ST).

[0150] refer to Figure 7D A deep trench isolation structure 303 can be formed in a deep trench DT, and a shallow trench isolation (STI) structure 102 can be formed in a shallow trench ST.

[0151] The deep trench isolation structure 303 can be formed by depositing silicon nitride (e.g., Si3N4) or aluminum oxide (e.g., Al2O3) in a deep trench DT using, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof, followed by planarization using, for example, chemical mechanical polishing (CMP). Subsequently, the STI structure 102 can be formed on the substrate 101' in a shallow trench ST by depositing silicon oxide (e.g., SiO2) using, for example, CVD, PVD, PECVD, or a combination thereof, followed by planarization using, for example, CMP. Thus, the bottom surface of the STI structure 102 between the semiconductor stacks 11' and 12' can be on the top surface of the substrate 101' and the deep trench isolation structure 303, or in contact with the top surface of the substrate 101' and the deep trench isolation structure 303.

[0152] refer to Figure 7E The intermediate sacrificial layer 115' can be removed and replaced by an intermediate isolation layer 115 surrounding each of the lower and upper stacks of semiconductor stacks 11' and 12'. This step is consistent with the reference... Figure 5E The steps described are the same, so repeated descriptions can be omitted here.

[0153] refer to Figure 7FEach of the first semiconductor stack 11' and the second semiconductor stack 12' can be patterned to form a space in which a lower source / drain region and an upper source / drain region above it will be formed. Furthermore, the substrate 101' exposed by the patterning of the semiconductor stacks 11' and 12' can be patterned to form placeholder recesses PR1 and PR2 therein. At this time, the intermediate isolation layer 115 can also be patterned to remain only as a side spacer 115S between the lower and upper stacks of each of the semiconductor stacks 11' and 12' and at the side surfaces of the lower stacks facing each other in the D2 direction. Since this step is consistent with the reference... Figure 5F The steps described are the same, so repeated descriptions can be omitted here.

[0154] refer to Figure 7G and Figure 7H The recesses PR1 and PR2 can be filled with the spacer structures P1 and P2 respectively, and can be achieved through the previous steps ( Figure 7F In the patterned semiconductor stacks 11' and 12', a first source / drain region 113 and a second source / drain region 123 are formed in each of the spaces S1 and S2 obtained by the lower and upper stacks of each of the semiconductor stacks 11' and 12'. Furthermore, a front-side isolation layer 116 may be formed around the semiconductor stacks 11' and 12' to form a first stacked semiconductor device 11 and a second stacked semiconductor device 12. Because these steps are consistent with reference to... Figures 5G to 5H The steps described are the same, so repeated descriptions can be omitted here.

[0155] refer to Figure 7I The side-channel structure 217 can be formed in the front isolation layer 116 to contact the second source / drain region 123 of the semiconductor stacks 11' and 12', and extend downward to contact the top surface of the deep trench isolation structure 303 formed in the substrate 101' through the STI structure 102 between the stacked semiconductor devices 11 and 12.

[0156] Side pathway structure 217 can be formed to pass through in a later step ( Figure 7N The back-side contact plug and back-side metal wire formed in the second source / drain region 123 connect the second source / drain region 123 to the positive voltage source.

[0157] To form the side-channel structure 217, the front isolation layer 116 can be patterned therein, for example, by dry etching or wet etching, to form a recess R1 that exposes at least a portion of the top surface and at least a portion of the side surface of each of the second source / drain regions 123, as well as a portion of the top surface of the deep trench isolation structure 303 formed in the substrate 101' between the semiconductor stacks 11' and 12'. Subsequently, the side-channel structure 217 can be formed in the recess R1 by depositing metal or metal alloy in the recess R1, for example, using CVD, PVD, PECVD, or a combination thereof, and then planarized using, for example, a CMP operation, such that the side-channel structure 217 can connect at least a portion of the top surface and at least a portion of the side surface of each of the second source / drain regions 123 to a portion of the top surface of the deep trench isolation structure 303 between the semiconductor stacks 11' and 12'.

[0158] The structural characteristics of the side passage structure 217 in the intermediate semiconductor device 300' can be the same as those of the side passage structure 217 in the intermediate semiconductor device 200', and therefore, its repeated description can be omitted here.

[0159] refer to Figure 7J Additional insulating material is formed on the top surface of the front insulating layer 116 to extend the front insulating layer 116, and multiple front metal lines 119 can be formed above the side passage structure 217. Because this step is similar to the reference... Figure 5J The steps described are the same, so repeated descriptions can be omitted here.

[0160] refer to Figure 7K The substrate 101' can be thinned to expose the occupant structures P1 and P2 and the deep trench isolation structure 303, and the remaining substrate 101' can be removed and replaced by the back side isolation layer 106.

[0161] The substrate 101' can be thinned by, for example, a back-side thinning operation in which the substrate 101' is mechanically ground to expose the bottom surfaces of the occupant structures P1 and P2 and the deep trench isolation structure 303, and then dry or wet etching is performed to remove the remaining substrate 101' surrounding the occupant structures P1 and P2 and the deep trench isolation structure 303.

[0162] The space obtained by removing the substrate 101' can be filled with a low-k material such as silicon oxide (e.g., SiO2) to form a back-side isolation layer 106, which is then planarized using, for example, a CMP operation to expose the bottom surfaces of the occupant structures P1 and P2 and the deep trench isolation structure 303 again.

[0163] To perform the substrate removal operation in this step and the subsequent back-side operation, the substrate removal operation in the previous step ( Figure 7J The intermediate semiconductor device 300' obtained is inverted to facilitate back-side operation.

[0164] refer to Figure 7L The portion of the deep trench isolation structure 303 located vertically below the side passage structure 217 can be removed to form a first back recess BR1 in the deep trench isolation structure 303, thereby exposing the bottom surface of the side passage structure 217.

[0165] The removal of a portion of the deep trench isolation structure 303 in this step can be performed based on a hard mask pattern formed on the bottom surface of the deep trench isolation structure 303, by means of, for example, dry etching or wet etching using an etchant such as hot phosphoric acid, thereby exposing the bottom surface of the side passage structure 217 through the back recess BR1.

[0166] refer to Figure 7M The back-side isolation layer 106 surrounding the occupant structures P1 and P2 can be removed by means of, for example, dry etching or wet etching using an etchant such as hydrofluoric acid (HF) to form a second back-side recess BR2 to expose the bottom surface of the first source / drain regions 113 of the respective semiconductor stacks 11' and 12'.

[0167] refer to Figure 7N The back-side recesses BR1 and BR2 on the bottom surfaces of the exposed side passage structure 217 and the first source / drain region 113, respectively, can be filled with back-side contact plugs 205 and 104 to complete the semiconductor device 300. Since this step is similar to the reference... Figure 5N The steps described are the same, so repeated descriptions can be omitted here.

[0168] Figure 8A and Figure 8B Manufacturing according to one or more embodiments, such as Figure 3 The flowchart shown illustrates a semiconductor device 300, which includes a back-side contact plug and a side-channel structure for the source / drain regions.

[0169] To pass Figure 8A and Figure 8B The semiconductor device formed by the flowchart can be compared with the reference Figures 7A to 7N The manufactured semiconductor devices are the same as or similar to 300.

[0170] In step S10, an initial semiconductor stack including a lower stack and an upper stack is provided on a substrate and patterned to form a first semiconductor stack and a second semiconductor stack, wherein shallow trenches are present on the substrate at the sides of each of the semiconductor stacks and between the semiconductor stacks.

[0171] In step S20, the top surface of the substrate exposed by the shallow trench between the two semiconductor stacks can be patterned to form a deep trench, which is filled with a deep trench isolation structure. The deep trench can be formed by patterning a portion of the substrate at the location where a back-side contact plug for a side-channel structure is formed in a later step. The deep trench isolation structure can be formed of silicon nitride or aluminum oxide.

[0172] In step S30, a shallow trench isolation (STI) structure can be formed on the deep trench isolation structure in the shallow trench.

[0173] In step S40, the two semiconductor stacks at the location where the source / drain regions are to be formed and the substrate below them can be patterned to form corresponding placeholder recesses.

[0174] In step S50, a occupant structure can be formed in the occupant recess, and a first source / drain region and a second source / drain region can be formed on the lower and upper stacks of each of the two semiconductor stacks.

[0175] In step S60, a front isolation layer may be formed to surround the source / drain region, and a side passage structure may be formed in the front isolation layer to connect to the second source / drain region of the two semiconductor stacks and to a portion of the top surface of the deep trench isolation structure.

[0176] In step S70, the substrate can be removed and replaced by a back-side isolation layer, and the portion of the deep trench isolation structure vertically below the side passage structure can be removed to form a first back-side recess in the deep trench isolation structure to expose the bottom surface of the side passage structure.

[0177] In step S80, the occupier structure may be removed to form a second back-side recess that exposes the bottom surface of the first source / drain region respectively.

[0178] In step S90, the back side recess can be filled with corresponding back side contact plugs connected to the bottom surface of the first source / drain region and the side passage structure of the two semiconductor stacks, and then back side metal lines connected to the back side contact plugs are formed respectively.

[0179] In the above embodiments, each of the stacked semiconductor devices 11 and 12 has a channel structure of different widths and a source / drain region of different widths at the first and second levels. However, this disclosure is not limited thereto. According to one or more embodiments, Figures 2 to 4The side passage structures 217 and 417, the back-side contact plugs 205 on the side passage structures 217 and 417, and the deep trench isolation structures 203 and 303 shown can also be formed in a semiconductor device formed of stacked semiconductor devices having channel structures of the same width and source / drain regions of the same width at a first level and a second level. In this case, the side spacer 115S may not be formed on the side surface of the first source / drain region at the first level. Furthermore, according to one or more embodiments, Figures 2 to 4 The side-access structures 217 and 417, the back-side contact plugs 205 on the side-access structures 217 and 417, and the deep trench isolation structures 203 and 303 shown can be formed in a semiconductor device comprising a single stacked semiconductor device. For example, the semiconductor device 200 can be formed to include only the second FET at the second level and not the first FET at the first level. In this case, the back-side contact plugs 104 can be connected to the second source / drain region 123, while the side-access structures 217 remain connected to the second source / drain region 123.

[0180] Furthermore, according to one or more embodiments, at least one of the first FET and the second FET forming the stacked semiconductor devices 11 and 12 can be replaced by a different type of FET (e.g., FinFET) other than nanosheet transistors.

[0181] In the above embodiments, semiconductor devices 100, 200, 300, and 400 can all form inverter circuits in semiconductor cell 10. For this purpose, side-access structures 117, 217, and 417 connect the second source / drain region 123 to a positive voltage source, and the back-side contact plug 104 connects the first source / drain region 113 to a negative voltage source. However, this disclosure is not limited thereto. According to one or more embodiments, an inverter circuit can be formed... Figures 2 to 4 The side path structures 117, 217 and 417 shown, the back contact plugs 205 on the side path structures 217 and 417, and the deep trench isolation structures 203 and 303 are used to connect at least one of the first source / drain region 113 and the second source / drain region 123 to another circuit element for signal routing purposes, thereby forming different types of circuits or logic circuits.

[0182] Figure 9 This is a schematic block diagram illustrating an electronic device including one or more semiconductor devices according to one or more embodiments, the one or more semiconductor devices including back-side contact plugs and side-channel structures for source / drain regions. According to one or more embodiments, the semiconductor devices of the electronic device may include... Figure 1B , Figure 2 , Figure 3 and Figure 4One or more of the semiconductor devices 100, 200, 300 and 400 shown.

[0183] refer to Figure 9 A System-on-Chip (SoC) 1000 can be an integrated circuit in which components of a computing system or other electronic system are integrated. As an example of an SoC 1000, an application processor (AP) may include at least one processor and components for various functions. An SoC 1000 may include a core 1011 (e.g., a processor), a digital signal processor (DSP) 1012, a graphics processing unit (GPU) 1013, embedded memory 1014, a communication interface 1015, and a memory interface 1016. Components of the SoC 1000 can communicate with each other via a bus 1007.

[0184] Core 1011 can handle control operations and instructions for components included in SoC 1000. For example, core 1011 can process a series of instructions to run an operating system and execute applications on that operating system. DSP 1012 can generate useful data by processing digital signals (e.g., digital signals provided from communication interface 1015). GPU 1013 can generate image data for output by a display device based on image data provided from embedded memory 1014 or memory interface 1016, or it can encode image data.

[0185] Embedded memory 1014 can store data necessary for the operation of core 1011, DSP 1012, and GPU 1013. Communication interface 1015 can provide an interface for communication networks or one-to-one communication. Memory interface 1016 can provide an interface for external memory of SoC 1000, such as dynamic random access memory (DRAM), flash memory, etc.

[0186] According to one or more embodiments, at least one of the core 1011, DSP 1012, GPU 1013, and / or embedded memory 1014 may include Figure 1B , Figure 2 , Figure 3 and Figure 4 One or more of the semiconductor devices 100, 200, 300 and 400 shown.

[0187] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting this disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the above embodiments without substantially departing from this disclosure.

Claims

1. A semiconductor device, comprising: First source / drain region; The second source / drain region above the first source / drain region; A side-channel structure is connected to the second source / drain region; A first back-side contact plug on the first source / drain region; A second back-side contact plug on the side passage structure; The first back-side metal wire on the first back-side contact plug; as well as The second back-side metal wire on the second back-side contact plug.

2. The semiconductor device of claim 1, further comprising a first deep trench isolation structure on the side surface of the second back-side contact plug.

3. The semiconductor device of claim 2, further comprising a second deep trench isolation structure on the opposite side surface of the second back-side contact plug.

4. The semiconductor device according to claim 2, further comprising a shallow trench isolation (STI) structure above the first deep trench isolation structure.

5. The semiconductor device of claim 4, wherein, The first deep trench isolation structure and the STI structure comprise different material compositions.

6. The semiconductor device according to claim 4, wherein, The STI structure is on the side surface of the first back-side contact plug.

7. The semiconductor device according to claim 2, wherein, The first deep trench isolation structure is also on the side surface of the first back contact plug facing the side surface of the second back contact plug.

8. The semiconductor device of claim 7, further comprising a third deep trench isolation structure on the opposite side surface of the first back-side contact plug.

9. The semiconductor device of claim 8, further comprising a shallow trench isolation (STI) structure above the first deep trench isolation structure. in, The STI structure is on the side surface of the first back-side contact plug.

10. The semiconductor device according to claim 1, further comprising: Shallow trench isolation STI structure on the lower surface of the side passage structure; as well as Backside isolation layer, beneath the STI structure, The bottom surface of the side passage structure is at the same level as the bottom surface of the STI structure.

11. A semiconductor device, comprising: Source / drain regions; A back-side contact plug is located on the bottom surface of the source / drain region; as well as The first deep trench isolation structure is on the side surface of the back contact plug.

12. The semiconductor device of claim 11, further comprising a shallow trench isolation (STI) structure above the first deep trench isolation structure. in, The STI structure is also located on the side surface of the back contact plug.

13. The semiconductor device according to claim 12, wherein, The first deep trench isolation structure and the STI structure have different material compositions.

14. The semiconductor device of claim 11, further comprising a second deep trench isolation structure on the opposite side surface of the back-side contact plug.

15. The semiconductor device according to claim 11, wherein, The bottom surface of the back contact plug is at the same level as the bottom surface of the first deep trench isolation structure.

16. The semiconductor device of claim 11, further comprising a back-side isolation layer on a side surface of the first deep trench isolation structure.

17. A method for manufacturing a semiconductor device, the method comprising: A first source / drain region and a second source / drain region above the first source / drain region are formed; A side-path structure is formed that connects to the second source / drain region; A first back-side contact plug is formed on the first source / drain region; A second back-side contact plug is formed on the side passage structure; A first back-side metal wire is formed on the first back-side contact plug; as well as A second back-side metal wire is formed on the second back-side contact plug.

18. The method of claim 17, further comprising forming a first deep trench isolation structure on the side surface of the second back-side contact plug.

19. The method according to claim 18, wherein, The first deep trench isolation structure is also formed on the side surface of the first back contact plug facing the side surface of the second back contact plug.

20. The method of claim 17, further comprising forming a shallow trench isolation (STI) structure above the first deep trench isolation structure.

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